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ia64/kvm: compilation fix. export account_system_vtime.
[pv_ops_mirror.git] / drivers / ide / pci / pdc202xx_old.c
blobfca89eda5c022cf8538eeaa0e89dd9344223d6ec
1 /*
2 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
3 * Copyright (C) 2006-2007 MontaVista Software, Inc.
4 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
5 *
6 * Portions Copyright (C) 1999 Promise Technology, Inc.
7 * Author: Frank Tiernan (frankt@promise.com)
8 * Released under terms of General Public License
9 */
10
11 #include <linux/types.h>
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/delay.h>
15 #include <linux/blkdev.h>
16 #include <linux/hdreg.h>
17 #include <linux/pci.h>
18 #include <linux/init.h>
19 #include <linux/ide.h>
20
21 #include <asm/io.h>
22
23 #define PDC202XX_DEBUG_DRIVE_INFO 0
24
25 static const char *pdc_quirk_drives[] = {
26 "QUANTUM FIREBALLlct08 08",
27 "QUANTUM FIREBALLP KA6.4",
28 "QUANTUM FIREBALLP KA9.1",
29 "QUANTUM FIREBALLP LM20.4",
30 "QUANTUM FIREBALLP KX13.6",
31 "QUANTUM FIREBALLP KX20.5",
32 "QUANTUM FIREBALLP KX27.3",
33 "QUANTUM FIREBALLP LM20.5",
34 NULL
35 };
36
37 static void pdc_old_disable_66MHz_clock(ide_hwif_t *);
38
39 static void pdc202xx_set_mode(ide_drive_t *drive, const u8 speed)
40 {
41 ide_hwif_t *hwif = HWIF(drive);
42 struct pci_dev *dev = to_pci_dev(hwif->dev);
43 u8 drive_pci = 0x60 + (drive->dn << 2);
44
45 u8 AP = 0, BP = 0, CP = 0;
46 u8 TA = 0, TB = 0, TC = 0;
47
48 #if PDC202XX_DEBUG_DRIVE_INFO
49 u32 drive_conf = 0;
50 pci_read_config_dword(dev, drive_pci, &drive_conf);
51 #endif
52
53 /*
54 * TODO: do this once per channel
55 */
56 if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
57 pdc_old_disable_66MHz_clock(hwif);
58
59 pci_read_config_byte(dev, drive_pci, &AP);
60 pci_read_config_byte(dev, drive_pci + 1, &BP);
61 pci_read_config_byte(dev, drive_pci + 2, &CP);
62
63 switch(speed) {
64 case XFER_UDMA_5:
65 case XFER_UDMA_4: TB = 0x20; TC = 0x01; break;
66 case XFER_UDMA_2: TB = 0x20; TC = 0x01; break;
67 case XFER_UDMA_3:
68 case XFER_UDMA_1: TB = 0x40; TC = 0x02; break;
69 case XFER_UDMA_0:
70 case XFER_MW_DMA_2: TB = 0x60; TC = 0x03; break;
71 case XFER_MW_DMA_1: TB = 0x60; TC = 0x04; break;
72 case XFER_MW_DMA_0: TB = 0xE0; TC = 0x0F; break;
73 case XFER_PIO_4: TA = 0x01; TB = 0x04; break;
74 case XFER_PIO_3: TA = 0x02; TB = 0x06; break;
75 case XFER_PIO_2: TA = 0x03; TB = 0x08; break;
76 case XFER_PIO_1: TA = 0x05; TB = 0x0C; break;
77 case XFER_PIO_0:
78 default: TA = 0x09; TB = 0x13; break;
79 }
80
81 if (speed < XFER_SW_DMA_0) {
82 /*
83 * preserve SYNC_INT / ERDDY_EN bits while clearing
84 * Prefetch_EN / IORDY_EN / PA[3:0] bits of register A
85 */
86 AP &= ~0x3f;
87 if (drive->id->capability & 4)
88 AP |= 0x20; /* set IORDY_EN bit */
89 if (drive->media == ide_disk)
90 AP |= 0x10; /* set Prefetch_EN bit */
91 /* clear PB[4:0] bits of register B */
92 BP &= ~0x1f;
93 pci_write_config_byte(dev, drive_pci, AP | TA);
94 pci_write_config_byte(dev, drive_pci + 1, BP | TB);
95 } else {
96 /* clear MB[2:0] bits of register B */
97 BP &= ~0xe0;
98 /* clear MC[3:0] bits of register C */
99 CP &= ~0x0f;
100 pci_write_config_byte(dev, drive_pci + 1, BP | TB);
101 pci_write_config_byte(dev, drive_pci + 2, CP | TC);
102 }
103
104 #if PDC202XX_DEBUG_DRIVE_INFO
105 printk(KERN_DEBUG "%s: %s drive%d 0x%08x ",
106 drive->name, ide_xfer_verbose(speed),
107 drive->dn, drive_conf);
108 pci_read_config_dword(dev, drive_pci, &drive_conf);
109 printk("0x%08x\n", drive_conf);
110 #endif
111 }
112
113 static void pdc202xx_set_pio_mode(ide_drive_t *drive, const u8 pio)
114 {
115 pdc202xx_set_mode(drive, XFER_PIO_0 + pio);
116 }
117
118 static u8 __devinit pdc2026x_cable_detect(ide_hwif_t *hwif)
119 {
120 struct pci_dev *dev = to_pci_dev(hwif->dev);
121 u16 CIS, mask = hwif->channel ? (1 << 11) : (1 << 10);
122
123 pci_read_config_word(dev, 0x50, &CIS);
124
125 return (CIS & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
126 }
127
128 /*
129 * Set the control register to use the 66MHz system
130 * clock for UDMA 3/4/5 mode operation when necessary.
131 *
132 * FIXME: this register is shared by both channels, some locking is needed
133 *
134 * It may also be possible to leave the 66MHz clock on
135 * and readjust the timing parameters.
136 */
137 static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
138 {
139 unsigned long clock_reg = hwif->extra_base + 0x01;
140 u8 clock = inb(clock_reg);
141
142 outb(clock | (hwif->channel ? 0x08 : 0x02), clock_reg);
143 }
144
145 static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
146 {
147 unsigned long clock_reg = hwif->extra_base + 0x01;
148 u8 clock = inb(clock_reg);
149
150 outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
151 }
152
153 static void pdc202xx_quirkproc(ide_drive_t *drive)
154 {
155 const char **list, *model = drive->id->model;
156
157 for (list = pdc_quirk_drives; *list != NULL; list++)
158 if (strstr(model, *list) != NULL) {
159 drive->quirk_list = 2;
160 return;
161 }
162
163 drive->quirk_list = 0;
164 }
165
166 static void pdc202xx_dma_start(ide_drive_t *drive)
167 {
168 if (drive->current_speed > XFER_UDMA_2)
169 pdc_old_enable_66MHz_clock(drive->hwif);
170 if (drive->media != ide_disk || drive->addressing == 1) {
171 struct request *rq = HWGROUP(drive)->rq;
172 ide_hwif_t *hwif = HWIF(drive);
173 unsigned long high_16 = hwif->extra_base - 16;
174 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
175 u32 word_count = 0;
176 u8 clock = inb(high_16 + 0x11);
177
178 outb(clock | (hwif->channel ? 0x08 : 0x02), high_16 + 0x11);
179 word_count = (rq->nr_sectors << 8);
180 word_count = (rq_data_dir(rq) == READ) ?
181 word_count | 0x05000000 :
182 word_count | 0x06000000;
183 outl(word_count, atapi_reg);
184 }
185 ide_dma_start(drive);
186 }
187
188 static int pdc202xx_dma_end(ide_drive_t *drive)
189 {
190 if (drive->media != ide_disk || drive->addressing == 1) {
191 ide_hwif_t *hwif = HWIF(drive);
192 unsigned long high_16 = hwif->extra_base - 16;
193 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
194 u8 clock = 0;
195
196 outl(0, atapi_reg); /* zero out extra */
197 clock = inb(high_16 + 0x11);
198 outb(clock & ~(hwif->channel ? 0x08:0x02), high_16 + 0x11);
199 }
200 if (drive->current_speed > XFER_UDMA_2)
201 pdc_old_disable_66MHz_clock(drive->hwif);
202 return __ide_dma_end(drive);
203 }
204
205 static int pdc202xx_dma_test_irq(ide_drive_t *drive)
206 {
207 ide_hwif_t *hwif = HWIF(drive);
208 unsigned long high_16 = hwif->extra_base - 16;
209 u8 dma_stat = inb(hwif->dma_status);
210 u8 sc1d = inb(high_16 + 0x001d);
211
212 if (hwif->channel) {
213 /* bit7: Error, bit6: Interrupting, bit5: FIFO Full, bit4: FIFO Empty */
214 if ((sc1d & 0x50) == 0x50)
215 goto somebody_else;
216 else if ((sc1d & 0x40) == 0x40)
217 return (dma_stat & 4) == 4;
218 } else {
219 /* bit3: Error, bit2: Interrupting, bit1: FIFO Full, bit0: FIFO Empty */
220 if ((sc1d & 0x05) == 0x05)
221 goto somebody_else;
222 else if ((sc1d & 0x04) == 0x04)
223 return (dma_stat & 4) == 4;
224 }
225 somebody_else:
226 return (dma_stat & 4) == 4; /* return 1 if INTR asserted */
227 }
228
229 static void pdc202xx_reset_host (ide_hwif_t *hwif)
230 {
231 unsigned long high_16 = hwif->extra_base - 16;
232 u8 udma_speed_flag = inb(high_16 | 0x001f);
233
234 outb(udma_speed_flag | 0x10, high_16 | 0x001f);
235 mdelay(100);
236 outb(udma_speed_flag & ~0x10, high_16 | 0x001f);
237 mdelay(2000); /* 2 seconds ?! */
238
239 printk(KERN_WARNING "PDC202XX: %s channel reset.\n",
240 hwif->channel ? "Secondary" : "Primary");
241 }
242
243 static void pdc202xx_reset (ide_drive_t *drive)
244 {
245 ide_hwif_t *hwif = HWIF(drive);
246 ide_hwif_t *mate = hwif->mate;
247
248 pdc202xx_reset_host(hwif);
249 pdc202xx_reset_host(mate);
250
251 ide_set_max_pio(drive);
252 }
253
254 static void pdc202xx_dma_lost_irq(ide_drive_t *drive)
255 {
256 pdc202xx_reset(drive);
257 ide_dma_lost_irq(drive);
258 }
259
260 static void pdc202xx_dma_timeout(ide_drive_t *drive)
261 {
262 pdc202xx_reset(drive);
263 ide_dma_timeout(drive);
264 }
265
266 static unsigned int __devinit init_chipset_pdc202xx(struct pci_dev *dev,
267 const char *name)
268 {
269 unsigned long dmabase = pci_resource_start(dev, 4);
270 u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;
271
272 if (dmabase == 0)
273 goto out;
274
275 udma_speed_flag = inb(dmabase | 0x1f);
276 primary_mode = inb(dmabase | 0x1a);
277 secondary_mode = inb(dmabase | 0x1b);
278 printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
279 "Primary %s Mode " \
280 "Secondary %s Mode.\n", pci_name(dev),
281 (udma_speed_flag & 1) ? "EN" : "DIS",
282 (primary_mode & 1) ? "MASTER" : "PCI",
283 (secondary_mode & 1) ? "MASTER" : "PCI" );
284
285 if (!(udma_speed_flag & 1)) {
286 printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
287 pci_name(dev), udma_speed_flag,
288 (udma_speed_flag|1));
289 outb(udma_speed_flag | 1, dmabase | 0x1f);
290 printk("%sACTIVE\n", (inb(dmabase | 0x1f) & 1) ? "" : "IN");
291 }
292 out:
293 return dev->irq;
294 }
295
296 static void __devinit pdc202ata4_fixup_irq(struct pci_dev *dev,
297 const char *name)
298 {
299 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
300 u8 irq = 0, irq2 = 0;
301 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
302 /* 0xbc */
303 pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2);
304 if (irq != irq2) {
305 pci_write_config_byte(dev,
306 (PCI_INTERRUPT_LINE)|0x80, irq); /* 0xbc */
307 printk(KERN_INFO "%s: PCI config space interrupt "
308 "mirror fixed\n", name);
309 }
310 }
311 }
312
313 #define IDE_HFLAGS_PDC202XX \
314 (IDE_HFLAG_ERROR_STOPS_FIFO | \
315 IDE_HFLAG_ABUSE_SET_DMA_MODE | \
316 IDE_HFLAG_OFF_BOARD)
317
318 static const struct ide_port_ops pdc20246_port_ops = {
319 .set_pio_mode = pdc202xx_set_pio_mode,
320 .set_dma_mode = pdc202xx_set_mode,
321 .quirkproc = pdc202xx_quirkproc,
322 };
323
324 static const struct ide_port_ops pdc2026x_port_ops = {
325 .set_pio_mode = pdc202xx_set_pio_mode,
326 .set_dma_mode = pdc202xx_set_mode,
327 .quirkproc = pdc202xx_quirkproc,
328 .resetproc = pdc202xx_reset,
329 .cable_detect = pdc2026x_cable_detect,
330 };
331
332 static const struct ide_dma_ops pdc20246_dma_ops = {
333 .dma_host_set = ide_dma_host_set,
334 .dma_setup = ide_dma_setup,
335 .dma_exec_cmd = ide_dma_exec_cmd,
336 .dma_start = ide_dma_start,
337 .dma_end = __ide_dma_end,
338 .dma_test_irq = pdc202xx_dma_test_irq,
339 .dma_lost_irq = pdc202xx_dma_lost_irq,
340 .dma_timeout = pdc202xx_dma_timeout,
341 };
342
343 static const struct ide_dma_ops pdc2026x_dma_ops = {
344 .dma_host_set = ide_dma_host_set,
345 .dma_setup = ide_dma_setup,
346 .dma_exec_cmd = ide_dma_exec_cmd,
347 .dma_start = pdc202xx_dma_start,
348 .dma_end = pdc202xx_dma_end,
349 .dma_test_irq = pdc202xx_dma_test_irq,
350 .dma_lost_irq = pdc202xx_dma_lost_irq,
351 .dma_timeout = pdc202xx_dma_timeout,
352 };
353
354 #define DECLARE_PDC2026X_DEV(name_str, udma, extra_flags) \
355 { \
356 .name = name_str, \
357 .init_chipset = init_chipset_pdc202xx, \
358 .port_ops = &pdc2026x_port_ops, \
359 .dma_ops = &pdc2026x_dma_ops, \
360 .host_flags = IDE_HFLAGS_PDC202XX | extra_flags, \
361 .pio_mask = ATA_PIO4, \
362 .mwdma_mask = ATA_MWDMA2, \
363 .udma_mask = udma, \
364 }
365
366 static const struct ide_port_info pdc202xx_chipsets[] __devinitdata = {
367 { /* 0 */
368 .name = "PDC20246",
369 .init_chipset = init_chipset_pdc202xx,
370 .port_ops = &pdc20246_port_ops,
371 .dma_ops = &pdc20246_dma_ops,
372 .host_flags = IDE_HFLAGS_PDC202XX,
373 .pio_mask = ATA_PIO4,
374 .mwdma_mask = ATA_MWDMA2,
375 .udma_mask = ATA_UDMA2,
376 },
377
378 /* 1 */ DECLARE_PDC2026X_DEV("PDC20262", ATA_UDMA4, 0),
379 /* 2 */ DECLARE_PDC2026X_DEV("PDC20263", ATA_UDMA4, 0),
380 /* 3 */ DECLARE_PDC2026X_DEV("PDC20265", ATA_UDMA5, IDE_HFLAG_RQSIZE_256),
381 /* 4 */ DECLARE_PDC2026X_DEV("PDC20267", ATA_UDMA5, IDE_HFLAG_RQSIZE_256),
382 };
383
384 /**
385 * pdc202xx_init_one - called when a PDC202xx is found
386 * @dev: the pdc202xx device
387 * @id: the matching pci id
388 *
389 * Called when the PCI registration layer (or the IDE initialization)
390 * finds a device matching our IDE device tables.
391 */
392
393 static int __devinit pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
394 {
395 const struct ide_port_info *d;
396 u8 idx = id->driver_data;
397
398 d = &pdc202xx_chipsets[idx];
399
400 if (idx < 3)
401 pdc202ata4_fixup_irq(dev, d->name);
402
403 if (idx == 3) {
404 struct pci_dev *bridge = dev->bus->self;
405
406 if (bridge &&
407 bridge->vendor == PCI_VENDOR_ID_INTEL &&
408 (bridge->device == PCI_DEVICE_ID_INTEL_I960 ||
409 bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) {
410 printk(KERN_INFO "ide: Skipping Promise PDC20265 "
411 "attached to I2O RAID controller\n");
412 return -ENODEV;
413 }
414 }
415
416 return ide_setup_pci_device(dev, d);
417 }
418
419 static const struct pci_device_id pdc202xx_pci_tbl[] = {
420 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 },
421 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 },
422 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 2 },
423 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 3 },
424 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 4 },
425 { 0, },
426 };
427 MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl);
428
429 static struct pci_driver driver = {
430 .name = "Promise_Old_IDE",
431 .id_table = pdc202xx_pci_tbl,
432 .probe = pdc202xx_init_one,
433 };
434
435 static int __init pdc202xx_ide_init(void)
436 {
437 return ide_pci_register_driver(&driver);
438 }
439
440 module_init(pdc202xx_ide_init);
441
442 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
443 MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
444 MODULE_LICENSE("GPL");
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