drivers/ide/pci/serverworks.c

   1 /*
   2  * Copyright (C) 1998-2000 Michel Aubry
   3  * Copyright (C) 1998-2000 Andrzej Krzysztofowicz
   4  * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
   5  * Copyright (C)      2007 Bartlomiej Zolnierkiewicz
   6  * Portions copyright (c) 2001 Sun Microsystems
   7  *
   8  *
   9  * RCC/ServerWorks IDE driver for Linux
  10  *
  11  *   OSB4: `Open South Bridge' IDE Interface (fn 1)
  12  *         supports UDMA mode 2 (33 MB/s)
  13  *
  14  *   CSB5: `Champion South Bridge' IDE Interface (fn 1)
  15  *         all revisions support UDMA mode 4 (66 MB/s)
  16  *         revision A2.0 and up support UDMA mode 5 (100 MB/s)
  17  *
  18  *         *** The CSB5 does not provide ANY register ***
  19  *         *** to detect 80-conductor cable presence. ***
  20  *
  21  *   CSB6: `Champion South Bridge' IDE Interface (optional: third channel)
  22  *
  23  *   HT1000: AKA BCM5785 - Hypertransport Southbridge for Opteron systems. IDE
  24  *   controller same as the CSB6. Single channel ATA100 only.
  25  *
  26  * Documentation:
  27  *      Available under NDA only. Errata info very hard to get.
  28  *
  29  */
  30
  31 #include <linux/types.h>
  32 #include <linux/module.h>
  33 #include <linux/kernel.h>
  34 #include <linux/pci.h>
  35 #include <linux/hdreg.h>
  36 #include <linux/ide.h>
  37 #include <linux/init.h>
  38
  39 #include <asm/io.h>
  40
  41 #define SVWKS_CSB5_REVISION_NEW 0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */
  42 #define SVWKS_CSB6_REVISION     0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */
  43
  44 /* Seagate Barracuda ATA IV Family drives in UDMA mode 5
  45  * can overrun their FIFOs when used with the CSB5 */
  46 static const char *svwks_bad_ata100[] = {
  47         "ST320011A",
  48         "ST340016A",
  49         "ST360021A",
  50         "ST380021A",
  51         NULL
  52 };
  53
  54 static struct pci_dev *isa_dev;
  55
  56 static int check_in_drive_lists (ide_drive_t *drive, const char **list)
  57 {
  58         while (*list)
  59                 if (!strcmp(*list++, drive->id->model))
  60                         return 1;
  61         return 0;
  62 }
  63
  64 static u8 svwks_udma_filter(ide_drive_t *drive)
  65 {
  66         struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
  67         u8 mask = 0;
  68
  69         if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE)
  70                 return 0x1f;
  71         if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
  72                 u32 reg = 0;
  73                 if (isa_dev)
  74                         pci_read_config_dword(isa_dev, 0x64, &reg);
  75
  76                 /*
  77                  *      Don't enable UDMA on disk devices for the moment
  78                  */
  79                 if(drive->media == ide_disk)
  80                         return 0;
  81                 /* Check the OSB4 DMA33 enable bit */
  82                 return ((reg & 0x00004000) == 0x00004000) ? 0x07 : 0;
  83         } else if (dev->revision < SVWKS_CSB5_REVISION_NEW) {
  84                 return 0x07;
  85         } else if (dev->revision >= SVWKS_CSB5_REVISION_NEW) {
  86                 u8 btr = 0, mode;
  87                 pci_read_config_byte(dev, 0x5A, &btr);
  88                 mode = btr & 0x3;
  89
  90                 /* If someone decides to do UDMA133 on CSB5 the same
  91                    issue will bite so be inclusive */
  92                 if (mode > 2 && check_in_drive_lists(drive, svwks_bad_ata100))
  93                         mode = 2;
  94
  95                 switch(mode) {
  96                 case 3:  mask = 0x3f; break;
  97                 case 2:  mask = 0x1f; break;
  98                 case 1:  mask = 0x07; break;
  99                 default: mask = 0x00; break;
 100                 }
 101         }
 102         if (((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
 103              (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) &&
 104             (!(PCI_FUNC(dev->devfn) & 1)))
 105                 mask = 0x1f;
 106
 107         return mask;
 108 }
 109
 110 static u8 svwks_csb_check (struct pci_dev *dev)
 111 {
 112         switch (dev->device) {
 113                 case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
 114                 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
 115                 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
 116                 case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
 117                         return 1;
 118                 default:
 119                         break;
 120         }
 121         return 0;
 122 }
 123
 124 static void svwks_set_pio_mode(ide_drive_t *drive, const u8 pio)
 125 {
 126         static const u8 pio_modes[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
 127         static const u8 drive_pci[] = { 0x41, 0x40, 0x43, 0x42 };
 128
 129         struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
 130
 131         pci_write_config_byte(dev, drive_pci[drive->dn], pio_modes[pio]);
 132
 133         if (svwks_csb_check(dev)) {
 134                 u16 csb_pio = 0;
 135
 136                 pci_read_config_word(dev, 0x4a, &csb_pio);
 137
 138                 csb_pio &= ~(0x0f << (4 * drive->dn));
 139                 csb_pio |= (pio << (4 * drive->dn));
 140
 141                 pci_write_config_word(dev, 0x4a, csb_pio);
 142         }
 143 }
 144
 145 static void svwks_set_dma_mode(ide_drive_t *drive, const u8 speed)
 146 {
 147         static const u8 udma_modes[]            = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05 };
 148         static const u8 dma_modes[]             = { 0x77, 0x21, 0x20 };
 149         static const u8 drive_pci2[]            = { 0x45, 0x44, 0x47, 0x46 };
 150
 151         ide_hwif_t *hwif        = HWIF(drive);
 152         struct pci_dev *dev     = to_pci_dev(hwif->dev);
 153         u8 unit                 = (drive->select.b.unit & 0x01);
 154
 155         u8 ultra_enable  = 0, ultra_timing = 0, dma_timing = 0;
 156
 157         pci_read_config_byte(dev, (0x56|hwif->channel), &ultra_timing);
 158         pci_read_config_byte(dev, 0x54, &ultra_enable);
 159
 160         ultra_timing    &= ~(0x0F << (4*unit));
 161         ultra_enable    &= ~(0x01 << drive->dn);
 162
 163         if (speed >= XFER_UDMA_0) {
 164                 dma_timing   |= dma_modes[2];
 165                 ultra_timing |= (udma_modes[speed - XFER_UDMA_0] << (4 * unit));
 166                 ultra_enable |= (0x01 << drive->dn);
 167         } else if (speed >= XFER_MW_DMA_0)
 168                 dma_timing   |= dma_modes[speed - XFER_MW_DMA_0];
 169
 170         pci_write_config_byte(dev, drive_pci2[drive->dn], dma_timing);
 171         pci_write_config_byte(dev, (0x56|hwif->channel), ultra_timing);
 172         pci_write_config_byte(dev, 0x54, ultra_enable);
 173 }
 174
 175 static unsigned int __devinit init_chipset_svwks (struct pci_dev *dev, const char *name)
 176 {
 177         unsigned int reg;
 178         u8 btr;
 179
 180         /* force Master Latency Timer value to 64 PCICLKs */
 181         pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x40);
 182
 183         /* OSB4 : South Bridge and IDE */
 184         if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
 185                 isa_dev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
 186                           PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL);
 187                 if (isa_dev) {
 188                         pci_read_config_dword(isa_dev, 0x64, &reg);
 189                         reg &= ~0x00002000; /* disable 600ns interrupt mask */
 190                         if(!(reg & 0x00004000))
 191                                 printk(KERN_DEBUG "%s: UDMA not BIOS enabled.\n", name);
 192                         reg |=  0x00004000; /* enable UDMA/33 support */
 193                         pci_write_config_dword(isa_dev, 0x64, reg);
 194                 }
 195         }
 196
 197         /* setup CSB5/CSB6 : South Bridge and IDE option RAID */
 198         else if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) ||
 199                  (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
 200                  (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
 201
 202                 /* Third Channel Test */
 203                 if (!(PCI_FUNC(dev->devfn) & 1)) {
 204                         struct pci_dev * findev = NULL;
 205                         u32 reg4c = 0;
 206                         findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
 207                                 PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL);
 208                         if (findev) {
 209                                 pci_read_config_dword(findev, 0x4C, &reg4c);
 210                                 reg4c &= ~0x000007FF;
 211                                 reg4c |=  0x00000040;
 212                                 reg4c |=  0x00000020;
 213                                 pci_write_config_dword(findev, 0x4C, reg4c);
 214                                 pci_dev_put(findev);
 215                         }
 216                         outb_p(0x06, 0x0c00);
 217                         dev->irq = inb_p(0x0c01);
 218                 } else {
 219                         struct pci_dev * findev = NULL;
 220                         u8 reg41 = 0;
 221
 222                         findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
 223                                         PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL);
 224                         if (findev) {
 225                                 pci_read_config_byte(findev, 0x41, &reg41);
 226                                 reg41 &= ~0x40;
 227                                 pci_write_config_byte(findev, 0x41, reg41);
 228                                 pci_dev_put(findev);
 229                         }
 230                         /*
 231                          * This is a device pin issue on CSB6.
 232                          * Since there will be a future raid mode,
 233                          * early versions of the chipset require the
 234                          * interrupt pin to be set, and it is a compatibility
 235                          * mode issue.
 236                          */
 237                         if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
 238                                 dev->irq = 0;
 239                 }
 240 //              pci_read_config_dword(dev, 0x40, &pioreg)
 241 //              pci_write_config_dword(dev, 0x40, 0x99999999);
 242 //              pci_read_config_dword(dev, 0x44, &dmareg);
 243 //              pci_write_config_dword(dev, 0x44, 0xFFFFFFFF);
 244                 /* setup the UDMA Control register
 245                  *
 246                  * 1. clear bit 6 to enable DMA
 247                  * 2. enable DMA modes with bits 0-1
 248                  *      00 : legacy
 249                  *      01 : udma2
 250                  *      10 : udma2/udma4
 251                  *      11 : udma2/udma4/udma5
 252                  */
 253                 pci_read_config_byte(dev, 0x5A, &btr);
 254                 btr &= ~0x40;
 255                 if (!(PCI_FUNC(dev->devfn) & 1))
 256                         btr |= 0x2;
 257                 else
 258                         btr |= (dev->revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
 259                 pci_write_config_byte(dev, 0x5A, btr);
 260         }
 261         /* Setup HT1000 SouthBridge Controller - Single Channel Only */
 262         else if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) {
 263                 pci_read_config_byte(dev, 0x5A, &btr);
 264                 btr &= ~0x40;
 265                 btr |= 0x3;
 266                 pci_write_config_byte(dev, 0x5A, btr);
 267         }
 268
 269         return dev->irq;
 270 }
 271
 272 static u8 __devinit ata66_svwks_svwks(ide_hwif_t *hwif)
 273 {
 274         return ATA_CBL_PATA80;
 275 }
 276
 277 /* On Dell PowerEdge servers with a CSB5/CSB6, the top two bits
 278  * of the subsystem device ID indicate presence of an 80-pin cable.
 279  * Bit 15 clear = secondary IDE channel does not have 80-pin cable.
 280  * Bit 15 set   = secondary IDE channel has 80-pin cable.
 281  * Bit 14 clear = primary IDE channel does not have 80-pin cable.
 282  * Bit 14 set   = primary IDE channel has 80-pin cable.
 283  */
 284 static u8 __devinit ata66_svwks_dell(ide_hwif_t *hwif)
 285 {
 286         struct pci_dev *dev = to_pci_dev(hwif->dev);
 287
 288         if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
 289             dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
 290             (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE ||
 291              dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE))
 292                 return ((1 << (hwif->channel + 14)) &
 293                         dev->subsystem_device) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
 294         return ATA_CBL_PATA40;
 295 }
 296
 297 /* Sun Cobalt Alpine hardware avoids the 80-pin cable
 298  * detect issue by attaching the drives directly to the board.
 299  * This check follows the Dell precedent (how scary is that?!)
 300  *
 301  * WARNING: this only works on Alpine hardware!
 302  */
 303 static u8 __devinit ata66_svwks_cobalt(ide_hwif_t *hwif)
 304 {
 305         struct pci_dev *dev = to_pci_dev(hwif->dev);
 306
 307         if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN &&
 308             dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
 309             dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE)
 310                 return ((1 << (hwif->channel + 14)) &
 311                         dev->subsystem_device) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
 312         return ATA_CBL_PATA40;
 313 }
 314
 315 static u8 __devinit svwks_cable_detect(ide_hwif_t *hwif)
 316 {
 317         struct pci_dev *dev = to_pci_dev(hwif->dev);
 318
 319         /* Server Works */
 320         if (dev->subsystem_vendor == PCI_VENDOR_ID_SERVERWORKS)
 321                 return ata66_svwks_svwks (hwif);
 322
 323         /* Dell PowerEdge */
 324         if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL)
 325                 return ata66_svwks_dell (hwif);
 326
 327         /* Cobalt Alpine */
 328         if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN)
 329                 return ata66_svwks_cobalt (hwif);
 330
 331         /* Per Specified Design by OEM, and ASIC Architect */
 332         if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
 333             (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2))
 334                 return ATA_CBL_PATA80;
 335
 336         return ATA_CBL_PATA40;
 337 }
 338
 339 static const struct ide_port_ops osb4_port_ops = {
 340         .set_pio_mode           = svwks_set_pio_mode,
 341         .set_dma_mode           = svwks_set_dma_mode,
 342         .udma_filter            = svwks_udma_filter,
 343 };
 344
 345 static const struct ide_port_ops svwks_port_ops = {
 346         .set_pio_mode           = svwks_set_pio_mode,
 347         .set_dma_mode           = svwks_set_dma_mode,
 348         .udma_filter            = svwks_udma_filter,
 349         .cable_detect           = svwks_cable_detect,
 350 };
 351
 352 #define IDE_HFLAGS_SVWKS \
 353         (IDE_HFLAG_LEGACY_IRQS | \
 354          IDE_HFLAG_ABUSE_SET_DMA_MODE)
 355
 356 static const struct ide_port_info serverworks_chipsets[] __devinitdata = {
 357         {       /* 0 */
 358                 .name           = "SvrWks OSB4",
 359                 .init_chipset   = init_chipset_svwks,
 360                 .port_ops       = &osb4_port_ops,
 361                 .host_flags     = IDE_HFLAGS_SVWKS,
 362                 .pio_mask       = ATA_PIO4,
 363                 .mwdma_mask     = ATA_MWDMA2,
 364                 .udma_mask      = 0x00, /* UDMA is problematic on OSB4 */
 365         },{     /* 1 */
 366                 .name           = "SvrWks CSB5",
 367                 .init_chipset   = init_chipset_svwks,
 368                 .port_ops       = &svwks_port_ops,
 369                 .host_flags     = IDE_HFLAGS_SVWKS,
 370                 .pio_mask       = ATA_PIO4,
 371                 .mwdma_mask     = ATA_MWDMA2,
 372                 .udma_mask      = ATA_UDMA5,
 373         },{     /* 2 */
 374                 .name           = "SvrWks CSB6",
 375                 .init_chipset   = init_chipset_svwks,
 376                 .port_ops       = &svwks_port_ops,
 377                 .host_flags     = IDE_HFLAGS_SVWKS,
 378                 .pio_mask       = ATA_PIO4,
 379                 .mwdma_mask     = ATA_MWDMA2,
 380                 .udma_mask      = ATA_UDMA5,
 381         },{     /* 3 */
 382                 .name           = "SvrWks CSB6",
 383                 .init_chipset   = init_chipset_svwks,
 384                 .port_ops       = &svwks_port_ops,
 385                 .host_flags     = IDE_HFLAGS_SVWKS | IDE_HFLAG_SINGLE,
 386                 .pio_mask       = ATA_PIO4,
 387                 .mwdma_mask     = ATA_MWDMA2,
 388                 .udma_mask      = ATA_UDMA5,
 389         },{     /* 4 */
 390                 .name           = "SvrWks HT1000",
 391                 .init_chipset   = init_chipset_svwks,
 392                 .port_ops       = &svwks_port_ops,
 393                 .host_flags     = IDE_HFLAGS_SVWKS | IDE_HFLAG_SINGLE,
 394                 .pio_mask       = ATA_PIO4,
 395                 .mwdma_mask     = ATA_MWDMA2,
 396                 .udma_mask      = ATA_UDMA5,
 397         }
 398 };
 399
 400 /**
 401  *      svwks_init_one  -       called when a OSB/CSB is found
 402  *      @dev: the svwks device
 403  *      @id: the matching pci id
 404  *
 405  *      Called when the PCI registration layer (or the IDE initialization)
 406  *      finds a device matching our IDE device tables.
 407  */
 408
 409 static int __devinit svwks_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 410 {
 411         struct ide_port_info d;
 412         u8 idx = id->driver_data;
 413
 414         d = serverworks_chipsets[idx];
 415
 416         if (idx == 1)
 417                 d.host_flags |= IDE_HFLAG_CLEAR_SIMPLEX;
 418         else if (idx == 2 || idx == 3) {
 419                 if ((PCI_FUNC(dev->devfn) & 1) == 0) {
 420                         if (pci_resource_start(dev, 0) != 0x01f1)
 421                                 d.host_flags |= IDE_HFLAG_NON_BOOTABLE;
 422                         d.host_flags |= IDE_HFLAG_SINGLE;
 423                 } else
 424                         d.host_flags &= ~IDE_HFLAG_SINGLE;
 425         }
 426
 427         return ide_setup_pci_device(dev, &d);
 428 }
 429
 430 static const struct pci_device_id svwks_pci_tbl[] = {
 431         { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE),   0 },
 432         { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE),   1 },
 433         { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE),   2 },
 434         { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2),  3 },
 435         { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE), 4 },
 436         { 0, },
 437 };
 438 MODULE_DEVICE_TABLE(pci, svwks_pci_tbl);
 439
 440 static struct pci_driver driver = {
 441         .name           = "Serverworks_IDE",
 442         .id_table       = svwks_pci_tbl,
 443         .probe          = svwks_init_one,
 444 };
 445
 446 static int __init svwks_ide_init(void)
 447 {
 448         return ide_pci_register_driver(&driver);
 449 }
 450
 451 module_init(svwks_ide_init);
 452
 453 MODULE_AUTHOR("Michael Aubry. Andrzej Krzysztofowicz, Andre Hedrick");
 454 MODULE_DESCRIPTION("PCI driver module for Serverworks OSB4/CSB5/CSB6 IDE");
 455 MODULE_LICENSE("GPL");