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ia64/kvm: compilation fix. export account_system_vtime.
[pv_ops_mirror.git] / drivers / ide / pci / sis5513.c
blob4b0b85d8faf5ae2cba38878d7db4a3ded5504aa7
1 /*
2 * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org>
3 * Copyright (C) 2002 Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer
4 * Copyright (C) 2003 Vojtech Pavlik <vojtech@suse.cz>
5 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
6 *
7 * May be copied or modified under the terms of the GNU General Public License
8 *
9 *
10 * Thanks :
11 *
12 * SiS Taiwan : for direct support and hardware.
13 * Daniela Engert : for initial ATA100 advices and numerous others.
14 * John Fremlin, Manfred Spraul, Dave Morgan, Peter Kjellerstedt :
15 * for checking code correctness, providing patches.
16 *
17 *
18 * Original tests and design on the SiS620 chipset.
19 * ATA100 tests and design on the SiS735 chipset.
20 * ATA16/33 support from specs
21 * ATA133 support for SiS961/962 by L.C. Chang <lcchang@sis.com.tw>
22 * ATA133 961/962/963 fixes by Vojtech Pavlik <vojtech@suse.cz>
23 *
24 * Documentation:
25 * SiS chipset documentation available under NDA to companies only
26 * (not to individuals).
27 */
28
29 /*
30 * The original SiS5513 comes from a SiS5511/55112/5513 chipset. The original
31 * SiS5513 was also used in the SiS5596/5513 chipset. Thus if we see a SiS5511
32 * or SiS5596, we can assume we see the first MWDMA-16 capable SiS5513 chip.
33 *
34 * Later SiS chipsets integrated the 5513 functionality into the NorthBridge,
35 * starting with SiS5571 and up to SiS745. The PCI ID didn't change, though. We
36 * can figure out that we have a more modern and more capable 5513 by looking
37 * for the respective NorthBridge IDs.
38 *
39 * Even later (96x family) SiS chipsets use the MuTIOL link and place the 5513
40 * into the SouthBrige. Here we cannot rely on looking up the NorthBridge PCI
41 * ID, while the now ATA-133 capable 5513 still has the same PCI ID.
42 * Fortunately the 5513 can be 'unmasked' by fiddling with some config space
43 * bits, changing its device id to the true one - 5517 for 961 and 5518 for
44 * 962/963.
45 */
46
47 #include <linux/types.h>
48 #include <linux/module.h>
49 #include <linux/kernel.h>
50 #include <linux/hdreg.h>
51 #include <linux/pci.h>
52 #include <linux/init.h>
53 #include <linux/ide.h>
54
55 #include "ide-timing.h"
56
57 /* registers layout and init values are chipset family dependant */
58
59 #define ATA_16 0x01
60 #define ATA_33 0x02
61 #define ATA_66 0x03
62 #define ATA_100a 0x04 /* SiS730/SiS550 is ATA100 with ATA66 layout */
63 #define ATA_100 0x05
64 #define ATA_133a 0x06 /* SiS961b with 133 support */
65 #define ATA_133 0x07 /* SiS962/963 */
66
67 static u8 chipset_family;
68
69 /*
70 * Devices supported
71 */
72 static const struct {
73 const char *name;
74 u16 host_id;
75 u8 chipset_family;
76 u8 flags;
77 } SiSHostChipInfo[] = {
78 { "SiS968", PCI_DEVICE_ID_SI_968, ATA_133 },
79 { "SiS966", PCI_DEVICE_ID_SI_966, ATA_133 },
80 { "SiS965", PCI_DEVICE_ID_SI_965, ATA_133 },
81 { "SiS745", PCI_DEVICE_ID_SI_745, ATA_100 },
82 { "SiS735", PCI_DEVICE_ID_SI_735, ATA_100 },
83 { "SiS733", PCI_DEVICE_ID_SI_733, ATA_100 },
84 { "SiS635", PCI_DEVICE_ID_SI_635, ATA_100 },
85 { "SiS633", PCI_DEVICE_ID_SI_633, ATA_100 },
86
87 { "SiS730", PCI_DEVICE_ID_SI_730, ATA_100a },
88 { "SiS550", PCI_DEVICE_ID_SI_550, ATA_100a },
89
90 { "SiS640", PCI_DEVICE_ID_SI_640, ATA_66 },
91 { "SiS630", PCI_DEVICE_ID_SI_630, ATA_66 },
92 { "SiS620", PCI_DEVICE_ID_SI_620, ATA_66 },
93 { "SiS540", PCI_DEVICE_ID_SI_540, ATA_66 },
94 { "SiS530", PCI_DEVICE_ID_SI_530, ATA_66 },
95
96 { "SiS5600", PCI_DEVICE_ID_SI_5600, ATA_33 },
97 { "SiS5598", PCI_DEVICE_ID_SI_5598, ATA_33 },
98 { "SiS5597", PCI_DEVICE_ID_SI_5597, ATA_33 },
99 { "SiS5591/2", PCI_DEVICE_ID_SI_5591, ATA_33 },
100 { "SiS5582", PCI_DEVICE_ID_SI_5582, ATA_33 },
101 { "SiS5581", PCI_DEVICE_ID_SI_5581, ATA_33 },
102
103 { "SiS5596", PCI_DEVICE_ID_SI_5596, ATA_16 },
104 { "SiS5571", PCI_DEVICE_ID_SI_5571, ATA_16 },
105 { "SiS5517", PCI_DEVICE_ID_SI_5517, ATA_16 },
106 { "SiS551x", PCI_DEVICE_ID_SI_5511, ATA_16 },
107 };
108
109 /* Cycle time bits and values vary across chip dma capabilities
110 These three arrays hold the register layout and the values to set.
111 Indexed by chipset_family and (dma_mode - XFER_UDMA_0) */
112
113 /* {0, ATA_16, ATA_33, ATA_66, ATA_100a, ATA_100, ATA_133} */
114 static u8 cycle_time_offset[] = { 0, 0, 5, 4, 4, 0, 0 };
115 static u8 cycle_time_range[] = { 0, 0, 2, 3, 3, 4, 4 };
116 static u8 cycle_time_value[][XFER_UDMA_6 - XFER_UDMA_0 + 1] = {
117 { 0, 0, 0, 0, 0, 0, 0 }, /* no UDMA */
118 { 0, 0, 0, 0, 0, 0, 0 }, /* no UDMA */
119 { 3, 2, 1, 0, 0, 0, 0 }, /* ATA_33 */
120 { 7, 5, 3, 2, 1, 0, 0 }, /* ATA_66 */
121 { 7, 5, 3, 2, 1, 0, 0 }, /* ATA_100a (730 specific),
122 different cycle_time range and offset */
123 { 11, 7, 5, 4, 2, 1, 0 }, /* ATA_100 */
124 { 15, 10, 7, 5, 3, 2, 1 }, /* ATA_133a (earliest 691 southbridges) */
125 { 15, 10, 7, 5, 3, 2, 1 }, /* ATA_133 */
126 };
127 /* CRC Valid Setup Time vary across IDE clock setting 33/66/100/133
128 See SiS962 data sheet for more detail */
129 static u8 cvs_time_value[][XFER_UDMA_6 - XFER_UDMA_0 + 1] = {
130 { 0, 0, 0, 0, 0, 0, 0 }, /* no UDMA */
131 { 0, 0, 0, 0, 0, 0, 0 }, /* no UDMA */
132 { 2, 1, 1, 0, 0, 0, 0 },
133 { 4, 3, 2, 1, 0, 0, 0 },
134 { 4, 3, 2, 1, 0, 0, 0 },
135 { 6, 4, 3, 1, 1, 1, 0 },
136 { 9, 6, 4, 2, 2, 2, 2 },
137 { 9, 6, 4, 2, 2, 2, 2 },
138 };
139 /* Initialize time, Active time, Recovery time vary across
140 IDE clock settings. These 3 arrays hold the register value
141 for PIO0/1/2/3/4 and DMA0/1/2 mode in order */
142 static u8 ini_time_value[][8] = {
143 { 0, 0, 0, 0, 0, 0, 0, 0 },
144 { 0, 0, 0, 0, 0, 0, 0, 0 },
145 { 2, 1, 0, 0, 0, 1, 0, 0 },
146 { 4, 3, 1, 1, 1, 3, 1, 1 },
147 { 4, 3, 1, 1, 1, 3, 1, 1 },
148 { 6, 4, 2, 2, 2, 4, 2, 2 },
149 { 9, 6, 3, 3, 3, 6, 3, 3 },
150 { 9, 6, 3, 3, 3, 6, 3, 3 },
151 };
152 static u8 act_time_value[][8] = {
153 { 0, 0, 0, 0, 0, 0, 0, 0 },
154 { 0, 0, 0, 0, 0, 0, 0, 0 },
155 { 9, 9, 9, 2, 2, 7, 2, 2 },
156 { 19, 19, 19, 5, 4, 14, 5, 4 },
157 { 19, 19, 19, 5, 4, 14, 5, 4 },
158 { 28, 28, 28, 7, 6, 21, 7, 6 },
159 { 38, 38, 38, 10, 9, 28, 10, 9 },
160 { 38, 38, 38, 10, 9, 28, 10, 9 },
161 };
162 static u8 rco_time_value[][8] = {
163 { 0, 0, 0, 0, 0, 0, 0, 0 },
164 { 0, 0, 0, 0, 0, 0, 0, 0 },
165 { 9, 2, 0, 2, 0, 7, 1, 1 },
166 { 19, 5, 1, 5, 2, 16, 3, 2 },
167 { 19, 5, 1, 5, 2, 16, 3, 2 },
168 { 30, 9, 3, 9, 4, 25, 6, 4 },
169 { 40, 12, 4, 12, 5, 34, 12, 5 },
170 { 40, 12, 4, 12, 5, 34, 12, 5 },
171 };
172
173 /*
174 * Printing configuration
175 */
176 /* Used for chipset type printing at boot time */
177 static char *chipset_capability[] = {
178 "ATA", "ATA 16",
179 "ATA 33", "ATA 66",
180 "ATA 100 (1st gen)", "ATA 100 (2nd gen)",
181 "ATA 133 (1st gen)", "ATA 133 (2nd gen)"
182 };
183
184 /*
185 * Configuration functions
186 */
187
188 static u8 sis_ata133_get_base(ide_drive_t *drive)
189 {
190 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
191 u32 reg54 = 0;
192
193 pci_read_config_dword(dev, 0x54, &reg54);
194
195 return ((reg54 & 0x40000000) ? 0x70 : 0x40) + drive->dn * 4;
196 }
197
198 static void sis_ata16_program_timings(ide_drive_t *drive, const u8 mode)
199 {
200 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
201 u16 t1 = 0;
202 u8 drive_pci = 0x40 + drive->dn * 2;
203
204 const u16 pio_timings[] = { 0x000, 0x607, 0x404, 0x303, 0x301 };
205 const u16 mwdma_timings[] = { 0x008, 0x302, 0x301 };
206
207 pci_read_config_word(dev, drive_pci, &t1);
208
209 /* clear active/recovery timings */
210 t1 &= ~0x070f;
211 if (mode >= XFER_MW_DMA_0) {
212 if (chipset_family > ATA_16)
213 t1 &= ~0x8000; /* disable UDMA */
214 t1 |= mwdma_timings[mode - XFER_MW_DMA_0];
215 } else
216 t1 |= pio_timings[mode - XFER_PIO_0];
217
218 pci_write_config_word(dev, drive_pci, t1);
219 }
220
221 static void sis_ata100_program_timings(ide_drive_t *drive, const u8 mode)
222 {
223 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
224 u8 t1, drive_pci = 0x40 + drive->dn * 2;
225
226 /* timing bits: 7:4 active 3:0 recovery */
227 const u8 pio_timings[] = { 0x00, 0x67, 0x44, 0x33, 0x31 };
228 const u8 mwdma_timings[] = { 0x08, 0x32, 0x31 };
229
230 if (mode >= XFER_MW_DMA_0) {
231 u8 t2 = 0;
232
233 pci_read_config_byte(dev, drive_pci, &t2);
234 t2 &= ~0x80; /* disable UDMA */
235 pci_write_config_byte(dev, drive_pci, t2);
236
237 t1 = mwdma_timings[mode - XFER_MW_DMA_0];
238 } else
239 t1 = pio_timings[mode - XFER_PIO_0];
240
241 pci_write_config_byte(dev, drive_pci + 1, t1);
242 }
243
244 static void sis_ata133_program_timings(ide_drive_t *drive, const u8 mode)
245 {
246 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
247 u32 t1 = 0;
248 u8 drive_pci = sis_ata133_get_base(drive), clk, idx;
249
250 pci_read_config_dword(dev, drive_pci, &t1);
251
252 t1 &= 0xc0c00fff;
253 clk = (t1 & 0x08) ? ATA_133 : ATA_100;
254 if (mode >= XFER_MW_DMA_0) {
255 t1 &= ~0x04; /* disable UDMA */
256 idx = mode - XFER_MW_DMA_0 + 5;
257 } else
258 idx = mode - XFER_PIO_0;
259 t1 |= ini_time_value[clk][idx] << 12;
260 t1 |= act_time_value[clk][idx] << 16;
261 t1 |= rco_time_value[clk][idx] << 24;
262
263 pci_write_config_dword(dev, drive_pci, t1);
264 }
265
266 static void sis_program_timings(ide_drive_t *drive, const u8 mode)
267 {
268 if (chipset_family < ATA_100) /* ATA_16/33/66/100a */
269 sis_ata16_program_timings(drive, mode);
270 else if (chipset_family < ATA_133) /* ATA_100/133a */
271 sis_ata100_program_timings(drive, mode);
272 else /* ATA_133 */
273 sis_ata133_program_timings(drive, mode);
274 }
275
276 static void config_drive_art_rwp(ide_drive_t *drive)
277 {
278 ide_hwif_t *hwif = HWIF(drive);
279 struct pci_dev *dev = to_pci_dev(hwif->dev);
280 u8 reg4bh = 0;
281 u8 rw_prefetch = 0;
282
283 pci_read_config_byte(dev, 0x4b, &reg4bh);
284
285 if (drive->media == ide_disk)
286 rw_prefetch = 0x11 << drive->dn;
287
288 if ((reg4bh & (0x11 << drive->dn)) != rw_prefetch)
289 pci_write_config_byte(dev, 0x4b, reg4bh|rw_prefetch);
290 }
291
292 static void sis_set_pio_mode(ide_drive_t *drive, const u8 pio)
293 {
294 config_drive_art_rwp(drive);
295 sis_program_timings(drive, XFER_PIO_0 + pio);
296 }
297
298 static void sis_ata133_program_udma_timings(ide_drive_t *drive, const u8 mode)
299 {
300 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
301 u32 regdw = 0;
302 u8 drive_pci = sis_ata133_get_base(drive), clk, idx;
303
304 pci_read_config_dword(dev, drive_pci, &regdw);
305
306 regdw |= 0x04;
307 regdw &= 0xfffff00f;
308 /* check if ATA133 enable */
309 clk = (regdw & 0x08) ? ATA_133 : ATA_100;
310 idx = mode - XFER_UDMA_0;
311 regdw |= cycle_time_value[clk][idx] << 4;
312 regdw |= cvs_time_value[clk][idx] << 8;
313
314 pci_write_config_dword(dev, drive_pci, regdw);
315 }
316
317 static void sis_ata33_program_udma_timings(ide_drive_t *drive, const u8 mode)
318 {
319 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
320 u8 drive_pci = 0x40 + drive->dn * 2, reg = 0, i = chipset_family;
321
322 pci_read_config_byte(dev, drive_pci + 1, &reg);
323
324 /* force the UDMA bit on if we want to use UDMA */
325 reg |= 0x80;
326 /* clean reg cycle time bits */
327 reg &= ~((0xff >> (8 - cycle_time_range[i])) << cycle_time_offset[i]);
328 /* set reg cycle time bits */
329 reg |= cycle_time_value[i][mode - XFER_UDMA_0] << cycle_time_offset[i];
330
331 pci_write_config_byte(dev, drive_pci + 1, reg);
332 }
333
334 static void sis_program_udma_timings(ide_drive_t *drive, const u8 mode)
335 {
336 if (chipset_family >= ATA_133) /* ATA_133 */
337 sis_ata133_program_udma_timings(drive, mode);
338 else /* ATA_33/66/100a/100/133a */
339 sis_ata33_program_udma_timings(drive, mode);
340 }
341
342 static void sis_set_dma_mode(ide_drive_t *drive, const u8 speed)
343 {
344 if (speed >= XFER_UDMA_0)
345 sis_program_udma_timings(drive, speed);
346 else
347 sis_program_timings(drive, speed);
348 }
349
350 static u8 sis_ata133_udma_filter(ide_drive_t *drive)
351 {
352 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
353 u32 regdw = 0;
354 u8 drive_pci = sis_ata133_get_base(drive);
355
356 pci_read_config_dword(dev, drive_pci, &regdw);
357
358 /* if ATA133 disable, we should not set speed above UDMA5 */
359 return (regdw & 0x08) ? ATA_UDMA6 : ATA_UDMA5;
360 }
361
362 static int __devinit sis_find_family(struct pci_dev *dev)
363 {
364 struct pci_dev *host;
365 int i = 0;
366
367 chipset_family = 0;
368
369 for (i = 0; i < ARRAY_SIZE(SiSHostChipInfo) && !chipset_family; i++) {
370
371 host = pci_get_device(PCI_VENDOR_ID_SI, SiSHostChipInfo[i].host_id, NULL);
372
373 if (!host)
374 continue;
375
376 chipset_family = SiSHostChipInfo[i].chipset_family;
377
378 /* Special case for SiS630 : 630S/ET is ATA_100a */
379 if (SiSHostChipInfo[i].host_id == PCI_DEVICE_ID_SI_630) {
380 if (host->revision >= 0x30)
381 chipset_family = ATA_100a;
382 }
383 pci_dev_put(host);
384
385 printk(KERN_INFO "SIS5513: %s %s controller\n",
386 SiSHostChipInfo[i].name, chipset_capability[chipset_family]);
387 }
388
389 if (!chipset_family) { /* Belongs to pci-quirks */
390
391 u32 idemisc;
392 u16 trueid;
393
394 /* Disable ID masking and register remapping */
395 pci_read_config_dword(dev, 0x54, &idemisc);
396 pci_write_config_dword(dev, 0x54, (idemisc & 0x7fffffff));
397 pci_read_config_word(dev, PCI_DEVICE_ID, &trueid);
398 pci_write_config_dword(dev, 0x54, idemisc);
399
400 if (trueid == 0x5518) {
401 printk(KERN_INFO "SIS5513: SiS 962/963 MuTIOL IDE UDMA133 controller\n");
402 chipset_family = ATA_133;
403
404 /* Check for 5513 compability mapping
405 * We must use this, else the port enabled code will fail,
406 * as it expects the enablebits at 0x4a.
407 */
408 if ((idemisc & 0x40000000) == 0) {
409 pci_write_config_dword(dev, 0x54, idemisc | 0x40000000);
410 printk(KERN_INFO "SIS5513: Switching to 5513 register mapping\n");
411 }
412 }
413 }
414
415 if (!chipset_family) { /* Belongs to pci-quirks */
416
417 struct pci_dev *lpc_bridge;
418 u16 trueid;
419 u8 prefctl;
420 u8 idecfg;
421
422 pci_read_config_byte(dev, 0x4a, &idecfg);
423 pci_write_config_byte(dev, 0x4a, idecfg | 0x10);
424 pci_read_config_word(dev, PCI_DEVICE_ID, &trueid);
425 pci_write_config_byte(dev, 0x4a, idecfg);
426
427 if (trueid == 0x5517) { /* SiS 961/961B */
428
429 lpc_bridge = pci_get_slot(dev->bus, 0x10); /* Bus 0, Dev 2, Fn 0 */
430 pci_read_config_byte(dev, 0x49, &prefctl);
431 pci_dev_put(lpc_bridge);
432
433 if (lpc_bridge->revision == 0x10 && (prefctl & 0x80)) {
434 printk(KERN_INFO "SIS5513: SiS 961B MuTIOL IDE UDMA133 controller\n");
435 chipset_family = ATA_133a;
436 } else {
437 printk(KERN_INFO "SIS5513: SiS 961 MuTIOL IDE UDMA100 controller\n");
438 chipset_family = ATA_100;
439 }
440 }
441 }
442
443 return chipset_family;
444 }
445
446 static unsigned int __devinit init_chipset_sis5513(struct pci_dev *dev,
447 const char *name)
448 {
449 /* Make general config ops here
450 1/ tell IDE channels to operate in Compatibility mode only
451 2/ tell old chips to allow per drive IDE timings */
452
453 u8 reg;
454 u16 regw;
455
456 switch (chipset_family) {
457 case ATA_133:
458 /* SiS962 operation mode */
459 pci_read_config_word(dev, 0x50, &regw);
460 if (regw & 0x08)
461 pci_write_config_word(dev, 0x50, regw&0xfff7);
462 pci_read_config_word(dev, 0x52, &regw);
463 if (regw & 0x08)
464 pci_write_config_word(dev, 0x52, regw&0xfff7);
465 break;
466 case ATA_133a:
467 case ATA_100:
468 /* Fixup latency */
469 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x80);
470 /* Set compatibility bit */
471 pci_read_config_byte(dev, 0x49, &reg);
472 if (!(reg & 0x01))
473 pci_write_config_byte(dev, 0x49, reg|0x01);
474 break;
475 case ATA_100a:
476 case ATA_66:
477 /* Fixup latency */
478 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x10);
479
480 /* On ATA_66 chips the bit was elsewhere */
481 pci_read_config_byte(dev, 0x52, &reg);
482 if (!(reg & 0x04))
483 pci_write_config_byte(dev, 0x52, reg|0x04);
484 break;
485 case ATA_33:
486 /* On ATA_33 we didn't have a single bit to set */
487 pci_read_config_byte(dev, 0x09, &reg);
488 if ((reg & 0x0f) != 0x00)
489 pci_write_config_byte(dev, 0x09, reg&0xf0);
490 case ATA_16:
491 /* force per drive recovery and active timings
492 needed on ATA_33 and below chips */
493 pci_read_config_byte(dev, 0x52, &reg);
494 if (!(reg & 0x08))
495 pci_write_config_byte(dev, 0x52, reg|0x08);
496 break;
497 }
498
499 return 0;
500 }
501
502 struct sis_laptop {
503 u16 device;
504 u16 subvendor;
505 u16 subdevice;
506 };
507
508 static const struct sis_laptop sis_laptop[] = {
509 /* devid, subvendor, subdev */
510 { 0x5513, 0x1043, 0x1107 }, /* ASUS A6K */
511 { 0x5513, 0x1734, 0x105f }, /* FSC Amilo A1630 */
512 { 0x5513, 0x1071, 0x8640 }, /* EasyNote K5305 */
513 /* end marker */
514 { 0, }
515 };
516
517 static u8 __devinit sis_cable_detect(ide_hwif_t *hwif)
518 {
519 struct pci_dev *pdev = to_pci_dev(hwif->dev);
520 const struct sis_laptop *lap = &sis_laptop[0];
521 u8 ata66 = 0;
522
523 while (lap->device) {
524 if (lap->device == pdev->device &&
525 lap->subvendor == pdev->subsystem_vendor &&
526 lap->subdevice == pdev->subsystem_device)
527 return ATA_CBL_PATA40_SHORT;
528 lap++;
529 }
530
531 if (chipset_family >= ATA_133) {
532 u16 regw = 0;
533 u16 reg_addr = hwif->channel ? 0x52: 0x50;
534 pci_read_config_word(pdev, reg_addr, &regw);
535 ata66 = (regw & 0x8000) ? 0 : 1;
536 } else if (chipset_family >= ATA_66) {
537 u8 reg48h = 0;
538 u8 mask = hwif->channel ? 0x20 : 0x10;
539 pci_read_config_byte(pdev, 0x48, &reg48h);
540 ata66 = (reg48h & mask) ? 0 : 1;
541 }
542
543 return ata66 ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
544 }
545
546 static const struct ide_port_ops sis_port_ops = {
547 .set_pio_mode = sis_set_pio_mode,
548 .set_dma_mode = sis_set_dma_mode,
549 .cable_detect = sis_cable_detect,
550 };
551
552 static const struct ide_port_ops sis_ata133_port_ops = {
553 .set_pio_mode = sis_set_pio_mode,
554 .set_dma_mode = sis_set_dma_mode,
555 .udma_filter = sis_ata133_udma_filter,
556 .cable_detect = sis_cable_detect,
557 };
558
559 static const struct ide_port_info sis5513_chipset __devinitdata = {
560 .name = "SIS5513",
561 .init_chipset = init_chipset_sis5513,
562 .enablebits = { {0x4a, 0x02, 0x02}, {0x4a, 0x04, 0x04} },
563 .host_flags = IDE_HFLAG_LEGACY_IRQS | IDE_HFLAG_NO_AUTODMA,
564 .pio_mask = ATA_PIO4,
565 .mwdma_mask = ATA_MWDMA2,
566 };
567
568 static int __devinit sis5513_init_one(struct pci_dev *dev, const struct pci_device_id *id)
569 {
570 struct ide_port_info d = sis5513_chipset;
571 u8 udma_rates[] = { 0x00, 0x00, 0x07, 0x1f, 0x3f, 0x3f, 0x7f, 0x7f };
572
573 if (sis_find_family(dev) == 0)
574 return -ENOTSUPP;
575
576 if (chipset_family >= ATA_133)
577 d.port_ops = &sis_ata133_port_ops;
578 else
579 d.port_ops = &sis_port_ops;
580
581 d.udma_mask = udma_rates[chipset_family];
582
583 return ide_setup_pci_device(dev, &d);
584 }
585
586 static const struct pci_device_id sis5513_pci_tbl[] = {
587 { PCI_VDEVICE(SI, PCI_DEVICE_ID_SI_5513), 0 },
588 { PCI_VDEVICE(SI, PCI_DEVICE_ID_SI_5518), 0 },
589 { PCI_VDEVICE(SI, PCI_DEVICE_ID_SI_1180), 0 },
590 { 0, },
591 };
592 MODULE_DEVICE_TABLE(pci, sis5513_pci_tbl);
593
594 static struct pci_driver driver = {
595 .name = "SIS_IDE",
596 .id_table = sis5513_pci_tbl,
597 .probe = sis5513_init_one,
598 };
599
600 static int __init sis5513_ide_init(void)
601 {
602 return ide_pci_register_driver(&driver);
603 }
604
605 module_init(sis5513_ide_init);
606
607 MODULE_AUTHOR("Lionel Bouton, L C Chang, Andre Hedrick, Vojtech Pavlik");
608 MODULE_DESCRIPTION("PCI driver module for SIS IDE");
609 MODULE_LICENSE("GPL");
610
611 /*
612 * TODO:
613 * - CLEANUP
614 * - Use drivers/ide/ide-timing.h !
615 * - More checks in the config registers (force values instead of
616 * relying on the BIOS setting them correctly).
617 * - Further optimisations ?
618 * . for example ATA66+ regs 0x48 & 0x4A
619 */
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