| blob | 8928ca4a932569d78ee1b75c122790f4a696408d |
1 /*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2006 Cisco Systems. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 *
34 * $Id: mthca_cmd.h 1349 2004-12-16 21:09:43Z roland $
35 */
37 #ifndef MTHCA_CMD_H
38 #define MTHCA_CMD_H
40 #include <rdma/ib_verbs.h>
42 #define MTHCA_MAILBOX_SIZE 4096
45 /* command completed successfully: */
47 /* Internal error (such as a bus error) occurred while processing command: */
49 /* Operation/command not supported or opcode modifier not supported: */
51 /* Parameter not supported or parameter out of range: */
53 /* System not enabled or bad system state: */
55 /* Attempt to access reserved or unallocaterd resource: */
57 /* Requested resource is currently executing a command, or is otherwise busy: */
59 /* memory error: */
61 /* Required capability exceeds device limits: */
63 /* Resource is not in the appropriate state or ownership: */
65 /* Index out of range: */
67 /* FW image corrupted: */
69 /* Attempt to modify a QP/EE which is not in the presumed state: */
71 /* Bad segment parameters (Address/Size): */
73 /* Memory Region has Memory Windows bound to: */
75 /* HCA local attached memory not present: */
77 /* Bad management packet (silently discarded): */
79 /* More outstanding CQEs in CQ than new CQ size: */
81 };
85 MTHCA_TRANS_RST2INIT,
86 MTHCA_TRANS_INIT2INIT,
87 MTHCA_TRANS_INIT2RTR,
88 MTHCA_TRANS_RTR2RTS,
89 MTHCA_TRANS_RTS2RTS,
90 MTHCA_TRANS_SQERR2RTS,
91 MTHCA_TRANS_ANY2ERR,
92 MTHCA_TRANS_RTS2SQD,
93 MTHCA_TRANS_SQD2SQD,
94 MTHCA_TRANS_SQD2RTS,
95 MTHCA_TRANS_ANY2RST,
96 };
115 };
118 dma_addr_t dma;
120 };
150 u16 stat_rate_support;
152 u32 flags;
181 u8 bmme_flags;
182 u32 reserved_lkey;
184 u64 max_icm_sz;
187 };
190 u32 vendor_id;
191 u32 device_id;
192 u32 revision_id;
194 u8 inta_pin;
195 };
198 u64 qpc_base;
199 u64 eec_base;
200 u64 srqc_base;
201 u64 cqc_base;
202 u64 eqpc_base;
203 u64 eeec_base;
204 u64 eqc_base;
205 u64 rdb_base;
206 u64 mc_base;
207 u64 mpt_base;
208 u64 mtt_base;
209 u64 uar_scratch_base;
210 u64 uarc_base;
211 u16 log_mc_entry_sz;
212 u16 mc_hash_sz;
213 u8 log_num_qps;
214 u8 log_num_eecs;
215 u8 log_num_srqs;
216 u8 log_num_cqs;
217 u8 log_num_eqs;
218 u8 log_mc_table_sz;
219 u8 mtt_seg_sz;
220 u8 log_mpt_sz;
221 u8 log_uar_sz;
222 u8 log_uarc_sz;
223 };
229 u16 gid_cap;
230 u16 pkey_cap;
232 u64 guid0;
234 u64 node_guid;
236 u64 si_guid;
237 };
242 u64 si_guid;
243 u32 cap_mask;
244 };
254 gfp_t gfp_mask);