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ia64/kvm: compilation fix. export account_system_vtime.
[pv_ops_mirror.git] / drivers / infiniband / hw / nes / nes_hw.h
blob745bf94f3f074283f9c6f9dc36547f976d64883e
1 /*
2 * Copyright (c) 2006 - 2008 NetEffect, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef __NES_HW_H
34 #define __NES_HW_H
35
36 #include <linux/inet_lro.h>
37
38 #define NES_PHY_TYPE_1G 2
39 #define NES_PHY_TYPE_IRIS 3
40 #define NES_PHY_TYPE_ARGUS 4
41 #define NES_PHY_TYPE_PUMA_1G 5
42 #define NES_PHY_TYPE_PUMA_10G 6
43
44 #define NES_MULTICAST_PF_MAX 8
45
46 enum pci_regs {
47 NES_INT_STAT = 0x0000,
48 NES_INT_MASK = 0x0004,
49 NES_INT_PENDING = 0x0008,
50 NES_INTF_INT_STAT = 0x000C,
51 NES_INTF_INT_MASK = 0x0010,
52 NES_TIMER_STAT = 0x0014,
53 NES_PERIODIC_CONTROL = 0x0018,
54 NES_ONE_SHOT_CONTROL = 0x001C,
55 NES_EEPROM_COMMAND = 0x0020,
56 NES_EEPROM_DATA = 0x0024,
57 NES_FLASH_COMMAND = 0x0028,
58 NES_FLASH_DATA = 0x002C,
59 NES_SOFTWARE_RESET = 0x0030,
60 NES_CQ_ACK = 0x0034,
61 NES_WQE_ALLOC = 0x0040,
62 NES_CQE_ALLOC = 0x0044,
63 };
64
65 enum indexed_regs {
66 NES_IDX_CREATE_CQP_LOW = 0x0000,
67 NES_IDX_CREATE_CQP_HIGH = 0x0004,
68 NES_IDX_QP_CONTROL = 0x0040,
69 NES_IDX_FLM_CONTROL = 0x0080,
70 NES_IDX_INT_CPU_STATUS = 0x00a0,
71 NES_IDX_GPIO_CONTROL = 0x00f0,
72 NES_IDX_GPIO_DATA = 0x00f4,
73 NES_IDX_TCP_CONFIG0 = 0x01e4,
74 NES_IDX_TCP_TIMER_CONFIG = 0x01ec,
75 NES_IDX_TCP_NOW = 0x01f0,
76 NES_IDX_QP_MAX_CFG_SIZES = 0x0200,
77 NES_IDX_QP_CTX_SIZE = 0x0218,
78 NES_IDX_TCP_TIMER_SIZE0 = 0x0238,
79 NES_IDX_TCP_TIMER_SIZE1 = 0x0240,
80 NES_IDX_ARP_CACHE_SIZE = 0x0258,
81 NES_IDX_CQ_CTX_SIZE = 0x0260,
82 NES_IDX_MRT_SIZE = 0x0278,
83 NES_IDX_PBL_REGION_SIZE = 0x0280,
84 NES_IDX_IRRQ_COUNT = 0x02b0,
85 NES_IDX_RX_WINDOW_BUFFER_PAGE_TABLE_SIZE = 0x02f0,
86 NES_IDX_RX_WINDOW_BUFFER_SIZE = 0x0300,
87 NES_IDX_DST_IP_ADDR = 0x0400,
88 NES_IDX_PCIX_DIAG = 0x08e8,
89 NES_IDX_MPP_DEBUG = 0x0a00,
90 NES_IDX_PORT_RX_DISCARDS = 0x0a30,
91 NES_IDX_PORT_TX_DISCARDS = 0x0a34,
92 NES_IDX_MPP_LB_DEBUG = 0x0b00,
93 NES_IDX_DENALI_CTL_22 = 0x1058,
94 NES_IDX_MAC_TX_CONTROL = 0x2000,
95 NES_IDX_MAC_TX_CONFIG = 0x2004,
96 NES_IDX_MAC_TX_PAUSE_QUANTA = 0x2008,
97 NES_IDX_MAC_RX_CONTROL = 0x200c,
98 NES_IDX_MAC_RX_CONFIG = 0x2010,
99 NES_IDX_MAC_EXACT_MATCH_BOTTOM = 0x201c,
100 NES_IDX_MAC_MDIO_CONTROL = 0x2084,
101 NES_IDX_MAC_TX_OCTETS_LOW = 0x2100,
102 NES_IDX_MAC_TX_OCTETS_HIGH = 0x2104,
103 NES_IDX_MAC_TX_FRAMES_LOW = 0x2108,
104 NES_IDX_MAC_TX_FRAMES_HIGH = 0x210c,
105 NES_IDX_MAC_TX_PAUSE_FRAMES = 0x2118,
106 NES_IDX_MAC_TX_ERRORS = 0x2138,
107 NES_IDX_MAC_RX_OCTETS_LOW = 0x213c,
108 NES_IDX_MAC_RX_OCTETS_HIGH = 0x2140,
109 NES_IDX_MAC_RX_FRAMES_LOW = 0x2144,
110 NES_IDX_MAC_RX_FRAMES_HIGH = 0x2148,
111 NES_IDX_MAC_RX_BC_FRAMES_LOW = 0x214c,
112 NES_IDX_MAC_RX_MC_FRAMES_HIGH = 0x2150,
113 NES_IDX_MAC_RX_PAUSE_FRAMES = 0x2154,
114 NES_IDX_MAC_RX_SHORT_FRAMES = 0x2174,
115 NES_IDX_MAC_RX_OVERSIZED_FRAMES = 0x2178,
116 NES_IDX_MAC_RX_JABBER_FRAMES = 0x217c,
117 NES_IDX_MAC_RX_CRC_ERR_FRAMES = 0x2180,
118 NES_IDX_MAC_RX_LENGTH_ERR_FRAMES = 0x2184,
119 NES_IDX_MAC_RX_SYMBOL_ERR_FRAMES = 0x2188,
120 NES_IDX_MAC_INT_STATUS = 0x21f0,
121 NES_IDX_MAC_INT_MASK = 0x21f4,
122 NES_IDX_PHY_PCS_CONTROL_STATUS0 = 0x2800,
123 NES_IDX_PHY_PCS_CONTROL_STATUS1 = 0x2a00,
124 NES_IDX_ETH_SERDES_COMMON_CONTROL0 = 0x2808,
125 NES_IDX_ETH_SERDES_COMMON_CONTROL1 = 0x2a08,
126 NES_IDX_ETH_SERDES_COMMON_STATUS0 = 0x280c,
127 NES_IDX_ETH_SERDES_COMMON_STATUS1 = 0x2a0c,
128 NES_IDX_ETH_SERDES_TX_EMP0 = 0x2810,
129 NES_IDX_ETH_SERDES_TX_EMP1 = 0x2a10,
130 NES_IDX_ETH_SERDES_TX_DRIVE0 = 0x2814,
131 NES_IDX_ETH_SERDES_TX_DRIVE1 = 0x2a14,
132 NES_IDX_ETH_SERDES_RX_MODE0 = 0x2818,
133 NES_IDX_ETH_SERDES_RX_MODE1 = 0x2a18,
134 NES_IDX_ETH_SERDES_RX_SIGDET0 = 0x281c,
135 NES_IDX_ETH_SERDES_RX_SIGDET1 = 0x2a1c,
136 NES_IDX_ETH_SERDES_BYPASS0 = 0x2820,
137 NES_IDX_ETH_SERDES_BYPASS1 = 0x2a20,
138 NES_IDX_ETH_SERDES_LOOPBACK_CONTROL0 = 0x2824,
139 NES_IDX_ETH_SERDES_LOOPBACK_CONTROL1 = 0x2a24,
140 NES_IDX_ETH_SERDES_RX_EQ_CONTROL0 = 0x2828,
141 NES_IDX_ETH_SERDES_RX_EQ_CONTROL1 = 0x2a28,
142 NES_IDX_ETH_SERDES_RX_EQ_STATUS0 = 0x282c,
143 NES_IDX_ETH_SERDES_RX_EQ_STATUS1 = 0x2a2c,
144 NES_IDX_ETH_SERDES_CDR_RESET0 = 0x2830,
145 NES_IDX_ETH_SERDES_CDR_RESET1 = 0x2a30,
146 NES_IDX_ETH_SERDES_CDR_CONTROL0 = 0x2834,
147 NES_IDX_ETH_SERDES_CDR_CONTROL1 = 0x2a34,
148 NES_IDX_ETH_SERDES_TX_HIGHZ_LANE_MODE0 = 0x2838,
149 NES_IDX_ETH_SERDES_TX_HIGHZ_LANE_MODE1 = 0x2a38,
150 NES_IDX_ENDNODE0_NSTAT_RX_DISCARD = 0x3080,
151 NES_IDX_ENDNODE0_NSTAT_RX_OCTETS_LO = 0x3000,
152 NES_IDX_ENDNODE0_NSTAT_RX_OCTETS_HI = 0x3004,
153 NES_IDX_ENDNODE0_NSTAT_RX_FRAMES_LO = 0x3008,
154 NES_IDX_ENDNODE0_NSTAT_RX_FRAMES_HI = 0x300c,
155 NES_IDX_ENDNODE0_NSTAT_TX_OCTETS_LO = 0x7000,
156 NES_IDX_ENDNODE0_NSTAT_TX_OCTETS_HI = 0x7004,
157 NES_IDX_ENDNODE0_NSTAT_TX_FRAMES_LO = 0x7008,
158 NES_IDX_ENDNODE0_NSTAT_TX_FRAMES_HI = 0x700c,
159 NES_IDX_CM_CONFIG = 0x5100,
160 NES_IDX_NIC_LOGPORT_TO_PHYPORT = 0x6000,
161 NES_IDX_NIC_PHYPORT_TO_USW = 0x6008,
162 NES_IDX_NIC_ACTIVE = 0x6010,
163 NES_IDX_NIC_UNICAST_ALL = 0x6018,
164 NES_IDX_NIC_MULTICAST_ALL = 0x6020,
165 NES_IDX_NIC_MULTICAST_ENABLE = 0x6028,
166 NES_IDX_NIC_BROADCAST_ON = 0x6030,
167 NES_IDX_USED_CHUNKS_TX = 0x60b0,
168 NES_IDX_TX_POOL_SIZE = 0x60b8,
169 NES_IDX_QUAD_HASH_TABLE_SIZE = 0x6148,
170 NES_IDX_PERFECT_FILTER_LOW = 0x6200,
171 NES_IDX_PERFECT_FILTER_HIGH = 0x6204,
172 NES_IDX_IPV4_TCP_REXMITS = 0x7080,
173 NES_IDX_DEBUG_ERROR_CONTROL_STATUS = 0x913c,
174 NES_IDX_DEBUG_ERROR_MASKS0 = 0x9140,
175 NES_IDX_DEBUG_ERROR_MASKS1 = 0x9144,
176 NES_IDX_DEBUG_ERROR_MASKS2 = 0x9148,
177 NES_IDX_DEBUG_ERROR_MASKS3 = 0x914c,
178 NES_IDX_DEBUG_ERROR_MASKS4 = 0x9150,
179 NES_IDX_DEBUG_ERROR_MASKS5 = 0x9154,
180 };
181
182 #define NES_IDX_MAC_TX_CONFIG_ENABLE_PAUSE 1
183 #define NES_IDX_MPP_DEBUG_PORT_DISABLE_PAUSE (1 << 17)
184
185 enum nes_cqp_opcodes {
186 NES_CQP_CREATE_QP = 0x00,
187 NES_CQP_MODIFY_QP = 0x01,
188 NES_CQP_DESTROY_QP = 0x02,
189 NES_CQP_CREATE_CQ = 0x03,
190 NES_CQP_MODIFY_CQ = 0x04,
191 NES_CQP_DESTROY_CQ = 0x05,
192 NES_CQP_ALLOCATE_STAG = 0x09,
193 NES_CQP_REGISTER_STAG = 0x0a,
194 NES_CQP_QUERY_STAG = 0x0b,
195 NES_CQP_REGISTER_SHARED_STAG = 0x0c,
196 NES_CQP_DEALLOCATE_STAG = 0x0d,
197 NES_CQP_MANAGE_ARP_CACHE = 0x0f,
198 NES_CQP_SUSPEND_QPS = 0x11,
199 NES_CQP_UPLOAD_CONTEXT = 0x13,
200 NES_CQP_CREATE_CEQ = 0x16,
201 NES_CQP_DESTROY_CEQ = 0x18,
202 NES_CQP_CREATE_AEQ = 0x19,
203 NES_CQP_DESTROY_AEQ = 0x1b,
204 NES_CQP_LMI_ACCESS = 0x20,
205 NES_CQP_FLUSH_WQES = 0x22,
206 NES_CQP_MANAGE_APBVT = 0x23
207 };
208
209 enum nes_cqp_wqe_word_idx {
210 NES_CQP_WQE_OPCODE_IDX = 0,
211 NES_CQP_WQE_ID_IDX = 1,
212 NES_CQP_WQE_COMP_CTX_LOW_IDX = 2,
213 NES_CQP_WQE_COMP_CTX_HIGH_IDX = 3,
214 NES_CQP_WQE_COMP_SCRATCH_LOW_IDX = 4,
215 NES_CQP_WQE_COMP_SCRATCH_HIGH_IDX = 5,
216 };
217
218 enum nes_cqp_cq_wqeword_idx {
219 NES_CQP_CQ_WQE_PBL_LOW_IDX = 6,
220 NES_CQP_CQ_WQE_PBL_HIGH_IDX = 7,
221 NES_CQP_CQ_WQE_CQ_CONTEXT_LOW_IDX = 8,
222 NES_CQP_CQ_WQE_CQ_CONTEXT_HIGH_IDX = 9,
223 NES_CQP_CQ_WQE_DOORBELL_INDEX_HIGH_IDX = 10,
224 };
225
226 enum nes_cqp_stag_wqeword_idx {
227 NES_CQP_STAG_WQE_PBL_BLK_COUNT_IDX = 1,
228 NES_CQP_STAG_WQE_LEN_HIGH_PD_IDX = 6,
229 NES_CQP_STAG_WQE_LEN_LOW_IDX = 7,
230 NES_CQP_STAG_WQE_STAG_IDX = 8,
231 NES_CQP_STAG_WQE_VA_LOW_IDX = 10,
232 NES_CQP_STAG_WQE_VA_HIGH_IDX = 11,
233 NES_CQP_STAG_WQE_PA_LOW_IDX = 12,
234 NES_CQP_STAG_WQE_PA_HIGH_IDX = 13,
235 NES_CQP_STAG_WQE_PBL_LEN_IDX = 14
236 };
237
238 #define NES_CQP_OP_IWARP_STATE_SHIFT 28
239
240 enum nes_cqp_qp_bits {
241 NES_CQP_QP_ARP_VALID = (1<<8),
242 NES_CQP_QP_WINBUF_VALID = (1<<9),
243 NES_CQP_QP_CONTEXT_VALID = (1<<10),
244 NES_CQP_QP_ORD_VALID = (1<<11),
245 NES_CQP_QP_WINBUF_DATAIND_EN = (1<<12),
246 NES_CQP_QP_VIRT_WQS = (1<<13),
247 NES_CQP_QP_DEL_HTE = (1<<14),
248 NES_CQP_QP_CQS_VALID = (1<<15),
249 NES_CQP_QP_TYPE_TSA = 0,
250 NES_CQP_QP_TYPE_IWARP = (1<<16),
251 NES_CQP_QP_TYPE_CQP = (4<<16),
252 NES_CQP_QP_TYPE_NIC = (5<<16),
253 NES_CQP_QP_MSS_CHG = (1<<20),
254 NES_CQP_QP_STATIC_RESOURCES = (1<<21),
255 NES_CQP_QP_IGNORE_MW_BOUND = (1<<22),
256 NES_CQP_QP_VWQ_USE_LMI = (1<<23),
257 NES_CQP_QP_IWARP_STATE_IDLE = (1<<NES_CQP_OP_IWARP_STATE_SHIFT),
258 NES_CQP_QP_IWARP_STATE_RTS = (2<<NES_CQP_OP_IWARP_STATE_SHIFT),
259 NES_CQP_QP_IWARP_STATE_CLOSING = (3<<NES_CQP_OP_IWARP_STATE_SHIFT),
260 NES_CQP_QP_IWARP_STATE_TERMINATE = (5<<NES_CQP_OP_IWARP_STATE_SHIFT),
261 NES_CQP_QP_IWARP_STATE_ERROR = (6<<NES_CQP_OP_IWARP_STATE_SHIFT),
262 NES_CQP_QP_IWARP_STATE_MASK = (7<<NES_CQP_OP_IWARP_STATE_SHIFT),
263 NES_CQP_QP_RESET = (1<<31),
264 };
265
266 enum nes_cqp_qp_wqe_word_idx {
267 NES_CQP_QP_WQE_CONTEXT_LOW_IDX = 6,
268 NES_CQP_QP_WQE_CONTEXT_HIGH_IDX = 7,
269 NES_CQP_QP_WQE_NEW_MSS_IDX = 15,
270 };
271
272 enum nes_nic_ctx_bits {
273 NES_NIC_CTX_RQ_SIZE_32 = (3<<8),
274 NES_NIC_CTX_RQ_SIZE_512 = (3<<8),
275 NES_NIC_CTX_SQ_SIZE_32 = (1<<10),
276 NES_NIC_CTX_SQ_SIZE_512 = (3<<10),
277 };
278
279 enum nes_nic_qp_ctx_word_idx {
280 NES_NIC_CTX_MISC_IDX = 0,
281 NES_NIC_CTX_SQ_LOW_IDX = 2,
282 NES_NIC_CTX_SQ_HIGH_IDX = 3,
283 NES_NIC_CTX_RQ_LOW_IDX = 4,
284 NES_NIC_CTX_RQ_HIGH_IDX = 5,
285 };
286
287 enum nes_cqp_cq_bits {
288 NES_CQP_CQ_CEQE_MASK = (1<<9),
289 NES_CQP_CQ_CEQ_VALID = (1<<10),
290 NES_CQP_CQ_RESIZE = (1<<11),
291 NES_CQP_CQ_CHK_OVERFLOW = (1<<12),
292 NES_CQP_CQ_4KB_CHUNK = (1<<14),
293 NES_CQP_CQ_VIRT = (1<<15),
294 };
295
296 enum nes_cqp_stag_bits {
297 NES_CQP_STAG_VA_TO = (1<<9),
298 NES_CQP_STAG_DEALLOC_PBLS = (1<<10),
299 NES_CQP_STAG_PBL_BLK_SIZE = (1<<11),
300 NES_CQP_STAG_MR = (1<<13),
301 NES_CQP_STAG_RIGHTS_LOCAL_READ = (1<<16),
302 NES_CQP_STAG_RIGHTS_LOCAL_WRITE = (1<<17),
303 NES_CQP_STAG_RIGHTS_REMOTE_READ = (1<<18),
304 NES_CQP_STAG_RIGHTS_REMOTE_WRITE = (1<<19),
305 NES_CQP_STAG_RIGHTS_WINDOW_BIND = (1<<20),
306 NES_CQP_STAG_REM_ACC_EN = (1<<21),
307 NES_CQP_STAG_LEAVE_PENDING = (1<<31),
308 };
309
310 enum nes_cqp_ceq_wqeword_idx {
311 NES_CQP_CEQ_WQE_ELEMENT_COUNT_IDX = 1,
312 NES_CQP_CEQ_WQE_PBL_LOW_IDX = 6,
313 NES_CQP_CEQ_WQE_PBL_HIGH_IDX = 7,
314 };
315
316 enum nes_cqp_ceq_bits {
317 NES_CQP_CEQ_4KB_CHUNK = (1<<14),
318 NES_CQP_CEQ_VIRT = (1<<15),
319 };
320
321 enum nes_cqp_aeq_wqeword_idx {
322 NES_CQP_AEQ_WQE_ELEMENT_COUNT_IDX = 1,
323 NES_CQP_AEQ_WQE_PBL_LOW_IDX = 6,
324 NES_CQP_AEQ_WQE_PBL_HIGH_IDX = 7,
325 };
326
327 enum nes_cqp_aeq_bits {
328 NES_CQP_AEQ_4KB_CHUNK = (1<<14),
329 NES_CQP_AEQ_VIRT = (1<<15),
330 };
331
332 enum nes_cqp_lmi_wqeword_idx {
333 NES_CQP_LMI_WQE_LMI_OFFSET_IDX = 1,
334 NES_CQP_LMI_WQE_FRAG_LOW_IDX = 8,
335 NES_CQP_LMI_WQE_FRAG_HIGH_IDX = 9,
336 NES_CQP_LMI_WQE_FRAG_LEN_IDX = 10,
337 };
338
339 enum nes_cqp_arp_wqeword_idx {
340 NES_CQP_ARP_WQE_MAC_ADDR_LOW_IDX = 6,
341 NES_CQP_ARP_WQE_MAC_HIGH_IDX = 7,
342 NES_CQP_ARP_WQE_REACHABILITY_MAX_IDX = 1,
343 };
344
345 enum nes_cqp_upload_wqeword_idx {
346 NES_CQP_UPLOAD_WQE_CTXT_LOW_IDX = 6,
347 NES_CQP_UPLOAD_WQE_CTXT_HIGH_IDX = 7,
348 NES_CQP_UPLOAD_WQE_HTE_IDX = 8,
349 };
350
351 enum nes_cqp_arp_bits {
352 NES_CQP_ARP_VALID = (1<<8),
353 NES_CQP_ARP_PERM = (1<<9),
354 };
355
356 enum nes_cqp_flush_bits {
357 NES_CQP_FLUSH_SQ = (1<<30),
358 NES_CQP_FLUSH_RQ = (1<<31),
359 };
360
361 enum nes_cqe_opcode_bits {
362 NES_CQE_STAG_VALID = (1<<6),
363 NES_CQE_ERROR = (1<<7),
364 NES_CQE_SQ = (1<<8),
365 NES_CQE_SE = (1<<9),
366 NES_CQE_PSH = (1<<29),
367 NES_CQE_FIN = (1<<30),
368 NES_CQE_VALID = (1<<31),
369 };
370
371
372 enum nes_cqe_word_idx {
373 NES_CQE_PAYLOAD_LENGTH_IDX = 0,
374 NES_CQE_COMP_COMP_CTX_LOW_IDX = 2,
375 NES_CQE_COMP_COMP_CTX_HIGH_IDX = 3,
376 NES_CQE_INV_STAG_IDX = 4,
377 NES_CQE_QP_ID_IDX = 5,
378 NES_CQE_ERROR_CODE_IDX = 6,
379 NES_CQE_OPCODE_IDX = 7,
380 };
381
382 enum nes_ceqe_word_idx {
383 NES_CEQE_CQ_CTX_LOW_IDX = 0,
384 NES_CEQE_CQ_CTX_HIGH_IDX = 1,
385 };
386
387 enum nes_ceqe_status_bit {
388 NES_CEQE_VALID = (1<<31),
389 };
390
391 enum nes_int_bits {
392 NES_INT_CEQ0 = (1<<0),
393 NES_INT_CEQ1 = (1<<1),
394 NES_INT_CEQ2 = (1<<2),
395 NES_INT_CEQ3 = (1<<3),
396 NES_INT_CEQ4 = (1<<4),
397 NES_INT_CEQ5 = (1<<5),
398 NES_INT_CEQ6 = (1<<6),
399 NES_INT_CEQ7 = (1<<7),
400 NES_INT_CEQ8 = (1<<8),
401 NES_INT_CEQ9 = (1<<9),
402 NES_INT_CEQ10 = (1<<10),
403 NES_INT_CEQ11 = (1<<11),
404 NES_INT_CEQ12 = (1<<12),
405 NES_INT_CEQ13 = (1<<13),
406 NES_INT_CEQ14 = (1<<14),
407 NES_INT_CEQ15 = (1<<15),
408 NES_INT_AEQ0 = (1<<16),
409 NES_INT_AEQ1 = (1<<17),
410 NES_INT_AEQ2 = (1<<18),
411 NES_INT_AEQ3 = (1<<19),
412 NES_INT_AEQ4 = (1<<20),
413 NES_INT_AEQ5 = (1<<21),
414 NES_INT_AEQ6 = (1<<22),
415 NES_INT_AEQ7 = (1<<23),
416 NES_INT_MAC0 = (1<<24),
417 NES_INT_MAC1 = (1<<25),
418 NES_INT_MAC2 = (1<<26),
419 NES_INT_MAC3 = (1<<27),
420 NES_INT_TSW = (1<<28),
421 NES_INT_TIMER = (1<<29),
422 NES_INT_INTF = (1<<30),
423 };
424
425 enum nes_intf_int_bits {
426 NES_INTF_INT_PCIERR = (1<<0),
427 NES_INTF_PERIODIC_TIMER = (1<<2),
428 NES_INTF_ONE_SHOT_TIMER = (1<<3),
429 NES_INTF_INT_CRITERR = (1<<14),
430 NES_INTF_INT_AEQ0_OFLOW = (1<<16),
431 NES_INTF_INT_AEQ1_OFLOW = (1<<17),
432 NES_INTF_INT_AEQ2_OFLOW = (1<<18),
433 NES_INTF_INT_AEQ3_OFLOW = (1<<19),
434 NES_INTF_INT_AEQ4_OFLOW = (1<<20),
435 NES_INTF_INT_AEQ5_OFLOW = (1<<21),
436 NES_INTF_INT_AEQ6_OFLOW = (1<<22),
437 NES_INTF_INT_AEQ7_OFLOW = (1<<23),
438 NES_INTF_INT_AEQ_OFLOW = (0xff<<16),
439 };
440
441 enum nes_mac_int_bits {
442 NES_MAC_INT_LINK_STAT_CHG = (1<<1),
443 NES_MAC_INT_XGMII_EXT = (1<<2),
444 NES_MAC_INT_TX_UNDERFLOW = (1<<6),
445 NES_MAC_INT_TX_ERROR = (1<<7),
446 };
447
448 enum nes_cqe_allocate_bits {
449 NES_CQE_ALLOC_INC_SELECT = (1<<28),
450 NES_CQE_ALLOC_NOTIFY_NEXT = (1<<29),
451 NES_CQE_ALLOC_NOTIFY_SE = (1<<30),
452 NES_CQE_ALLOC_RESET = (1<<31),
453 };
454
455 enum nes_nic_rq_wqe_word_idx {
456 NES_NIC_RQ_WQE_LENGTH_1_0_IDX = 0,
457 NES_NIC_RQ_WQE_LENGTH_3_2_IDX = 1,
458 NES_NIC_RQ_WQE_FRAG0_LOW_IDX = 2,
459 NES_NIC_RQ_WQE_FRAG0_HIGH_IDX = 3,
460 NES_NIC_RQ_WQE_FRAG1_LOW_IDX = 4,
461 NES_NIC_RQ_WQE_FRAG1_HIGH_IDX = 5,
462 NES_NIC_RQ_WQE_FRAG2_LOW_IDX = 6,
463 NES_NIC_RQ_WQE_FRAG2_HIGH_IDX = 7,
464 NES_NIC_RQ_WQE_FRAG3_LOW_IDX = 8,
465 NES_NIC_RQ_WQE_FRAG3_HIGH_IDX = 9,
466 };
467
468 enum nes_nic_sq_wqe_word_idx {
469 NES_NIC_SQ_WQE_MISC_IDX = 0,
470 NES_NIC_SQ_WQE_TOTAL_LENGTH_IDX = 1,
471 NES_NIC_SQ_WQE_LSO_INFO_IDX = 2,
472 NES_NIC_SQ_WQE_LENGTH_0_TAG_IDX = 3,
473 NES_NIC_SQ_WQE_LENGTH_2_1_IDX = 4,
474 NES_NIC_SQ_WQE_LENGTH_4_3_IDX = 5,
475 NES_NIC_SQ_WQE_FRAG0_LOW_IDX = 6,
476 NES_NIC_SQ_WQE_FRAG0_HIGH_IDX = 7,
477 NES_NIC_SQ_WQE_FRAG1_LOW_IDX = 8,
478 NES_NIC_SQ_WQE_FRAG1_HIGH_IDX = 9,
479 NES_NIC_SQ_WQE_FRAG2_LOW_IDX = 10,
480 NES_NIC_SQ_WQE_FRAG2_HIGH_IDX = 11,
481 NES_NIC_SQ_WQE_FRAG3_LOW_IDX = 12,
482 NES_NIC_SQ_WQE_FRAG3_HIGH_IDX = 13,
483 NES_NIC_SQ_WQE_FRAG4_LOW_IDX = 14,
484 NES_NIC_SQ_WQE_FRAG4_HIGH_IDX = 15,
485 };
486
487 enum nes_iwarp_sq_wqe_word_idx {
488 NES_IWARP_SQ_WQE_MISC_IDX = 0,
489 NES_IWARP_SQ_WQE_TOTAL_PAYLOAD_IDX = 1,
490 NES_IWARP_SQ_WQE_COMP_CTX_LOW_IDX = 2,
491 NES_IWARP_SQ_WQE_COMP_CTX_HIGH_IDX = 3,
492 NES_IWARP_SQ_WQE_COMP_SCRATCH_LOW_IDX = 4,
493 NES_IWARP_SQ_WQE_COMP_SCRATCH_HIGH_IDX = 5,
494 NES_IWARP_SQ_WQE_INV_STAG_LOW_IDX = 7,
495 NES_IWARP_SQ_WQE_RDMA_TO_LOW_IDX = 8,
496 NES_IWARP_SQ_WQE_RDMA_TO_HIGH_IDX = 9,
497 NES_IWARP_SQ_WQE_RDMA_LENGTH_IDX = 10,
498 NES_IWARP_SQ_WQE_RDMA_STAG_IDX = 11,
499 NES_IWARP_SQ_WQE_IMM_DATA_START_IDX = 12,
500 NES_IWARP_SQ_WQE_FRAG0_LOW_IDX = 16,
501 NES_IWARP_SQ_WQE_FRAG0_HIGH_IDX = 17,
502 NES_IWARP_SQ_WQE_LENGTH0_IDX = 18,
503 NES_IWARP_SQ_WQE_STAG0_IDX = 19,
504 NES_IWARP_SQ_WQE_FRAG1_LOW_IDX = 20,
505 NES_IWARP_SQ_WQE_FRAG1_HIGH_IDX = 21,
506 NES_IWARP_SQ_WQE_LENGTH1_IDX = 22,
507 NES_IWARP_SQ_WQE_STAG1_IDX = 23,
508 NES_IWARP_SQ_WQE_FRAG2_LOW_IDX = 24,
509 NES_IWARP_SQ_WQE_FRAG2_HIGH_IDX = 25,
510 NES_IWARP_SQ_WQE_LENGTH2_IDX = 26,
511 NES_IWARP_SQ_WQE_STAG2_IDX = 27,
512 NES_IWARP_SQ_WQE_FRAG3_LOW_IDX = 28,
513 NES_IWARP_SQ_WQE_FRAG3_HIGH_IDX = 29,
514 NES_IWARP_SQ_WQE_LENGTH3_IDX = 30,
515 NES_IWARP_SQ_WQE_STAG3_IDX = 31,
516 };
517
518 enum nes_iwarp_sq_bind_wqe_word_idx {
519 NES_IWARP_SQ_BIND_WQE_MR_IDX = 6,
520 NES_IWARP_SQ_BIND_WQE_MW_IDX = 7,
521 NES_IWARP_SQ_BIND_WQE_LENGTH_LOW_IDX = 8,
522 NES_IWARP_SQ_BIND_WQE_LENGTH_HIGH_IDX = 9,
523 NES_IWARP_SQ_BIND_WQE_VA_FBO_LOW_IDX = 10,
524 NES_IWARP_SQ_BIND_WQE_VA_FBO_HIGH_IDX = 11,
525 };
526
527 enum nes_iwarp_sq_fmr_wqe_word_idx {
528 NES_IWARP_SQ_FMR_WQE_MR_STAG_IDX = 7,
529 NES_IWARP_SQ_FMR_WQE_LENGTH_LOW_IDX = 8,
530 NES_IWARP_SQ_FMR_WQE_LENGTH_HIGH_IDX = 9,
531 NES_IWARP_SQ_FMR_WQE_VA_FBO_LOW_IDX = 10,
532 NES_IWARP_SQ_FMR_WQE_VA_FBO_HIGH_IDX = 11,
533 NES_IWARP_SQ_FMR_WQE_PBL_ADDR_LOW_IDX = 12,
534 NES_IWARP_SQ_FMR_WQE_PBL_ADDR_HIGH_IDX = 13,
535 NES_IWARP_SQ_FMR_WQE_PBL_LENGTH_IDX = 14,
536 };
537
538 enum nes_iwarp_sq_locinv_wqe_word_idx {
539 NES_IWARP_SQ_LOCINV_WQE_INV_STAG_IDX = 6,
540 };
541
542
543 enum nes_iwarp_rq_wqe_word_idx {
544 NES_IWARP_RQ_WQE_TOTAL_PAYLOAD_IDX = 1,
545 NES_IWARP_RQ_WQE_COMP_CTX_LOW_IDX = 2,
546 NES_IWARP_RQ_WQE_COMP_CTX_HIGH_IDX = 3,
547 NES_IWARP_RQ_WQE_COMP_SCRATCH_LOW_IDX = 4,
548 NES_IWARP_RQ_WQE_COMP_SCRATCH_HIGH_IDX = 5,
549 NES_IWARP_RQ_WQE_FRAG0_LOW_IDX = 8,
550 NES_IWARP_RQ_WQE_FRAG0_HIGH_IDX = 9,
551 NES_IWARP_RQ_WQE_LENGTH0_IDX = 10,
552 NES_IWARP_RQ_WQE_STAG0_IDX = 11,
553 NES_IWARP_RQ_WQE_FRAG1_LOW_IDX = 12,
554 NES_IWARP_RQ_WQE_FRAG1_HIGH_IDX = 13,
555 NES_IWARP_RQ_WQE_LENGTH1_IDX = 14,
556 NES_IWARP_RQ_WQE_STAG1_IDX = 15,
557 NES_IWARP_RQ_WQE_FRAG2_LOW_IDX = 16,
558 NES_IWARP_RQ_WQE_FRAG2_HIGH_IDX = 17,
559 NES_IWARP_RQ_WQE_LENGTH2_IDX = 18,
560 NES_IWARP_RQ_WQE_STAG2_IDX = 19,
561 NES_IWARP_RQ_WQE_FRAG3_LOW_IDX = 20,
562 NES_IWARP_RQ_WQE_FRAG3_HIGH_IDX = 21,
563 NES_IWARP_RQ_WQE_LENGTH3_IDX = 22,
564 NES_IWARP_RQ_WQE_STAG3_IDX = 23,
565 };
566
567 enum nes_nic_sq_wqe_bits {
568 NES_NIC_SQ_WQE_PHDR_CS_READY = (1<<21),
569 NES_NIC_SQ_WQE_LSO_ENABLE = (1<<22),
570 NES_NIC_SQ_WQE_TAGVALUE_ENABLE = (1<<23),
571 NES_NIC_SQ_WQE_DISABLE_CHKSUM = (1<<30),
572 NES_NIC_SQ_WQE_COMPLETION = (1<<31),
573 };
574
575 enum nes_nic_cqe_word_idx {
576 NES_NIC_CQE_ACCQP_ID_IDX = 0,
577 NES_NIC_CQE_TAG_PKT_TYPE_IDX = 2,
578 NES_NIC_CQE_MISC_IDX = 3,
579 };
580
581 #define NES_PKT_TYPE_APBVT_BITS 0xC112
582 #define NES_PKT_TYPE_APBVT_MASK 0xff3e
583
584 #define NES_PKT_TYPE_PVALID_BITS 0x10000000
585 #define NES_PKT_TYPE_PVALID_MASK 0x30000000
586
587 #define NES_PKT_TYPE_TCPV4_BITS 0x0110
588 #define NES_PKT_TYPE_TCPV4_MASK 0x3f30
589
590 #define NES_PKT_TYPE_UDPV4_BITS 0x0210
591 #define NES_PKT_TYPE_UDPV4_MASK 0x3f30
592
593 #define NES_PKT_TYPE_IPV4_BITS 0x0010
594 #define NES_PKT_TYPE_IPV4_MASK 0x3f30
595
596 #define NES_PKT_TYPE_OTHER_BITS 0x0000
597 #define NES_PKT_TYPE_OTHER_MASK 0x0030
598
599 #define NES_NIC_CQE_ERRV_SHIFT 16
600 enum nes_nic_ev_bits {
601 NES_NIC_ERRV_BITS_MODE = (1<<0),
602 NES_NIC_ERRV_BITS_IPV4_CSUM_ERR = (1<<1),
603 NES_NIC_ERRV_BITS_TCPUDP_CSUM_ERR = (1<<2),
604 NES_NIC_ERRV_BITS_WQE_OVERRUN = (1<<3),
605 NES_NIC_ERRV_BITS_IPH_ERR = (1<<4),
606 };
607
608 enum nes_nic_cqe_bits {
609 NES_NIC_CQE_ERRV_MASK = (0xff<<NES_NIC_CQE_ERRV_SHIFT),
610 NES_NIC_CQE_SQ = (1<<24),
611 NES_NIC_CQE_ACCQP_PORT = (1<<28),
612 NES_NIC_CQE_ACCQP_VALID = (1<<29),
613 NES_NIC_CQE_TAG_VALID = (1<<30),
614 NES_NIC_CQE_VALID = (1<<31),
615 };
616
617 enum nes_aeqe_word_idx {
618 NES_AEQE_COMP_CTXT_LOW_IDX = 0,
619 NES_AEQE_COMP_CTXT_HIGH_IDX = 1,
620 NES_AEQE_COMP_QP_CQ_ID_IDX = 2,
621 NES_AEQE_MISC_IDX = 3,
622 };
623
624 enum nes_aeqe_bits {
625 NES_AEQE_QP = (1<<16),
626 NES_AEQE_CQ = (1<<17),
627 NES_AEQE_SQ = (1<<18),
628 NES_AEQE_INBOUND_RDMA = (1<<19),
629 NES_AEQE_IWARP_STATE_MASK = (7<<20),
630 NES_AEQE_TCP_STATE_MASK = (0xf<<24),
631 NES_AEQE_VALID = (1<<31),
632 };
633
634 #define NES_AEQE_IWARP_STATE_SHIFT 20
635 #define NES_AEQE_TCP_STATE_SHIFT 24
636
637 enum nes_aeqe_iwarp_state {
638 NES_AEQE_IWARP_STATE_NON_EXISTANT = 0,
639 NES_AEQE_IWARP_STATE_IDLE = 1,
640 NES_AEQE_IWARP_STATE_RTS = 2,
641 NES_AEQE_IWARP_STATE_CLOSING = 3,
642 NES_AEQE_IWARP_STATE_TERMINATE = 5,
643 NES_AEQE_IWARP_STATE_ERROR = 6
644 };
645
646 enum nes_aeqe_tcp_state {
647 NES_AEQE_TCP_STATE_NON_EXISTANT = 0,
648 NES_AEQE_TCP_STATE_CLOSED = 1,
649 NES_AEQE_TCP_STATE_LISTEN = 2,
650 NES_AEQE_TCP_STATE_SYN_SENT = 3,
651 NES_AEQE_TCP_STATE_SYN_RCVD = 4,
652 NES_AEQE_TCP_STATE_ESTABLISHED = 5,
653 NES_AEQE_TCP_STATE_CLOSE_WAIT = 6,
654 NES_AEQE_TCP_STATE_FIN_WAIT_1 = 7,
655 NES_AEQE_TCP_STATE_CLOSING = 8,
656 NES_AEQE_TCP_STATE_LAST_ACK = 9,
657 NES_AEQE_TCP_STATE_FIN_WAIT_2 = 10,
658 NES_AEQE_TCP_STATE_TIME_WAIT = 11
659 };
660
661 enum nes_aeqe_aeid {
662 NES_AEQE_AEID_AMP_UNALLOCATED_STAG = 0x0102,
663 NES_AEQE_AEID_AMP_INVALID_STAG = 0x0103,
664 NES_AEQE_AEID_AMP_BAD_QP = 0x0104,
665 NES_AEQE_AEID_AMP_BAD_PD = 0x0105,
666 NES_AEQE_AEID_AMP_BAD_STAG_KEY = 0x0106,
667 NES_AEQE_AEID_AMP_BAD_STAG_INDEX = 0x0107,
668 NES_AEQE_AEID_AMP_BOUNDS_VIOLATION = 0x0108,
669 NES_AEQE_AEID_AMP_RIGHTS_VIOLATION = 0x0109,
670 NES_AEQE_AEID_AMP_TO_WRAP = 0x010a,
671 NES_AEQE_AEID_AMP_FASTREG_SHARED = 0x010b,
672 NES_AEQE_AEID_AMP_FASTREG_VALID_STAG = 0x010c,
673 NES_AEQE_AEID_AMP_FASTREG_MW_STAG = 0x010d,
674 NES_AEQE_AEID_AMP_FASTREG_INVALID_RIGHTS = 0x010e,
675 NES_AEQE_AEID_AMP_FASTREG_PBL_TABLE_OVERFLOW = 0x010f,
676 NES_AEQE_AEID_AMP_FASTREG_INVALID_LENGTH = 0x0110,
677 NES_AEQE_AEID_AMP_INVALIDATE_SHARED = 0x0111,
678 NES_AEQE_AEID_AMP_INVALIDATE_NO_REMOTE_ACCESS_RIGHTS = 0x0112,
679 NES_AEQE_AEID_AMP_INVALIDATE_MR_WITH_BOUND_WINDOWS = 0x0113,
680 NES_AEQE_AEID_AMP_MWBIND_VALID_STAG = 0x0114,
681 NES_AEQE_AEID_AMP_MWBIND_OF_MR_STAG = 0x0115,
682 NES_AEQE_AEID_AMP_MWBIND_TO_ZERO_BASED_STAG = 0x0116,
683 NES_AEQE_AEID_AMP_MWBIND_TO_MW_STAG = 0x0117,
684 NES_AEQE_AEID_AMP_MWBIND_INVALID_RIGHTS = 0x0118,
685 NES_AEQE_AEID_AMP_MWBIND_INVALID_BOUNDS = 0x0119,
686 NES_AEQE_AEID_AMP_MWBIND_TO_INVALID_PARENT = 0x011a,
687 NES_AEQE_AEID_AMP_MWBIND_BIND_DISABLED = 0x011b,
688 NES_AEQE_AEID_BAD_CLOSE = 0x0201,
689 NES_AEQE_AEID_RDMAP_ROE_BAD_LLP_CLOSE = 0x0202,
690 NES_AEQE_AEID_CQ_OPERATION_ERROR = 0x0203,
691 NES_AEQE_AEID_PRIV_OPERATION_DENIED = 0x0204,
692 NES_AEQE_AEID_RDMA_READ_WHILE_ORD_ZERO = 0x0205,
693 NES_AEQE_AEID_STAG_ZERO_INVALID = 0x0206,
694 NES_AEQE_AEID_DDP_INVALID_MSN_GAP_IN_MSN = 0x0301,
695 NES_AEQE_AEID_DDP_INVALID_MSN_RANGE_IS_NOT_VALID = 0x0302,
696 NES_AEQE_AEID_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER = 0x0303,
697 NES_AEQE_AEID_DDP_UBE_INVALID_DDP_VERSION = 0x0304,
698 NES_AEQE_AEID_DDP_UBE_INVALID_MO = 0x0305,
699 NES_AEQE_AEID_DDP_UBE_INVALID_MSN_NO_BUFFER_AVAILABLE = 0x0306,
700 NES_AEQE_AEID_DDP_UBE_INVALID_QN = 0x0307,
701 NES_AEQE_AEID_DDP_NO_L_BIT = 0x0308,
702 NES_AEQE_AEID_RDMAP_ROE_INVALID_RDMAP_VERSION = 0x0311,
703 NES_AEQE_AEID_RDMAP_ROE_UNEXPECTED_OPCODE = 0x0312,
704 NES_AEQE_AEID_ROE_INVALID_RDMA_READ_REQUEST = 0x0313,
705 NES_AEQE_AEID_ROE_INVALID_RDMA_WRITE_OR_READ_RESP = 0x0314,
706 NES_AEQE_AEID_INVALID_ARP_ENTRY = 0x0401,
707 NES_AEQE_AEID_INVALID_TCP_OPTION_RCVD = 0x0402,
708 NES_AEQE_AEID_STALE_ARP_ENTRY = 0x0403,
709 NES_AEQE_AEID_LLP_CLOSE_COMPLETE = 0x0501,
710 NES_AEQE_AEID_LLP_CONNECTION_RESET = 0x0502,
711 NES_AEQE_AEID_LLP_FIN_RECEIVED = 0x0503,
712 NES_AEQE_AEID_LLP_RECEIVED_MARKER_AND_LENGTH_FIELDS_DONT_MATCH = 0x0504,
713 NES_AEQE_AEID_LLP_RECEIVED_MPA_CRC_ERROR = 0x0505,
714 NES_AEQE_AEID_LLP_SEGMENT_TOO_LARGE = 0x0506,
715 NES_AEQE_AEID_LLP_SEGMENT_TOO_SMALL = 0x0507,
716 NES_AEQE_AEID_LLP_SYN_RECEIVED = 0x0508,
717 NES_AEQE_AEID_LLP_TERMINATE_RECEIVED = 0x0509,
718 NES_AEQE_AEID_LLP_TOO_MANY_RETRIES = 0x050a,
719 NES_AEQE_AEID_LLP_TOO_MANY_KEEPALIVE_RETRIES = 0x050b,
720 NES_AEQE_AEID_RESET_SENT = 0x0601,
721 NES_AEQE_AEID_TERMINATE_SENT = 0x0602,
722 NES_AEQE_AEID_DDP_LCE_LOCAL_CATASTROPHIC = 0x0700
723 };
724
725 enum nes_iwarp_sq_opcodes {
726 NES_IWARP_SQ_WQE_WRPDU = (1<<15),
727 NES_IWARP_SQ_WQE_PSH = (1<<21),
728 NES_IWARP_SQ_WQE_STREAMING = (1<<23),
729 NES_IWARP_SQ_WQE_IMM_DATA = (1<<28),
730 NES_IWARP_SQ_WQE_READ_FENCE = (1<<29),
731 NES_IWARP_SQ_WQE_LOCAL_FENCE = (1<<30),
732 NES_IWARP_SQ_WQE_SIGNALED_COMPL = (1<<31),
733 };
734
735 enum nes_iwarp_sq_wqe_bits {
736 NES_IWARP_SQ_OP_RDMAW = 0,
737 NES_IWARP_SQ_OP_RDMAR = 1,
738 NES_IWARP_SQ_OP_SEND = 3,
739 NES_IWARP_SQ_OP_SENDINV = 4,
740 NES_IWARP_SQ_OP_SENDSE = 5,
741 NES_IWARP_SQ_OP_SENDSEINV = 6,
742 NES_IWARP_SQ_OP_BIND = 8,
743 NES_IWARP_SQ_OP_FAST_REG = 9,
744 NES_IWARP_SQ_OP_LOCINV = 10,
745 NES_IWARP_SQ_OP_RDMAR_LOCINV = 11,
746 NES_IWARP_SQ_OP_NOP = 12,
747 };
748
749 #define NES_EEPROM_READ_REQUEST (1<<16)
750 #define NES_MAC_ADDR_VALID (1<<20)
751
752 /*
753 * NES index registers init values.
754 */
755 struct nes_init_values {
756 u32 index;
757 u32 data;
758 u8 wrt;
759 };
760
761 /*
762 * NES registers in BAR0.
763 */
764 struct nes_pci_regs {
765 u32 int_status;
766 u32 int_mask;
767 u32 int_pending;
768 u32 intf_int_status;
769 u32 intf_int_mask;
770 u32 other_regs[59]; /* pad out to 256 bytes for now */
771 };
772
773 #define NES_CQP_SQ_SIZE 128
774 #define NES_CCQ_SIZE 128
775 #define NES_NIC_WQ_SIZE 512
776 #define NES_NIC_CTX_SIZE ((NES_NIC_CTX_RQ_SIZE_512) | (NES_NIC_CTX_SQ_SIZE_512))
777 #define NES_NIC_BACK_STORE 0x00038000
778
779 struct nes_device;
780
781 struct nes_hw_nic_qp_context {
782 __le32 context_words[6];
783 };
784
785 struct nes_hw_nic_sq_wqe {
786 __le32 wqe_words[16];
787 };
788
789 struct nes_hw_nic_rq_wqe {
790 __le32 wqe_words[16];
791 };
792
793 struct nes_hw_nic_cqe {
794 __le32 cqe_words[4];
795 };
796
797 struct nes_hw_cqp_qp_context {
798 __le32 context_words[4];
799 };
800
801 struct nes_hw_cqp_wqe {
802 __le32 wqe_words[16];
803 };
804
805 struct nes_hw_qp_wqe {
806 __le32 wqe_words[32];
807 };
808
809 struct nes_hw_cqe {
810 __le32 cqe_words[8];
811 };
812
813 struct nes_hw_ceqe {
814 __le32 ceqe_words[2];
815 };
816
817 struct nes_hw_aeqe {
818 __le32 aeqe_words[4];
819 };
820
821 struct nes_cqp_request {
822 union {
823 u64 cqp_callback_context;
824 void *cqp_callback_pointer;
825 };
826 wait_queue_head_t waitq;
827 struct nes_hw_cqp_wqe cqp_wqe;
828 struct list_head list;
829 atomic_t refcount;
830 void (*cqp_callback)(struct nes_device *nesdev, struct nes_cqp_request *cqp_request);
831 u16 major_code;
832 u16 minor_code;
833 u8 waiting;
834 u8 request_done;
835 u8 dynamic;
836 u8 callback;
837 };
838
839 struct nes_hw_cqp {
840 struct nes_hw_cqp_wqe *sq_vbase;
841 dma_addr_t sq_pbase;
842 spinlock_t lock;
843 wait_queue_head_t waitq;
844 u16 qp_id;
845 u16 sq_head;
846 u16 sq_tail;
847 u16 sq_size;
848 };
849
850 #define NES_FIRST_FRAG_SIZE 128
851 struct nes_first_frag {
852 u8 buffer[NES_FIRST_FRAG_SIZE];
853 };
854
855 struct nes_hw_nic {
856 struct nes_first_frag *first_frag_vbase; /* virtual address of first frags */
857 struct nes_hw_nic_sq_wqe *sq_vbase; /* virtual address of sq */
858 struct nes_hw_nic_rq_wqe *rq_vbase; /* virtual address of rq */
859 struct sk_buff *tx_skb[NES_NIC_WQ_SIZE];
860 struct sk_buff *rx_skb[NES_NIC_WQ_SIZE];
861 dma_addr_t frag_paddr[NES_NIC_WQ_SIZE];
862 unsigned long first_frag_overflow[BITS_TO_LONGS(NES_NIC_WQ_SIZE)];
863 dma_addr_t sq_pbase; /* PCI memory for host rings */
864 dma_addr_t rq_pbase; /* PCI memory for host rings */
865
866 u16 qp_id;
867 u16 sq_head;
868 u16 sq_tail;
869 u16 sq_size;
870 u16 rq_head;
871 u16 rq_tail;
872 u16 rq_size;
873 u8 replenishing_rq;
874 u8 reserved;
875
876 spinlock_t sq_lock;
877 spinlock_t rq_lock;
878 };
879
880 struct nes_hw_nic_cq {
881 struct nes_hw_nic_cqe volatile *cq_vbase; /* PCI memory for host rings */
882 void (*ce_handler)(struct nes_device *nesdev, struct nes_hw_nic_cq *cq);
883 dma_addr_t cq_pbase; /* PCI memory for host rings */
884 int rx_cqes_completed;
885 int cqe_allocs_pending;
886 int rx_pkts_indicated;
887 u16 cq_head;
888 u16 cq_size;
889 u16 cq_number;
890 u8 cqes_pending;
891 };
892
893 struct nes_hw_qp {
894 struct nes_hw_qp_wqe *sq_vbase; /* PCI memory for host rings */
895 struct nes_hw_qp_wqe *rq_vbase; /* PCI memory for host rings */
896 void *q2_vbase; /* PCI memory for host rings */
897 dma_addr_t sq_pbase; /* PCI memory for host rings */
898 dma_addr_t rq_pbase; /* PCI memory for host rings */
899 dma_addr_t q2_pbase; /* PCI memory for host rings */
900 u32 qp_id;
901 u16 sq_head;
902 u16 sq_tail;
903 u16 sq_size;
904 u16 rq_head;
905 u16 rq_tail;
906 u16 rq_size;
907 u8 rq_encoded_size;
908 u8 sq_encoded_size;
909 };
910
911 struct nes_hw_cq {
912 struct nes_hw_cqe *cq_vbase; /* PCI memory for host rings */
913 void (*ce_handler)(struct nes_device *nesdev, struct nes_hw_cq *cq);
914 dma_addr_t cq_pbase; /* PCI memory for host rings */
915 u16 cq_head;
916 u16 cq_size;
917 u16 cq_number;
918 };
919
920 struct nes_hw_ceq {
921 struct nes_hw_ceqe volatile *ceq_vbase; /* PCI memory for host rings */
922 dma_addr_t ceq_pbase; /* PCI memory for host rings */
923 u16 ceq_head;
924 u16 ceq_size;
925 };
926
927 struct nes_hw_aeq {
928 struct nes_hw_aeqe volatile *aeq_vbase; /* PCI memory for host rings */
929 dma_addr_t aeq_pbase; /* PCI memory for host rings */
930 u16 aeq_head;
931 u16 aeq_size;
932 };
933
934 struct nic_qp_map {
935 u8 qpid;
936 u8 nic_index;
937 u8 logical_port;
938 u8 is_hnic;
939 };
940
941 #define NES_CQP_ARP_AEQ_INDEX_MASK 0x000f0000
942 #define NES_CQP_ARP_AEQ_INDEX_SHIFT 16
943
944 #define NES_CQP_APBVT_ADD 0x00008000
945 #define NES_CQP_APBVT_NIC_SHIFT 16
946
947 #define NES_ARP_ADD 1
948 #define NES_ARP_DELETE 2
949 #define NES_ARP_RESOLVE 3
950
951 #define NES_MAC_SW_IDLE 0
952 #define NES_MAC_SW_INTERRUPT 1
953 #define NES_MAC_SW_MH 2
954
955 struct nes_arp_entry {
956 u32 ip_addr;
957 u8 mac_addr[ETH_ALEN];
958 };
959
960 #define NES_NIC_FAST_TIMER 96
961 #define NES_NIC_FAST_TIMER_LOW 40
962 #define NES_NIC_FAST_TIMER_HIGH 1000
963 #define DEFAULT_NES_QL_HIGH 256
964 #define DEFAULT_NES_QL_LOW 16
965 #define DEFAULT_NES_QL_TARGET 64
966 #define DEFAULT_JUMBO_NES_QL_LOW 12
967 #define DEFAULT_JUMBO_NES_QL_TARGET 40
968 #define DEFAULT_JUMBO_NES_QL_HIGH 128
969 #define NES_NIC_CQ_DOWNWARD_TREND 16
970
971 struct nes_hw_tune_timer {
972 /* u16 cq_count; */
973 u16 threshold_low;
974 u16 threshold_target;
975 u16 threshold_high;
976 u16 timer_in_use;
977 u16 timer_in_use_old;
978 u16 timer_in_use_min;
979 u16 timer_in_use_max;
980 u8 timer_direction_upward;
981 u8 timer_direction_downward;
982 u16 cq_count_old;
983 u8 cq_direction_downward;
984 };
985
986 #define NES_TIMER_INT_LIMIT 2
987 #define NES_TIMER_INT_LIMIT_DYNAMIC 10
988 #define NES_TIMER_ENABLE_LIMIT 4
989 #define NES_MAX_LINK_INTERRUPTS 128
990 #define NES_MAX_LINK_CHECK 200
991 #define NES_MAX_LRO_DESCRIPTORS 32
992 #define NES_LRO_MAX_AGGR 64
993
994 struct nes_adapter {
995 u64 fw_ver;
996 unsigned long *allocated_qps;
997 unsigned long *allocated_cqs;
998 unsigned long *allocated_mrs;
999 unsigned long *allocated_pds;
1000 unsigned long *allocated_arps;
1001 struct nes_qp **qp_table;
1002 struct workqueue_struct *work_q;
1003
1004 struct list_head list;
1005 struct list_head active_listeners;
1006 /* list of the netdev's associated with each logical port */
1007 struct list_head nesvnic_list[4];
1008
1009 struct timer_list mh_timer;
1010 struct timer_list lc_timer;
1011 struct work_struct work;
1012 spinlock_t resource_lock;
1013 spinlock_t phy_lock;
1014 spinlock_t pbl_lock;
1015 spinlock_t periodic_timer_lock;
1016
1017 struct nes_arp_entry arp_table[NES_MAX_ARP_TABLE_SIZE];
1018
1019 /* Adapter CEQ and AEQs */
1020 struct nes_hw_ceq ceq[16];
1021 struct nes_hw_aeq aeq[8];
1022
1023 struct nes_hw_tune_timer tune_timer;
1024
1025 unsigned long doorbell_start;
1026
1027 u32 hw_rev;
1028 u32 vendor_id;
1029 u32 vendor_part_id;
1030 u32 device_cap_flags;
1031 u32 tick_delta;
1032 u32 timer_int_req;
1033 u32 arp_table_size;
1034 u32 next_arp_index;
1035
1036 u32 max_mr;
1037 u32 max_256pbl;
1038 u32 max_4kpbl;
1039 u32 free_256pbl;
1040 u32 free_4kpbl;
1041 u32 max_mr_size;
1042 u32 max_qp;
1043 u32 next_qp;
1044 u32 max_irrq;
1045 u32 max_qp_wr;
1046 u32 max_sge;
1047 u32 max_cq;
1048 u32 next_cq;
1049 u32 max_cqe;
1050 u32 max_pd;
1051 u32 base_pd;
1052 u32 next_pd;
1053 u32 hte_index_mask;
1054
1055 /* EEPROM information */
1056 u32 rx_pool_size;
1057 u32 tx_pool_size;
1058 u32 rx_threshold;
1059 u32 tcp_timer_core_clk_divisor;
1060 u32 iwarp_config;
1061 u32 cm_config;
1062 u32 sws_timer_config;
1063 u32 tcp_config1;
1064 u32 wqm_wat;
1065 u32 core_clock;
1066 u32 firmware_version;
1067
1068 u32 nic_rx_eth_route_err;
1069
1070 u32 et_rx_coalesce_usecs;
1071 u32 et_rx_max_coalesced_frames;
1072 u32 et_rx_coalesce_usecs_irq;
1073 u32 et_rx_max_coalesced_frames_irq;
1074 u32 et_pkt_rate_low;
1075 u32 et_rx_coalesce_usecs_low;
1076 u32 et_rx_max_coalesced_frames_low;
1077 u32 et_pkt_rate_high;
1078 u32 et_rx_coalesce_usecs_high;
1079 u32 et_rx_max_coalesced_frames_high;
1080 u32 et_rate_sample_interval;
1081 u32 timer_int_limit;
1082
1083 /* Adapter base MAC address */
1084 u32 mac_addr_low;
1085 u16 mac_addr_high;
1086
1087 u16 firmware_eeprom_offset;
1088 u16 software_eeprom_offset;
1089
1090 u16 max_irrq_wr;
1091
1092 /* pd config for each port */
1093 u16 pd_config_size[4];
1094 u16 pd_config_base[4];
1095
1096 u16 link_interrupt_count[4];
1097
1098 /* the phy index for each port */
1099 u8 phy_index[4];
1100 u8 mac_sw_state[4];
1101 u8 mac_link_down[4];
1102 u8 phy_type[4];
1103
1104 /* PCI information */
1105 unsigned int devfn;
1106 unsigned char bus_number;
1107 unsigned char OneG_Mode;
1108
1109 unsigned char ref_count;
1110 u8 netdev_count;
1111 u8 netdev_max; /* from host nic address count in EEPROM */
1112 u8 port_count;
1113 u8 virtwq;
1114 u8 et_use_adaptive_rx_coalesce;
1115 u8 adapter_fcn_count;
1116 };
1117
1118 struct nes_pbl {
1119 u64 *pbl_vbase;
1120 dma_addr_t pbl_pbase;
1121 struct page *page;
1122 unsigned long user_base;
1123 u32 pbl_size;
1124 struct list_head list;
1125 /* TODO: need to add list for two level tables */
1126 };
1127
1128 struct nes_listener {
1129 struct work_struct work;
1130 struct workqueue_struct *wq;
1131 struct nes_vnic *nesvnic;
1132 struct iw_cm_id *cm_id;
1133 struct list_head list;
1134 unsigned long socket;
1135 u8 accept_failed;
1136 };
1137
1138 struct nes_ib_device;
1139
1140 struct nes_vnic {
1141 struct nes_ib_device *nesibdev;
1142 u64 sq_full;
1143 u64 sq_locked;
1144 u64 tso_requests;
1145 u64 segmented_tso_requests;
1146 u64 linearized_skbs;
1147 u64 tx_sw_dropped;
1148 u64 endnode_nstat_rx_discard;
1149 u64 endnode_nstat_rx_octets;
1150 u64 endnode_nstat_rx_frames;
1151 u64 endnode_nstat_tx_octets;
1152 u64 endnode_nstat_tx_frames;
1153 u64 endnode_ipv4_tcp_retransmits;
1154 /* void *mem; */
1155 struct nes_device *nesdev;
1156 struct net_device *netdev;
1157 struct vlan_group *vlan_grp;
1158 atomic_t rx_skbs_needed;
1159 atomic_t rx_skb_timer_running;
1160 int budget;
1161 u32 msg_enable;
1162 /* u32 tx_avail; */
1163 __be32 local_ipaddr;
1164 struct napi_struct napi;
1165 spinlock_t tx_lock; /* could use netdev tx lock? */
1166 struct timer_list rq_wqes_timer;
1167 u32 nic_mem_size;
1168 void *nic_vbase;
1169 dma_addr_t nic_pbase;
1170 struct nes_hw_nic nic;
1171 struct nes_hw_nic_cq nic_cq;
1172 u32 mcrq_qp_id;
1173 struct nes_ucontext *mcrq_ucontext;
1174 struct nes_cqp_request* (*get_cqp_request)(struct nes_device *nesdev);
1175 void (*post_cqp_request)(struct nes_device*, struct nes_cqp_request *, int);
1176 int (*mcrq_mcast_filter)( struct nes_vnic* nesvnic, __u8* dmi_addr );
1177 struct net_device_stats netstats;
1178 /* used to put the netdev on the adapters logical port list */
1179 struct list_head list;
1180 u16 max_frame_size;
1181 u8 netdev_open;
1182 u8 linkup;
1183 u8 logical_port;
1184 u8 netdev_index; /* might not be needed, indexes nesdev->netdev */
1185 u8 perfect_filter_index;
1186 u8 nic_index;
1187 u8 qp_nic_index[4];
1188 u8 next_qp_nic_index;
1189 u8 of_device_registered;
1190 u8 rdma_enabled;
1191 u8 rx_checksum_disabled;
1192 u32 lro_max_aggr;
1193 struct net_lro_mgr lro_mgr;
1194 struct net_lro_desc lro_desc[NES_MAX_LRO_DESCRIPTORS];
1195 };
1196
1197 struct nes_ib_device {
1198 struct ib_device ibdev;
1199 struct nes_vnic *nesvnic;
1200
1201 /* Virtual RNIC Limits */
1202 u32 max_mr;
1203 u32 max_qp;
1204 u32 max_cq;
1205 u32 max_pd;
1206 u32 num_mr;
1207 u32 num_qp;
1208 u32 num_cq;
1209 u32 num_pd;
1210 };
1211
1212 #define nes_vlan_rx vlan_hwaccel_receive_skb
1213 #define nes_netif_rx netif_receive_skb
1214
1215 #endif /* __NES_HW_H */
Mirror for ia64_pv_ops.git