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ia64/kvm: compilation fix. export account_system_vtime.
[pv_ops_mirror.git] / drivers / media / video / pxa_camera.c
blob7cc8e9b19fb794fb57139515692de6d460afbd96
1 /*
2 * V4L2 Driver for PXA camera host
3 *
4 * Copyright (C) 2006, Sascha Hauer, Pengutronix
5 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/io.h>
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/errno.h>
19 #include <linux/fs.h>
20 #include <linux/interrupt.h>
21 #include <linux/kernel.h>
22 #include <linux/mm.h>
23 #include <linux/moduleparam.h>
24 #include <linux/time.h>
25 #include <linux/version.h>
26 #include <linux/device.h>
27 #include <linux/platform_device.h>
28 #include <linux/mutex.h>
29 #include <linux/clk.h>
30
31 #include <media/v4l2-common.h>
32 #include <media/v4l2-dev.h>
33 #include <media/soc_camera.h>
34
35 #include <linux/videodev2.h>
36
37 #include <asm/dma.h>
38 #include <asm/arch/pxa-regs.h>
39 #include <asm/arch/camera.h>
40
41 #define PXA_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5)
42 #define PXA_CAM_DRV_NAME "pxa27x-camera"
43
44 #define CICR0_SIM_MP (0 << 24)
45 #define CICR0_SIM_SP (1 << 24)
46 #define CICR0_SIM_MS (2 << 24)
47 #define CICR0_SIM_EP (3 << 24)
48 #define CICR0_SIM_ES (4 << 24)
49
50 #define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */
51 #define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */
52 #define CICR1_COLOR_SP_VAL(x) (((x) << 3) & CICR1_COLOR_SP) /* color space */
53 #define CICR1_RGB_BPP_VAL(x) (((x) << 7) & CICR1_RGB_BPP) /* bpp for rgb */
54 #define CICR1_RGBT_CONV_VAL(x) (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */
55
56 #define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */
57 #define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */
58 #define CICR2_HSW_VAL(x) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */
59 #define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */
60 #define CICR2_FSW_VAL(x) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */
61
62 #define CICR3_BFW_VAL(x) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */
63 #define CICR3_EFW_VAL(x) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */
64 #define CICR3_VSW_VAL(x) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */
65 #define CICR3_LPF_VAL(x) (((x) << 0) & CICR3_LPF) /* Lines per frame */
66
67 #define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \
68 CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \
69 CICR0_EOFM | CICR0_FOM)
70
71 static DEFINE_MUTEX(camera_lock);
72
73 /*
74 * Structures
75 */
76 enum pxa_camera_active_dma {
77 DMA_Y = 0x1,
78 DMA_U = 0x2,
79 DMA_V = 0x4,
80 };
81
82 /* descriptor needed for the PXA DMA engine */
83 struct pxa_cam_dma {
84 dma_addr_t sg_dma;
85 struct pxa_dma_desc *sg_cpu;
86 size_t sg_size;
87 int sglen;
88 };
89
90 /* buffer for one video frame */
91 struct pxa_buffer {
92 /* common v4l buffer stuff -- must be first */
93 struct videobuf_buffer vb;
94
95 const struct soc_camera_data_format *fmt;
96
97 /* our descriptor lists for Y, U and V channels */
98 struct pxa_cam_dma dmas[3];
99
100 int inwork;
101
102 enum pxa_camera_active_dma active_dma;
103 };
104
105 struct pxa_camera_dev {
106 struct device *dev;
107 /* PXA27x is only supposed to handle one camera on its Quick Capture
108 * interface. If anyone ever builds hardware to enable more than
109 * one camera, they will have to modify this driver too */
110 struct soc_camera_device *icd;
111 struct clk *clk;
112
113 unsigned int irq;
114 void __iomem *base;
115
116 int channels;
117 unsigned int dma_chans[3];
118
119 struct pxacamera_platform_data *pdata;
120 struct resource *res;
121 unsigned long platform_flags;
122 unsigned long platform_mclk_10khz;
123
124 struct list_head capture;
125
126 spinlock_t lock;
127
128 struct pxa_buffer *active;
129 struct pxa_dma_desc *sg_tail[3];
130 };
131
132 static const char *pxa_cam_driver_description = "PXA_Camera";
133
134 static unsigned int vid_limit = 16; /* Video memory limit, in Mb */
135
136 /*
137 * Videobuf operations
138 */
139 static int pxa_videobuf_setup(struct videobuf_queue *vq, unsigned int *count,
140 unsigned int *size)
141 {
142 struct soc_camera_device *icd = vq->priv_data;
143 struct soc_camera_host *ici =
144 to_soc_camera_host(icd->dev.parent);
145 struct pxa_camera_dev *pcdev = ici->priv;
146
147 dev_dbg(&icd->dev, "count=%d, size=%d\n", *count, *size);
148
149 /* planar capture requires Y, U and V buffers to be page aligned */
150 if (pcdev->channels == 3) {
151 *size = PAGE_ALIGN(icd->width * icd->height); /* Y pages */
152 *size += PAGE_ALIGN(icd->width * icd->height / 2); /* U pages */
153 *size += PAGE_ALIGN(icd->width * icd->height / 2); /* V pages */
154 } else {
155 *size = icd->width * icd->height *
156 ((icd->current_fmt->depth + 7) >> 3);
157 }
158
159 if (0 == *count)
160 *count = 32;
161 while (*size * *count > vid_limit * 1024 * 1024)
162 (*count)--;
163
164 return 0;
165 }
166
167 static void free_buffer(struct videobuf_queue *vq, struct pxa_buffer *buf)
168 {
169 struct soc_camera_device *icd = vq->priv_data;
170 struct soc_camera_host *ici =
171 to_soc_camera_host(icd->dev.parent);
172 struct pxa_camera_dev *pcdev = ici->priv;
173 struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb);
174 int i;
175
176 BUG_ON(in_interrupt());
177
178 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
179 &buf->vb, buf->vb.baddr, buf->vb.bsize);
180
181 /* This waits until this buffer is out of danger, i.e., until it is no
182 * longer in STATE_QUEUED or STATE_ACTIVE */
183 videobuf_waiton(&buf->vb, 0, 0);
184 videobuf_dma_unmap(vq, dma);
185 videobuf_dma_free(dma);
186
187 for (i = 0; i < ARRAY_SIZE(buf->dmas); i++) {
188 if (buf->dmas[i].sg_cpu)
189 dma_free_coherent(pcdev->dev, buf->dmas[i].sg_size,
190 buf->dmas[i].sg_cpu,
191 buf->dmas[i].sg_dma);
192 buf->dmas[i].sg_cpu = NULL;
193 }
194
195 buf->vb.state = VIDEOBUF_NEEDS_INIT;
196 }
197
198 static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev,
199 struct pxa_buffer *buf,
200 struct videobuf_dmabuf *dma, int channel,
201 int sglen, int sg_start, int cibr,
202 unsigned int size)
203 {
204 struct pxa_cam_dma *pxa_dma = &buf->dmas[channel];
205 int i;
206
207 if (pxa_dma->sg_cpu)
208 dma_free_coherent(pcdev->dev, pxa_dma->sg_size,
209 pxa_dma->sg_cpu, pxa_dma->sg_dma);
210
211 pxa_dma->sg_size = (sglen + 1) * sizeof(struct pxa_dma_desc);
212 pxa_dma->sg_cpu = dma_alloc_coherent(pcdev->dev, pxa_dma->sg_size,
213 &pxa_dma->sg_dma, GFP_KERNEL);
214 if (!pxa_dma->sg_cpu)
215 return -ENOMEM;
216
217 pxa_dma->sglen = sglen;
218
219 for (i = 0; i < sglen; i++) {
220 int sg_i = sg_start + i;
221 struct scatterlist *sg = dma->sglist;
222 unsigned int dma_len = sg_dma_len(&sg[sg_i]), xfer_len;
223
224 pxa_dma->sg_cpu[i].dsadr = pcdev->res->start + cibr;
225 pxa_dma->sg_cpu[i].dtadr = sg_dma_address(&sg[sg_i]);
226
227 /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */
228 xfer_len = (min(dma_len, size) + 7) & ~7;
229
230 pxa_dma->sg_cpu[i].dcmd =
231 DCMD_FLOWSRC | DCMD_BURST8 | DCMD_INCTRGADDR | xfer_len;
232 size -= dma_len;
233 pxa_dma->sg_cpu[i].ddadr =
234 pxa_dma->sg_dma + (i + 1) * sizeof(struct pxa_dma_desc);
235 }
236
237 pxa_dma->sg_cpu[sglen - 1].ddadr = DDADR_STOP;
238 pxa_dma->sg_cpu[sglen - 1].dcmd |= DCMD_ENDIRQEN;
239
240 return 0;
241 }
242
243 static int pxa_videobuf_prepare(struct videobuf_queue *vq,
244 struct videobuf_buffer *vb, enum v4l2_field field)
245 {
246 struct soc_camera_device *icd = vq->priv_data;
247 struct soc_camera_host *ici =
248 to_soc_camera_host(icd->dev.parent);
249 struct pxa_camera_dev *pcdev = ici->priv;
250 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
251 int ret;
252 int sglen_y, sglen_yu = 0, sglen_u = 0, sglen_v = 0;
253 int size_y, size_u = 0, size_v = 0;
254
255 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
256 vb, vb->baddr, vb->bsize);
257
258 /* Added list head initialization on alloc */
259 WARN_ON(!list_empty(&vb->queue));
260
261 #ifdef DEBUG
262 /* This can be useful if you want to see if we actually fill
263 * the buffer with something */
264 memset((void *)vb->baddr, 0xaa, vb->bsize);
265 #endif
266
267 BUG_ON(NULL == icd->current_fmt);
268
269 /* I think, in buf_prepare you only have to protect global data,
270 * the actual buffer is yours */
271 buf->inwork = 1;
272
273 if (buf->fmt != icd->current_fmt ||
274 vb->width != icd->width ||
275 vb->height != icd->height ||
276 vb->field != field) {
277 buf->fmt = icd->current_fmt;
278 vb->width = icd->width;
279 vb->height = icd->height;
280 vb->field = field;
281 vb->state = VIDEOBUF_NEEDS_INIT;
282 }
283
284 vb->size = vb->width * vb->height * ((buf->fmt->depth + 7) >> 3);
285 if (0 != vb->baddr && vb->bsize < vb->size) {
286 ret = -EINVAL;
287 goto out;
288 }
289
290 if (vb->state == VIDEOBUF_NEEDS_INIT) {
291 unsigned int size = vb->size;
292 struct videobuf_dmabuf *dma = videobuf_to_dma(vb);
293
294 ret = videobuf_iolock(vq, vb, NULL);
295 if (ret)
296 goto fail;
297
298 if (pcdev->channels == 3) {
299 /* FIXME the calculations should be more precise */
300 sglen_y = dma->sglen / 2;
301 sglen_u = sglen_v = dma->sglen / 4 + 1;
302 sglen_yu = sglen_y + sglen_u;
303 size_y = size / 2;
304 size_u = size_v = size / 4;
305 } else {
306 sglen_y = dma->sglen;
307 size_y = size;
308 }
309
310 /* init DMA for Y channel */
311 ret = pxa_init_dma_channel(pcdev, buf, dma, 0, sglen_y,
312 0, 0x28, size_y);
313
314 if (ret) {
315 dev_err(pcdev->dev,
316 "DMA initialization for Y/RGB failed\n");
317 goto fail;
318 }
319
320 if (pcdev->channels == 3) {
321 /* init DMA for U channel */
322 ret = pxa_init_dma_channel(pcdev, buf, dma, 1, sglen_u,
323 sglen_y, 0x30, size_u);
324 if (ret) {
325 dev_err(pcdev->dev,
326 "DMA initialization for U failed\n");
327 goto fail_u;
328 }
329
330 /* init DMA for V channel */
331 ret = pxa_init_dma_channel(pcdev, buf, dma, 2, sglen_v,
332 sglen_yu, 0x38, size_v);
333 if (ret) {
334 dev_err(pcdev->dev,
335 "DMA initialization for V failed\n");
336 goto fail_v;
337 }
338 }
339
340 vb->state = VIDEOBUF_PREPARED;
341 }
342
343 buf->inwork = 0;
344 buf->active_dma = DMA_Y;
345 if (pcdev->channels == 3)
346 buf->active_dma |= DMA_U | DMA_V;
347
348 return 0;
349
350 fail_v:
351 dma_free_coherent(pcdev->dev, buf->dmas[1].sg_size,
352 buf->dmas[1].sg_cpu, buf->dmas[1].sg_dma);
353 fail_u:
354 dma_free_coherent(pcdev->dev, buf->dmas[0].sg_size,
355 buf->dmas[0].sg_cpu, buf->dmas[0].sg_dma);
356 fail:
357 free_buffer(vq, buf);
358 out:
359 buf->inwork = 0;
360 return ret;
361 }
362
363 static void pxa_videobuf_queue(struct videobuf_queue *vq,
364 struct videobuf_buffer *vb)
365 {
366 struct soc_camera_device *icd = vq->priv_data;
367 struct soc_camera_host *ici =
368 to_soc_camera_host(icd->dev.parent);
369 struct pxa_camera_dev *pcdev = ici->priv;
370 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
371 struct pxa_buffer *active;
372 unsigned long flags;
373 int i;
374
375 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
376 vb, vb->baddr, vb->bsize);
377 spin_lock_irqsave(&pcdev->lock, flags);
378
379 list_add_tail(&vb->queue, &pcdev->capture);
380
381 vb->state = VIDEOBUF_ACTIVE;
382 active = pcdev->active;
383
384 if (!active) {
385 CIFR |= CIFR_RESET_F;
386
387 for (i = 0; i < pcdev->channels; i++) {
388 DDADR(pcdev->dma_chans[i]) = buf->dmas[i].sg_dma;
389 DCSR(pcdev->dma_chans[i]) = DCSR_RUN;
390 pcdev->sg_tail[i] = buf->dmas[i].sg_cpu + buf->dmas[i].sglen - 1;
391 }
392
393 pcdev->active = buf;
394 CICR0 |= CICR0_ENB;
395 } else {
396 struct pxa_cam_dma *buf_dma;
397 struct pxa_cam_dma *act_dma;
398 int nents;
399
400 for (i = 0; i < pcdev->channels; i++) {
401 buf_dma = &buf->dmas[i];
402 act_dma = &active->dmas[i];
403 nents = buf_dma->sglen;
404
405 /* Stop DMA engine */
406 DCSR(pcdev->dma_chans[i]) = 0;
407
408 /* Add the descriptors we just initialized to
409 the currently running chain */
410 pcdev->sg_tail[i]->ddadr = buf_dma->sg_dma;
411 pcdev->sg_tail[i] = buf_dma->sg_cpu + buf_dma->sglen - 1;
412
413 /* Setup a dummy descriptor with the DMA engines current
414 * state
415 */
416 buf_dma->sg_cpu[nents].dsadr =
417 pcdev->res->start + 0x28 + i*8; /* CIBRx */
418 buf_dma->sg_cpu[nents].dtadr =
419 DTADR(pcdev->dma_chans[i]);
420 buf_dma->sg_cpu[nents].dcmd =
421 DCMD(pcdev->dma_chans[i]);
422
423 if (DDADR(pcdev->dma_chans[i]) == DDADR_STOP) {
424 /* The DMA engine is on the last
425 descriptor, set the next descriptors
426 address to the descriptors we just
427 initialized */
428 buf_dma->sg_cpu[nents].ddadr = buf_dma->sg_dma;
429 } else {
430 buf_dma->sg_cpu[nents].ddadr =
431 DDADR(pcdev->dma_chans[i]);
432 }
433
434 /* The next descriptor is the dummy descriptor */
435 DDADR(pcdev->dma_chans[i]) = buf_dma->sg_dma + nents *
436 sizeof(struct pxa_dma_desc);
437
438 DCSR(pcdev->dma_chans[i]) = DCSR_RUN;
439 }
440 }
441
442 spin_unlock_irqrestore(&pcdev->lock, flags);
443 }
444
445 static void pxa_videobuf_release(struct videobuf_queue *vq,
446 struct videobuf_buffer *vb)
447 {
448 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
449 #ifdef DEBUG
450 struct soc_camera_device *icd = vq->priv_data;
451
452 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
453 vb, vb->baddr, vb->bsize);
454
455 switch (vb->state) {
456 case VIDEOBUF_ACTIVE:
457 dev_dbg(&icd->dev, "%s (active)\n", __func__);
458 break;
459 case VIDEOBUF_QUEUED:
460 dev_dbg(&icd->dev, "%s (queued)\n", __func__);
461 break;
462 case VIDEOBUF_PREPARED:
463 dev_dbg(&icd->dev, "%s (prepared)\n", __func__);
464 break;
465 default:
466 dev_dbg(&icd->dev, "%s (unknown)\n", __func__);
467 break;
468 }
469 #endif
470
471 free_buffer(vq, buf);
472 }
473
474 static void pxa_camera_wakeup(struct pxa_camera_dev *pcdev,
475 struct videobuf_buffer *vb,
476 struct pxa_buffer *buf)
477 {
478 /* _init is used to debug races, see comment in pxa_camera_reqbufs() */
479 list_del_init(&vb->queue);
480 vb->state = VIDEOBUF_DONE;
481 do_gettimeofday(&vb->ts);
482 vb->field_count++;
483 wake_up(&vb->done);
484
485 if (list_empty(&pcdev->capture)) {
486 pcdev->active = NULL;
487 DCSR(pcdev->dma_chans[0]) = 0;
488 DCSR(pcdev->dma_chans[1]) = 0;
489 DCSR(pcdev->dma_chans[2]) = 0;
490 CICR0 &= ~CICR0_ENB;
491 return;
492 }
493
494 pcdev->active = list_entry(pcdev->capture.next,
495 struct pxa_buffer, vb.queue);
496 }
497
498 static void pxa_camera_dma_irq(int channel, struct pxa_camera_dev *pcdev,
499 enum pxa_camera_active_dma act_dma)
500 {
501 struct pxa_buffer *buf;
502 unsigned long flags;
503 u32 status, camera_status, overrun;
504 struct videobuf_buffer *vb;
505
506 spin_lock_irqsave(&pcdev->lock, flags);
507
508 status = DCSR(channel);
509 DCSR(channel) = status | DCSR_ENDINTR;
510
511 if (status & DCSR_BUSERR) {
512 dev_err(pcdev->dev, "DMA Bus Error IRQ!\n");
513 goto out;
514 }
515
516 if (!(status & DCSR_ENDINTR)) {
517 dev_err(pcdev->dev, "Unknown DMA IRQ source, "
518 "status: 0x%08x\n", status);
519 goto out;
520 }
521
522 if (!pcdev->active) {
523 dev_err(pcdev->dev, "DMA End IRQ with no active buffer!\n");
524 goto out;
525 }
526
527 camera_status = CISR;
528 overrun = CISR_IFO_0;
529 if (pcdev->channels == 3)
530 overrun |= CISR_IFO_1 | CISR_IFO_2;
531 if (camera_status & overrun) {
532 dev_dbg(pcdev->dev, "FIFO overrun! CISR: %x\n", camera_status);
533 /* Stop the Capture Interface */
534 CICR0 &= ~CICR0_ENB;
535 /* Stop DMA */
536 DCSR(channel) = 0;
537 /* Reset the FIFOs */
538 CIFR |= CIFR_RESET_F;
539 /* Enable End-Of-Frame Interrupt */
540 CICR0 &= ~CICR0_EOFM;
541 /* Restart the Capture Interface */
542 CICR0 |= CICR0_ENB;
543 goto out;
544 }
545
546 vb = &pcdev->active->vb;
547 buf = container_of(vb, struct pxa_buffer, vb);
548 WARN_ON(buf->inwork || list_empty(&vb->queue));
549 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
550 vb, vb->baddr, vb->bsize);
551
552 buf->active_dma &= ~act_dma;
553 if (!buf->active_dma)
554 pxa_camera_wakeup(pcdev, vb, buf);
555
556 out:
557 spin_unlock_irqrestore(&pcdev->lock, flags);
558 }
559
560 static void pxa_camera_dma_irq_y(int channel, void *data)
561 {
562 struct pxa_camera_dev *pcdev = data;
563 pxa_camera_dma_irq(channel, pcdev, DMA_Y);
564 }
565
566 static void pxa_camera_dma_irq_u(int channel, void *data)
567 {
568 struct pxa_camera_dev *pcdev = data;
569 pxa_camera_dma_irq(channel, pcdev, DMA_U);
570 }
571
572 static void pxa_camera_dma_irq_v(int channel, void *data)
573 {
574 struct pxa_camera_dev *pcdev = data;
575 pxa_camera_dma_irq(channel, pcdev, DMA_V);
576 }
577
578 static struct videobuf_queue_ops pxa_videobuf_ops = {
579 .buf_setup = pxa_videobuf_setup,
580 .buf_prepare = pxa_videobuf_prepare,
581 .buf_queue = pxa_videobuf_queue,
582 .buf_release = pxa_videobuf_release,
583 };
584
585 static int mclk_get_divisor(struct pxa_camera_dev *pcdev)
586 {
587 unsigned int mclk_10khz = pcdev->platform_mclk_10khz;
588 unsigned long div;
589 unsigned long lcdclk;
590
591 lcdclk = clk_get_rate(pcdev->clk) / 10000;
592
593 /* We verify platform_mclk_10khz != 0, so if anyone breaks it, here
594 * they get a nice Oops */
595 div = (lcdclk + 2 * mclk_10khz - 1) / (2 * mclk_10khz) - 1;
596
597 dev_dbg(pcdev->dev, "LCD clock %lukHz, target freq %dkHz, "
598 "divisor %lu\n", lcdclk * 10, mclk_10khz * 10, div);
599
600 return div;
601 }
602
603 static void pxa_camera_activate(struct pxa_camera_dev *pcdev)
604 {
605 struct pxacamera_platform_data *pdata = pcdev->pdata;
606 u32 cicr4 = 0;
607
608 dev_dbg(pcdev->dev, "Registered platform device at %p data %p\n",
609 pcdev, pdata);
610
611 if (pdata && pdata->init) {
612 dev_dbg(pcdev->dev, "%s: Init gpios\n", __func__);
613 pdata->init(pcdev->dev);
614 }
615
616 if (pdata && pdata->power) {
617 dev_dbg(pcdev->dev, "%s: Power on camera\n", __func__);
618 pdata->power(pcdev->dev, 1);
619 }
620
621 if (pdata && pdata->reset) {
622 dev_dbg(pcdev->dev, "%s: Releasing camera reset\n",
623 __func__);
624 pdata->reset(pcdev->dev, 1);
625 }
626
627 CICR0 = 0x3FF; /* disable all interrupts */
628
629 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
630 cicr4 |= CICR4_PCLK_EN;
631 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
632 cicr4 |= CICR4_MCLK_EN;
633 if (pcdev->platform_flags & PXA_CAMERA_PCP)
634 cicr4 |= CICR4_PCP;
635 if (pcdev->platform_flags & PXA_CAMERA_HSP)
636 cicr4 |= CICR4_HSP;
637 if (pcdev->platform_flags & PXA_CAMERA_VSP)
638 cicr4 |= CICR4_VSP;
639
640 CICR4 = mclk_get_divisor(pcdev) | cicr4;
641
642 clk_enable(pcdev->clk);
643 }
644
645 static void pxa_camera_deactivate(struct pxa_camera_dev *pcdev)
646 {
647 struct pxacamera_platform_data *board = pcdev->pdata;
648
649 clk_disable(pcdev->clk);
650
651 if (board && board->reset) {
652 dev_dbg(pcdev->dev, "%s: Asserting camera reset\n",
653 __func__);
654 board->reset(pcdev->dev, 0);
655 }
656
657 if (board && board->power) {
658 dev_dbg(pcdev->dev, "%s: Power off camera\n", __func__);
659 board->power(pcdev->dev, 0);
660 }
661 }
662
663 static irqreturn_t pxa_camera_irq(int irq, void *data)
664 {
665 struct pxa_camera_dev *pcdev = data;
666 unsigned int status = CISR;
667
668 dev_dbg(pcdev->dev, "Camera interrupt status 0x%x\n", status);
669
670 if (!status)
671 return IRQ_NONE;
672
673 CISR = status;
674
675 if (status & CISR_EOF) {
676 int i;
677 for (i = 0; i < pcdev->channels; i++) {
678 DDADR(pcdev->dma_chans[i]) =
679 pcdev->active->dmas[i].sg_dma;
680 DCSR(pcdev->dma_chans[i]) = DCSR_RUN;
681 }
682 CICR0 |= CICR0_EOFM;
683 }
684
685 return IRQ_HANDLED;
686 }
687
688 /* The following two functions absolutely depend on the fact, that
689 * there can be only one camera on PXA quick capture interface */
690 static int pxa_camera_add_device(struct soc_camera_device *icd)
691 {
692 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
693 struct pxa_camera_dev *pcdev = ici->priv;
694 int ret;
695
696 mutex_lock(&camera_lock);
697
698 if (pcdev->icd) {
699 ret = -EBUSY;
700 goto ebusy;
701 }
702
703 dev_info(&icd->dev, "PXA Camera driver attached to camera %d\n",
704 icd->devnum);
705
706 pxa_camera_activate(pcdev);
707 ret = icd->ops->init(icd);
708
709 if (!ret)
710 pcdev->icd = icd;
711
712 ebusy:
713 mutex_unlock(&camera_lock);
714
715 return ret;
716 }
717
718 static void pxa_camera_remove_device(struct soc_camera_device *icd)
719 {
720 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
721 struct pxa_camera_dev *pcdev = ici->priv;
722
723 BUG_ON(icd != pcdev->icd);
724
725 dev_info(&icd->dev, "PXA Camera driver detached from camera %d\n",
726 icd->devnum);
727
728 /* disable capture, disable interrupts */
729 CICR0 = 0x3ff;
730
731 /* Stop DMA engine */
732 DCSR(pcdev->dma_chans[0]) = 0;
733 DCSR(pcdev->dma_chans[1]) = 0;
734 DCSR(pcdev->dma_chans[2]) = 0;
735
736 icd->ops->release(icd);
737
738 pxa_camera_deactivate(pcdev);
739
740 pcdev->icd = NULL;
741 }
742
743 static int test_platform_param(struct pxa_camera_dev *pcdev,
744 unsigned char buswidth, unsigned long *flags)
745 {
746 /*
747 * Platform specified synchronization and pixel clock polarities are
748 * only a recommendation and are only used during probing. The PXA270
749 * quick capture interface supports both.
750 */
751 *flags = (pcdev->platform_flags & PXA_CAMERA_MASTER ?
752 SOCAM_MASTER : SOCAM_SLAVE) |
753 SOCAM_HSYNC_ACTIVE_HIGH |
754 SOCAM_HSYNC_ACTIVE_LOW |
755 SOCAM_VSYNC_ACTIVE_HIGH |
756 SOCAM_VSYNC_ACTIVE_LOW |
757 SOCAM_PCLK_SAMPLE_RISING |
758 SOCAM_PCLK_SAMPLE_FALLING;
759
760 /* If requested data width is supported by the platform, use it */
761 switch (buswidth) {
762 case 10:
763 if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10))
764 return -EINVAL;
765 *flags |= SOCAM_DATAWIDTH_10;
766 break;
767 case 9:
768 if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9))
769 return -EINVAL;
770 *flags |= SOCAM_DATAWIDTH_9;
771 break;
772 case 8:
773 if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8))
774 return -EINVAL;
775 *flags |= SOCAM_DATAWIDTH_8;
776 }
777
778 return 0;
779 }
780
781 static int pxa_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt)
782 {
783 struct soc_camera_host *ici =
784 to_soc_camera_host(icd->dev.parent);
785 struct pxa_camera_dev *pcdev = ici->priv;
786 unsigned long dw, bpp, bus_flags, camera_flags, common_flags;
787 u32 cicr0, cicr1, cicr4 = 0;
788 int ret = test_platform_param(pcdev, icd->buswidth, &bus_flags);
789
790 if (ret < 0)
791 return ret;
792
793 camera_flags = icd->ops->query_bus_param(icd);
794
795 common_flags = soc_camera_bus_param_compatible(camera_flags, bus_flags);
796 if (!common_flags)
797 return -EINVAL;
798
799 pcdev->channels = 1;
800
801 /* Make choises, based on platform preferences */
802 if ((common_flags & SOCAM_HSYNC_ACTIVE_HIGH) &&
803 (common_flags & SOCAM_HSYNC_ACTIVE_LOW)) {
804 if (pcdev->platform_flags & PXA_CAMERA_HSP)
805 common_flags &= ~SOCAM_HSYNC_ACTIVE_HIGH;
806 else
807 common_flags &= ~SOCAM_HSYNC_ACTIVE_LOW;
808 }
809
810 if ((common_flags & SOCAM_VSYNC_ACTIVE_HIGH) &&
811 (common_flags & SOCAM_VSYNC_ACTIVE_LOW)) {
812 if (pcdev->platform_flags & PXA_CAMERA_VSP)
813 common_flags &= ~SOCAM_VSYNC_ACTIVE_HIGH;
814 else
815 common_flags &= ~SOCAM_VSYNC_ACTIVE_LOW;
816 }
817
818 if ((common_flags & SOCAM_PCLK_SAMPLE_RISING) &&
819 (common_flags & SOCAM_PCLK_SAMPLE_FALLING)) {
820 if (pcdev->platform_flags & PXA_CAMERA_PCP)
821 common_flags &= ~SOCAM_PCLK_SAMPLE_RISING;
822 else
823 common_flags &= ~SOCAM_PCLK_SAMPLE_FALLING;
824 }
825
826 ret = icd->ops->set_bus_param(icd, common_flags);
827 if (ret < 0)
828 return ret;
829
830 /* Datawidth is now guaranteed to be equal to one of the three values.
831 * We fix bit-per-pixel equal to data-width... */
832 switch (common_flags & SOCAM_DATAWIDTH_MASK) {
833 case SOCAM_DATAWIDTH_10:
834 icd->buswidth = 10;
835 dw = 4;
836 bpp = 0x40;
837 break;
838 case SOCAM_DATAWIDTH_9:
839 icd->buswidth = 9;
840 dw = 3;
841 bpp = 0x20;
842 break;
843 default:
844 /* Actually it can only be 8 now,
845 * default is just to silence compiler warnings */
846 case SOCAM_DATAWIDTH_8:
847 icd->buswidth = 8;
848 dw = 2;
849 bpp = 0;
850 }
851
852 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
853 cicr4 |= CICR4_PCLK_EN;
854 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
855 cicr4 |= CICR4_MCLK_EN;
856 if (common_flags & SOCAM_PCLK_SAMPLE_FALLING)
857 cicr4 |= CICR4_PCP;
858 if (common_flags & SOCAM_HSYNC_ACTIVE_LOW)
859 cicr4 |= CICR4_HSP;
860 if (common_flags & SOCAM_VSYNC_ACTIVE_LOW)
861 cicr4 |= CICR4_VSP;
862
863 cicr0 = CICR0;
864 if (cicr0 & CICR0_ENB)
865 CICR0 = cicr0 & ~CICR0_ENB;
866
867 cicr1 = CICR1_PPL_VAL(icd->width - 1) | bpp | dw;
868
869 switch (pixfmt) {
870 case V4L2_PIX_FMT_YUV422P:
871 pcdev->channels = 3;
872 cicr1 |= CICR1_YCBCR_F;
873 case V4L2_PIX_FMT_YUYV:
874 cicr1 |= CICR1_COLOR_SP_VAL(2);
875 break;
876 case V4L2_PIX_FMT_RGB555:
877 cicr1 |= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) |
878 CICR1_TBIT | CICR1_COLOR_SP_VAL(1);
879 break;
880 case V4L2_PIX_FMT_RGB565:
881 cicr1 |= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2);
882 break;
883 }
884
885 CICR1 = cicr1;
886 CICR2 = 0;
887 CICR3 = CICR3_LPF_VAL(icd->height - 1) |
888 CICR3_BFW_VAL(min((unsigned short)255, icd->y_skip_top));
889 CICR4 = mclk_get_divisor(pcdev) | cicr4;
890
891 /* CIF interrupts are not used, only DMA */
892 CICR0 = (pcdev->platform_flags & PXA_CAMERA_MASTER ?
893 CICR0_SIM_MP : (CICR0_SL_CAP_EN | CICR0_SIM_SP)) |
894 CICR0_DMAEN | CICR0_IRQ_MASK | (cicr0 & CICR0_ENB);
895
896 return 0;
897 }
898
899 static int pxa_camera_try_bus_param(struct soc_camera_device *icd, __u32 pixfmt)
900 {
901 struct soc_camera_host *ici =
902 to_soc_camera_host(icd->dev.parent);
903 struct pxa_camera_dev *pcdev = ici->priv;
904 unsigned long bus_flags, camera_flags;
905 int ret = test_platform_param(pcdev, icd->buswidth, &bus_flags);
906
907 if (ret < 0)
908 return ret;
909
910 camera_flags = icd->ops->query_bus_param(icd);
911
912 return soc_camera_bus_param_compatible(camera_flags, bus_flags) ? 0 : -EINVAL;
913 }
914
915 static int pxa_camera_set_fmt_cap(struct soc_camera_device *icd,
916 __u32 pixfmt, struct v4l2_rect *rect)
917 {
918 return icd->ops->set_fmt_cap(icd, pixfmt, rect);
919 }
920
921 static int pxa_camera_try_fmt_cap(struct soc_camera_device *icd,
922 struct v4l2_format *f)
923 {
924 /* limit to pxa hardware capabilities */
925 if (f->fmt.pix.height < 32)
926 f->fmt.pix.height = 32;
927 if (f->fmt.pix.height > 2048)
928 f->fmt.pix.height = 2048;
929 if (f->fmt.pix.width < 48)
930 f->fmt.pix.width = 48;
931 if (f->fmt.pix.width > 2048)
932 f->fmt.pix.width = 2048;
933 f->fmt.pix.width &= ~0x01;
934
935 /* limit to sensor capabilities */
936 return icd->ops->try_fmt_cap(icd, f);
937 }
938
939 static int pxa_camera_reqbufs(struct soc_camera_file *icf,
940 struct v4l2_requestbuffers *p)
941 {
942 int i;
943
944 /* This is for locking debugging only. I removed spinlocks and now I
945 * check whether .prepare is ever called on a linked buffer, or whether
946 * a dma IRQ can occur for an in-work or unlinked buffer. Until now
947 * it hadn't triggered */
948 for (i = 0; i < p->count; i++) {
949 struct pxa_buffer *buf = container_of(icf->vb_vidq.bufs[i],
950 struct pxa_buffer, vb);
951 buf->inwork = 0;
952 INIT_LIST_HEAD(&buf->vb.queue);
953 }
954
955 return 0;
956 }
957
958 static unsigned int pxa_camera_poll(struct file *file, poll_table *pt)
959 {
960 struct soc_camera_file *icf = file->private_data;
961 struct pxa_buffer *buf;
962
963 buf = list_entry(icf->vb_vidq.stream.next, struct pxa_buffer,
964 vb.stream);
965
966 poll_wait(file, &buf->vb.done, pt);
967
968 if (buf->vb.state == VIDEOBUF_DONE ||
969 buf->vb.state == VIDEOBUF_ERROR)
970 return POLLIN|POLLRDNORM;
971
972 return 0;
973 }
974
975 static int pxa_camera_querycap(struct soc_camera_host *ici,
976 struct v4l2_capability *cap)
977 {
978 /* cap->name is set by the firendly caller:-> */
979 strlcpy(cap->card, pxa_cam_driver_description, sizeof(cap->card));
980 cap->version = PXA_CAM_VERSION_CODE;
981 cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
982
983 return 0;
984 }
985
986 static spinlock_t *pxa_camera_spinlock_alloc(struct soc_camera_file *icf)
987 {
988 struct soc_camera_host *ici =
989 to_soc_camera_host(icf->icd->dev.parent);
990 struct pxa_camera_dev *pcdev = ici->priv;
991
992 return &pcdev->lock;
993 }
994
995 static struct soc_camera_host_ops pxa_soc_camera_host_ops = {
996 .owner = THIS_MODULE,
997 .add = pxa_camera_add_device,
998 .remove = pxa_camera_remove_device,
999 .set_fmt_cap = pxa_camera_set_fmt_cap,
1000 .try_fmt_cap = pxa_camera_try_fmt_cap,
1001 .reqbufs = pxa_camera_reqbufs,
1002 .poll = pxa_camera_poll,
1003 .querycap = pxa_camera_querycap,
1004 .try_bus_param = pxa_camera_try_bus_param,
1005 .set_bus_param = pxa_camera_set_bus_param,
1006 .spinlock_alloc = pxa_camera_spinlock_alloc,
1007 };
1008
1009 /* Should be allocated dynamically too, but we have only one. */
1010 static struct soc_camera_host pxa_soc_camera_host = {
1011 .drv_name = PXA_CAM_DRV_NAME,
1012 .vbq_ops = &pxa_videobuf_ops,
1013 .msize = sizeof(struct pxa_buffer),
1014 .ops = &pxa_soc_camera_host_ops,
1015 };
1016
1017 static int pxa_camera_probe(struct platform_device *pdev)
1018 {
1019 struct pxa_camera_dev *pcdev;
1020 struct resource *res;
1021 void __iomem *base;
1022 unsigned int irq;
1023 int err = 0;
1024
1025 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1026 irq = platform_get_irq(pdev, 0);
1027 if (!res || !irq) {
1028 err = -ENODEV;
1029 goto exit;
1030 }
1031
1032 pcdev = kzalloc(sizeof(*pcdev), GFP_KERNEL);
1033 if (!pcdev) {
1034 dev_err(&pdev->dev, "Could not allocate pcdev\n");
1035 err = -ENOMEM;
1036 goto exit;
1037 }
1038
1039 pcdev->clk = clk_get(&pdev->dev, "CAMCLK");
1040 if (IS_ERR(pcdev->clk)) {
1041 err = PTR_ERR(pcdev->clk);
1042 goto exit_kfree;
1043 }
1044
1045 dev_set_drvdata(&pdev->dev, pcdev);
1046 pcdev->res = res;
1047
1048 pcdev->pdata = pdev->dev.platform_data;
1049 pcdev->platform_flags = pcdev->pdata->flags;
1050 if (!(pcdev->platform_flags & (PXA_CAMERA_DATAWIDTH_8 |
1051 PXA_CAMERA_DATAWIDTH_9 | PXA_CAMERA_DATAWIDTH_10))) {
1052 /* Platform hasn't set available data widths. This is bad.
1053 * Warn and use a default. */
1054 dev_warn(&pdev->dev, "WARNING! Platform hasn't set available "
1055 "data widths, using default 10 bit\n");
1056 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10;
1057 }
1058 pcdev->platform_mclk_10khz = pcdev->pdata->mclk_10khz;
1059 if (!pcdev->platform_mclk_10khz) {
1060 dev_warn(&pdev->dev,
1061 "mclk_10khz == 0! Please, fix your platform data. "
1062 "Using default 20MHz\n");
1063 pcdev->platform_mclk_10khz = 2000;
1064 }
1065
1066 INIT_LIST_HEAD(&pcdev->capture);
1067 spin_lock_init(&pcdev->lock);
1068
1069 /*
1070 * Request the regions.
1071 */
1072 if (!request_mem_region(res->start, res->end - res->start + 1,
1073 PXA_CAM_DRV_NAME)) {
1074 err = -EBUSY;
1075 goto exit_clk;
1076 }
1077
1078 base = ioremap(res->start, res->end - res->start + 1);
1079 if (!base) {
1080 err = -ENOMEM;
1081 goto exit_release;
1082 }
1083 pcdev->irq = irq;
1084 pcdev->base = base;
1085 pcdev->dev = &pdev->dev;
1086
1087 /* request dma */
1088 pcdev->dma_chans[0] = pxa_request_dma("CI_Y", DMA_PRIO_HIGH,
1089 pxa_camera_dma_irq_y, pcdev);
1090 if (pcdev->dma_chans[0] < 0) {
1091 dev_err(pcdev->dev, "Can't request DMA for Y\n");
1092 err = -ENOMEM;
1093 goto exit_iounmap;
1094 }
1095 dev_dbg(pcdev->dev, "got DMA channel %d\n", pcdev->dma_chans[0]);
1096
1097 pcdev->dma_chans[1] = pxa_request_dma("CI_U", DMA_PRIO_HIGH,
1098 pxa_camera_dma_irq_u, pcdev);
1099 if (pcdev->dma_chans[1] < 0) {
1100 dev_err(pcdev->dev, "Can't request DMA for U\n");
1101 err = -ENOMEM;
1102 goto exit_free_dma_y;
1103 }
1104 dev_dbg(pcdev->dev, "got DMA channel (U) %d\n", pcdev->dma_chans[1]);
1105
1106 pcdev->dma_chans[2] = pxa_request_dma("CI_V", DMA_PRIO_HIGH,
1107 pxa_camera_dma_irq_v, pcdev);
1108 if (pcdev->dma_chans[0] < 0) {
1109 dev_err(pcdev->dev, "Can't request DMA for V\n");
1110 err = -ENOMEM;
1111 goto exit_free_dma_u;
1112 }
1113 dev_dbg(pcdev->dev, "got DMA channel (V) %d\n", pcdev->dma_chans[2]);
1114
1115 DRCMR68 = pcdev->dma_chans[0] | DRCMR_MAPVLD;
1116 DRCMR69 = pcdev->dma_chans[1] | DRCMR_MAPVLD;
1117 DRCMR70 = pcdev->dma_chans[2] | DRCMR_MAPVLD;
1118
1119 /* request irq */
1120 err = request_irq(pcdev->irq, pxa_camera_irq, 0, PXA_CAM_DRV_NAME,
1121 pcdev);
1122 if (err) {
1123 dev_err(pcdev->dev, "Camera interrupt register failed \n");
1124 goto exit_free_dma;
1125 }
1126
1127 pxa_soc_camera_host.priv = pcdev;
1128 pxa_soc_camera_host.dev.parent = &pdev->dev;
1129 pxa_soc_camera_host.nr = pdev->id;
1130 err = soc_camera_host_register(&pxa_soc_camera_host);
1131 if (err)
1132 goto exit_free_irq;
1133
1134 return 0;
1135
1136 exit_free_irq:
1137 free_irq(pcdev->irq, pcdev);
1138 exit_free_dma:
1139 pxa_free_dma(pcdev->dma_chans[2]);
1140 exit_free_dma_u:
1141 pxa_free_dma(pcdev->dma_chans[1]);
1142 exit_free_dma_y:
1143 pxa_free_dma(pcdev->dma_chans[0]);
1144 exit_iounmap:
1145 iounmap(base);
1146 exit_release:
1147 release_mem_region(res->start, res->end - res->start + 1);
1148 exit_clk:
1149 clk_put(pcdev->clk);
1150 exit_kfree:
1151 kfree(pcdev);
1152 exit:
1153 return err;
1154 }
1155
1156 static int __devexit pxa_camera_remove(struct platform_device *pdev)
1157 {
1158 struct pxa_camera_dev *pcdev = platform_get_drvdata(pdev);
1159 struct resource *res;
1160
1161 clk_put(pcdev->clk);
1162
1163 pxa_free_dma(pcdev->dma_chans[0]);
1164 pxa_free_dma(pcdev->dma_chans[1]);
1165 pxa_free_dma(pcdev->dma_chans[2]);
1166 free_irq(pcdev->irq, pcdev);
1167
1168 soc_camera_host_unregister(&pxa_soc_camera_host);
1169
1170 iounmap(pcdev->base);
1171
1172 res = pcdev->res;
1173 release_mem_region(res->start, res->end - res->start + 1);
1174
1175 kfree(pcdev);
1176
1177 dev_info(&pdev->dev, "PXA Camera driver unloaded\n");
1178
1179 return 0;
1180 }
1181
1182 static struct platform_driver pxa_camera_driver = {
1183 .driver = {
1184 .name = PXA_CAM_DRV_NAME,
1185 },
1186 .probe = pxa_camera_probe,
1187 .remove = __exit_p(pxa_camera_remove),
1188 };
1189
1190
1191 static int __devinit pxa_camera_init(void)
1192 {
1193 return platform_driver_register(&pxa_camera_driver);
1194 }
1195
1196 static void __exit pxa_camera_exit(void)
1197 {
1198 return platform_driver_unregister(&pxa_camera_driver);
1199 }
1200
1201 module_init(pxa_camera_init);
1202 module_exit(pxa_camera_exit);
1203
1204 MODULE_DESCRIPTION("PXA27x SoC Camera Host driver");
1205 MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>");
1206 MODULE_LICENSE("GPL");
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