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ia64/kvm: compilation fix. export account_system_vtime.
[pv_ops_mirror.git] / drivers / mtd / nand / s3c2410.c
blobb34a460ab67915afe3812d6ced1410cfff6c16b7
1 /* linux/drivers/mtd/nand/s3c2410.c
2 *
3 * Copyright (c) 2004,2005 Simtec Electronics
4 * http://www.simtec.co.uk/products/SWLINUX/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * Samsung S3C2410/S3C240 NAND driver
8 *
9 * Changelog:
10 * 21-Sep-2004 BJD Initial version
11 * 23-Sep-2004 BJD Multiple device support
12 * 28-Sep-2004 BJD Fixed ECC placement for Hardware mode
13 * 12-Oct-2004 BJD Fixed errors in use of platform data
14 * 18-Feb-2005 BJD Fix sparse errors
15 * 14-Mar-2005 BJD Applied tglx's code reduction patch
16 * 02-May-2005 BJD Fixed s3c2440 support
17 * 02-May-2005 BJD Reduced hwcontrol decode
18 * 20-Jun-2005 BJD Updated s3c2440 support, fixed timing bug
19 * 08-Jul-2005 BJD Fix OOPS when no platform data supplied
20 * 20-Oct-2005 BJD Fix timing calculation bug
21 * 14-Jan-2006 BJD Allow clock to be stopped when idle
22 *
23 * $Id: s3c2410.c,v 1.23 2006/04/01 18:06:29 bjd Exp $
24 *
25 * This program is free software; you can redistribute it and/or modify
26 * it under the terms of the GNU General Public License as published by
27 * the Free Software Foundation; either version 2 of the License, or
28 * (at your option) any later version.
29 *
30 * This program is distributed in the hope that it will be useful,
31 * but WITHOUT ANY WARRANTY; without even the implied warranty of
32 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
33 * GNU General Public License for more details.
34 *
35 * You should have received a copy of the GNU General Public License
36 * along with this program; if not, write to the Free Software
37 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
38 */
39
40 #ifdef CONFIG_MTD_NAND_S3C2410_DEBUG
41 #define DEBUG
42 #endif
43
44 #include <linux/module.h>
45 #include <linux/types.h>
46 #include <linux/init.h>
47 #include <linux/kernel.h>
48 #include <linux/string.h>
49 #include <linux/ioport.h>
50 #include <linux/platform_device.h>
51 #include <linux/delay.h>
52 #include <linux/err.h>
53 #include <linux/slab.h>
54 #include <linux/clk.h>
55
56 #include <linux/mtd/mtd.h>
57 #include <linux/mtd/nand.h>
58 #include <linux/mtd/nand_ecc.h>
59 #include <linux/mtd/partitions.h>
60
61 #include <asm/io.h>
62
63 #include <asm/plat-s3c/regs-nand.h>
64 #include <asm/plat-s3c/nand.h>
65
66 #ifdef CONFIG_MTD_NAND_S3C2410_HWECC
67 static int hardware_ecc = 1;
68 #else
69 static int hardware_ecc = 0;
70 #endif
71
72 #ifdef CONFIG_MTD_NAND_S3C2410_CLKSTOP
73 static int clock_stop = 1;
74 #else
75 static const int clock_stop = 0;
76 #endif
77
78
79 /* new oob placement block for use with hardware ecc generation
80 */
81
82 static struct nand_ecclayout nand_hw_eccoob = {
83 .eccbytes = 3,
84 .eccpos = {0, 1, 2},
85 .oobfree = {{8, 8}}
86 };
87
88 /* controller and mtd information */
89
90 struct s3c2410_nand_info;
91
92 struct s3c2410_nand_mtd {
93 struct mtd_info mtd;
94 struct nand_chip chip;
95 struct s3c2410_nand_set *set;
96 struct s3c2410_nand_info *info;
97 int scan_res;
98 };
99
100 enum s3c_cpu_type {
101 TYPE_S3C2410,
102 TYPE_S3C2412,
103 TYPE_S3C2440,
104 };
105
106 /* overview of the s3c2410 nand state */
107
108 struct s3c2410_nand_info {
109 /* mtd info */
110 struct nand_hw_control controller;
111 struct s3c2410_nand_mtd *mtds;
112 struct s3c2410_platform_nand *platform;
113
114 /* device info */
115 struct device *device;
116 struct resource *area;
117 struct clk *clk;
118 void __iomem *regs;
119 void __iomem *sel_reg;
120 int sel_bit;
121 int mtd_count;
122 unsigned long save_sel;
123
124 enum s3c_cpu_type cpu_type;
125 };
126
127 /* conversion functions */
128
129 static struct s3c2410_nand_mtd *s3c2410_nand_mtd_toours(struct mtd_info *mtd)
130 {
131 return container_of(mtd, struct s3c2410_nand_mtd, mtd);
132 }
133
134 static struct s3c2410_nand_info *s3c2410_nand_mtd_toinfo(struct mtd_info *mtd)
135 {
136 return s3c2410_nand_mtd_toours(mtd)->info;
137 }
138
139 static struct s3c2410_nand_info *to_nand_info(struct platform_device *dev)
140 {
141 return platform_get_drvdata(dev);
142 }
143
144 static struct s3c2410_platform_nand *to_nand_plat(struct platform_device *dev)
145 {
146 return dev->dev.platform_data;
147 }
148
149 static inline int allow_clk_stop(struct s3c2410_nand_info *info)
150 {
151 return clock_stop;
152 }
153
154 /* timing calculations */
155
156 #define NS_IN_KHZ 1000000
157
158 static int s3c_nand_calc_rate(int wanted, unsigned long clk, int max)
159 {
160 int result;
161
162 result = (wanted * clk) / NS_IN_KHZ;
163 result++;
164
165 pr_debug("result %d from %ld, %d\n", result, clk, wanted);
166
167 if (result > max) {
168 printk("%d ns is too big for current clock rate %ld\n", wanted, clk);
169 return -1;
170 }
171
172 if (result < 1)
173 result = 1;
174
175 return result;
176 }
177
178 #define to_ns(ticks,clk) (((ticks) * NS_IN_KHZ) / (unsigned int)(clk))
179
180 /* controller setup */
181
182 static int s3c2410_nand_inithw(struct s3c2410_nand_info *info,
183 struct platform_device *pdev)
184 {
185 struct s3c2410_platform_nand *plat = to_nand_plat(pdev);
186 unsigned long clkrate = clk_get_rate(info->clk);
187 int tacls_max = (info->cpu_type == TYPE_S3C2412) ? 8 : 4;
188 int tacls, twrph0, twrph1;
189 unsigned long cfg = 0;
190
191 /* calculate the timing information for the controller */
192
193 clkrate /= 1000; /* turn clock into kHz for ease of use */
194
195 if (plat != NULL) {
196 tacls = s3c_nand_calc_rate(plat->tacls, clkrate, tacls_max);
197 twrph0 = s3c_nand_calc_rate(plat->twrph0, clkrate, 8);
198 twrph1 = s3c_nand_calc_rate(plat->twrph1, clkrate, 8);
199 } else {
200 /* default timings */
201 tacls = tacls_max;
202 twrph0 = 8;
203 twrph1 = 8;
204 }
205
206 if (tacls < 0 || twrph0 < 0 || twrph1 < 0) {
207 dev_err(info->device, "cannot get suitable timings\n");
208 return -EINVAL;
209 }
210
211 dev_info(info->device, "Tacls=%d, %dns Twrph0=%d %dns, Twrph1=%d %dns\n",
212 tacls, to_ns(tacls, clkrate), twrph0, to_ns(twrph0, clkrate), twrph1, to_ns(twrph1, clkrate));
213
214 switch (info->cpu_type) {
215 case TYPE_S3C2410:
216 cfg = S3C2410_NFCONF_EN;
217 cfg |= S3C2410_NFCONF_TACLS(tacls - 1);
218 cfg |= S3C2410_NFCONF_TWRPH0(twrph0 - 1);
219 cfg |= S3C2410_NFCONF_TWRPH1(twrph1 - 1);
220 break;
221
222 case TYPE_S3C2440:
223 case TYPE_S3C2412:
224 cfg = S3C2440_NFCONF_TACLS(tacls - 1);
225 cfg |= S3C2440_NFCONF_TWRPH0(twrph0 - 1);
226 cfg |= S3C2440_NFCONF_TWRPH1(twrph1 - 1);
227
228 /* enable the controller and de-assert nFCE */
229
230 writel(S3C2440_NFCONT_ENABLE, info->regs + S3C2440_NFCONT);
231 }
232
233 dev_dbg(info->device, "NF_CONF is 0x%lx\n", cfg);
234
235 writel(cfg, info->regs + S3C2410_NFCONF);
236 return 0;
237 }
238
239 /* select chip */
240
241 static void s3c2410_nand_select_chip(struct mtd_info *mtd, int chip)
242 {
243 struct s3c2410_nand_info *info;
244 struct s3c2410_nand_mtd *nmtd;
245 struct nand_chip *this = mtd->priv;
246 unsigned long cur;
247
248 nmtd = this->priv;
249 info = nmtd->info;
250
251 if (chip != -1 && allow_clk_stop(info))
252 clk_enable(info->clk);
253
254 cur = readl(info->sel_reg);
255
256 if (chip == -1) {
257 cur |= info->sel_bit;
258 } else {
259 if (nmtd->set != NULL && chip > nmtd->set->nr_chips) {
260 dev_err(info->device, "invalid chip %d\n", chip);
261 return;
262 }
263
264 if (info->platform != NULL) {
265 if (info->platform->select_chip != NULL)
266 (info->platform->select_chip) (nmtd->set, chip);
267 }
268
269 cur &= ~info->sel_bit;
270 }
271
272 writel(cur, info->sel_reg);
273
274 if (chip == -1 && allow_clk_stop(info))
275 clk_disable(info->clk);
276 }
277
278 /* s3c2410_nand_hwcontrol
279 *
280 * Issue command and address cycles to the chip
281 */
282
283 static void s3c2410_nand_hwcontrol(struct mtd_info *mtd, int cmd,
284 unsigned int ctrl)
285 {
286 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
287
288 if (cmd == NAND_CMD_NONE)
289 return;
290
291 if (ctrl & NAND_CLE)
292 writeb(cmd, info->regs + S3C2410_NFCMD);
293 else
294 writeb(cmd, info->regs + S3C2410_NFADDR);
295 }
296
297 /* command and control functions */
298
299 static void s3c2440_nand_hwcontrol(struct mtd_info *mtd, int cmd,
300 unsigned int ctrl)
301 {
302 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
303
304 if (cmd == NAND_CMD_NONE)
305 return;
306
307 if (ctrl & NAND_CLE)
308 writeb(cmd, info->regs + S3C2440_NFCMD);
309 else
310 writeb(cmd, info->regs + S3C2440_NFADDR);
311 }
312
313 /* s3c2410_nand_devready()
314 *
315 * returns 0 if the nand is busy, 1 if it is ready
316 */
317
318 static int s3c2410_nand_devready(struct mtd_info *mtd)
319 {
320 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
321 return readb(info->regs + S3C2410_NFSTAT) & S3C2410_NFSTAT_BUSY;
322 }
323
324 static int s3c2440_nand_devready(struct mtd_info *mtd)
325 {
326 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
327 return readb(info->regs + S3C2440_NFSTAT) & S3C2440_NFSTAT_READY;
328 }
329
330 static int s3c2412_nand_devready(struct mtd_info *mtd)
331 {
332 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
333 return readb(info->regs + S3C2412_NFSTAT) & S3C2412_NFSTAT_READY;
334 }
335
336 /* ECC handling functions */
337
338 static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat,
339 u_char *read_ecc, u_char *calc_ecc)
340 {
341 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
342 unsigned int diff0, diff1, diff2;
343 unsigned int bit, byte;
344
345 pr_debug("%s(%p,%p,%p,%p)\n", __func__, mtd, dat, read_ecc, calc_ecc);
346
347 diff0 = read_ecc[0] ^ calc_ecc[0];
348 diff1 = read_ecc[1] ^ calc_ecc[1];
349 diff2 = read_ecc[2] ^ calc_ecc[2];
350
351 pr_debug("%s: rd %02x%02x%02x calc %02x%02x%02x diff %02x%02x%02x\n",
352 __func__,
353 read_ecc[0], read_ecc[1], read_ecc[2],
354 calc_ecc[0], calc_ecc[1], calc_ecc[2],
355 diff0, diff1, diff2);
356
357 if (diff0 == 0 && diff1 == 0 && diff2 == 0)
358 return 0; /* ECC is ok */
359
360 /* sometimes people do not think about using the ECC, so check
361 * to see if we have an 0xff,0xff,0xff read ECC and then ignore
362 * the error, on the assumption that this is an un-eccd page.
363 */
364 if (read_ecc[0] == 0xff && read_ecc[1] == 0xff && read_ecc[2] == 0xff
365 && info->platform->ignore_unset_ecc)
366 return 0;
367
368 /* Can we correct this ECC (ie, one row and column change).
369 * Note, this is similar to the 256 error code on smartmedia */
370
371 if (((diff0 ^ (diff0 >> 1)) & 0x55) == 0x55 &&
372 ((diff1 ^ (diff1 >> 1)) & 0x55) == 0x55 &&
373 ((diff2 ^ (diff2 >> 1)) & 0x55) == 0x55) {
374 /* calculate the bit position of the error */
375
376 bit = ((diff2 >> 3) & 1) |
377 ((diff2 >> 4) & 2) |
378 ((diff2 >> 5) & 4);
379
380 /* calculate the byte position of the error */
381
382 byte = ((diff2 << 7) & 0x100) |
383 ((diff1 << 0) & 0x80) |
384 ((diff1 << 1) & 0x40) |
385 ((diff1 << 2) & 0x20) |
386 ((diff1 << 3) & 0x10) |
387 ((diff0 >> 4) & 0x08) |
388 ((diff0 >> 3) & 0x04) |
389 ((diff0 >> 2) & 0x02) |
390 ((diff0 >> 1) & 0x01);
391
392 dev_dbg(info->device, "correcting error bit %d, byte %d\n",
393 bit, byte);
394
395 dat[byte] ^= (1 << bit);
396 return 1;
397 }
398
399 /* if there is only one bit difference in the ECC, then
400 * one of only a row or column parity has changed, which
401 * means the error is most probably in the ECC itself */
402
403 diff0 |= (diff1 << 8);
404 diff0 |= (diff2 << 16);
405
406 if ((diff0 & ~(1<<fls(diff0))) == 0)
407 return 1;
408
409 return -1;
410 }
411
412 /* ECC functions
413 *
414 * These allow the s3c2410 and s3c2440 to use the controller's ECC
415 * generator block to ECC the data as it passes through]
416 */
417
418 static void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode)
419 {
420 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
421 unsigned long ctrl;
422
423 ctrl = readl(info->regs + S3C2410_NFCONF);
424 ctrl |= S3C2410_NFCONF_INITECC;
425 writel(ctrl, info->regs + S3C2410_NFCONF);
426 }
427
428 static void s3c2412_nand_enable_hwecc(struct mtd_info *mtd, int mode)
429 {
430 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
431 unsigned long ctrl;
432
433 ctrl = readl(info->regs + S3C2440_NFCONT);
434 writel(ctrl | S3C2412_NFCONT_INIT_MAIN_ECC, info->regs + S3C2440_NFCONT);
435 }
436
437 static void s3c2440_nand_enable_hwecc(struct mtd_info *mtd, int mode)
438 {
439 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
440 unsigned long ctrl;
441
442 ctrl = readl(info->regs + S3C2440_NFCONT);
443 writel(ctrl | S3C2440_NFCONT_INITECC, info->regs + S3C2440_NFCONT);
444 }
445
446 static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
447 {
448 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
449
450 ecc_code[0] = readb(info->regs + S3C2410_NFECC + 0);
451 ecc_code[1] = readb(info->regs + S3C2410_NFECC + 1);
452 ecc_code[2] = readb(info->regs + S3C2410_NFECC + 2);
453
454 pr_debug("%s: returning ecc %02x%02x%02x\n", __func__,
455 ecc_code[0], ecc_code[1], ecc_code[2]);
456
457 return 0;
458 }
459
460 static int s3c2412_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
461 {
462 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
463 unsigned long ecc = readl(info->regs + S3C2412_NFMECC0);
464
465 ecc_code[0] = ecc;
466 ecc_code[1] = ecc >> 8;
467 ecc_code[2] = ecc >> 16;
468
469 pr_debug("calculate_ecc: returning ecc %02x,%02x,%02x\n", ecc_code[0], ecc_code[1], ecc_code[2]);
470
471 return 0;
472 }
473
474 static int s3c2440_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
475 {
476 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
477 unsigned long ecc = readl(info->regs + S3C2440_NFMECC0);
478
479 ecc_code[0] = ecc;
480 ecc_code[1] = ecc >> 8;
481 ecc_code[2] = ecc >> 16;
482
483 pr_debug("%s: returning ecc %06lx\n", __func__, ecc & 0xffffff);
484
485 return 0;
486 }
487
488 /* over-ride the standard functions for a little more speed. We can
489 * use read/write block to move the data buffers to/from the controller
490 */
491
492 static void s3c2410_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
493 {
494 struct nand_chip *this = mtd->priv;
495 readsb(this->IO_ADDR_R, buf, len);
496 }
497
498 static void s3c2440_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
499 {
500 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
501 readsl(info->regs + S3C2440_NFDATA, buf, len / 4);
502 }
503
504 static void s3c2410_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
505 {
506 struct nand_chip *this = mtd->priv;
507 writesb(this->IO_ADDR_W, buf, len);
508 }
509
510 static void s3c2440_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
511 {
512 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
513 writesl(info->regs + S3C2440_NFDATA, buf, len / 4);
514 }
515
516 /* device management functions */
517
518 static int s3c2410_nand_remove(struct platform_device *pdev)
519 {
520 struct s3c2410_nand_info *info = to_nand_info(pdev);
521
522 platform_set_drvdata(pdev, NULL);
523
524 if (info == NULL)
525 return 0;
526
527 /* first thing we need to do is release all our mtds
528 * and their partitions, then go through freeing the
529 * resources used
530 */
531
532 if (info->mtds != NULL) {
533 struct s3c2410_nand_mtd *ptr = info->mtds;
534 int mtdno;
535
536 for (mtdno = 0; mtdno < info->mtd_count; mtdno++, ptr++) {
537 pr_debug("releasing mtd %d (%p)\n", mtdno, ptr);
538 nand_release(&ptr->mtd);
539 }
540
541 kfree(info->mtds);
542 }
543
544 /* free the common resources */
545
546 if (info->clk != NULL && !IS_ERR(info->clk)) {
547 if (!allow_clk_stop(info))
548 clk_disable(info->clk);
549 clk_put(info->clk);
550 }
551
552 if (info->regs != NULL) {
553 iounmap(info->regs);
554 info->regs = NULL;
555 }
556
557 if (info->area != NULL) {
558 release_resource(info->area);
559 kfree(info->area);
560 info->area = NULL;
561 }
562
563 kfree(info);
564
565 return 0;
566 }
567
568 #ifdef CONFIG_MTD_PARTITIONS
569 static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info,
570 struct s3c2410_nand_mtd *mtd,
571 struct s3c2410_nand_set *set)
572 {
573 if (set == NULL)
574 return add_mtd_device(&mtd->mtd);
575
576 if (set->nr_partitions > 0 && set->partitions != NULL) {
577 return add_mtd_partitions(&mtd->mtd, set->partitions, set->nr_partitions);
578 }
579
580 return add_mtd_device(&mtd->mtd);
581 }
582 #else
583 static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info,
584 struct s3c2410_nand_mtd *mtd,
585 struct s3c2410_nand_set *set)
586 {
587 return add_mtd_device(&mtd->mtd);
588 }
589 #endif
590
591 /* s3c2410_nand_init_chip
592 *
593 * init a single instance of an chip
594 */
595
596 static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info,
597 struct s3c2410_nand_mtd *nmtd,
598 struct s3c2410_nand_set *set)
599 {
600 struct nand_chip *chip = &nmtd->chip;
601 void __iomem *regs = info->regs;
602
603 chip->write_buf = s3c2410_nand_write_buf;
604 chip->read_buf = s3c2410_nand_read_buf;
605 chip->select_chip = s3c2410_nand_select_chip;
606 chip->chip_delay = 50;
607 chip->priv = nmtd;
608 chip->options = 0;
609 chip->controller = &info->controller;
610
611 switch (info->cpu_type) {
612 case TYPE_S3C2410:
613 chip->IO_ADDR_W = regs + S3C2410_NFDATA;
614 info->sel_reg = regs + S3C2410_NFCONF;
615 info->sel_bit = S3C2410_NFCONF_nFCE;
616 chip->cmd_ctrl = s3c2410_nand_hwcontrol;
617 chip->dev_ready = s3c2410_nand_devready;
618 break;
619
620 case TYPE_S3C2440:
621 chip->IO_ADDR_W = regs + S3C2440_NFDATA;
622 info->sel_reg = regs + S3C2440_NFCONT;
623 info->sel_bit = S3C2440_NFCONT_nFCE;
624 chip->cmd_ctrl = s3c2440_nand_hwcontrol;
625 chip->dev_ready = s3c2440_nand_devready;
626 chip->read_buf = s3c2440_nand_read_buf;
627 chip->write_buf = s3c2440_nand_write_buf;
628 break;
629
630 case TYPE_S3C2412:
631 chip->IO_ADDR_W = regs + S3C2440_NFDATA;
632 info->sel_reg = regs + S3C2440_NFCONT;
633 info->sel_bit = S3C2412_NFCONT_nFCE0;
634 chip->cmd_ctrl = s3c2440_nand_hwcontrol;
635 chip->dev_ready = s3c2412_nand_devready;
636
637 if (readl(regs + S3C2410_NFCONF) & S3C2412_NFCONF_NANDBOOT)
638 dev_info(info->device, "System booted from NAND\n");
639
640 break;
641 }
642
643 chip->IO_ADDR_R = chip->IO_ADDR_W;
644
645 nmtd->info = info;
646 nmtd->mtd.priv = chip;
647 nmtd->mtd.owner = THIS_MODULE;
648 nmtd->set = set;
649
650 if (hardware_ecc) {
651 chip->ecc.calculate = s3c2410_nand_calculate_ecc;
652 chip->ecc.correct = s3c2410_nand_correct_data;
653 chip->ecc.mode = NAND_ECC_HW;
654
655 switch (info->cpu_type) {
656 case TYPE_S3C2410:
657 chip->ecc.hwctl = s3c2410_nand_enable_hwecc;
658 chip->ecc.calculate = s3c2410_nand_calculate_ecc;
659 break;
660
661 case TYPE_S3C2412:
662 chip->ecc.hwctl = s3c2412_nand_enable_hwecc;
663 chip->ecc.calculate = s3c2412_nand_calculate_ecc;
664 break;
665
666 case TYPE_S3C2440:
667 chip->ecc.hwctl = s3c2440_nand_enable_hwecc;
668 chip->ecc.calculate = s3c2440_nand_calculate_ecc;
669 break;
670
671 }
672 } else {
673 chip->ecc.mode = NAND_ECC_SOFT;
674 }
675
676 if (set->ecc_layout != NULL)
677 chip->ecc.layout = set->ecc_layout;
678
679 if (set->disable_ecc)
680 chip->ecc.mode = NAND_ECC_NONE;
681 }
682
683 /* s3c2410_nand_update_chip
684 *
685 * post-probe chip update, to change any items, such as the
686 * layout for large page nand
687 */
688
689 static void s3c2410_nand_update_chip(struct s3c2410_nand_info *info,
690 struct s3c2410_nand_mtd *nmtd)
691 {
692 struct nand_chip *chip = &nmtd->chip;
693
694 printk("%s: chip %p: %d\n", __func__, chip, chip->page_shift);
695
696 if (hardware_ecc) {
697 /* change the behaviour depending on wether we are using
698 * the large or small page nand device */
699
700 if (chip->page_shift > 10) {
701 chip->ecc.size = 256;
702 chip->ecc.bytes = 3;
703 } else {
704 chip->ecc.size = 512;
705 chip->ecc.bytes = 3;
706 chip->ecc.layout = &nand_hw_eccoob;
707 }
708 }
709 }
710
711 /* s3c2410_nand_probe
712 *
713 * called by device layer when it finds a device matching
714 * one our driver can handled. This code checks to see if
715 * it can allocate all necessary resources then calls the
716 * nand layer to look for devices
717 */
718
719 static int s3c24xx_nand_probe(struct platform_device *pdev,
720 enum s3c_cpu_type cpu_type)
721 {
722 struct s3c2410_platform_nand *plat = to_nand_plat(pdev);
723 struct s3c2410_nand_info *info;
724 struct s3c2410_nand_mtd *nmtd;
725 struct s3c2410_nand_set *sets;
726 struct resource *res;
727 int err = 0;
728 int size;
729 int nr_sets;
730 int setno;
731
732 pr_debug("s3c2410_nand_probe(%p)\n", pdev);
733
734 info = kmalloc(sizeof(*info), GFP_KERNEL);
735 if (info == NULL) {
736 dev_err(&pdev->dev, "no memory for flash info\n");
737 err = -ENOMEM;
738 goto exit_error;
739 }
740
741 memzero(info, sizeof(*info));
742 platform_set_drvdata(pdev, info);
743
744 spin_lock_init(&info->controller.lock);
745 init_waitqueue_head(&info->controller.wq);
746
747 /* get the clock source and enable it */
748
749 info->clk = clk_get(&pdev->dev, "nand");
750 if (IS_ERR(info->clk)) {
751 dev_err(&pdev->dev, "failed to get clock\n");
752 err = -ENOENT;
753 goto exit_error;
754 }
755
756 clk_enable(info->clk);
757
758 /* allocate and map the resource */
759
760 /* currently we assume we have the one resource */
761 res = pdev->resource;
762 size = res->end - res->start + 1;
763
764 info->area = request_mem_region(res->start, size, pdev->name);
765
766 if (info->area == NULL) {
767 dev_err(&pdev->dev, "cannot reserve register region\n");
768 err = -ENOENT;
769 goto exit_error;
770 }
771
772 info->device = &pdev->dev;
773 info->platform = plat;
774 info->regs = ioremap(res->start, size);
775 info->cpu_type = cpu_type;
776
777 if (info->regs == NULL) {
778 dev_err(&pdev->dev, "cannot reserve register region\n");
779 err = -EIO;
780 goto exit_error;
781 }
782
783 dev_dbg(&pdev->dev, "mapped registers at %p\n", info->regs);
784
785 /* initialise the hardware */
786
787 err = s3c2410_nand_inithw(info, pdev);
788 if (err != 0)
789 goto exit_error;
790
791 sets = (plat != NULL) ? plat->sets : NULL;
792 nr_sets = (plat != NULL) ? plat->nr_sets : 1;
793
794 info->mtd_count = nr_sets;
795
796 /* allocate our information */
797
798 size = nr_sets * sizeof(*info->mtds);
799 info->mtds = kmalloc(size, GFP_KERNEL);
800 if (info->mtds == NULL) {
801 dev_err(&pdev->dev, "failed to allocate mtd storage\n");
802 err = -ENOMEM;
803 goto exit_error;
804 }
805
806 memzero(info->mtds, size);
807
808 /* initialise all possible chips */
809
810 nmtd = info->mtds;
811
812 for (setno = 0; setno < nr_sets; setno++, nmtd++) {
813 pr_debug("initialising set %d (%p, info %p)\n", setno, nmtd, info);
814
815 s3c2410_nand_init_chip(info, nmtd, sets);
816
817 nmtd->scan_res = nand_scan_ident(&nmtd->mtd,
818 (sets) ? sets->nr_chips : 1);
819
820 if (nmtd->scan_res == 0) {
821 s3c2410_nand_update_chip(info, nmtd);
822 nand_scan_tail(&nmtd->mtd);
823 s3c2410_nand_add_partition(info, nmtd, sets);
824 }
825
826 if (sets != NULL)
827 sets++;
828 }
829
830 if (allow_clk_stop(info)) {
831 dev_info(&pdev->dev, "clock idle support enabled\n");
832 clk_disable(info->clk);
833 }
834
835 pr_debug("initialised ok\n");
836 return 0;
837
838 exit_error:
839 s3c2410_nand_remove(pdev);
840
841 if (err == 0)
842 err = -EINVAL;
843 return err;
844 }
845
846 /* PM Support */
847 #ifdef CONFIG_PM
848
849 static int s3c24xx_nand_suspend(struct platform_device *dev, pm_message_t pm)
850 {
851 struct s3c2410_nand_info *info = platform_get_drvdata(dev);
852
853 if (info) {
854 info->save_sel = readl(info->sel_reg);
855
856 /* For the moment, we must ensure nFCE is high during
857 * the time we are suspended. This really should be
858 * handled by suspending the MTDs we are using, but
859 * that is currently not the case. */
860
861 writel(info->save_sel | info->sel_bit, info->sel_reg);
862
863 if (!allow_clk_stop(info))
864 clk_disable(info->clk);
865 }
866
867 return 0;
868 }
869
870 static int s3c24xx_nand_resume(struct platform_device *dev)
871 {
872 struct s3c2410_nand_info *info = platform_get_drvdata(dev);
873 unsigned long sel;
874
875 if (info) {
876 clk_enable(info->clk);
877 s3c2410_nand_inithw(info, dev);
878
879 /* Restore the state of the nFCE line. */
880
881 sel = readl(info->sel_reg);
882 sel &= ~info->sel_bit;
883 sel |= info->save_sel & info->sel_bit;
884 writel(sel, info->sel_reg);
885
886 if (allow_clk_stop(info))
887 clk_disable(info->clk);
888 }
889
890 return 0;
891 }
892
893 #else
894 #define s3c24xx_nand_suspend NULL
895 #define s3c24xx_nand_resume NULL
896 #endif
897
898 /* driver device registration */
899
900 static int s3c2410_nand_probe(struct platform_device *dev)
901 {
902 return s3c24xx_nand_probe(dev, TYPE_S3C2410);
903 }
904
905 static int s3c2440_nand_probe(struct platform_device *dev)
906 {
907 return s3c24xx_nand_probe(dev, TYPE_S3C2440);
908 }
909
910 static int s3c2412_nand_probe(struct platform_device *dev)
911 {
912 return s3c24xx_nand_probe(dev, TYPE_S3C2412);
913 }
914
915 static struct platform_driver s3c2410_nand_driver = {
916 .probe = s3c2410_nand_probe,
917 .remove = s3c2410_nand_remove,
918 .suspend = s3c24xx_nand_suspend,
919 .resume = s3c24xx_nand_resume,
920 .driver = {
921 .name = "s3c2410-nand",
922 .owner = THIS_MODULE,
923 },
924 };
925
926 static struct platform_driver s3c2440_nand_driver = {
927 .probe = s3c2440_nand_probe,
928 .remove = s3c2410_nand_remove,
929 .suspend = s3c24xx_nand_suspend,
930 .resume = s3c24xx_nand_resume,
931 .driver = {
932 .name = "s3c2440-nand",
933 .owner = THIS_MODULE,
934 },
935 };
936
937 static struct platform_driver s3c2412_nand_driver = {
938 .probe = s3c2412_nand_probe,
939 .remove = s3c2410_nand_remove,
940 .suspend = s3c24xx_nand_suspend,
941 .resume = s3c24xx_nand_resume,
942 .driver = {
943 .name = "s3c2412-nand",
944 .owner = THIS_MODULE,
945 },
946 };
947
948 static int __init s3c2410_nand_init(void)
949 {
950 printk("S3C24XX NAND Driver, (c) 2004 Simtec Electronics\n");
951
952 platform_driver_register(&s3c2412_nand_driver);
953 platform_driver_register(&s3c2440_nand_driver);
954 return platform_driver_register(&s3c2410_nand_driver);
955 }
956
957 static void __exit s3c2410_nand_exit(void)
958 {
959 platform_driver_unregister(&s3c2412_nand_driver);
960 platform_driver_unregister(&s3c2440_nand_driver);
961 platform_driver_unregister(&s3c2410_nand_driver);
962 }
963
964 module_init(s3c2410_nand_init);
965 module_exit(s3c2410_nand_exit);
966
967 MODULE_LICENSE("GPL");
968 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
969 MODULE_DESCRIPTION("S3C24XX MTD NAND driver");
970 MODULE_ALIAS("platform:s3c2410-nand");
971 MODULE_ALIAS("platform:s3c2412-nand");
972 MODULE_ALIAS("platform:s3c2440-nand");
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