drivers/net/cxgb3/adapter.h

   1 /*
   2  * Copyright (c) 2003-2007 Chelsio, Inc. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 /* This file should not be included directly.  Include common.h instead. */
  34
  35 #ifndef __T3_ADAPTER_H__
  36 #define __T3_ADAPTER_H__
  37
  38 #include <linux/pci.h>
  39 #include <linux/spinlock.h>
  40 #include <linux/interrupt.h>
  41 #include <linux/timer.h>
  42 #include <linux/cache.h>
  43 #include <linux/mutex.h>
  44 #include <linux/bitops.h>
  45 #include "t3cdev.h"
  46 #include <asm/io.h>
  47
  48 struct vlan_group;
  49 struct adapter;
  50 struct sge_qset;
  51
  52 struct port_info {
  53         struct adapter *adapter;
  54         struct vlan_group *vlan_grp;
  55         struct sge_qset *qs;
  56         const struct port_type_info *port_type;
  57         u8 port_id;
  58         u8 rx_csum_offload;
  59         u8 nqsets;
  60         u8 first_qset;
  61         struct cphy phy;
  62         struct cmac mac;
  63         struct link_config link_config;
  64         struct net_device_stats netstats;
  65         int activity;
  66 };
  67
  68 enum {                          /* adapter flags */
  69         FULL_INIT_DONE = (1 << 0),
  70         USING_MSI = (1 << 1),
  71         USING_MSIX = (1 << 2),
  72         QUEUES_BOUND = (1 << 3),
  73         TP_PARITY_INIT = (1 << 4),
  74         NAPI_INIT = (1 << 5),
  75 };
  76
  77 struct fl_pg_chunk {
  78         struct page *page;
  79         void *va;
  80         unsigned int offset;
  81 };
  82
  83 struct rx_desc;
  84 struct rx_sw_desc;
  85
  86 struct sge_fl {                     /* SGE per free-buffer list state */
  87         unsigned int buf_size;      /* size of each Rx buffer */
  88         unsigned int credits;       /* # of available Rx buffers */
  89         unsigned int size;          /* capacity of free list */
  90         unsigned int cidx;          /* consumer index */
  91         unsigned int pidx;          /* producer index */
  92         unsigned int gen;           /* free list generation */
  93         struct fl_pg_chunk pg_chunk;/* page chunk cache */
  94         unsigned int use_pages;     /* whether FL uses pages or sk_buffs */
  95         struct rx_desc *desc;       /* address of HW Rx descriptor ring */
  96         struct rx_sw_desc *sdesc;   /* address of SW Rx descriptor ring */
  97         dma_addr_t   phys_addr;     /* physical address of HW ring start */
  98         unsigned int cntxt_id;      /* SGE context id for the free list */
  99         unsigned long empty;        /* # of times queue ran out of buffers */
 100         unsigned long alloc_failed; /* # of times buffer allocation failed */
 101 };
 102
 103 /*
 104  * Bundle size for grouping offload RX packets for delivery to the stack.
 105  * Don't make this too big as we do prefetch on each packet in a bundle.
 106  */
 107 # define RX_BUNDLE_SIZE 8
 108
 109 struct rsp_desc;
 110
 111 struct sge_rspq {               /* state for an SGE response queue */
 112         unsigned int credits;   /* # of pending response credits */
 113         unsigned int size;      /* capacity of response queue */
 114         unsigned int cidx;      /* consumer index */
 115         unsigned int gen;       /* current generation bit */
 116         unsigned int polling;   /* is the queue serviced through NAPI? */
 117         unsigned int holdoff_tmr;       /* interrupt holdoff timer in 100ns */
 118         unsigned int next_holdoff;      /* holdoff time for next interrupt */
 119         struct rsp_desc *desc;  /* address of HW response ring */
 120         dma_addr_t phys_addr;   /* physical address of the ring */
 121         unsigned int cntxt_id;  /* SGE context id for the response q */
 122         spinlock_t lock;        /* guards response processing */
 123         struct sk_buff *rx_head;        /* offload packet receive queue head */
 124         struct sk_buff *rx_tail;        /* offload packet receive queue tail */
 125
 126         unsigned long offload_pkts;
 127         unsigned long offload_bundles;
 128         unsigned long eth_pkts; /* # of ethernet packets */
 129         unsigned long pure_rsps;        /* # of pure (non-data) responses */
 130         unsigned long imm_data; /* responses with immediate data */
 131         unsigned long rx_drops; /* # of packets dropped due to no mem */
 132         unsigned long async_notif; /* # of asynchronous notification events */
 133         unsigned long empty;    /* # of times queue ran out of credits */
 134         unsigned long nomem;    /* # of responses deferred due to no mem */
 135         unsigned long unhandled_irqs;   /* # of spurious intrs */
 136         unsigned long starved;
 137         unsigned long restarted;
 138 };
 139
 140 struct tx_desc;
 141 struct tx_sw_desc;
 142
 143 struct sge_txq {                /* state for an SGE Tx queue */
 144         unsigned long flags;    /* HW DMA fetch status */
 145         unsigned int in_use;    /* # of in-use Tx descriptors */
 146         unsigned int size;      /* # of descriptors */
 147         unsigned int processed; /* total # of descs HW has processed */
 148         unsigned int cleaned;   /* total # of descs SW has reclaimed */
 149         unsigned int stop_thres;        /* SW TX queue suspend threshold */
 150         unsigned int cidx;      /* consumer index */
 151         unsigned int pidx;      /* producer index */
 152         unsigned int gen;       /* current value of generation bit */
 153         unsigned int unacked;   /* Tx descriptors used since last COMPL */
 154         struct tx_desc *desc;   /* address of HW Tx descriptor ring */
 155         struct tx_sw_desc *sdesc;       /* address of SW Tx descriptor ring */
 156         spinlock_t lock;        /* guards enqueueing of new packets */
 157         unsigned int token;     /* WR token */
 158         dma_addr_t phys_addr;   /* physical address of the ring */
 159         struct sk_buff_head sendq;      /* List of backpressured offload packets */
 160         struct tasklet_struct qresume_tsk;      /* restarts the queue */
 161         unsigned int cntxt_id;  /* SGE context id for the Tx q */
 162         unsigned long stops;    /* # of times q has been stopped */
 163         unsigned long restarts; /* # of queue restarts */
 164 };
 165
 166 enum {                          /* per port SGE statistics */
 167         SGE_PSTAT_TSO,          /* # of TSO requests */
 168         SGE_PSTAT_RX_CSUM_GOOD, /* # of successful RX csum offloads */
 169         SGE_PSTAT_TX_CSUM,      /* # of TX checksum offloads */
 170         SGE_PSTAT_VLANEX,       /* # of VLAN tag extractions */
 171         SGE_PSTAT_VLANINS,      /* # of VLAN tag insertions */
 172
 173         SGE_PSTAT_MAX           /* must be last */
 174 };
 175
 176 struct sge_qset {               /* an SGE queue set */
 177         struct adapter *adap;
 178         struct napi_struct napi;
 179         struct sge_rspq rspq;
 180         struct sge_fl fl[SGE_RXQ_PER_SET];
 181         struct sge_txq txq[SGE_TXQ_PER_SET];
 182         struct net_device *netdev;
 183         unsigned long txq_stopped;      /* which Tx queues are stopped */
 184         struct timer_list tx_reclaim_timer;     /* reclaims TX buffers */
 185         unsigned long port_stats[SGE_PSTAT_MAX];
 186 } ____cacheline_aligned;
 187
 188 struct sge {
 189         struct sge_qset qs[SGE_QSETS];
 190         spinlock_t reg_lock;    /* guards non-atomic SGE registers (eg context) */
 191 };
 192
 193 struct adapter {
 194         struct t3cdev tdev;
 195         struct list_head adapter_list;
 196         void __iomem *regs;
 197         struct pci_dev *pdev;
 198         unsigned long registered_device_map;
 199         unsigned long open_device_map;
 200         unsigned long flags;
 201
 202         const char *name;
 203         int msg_enable;
 204         unsigned int mmio_len;
 205
 206         struct adapter_params params;
 207         unsigned int slow_intr_mask;
 208         unsigned long irq_stats[IRQ_NUM_STATS];
 209
 210         struct {
 211                 unsigned short vec;
 212                 char desc[22];
 213         } msix_info[SGE_QSETS + 1];
 214
 215         /* T3 modules */
 216         struct sge sge;
 217         struct mc7 pmrx;
 218         struct mc7 pmtx;
 219         struct mc7 cm;
 220         struct mc5 mc5;
 221
 222         struct net_device *port[MAX_NPORTS];
 223         unsigned int check_task_cnt;
 224         struct delayed_work adap_check_task;
 225         struct work_struct ext_intr_handler_task;
 226
 227         struct dentry *debugfs_root;
 228
 229         struct mutex mdio_lock;
 230         spinlock_t stats_lock;
 231         spinlock_t work_lock;
 232 };
 233
 234 static inline u32 t3_read_reg(struct adapter *adapter, u32 reg_addr)
 235 {
 236         u32 val = readl(adapter->regs + reg_addr);
 237
 238         CH_DBG(adapter, MMIO, "read register 0x%x value 0x%x\n", reg_addr, val);
 239         return val;
 240 }
 241
 242 static inline void t3_write_reg(struct adapter *adapter, u32 reg_addr, u32 val)
 243 {
 244         CH_DBG(adapter, MMIO, "setting register 0x%x to 0x%x\n", reg_addr, val);
 245         writel(val, adapter->regs + reg_addr);
 246 }
 247
 248 static inline struct port_info *adap2pinfo(struct adapter *adap, int idx)
 249 {
 250         return netdev_priv(adap->port[idx]);
 251 }
 252
 253 #define OFFLOAD_DEVMAP_BIT 15
 254
 255 #define tdev2adap(d) container_of(d, struct adapter, tdev)
 256
 257 static inline int offload_running(struct adapter *adapter)
 258 {
 259         return test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map);
 260 }
 261
 262 int t3_offload_tx(struct t3cdev *tdev, struct sk_buff *skb);
 263
 264 void t3_os_ext_intr_handler(struct adapter *adapter);
 265 void t3_os_link_changed(struct adapter *adapter, int port_id, int link_status,
 266                         int speed, int duplex, int fc);
 267
 268 void t3_sge_start(struct adapter *adap);
 269 void t3_sge_stop(struct adapter *adap);
 270 void t3_free_sge_resources(struct adapter *adap);
 271 void t3_sge_err_intr_handler(struct adapter *adapter);
 272 irq_handler_t t3_intr_handler(struct adapter *adap, int polling);
 273 int t3_eth_xmit(struct sk_buff *skb, struct net_device *dev);
 274 int t3_mgmt_tx(struct adapter *adap, struct sk_buff *skb);
 275 void t3_update_qset_coalesce(struct sge_qset *qs, const struct qset_params *p);
 276 int t3_sge_alloc_qset(struct adapter *adapter, unsigned int id, int nports,
 277                       int irq_vec_idx, const struct qset_params *p,
 278                       int ntxq, struct net_device *dev);
 279 int t3_get_desc(const struct sge_qset *qs, unsigned int qnum, unsigned int idx,
 280                 unsigned char *data);
 281 irqreturn_t t3_sge_intr_msix(int irq, void *cookie);
 282
 283 #endif                          /* __T3_ADAPTER_H__ */