drivers/net/mlx4/srq.c

   1 /*
   2  * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/init.h>
  34
  35 #include <linux/mlx4/cmd.h>
  36
  37 #include "mlx4.h"
  38 #include "icm.h"
  39
  40 struct mlx4_srq_context {
  41         __be32                  state_logsize_srqn;
  42         u8                      logstride;
  43         u8                      reserved1[3];
  44         u8                      pg_offset;
  45         u8                      reserved2[3];
  46         u32                     reserved3;
  47         u8                      log_page_size;
  48         u8                      reserved4[2];
  49         u8                      mtt_base_addr_h;
  50         __be32                  mtt_base_addr_l;
  51         __be32                  pd;
  52         __be16                  limit_watermark;
  53         __be16                  wqe_cnt;
  54         u16                     reserved5;
  55         __be16                  wqe_counter;
  56         u32                     reserved6;
  57         __be64                  db_rec_addr;
  58 };
  59
  60 void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type)
  61 {
  62         struct mlx4_srq_table *srq_table = &mlx4_priv(dev)->srq_table;
  63         struct mlx4_srq *srq;
  64
  65         spin_lock(&srq_table->lock);
  66
  67         srq = radix_tree_lookup(&srq_table->tree, srqn & (dev->caps.num_srqs - 1));
  68         if (srq)
  69                 atomic_inc(&srq->refcount);
  70
  71         spin_unlock(&srq_table->lock);
  72
  73         if (!srq) {
  74                 mlx4_warn(dev, "Async event for bogus SRQ %08x\n", srqn);
  75                 return;
  76         }
  77
  78         srq->event(srq, event_type);
  79
  80         if (atomic_dec_and_test(&srq->refcount))
  81                 complete(&srq->free);
  82 }
  83
  84 static int mlx4_SW2HW_SRQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
  85                           int srq_num)
  86 {
  87         return mlx4_cmd(dev, mailbox->dma, srq_num, 0, MLX4_CMD_SW2HW_SRQ,
  88                         MLX4_CMD_TIME_CLASS_A);
  89 }
  90
  91 static int mlx4_HW2SW_SRQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
  92                           int srq_num)
  93 {
  94         return mlx4_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, srq_num,
  95                             mailbox ? 0 : 1, MLX4_CMD_HW2SW_SRQ,
  96                             MLX4_CMD_TIME_CLASS_A);
  97 }
  98
  99 static int mlx4_ARM_SRQ(struct mlx4_dev *dev, int srq_num, int limit_watermark)
 100 {
 101         return mlx4_cmd(dev, limit_watermark, srq_num, 0, MLX4_CMD_ARM_SRQ,
 102                         MLX4_CMD_TIME_CLASS_B);
 103 }
 104
 105 static int mlx4_QUERY_SRQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
 106                           int srq_num)
 107 {
 108         return mlx4_cmd_box(dev, 0, mailbox->dma, srq_num, 0, MLX4_CMD_QUERY_SRQ,
 109                             MLX4_CMD_TIME_CLASS_A);
 110 }
 111
 112 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, struct mlx4_mtt *mtt,
 113                    u64 db_rec, struct mlx4_srq *srq)
 114 {
 115         struct mlx4_srq_table *srq_table = &mlx4_priv(dev)->srq_table;
 116         struct mlx4_cmd_mailbox *mailbox;
 117         struct mlx4_srq_context *srq_context;
 118         u64 mtt_addr;
 119         int err;
 120
 121         srq->srqn = mlx4_bitmap_alloc(&srq_table->bitmap);
 122         if (srq->srqn == -1)
 123                 return -ENOMEM;
 124
 125         err = mlx4_table_get(dev, &srq_table->table, srq->srqn);
 126         if (err)
 127                 goto err_out;
 128
 129         err = mlx4_table_get(dev, &srq_table->cmpt_table, srq->srqn);
 130         if (err)
 131                 goto err_put;
 132
 133         spin_lock_irq(&srq_table->lock);
 134         err = radix_tree_insert(&srq_table->tree, srq->srqn, srq);
 135         spin_unlock_irq(&srq_table->lock);
 136         if (err)
 137                 goto err_cmpt_put;
 138
 139         mailbox = mlx4_alloc_cmd_mailbox(dev);
 140         if (IS_ERR(mailbox)) {
 141                 err = PTR_ERR(mailbox);
 142                 goto err_radix;
 143         }
 144
 145         srq_context = mailbox->buf;
 146         memset(srq_context, 0, sizeof *srq_context);
 147
 148         srq_context->state_logsize_srqn = cpu_to_be32((ilog2(srq->max) << 24) |
 149                                                       srq->srqn);
 150         srq_context->logstride          = srq->wqe_shift - 4;
 151         srq_context->log_page_size      = mtt->page_shift - MLX4_ICM_PAGE_SHIFT;
 152
 153         mtt_addr = mlx4_mtt_addr(dev, mtt);
 154         srq_context->mtt_base_addr_h    = mtt_addr >> 32;
 155         srq_context->mtt_base_addr_l    = cpu_to_be32(mtt_addr & 0xffffffff);
 156         srq_context->pd                 = cpu_to_be32(pdn);
 157         srq_context->db_rec_addr        = cpu_to_be64(db_rec);
 158
 159         err = mlx4_SW2HW_SRQ(dev, mailbox, srq->srqn);
 160         mlx4_free_cmd_mailbox(dev, mailbox);
 161         if (err)
 162                 goto err_radix;
 163
 164         atomic_set(&srq->refcount, 1);
 165         init_completion(&srq->free);
 166
 167         return 0;
 168
 169 err_radix:
 170         spin_lock_irq(&srq_table->lock);
 171         radix_tree_delete(&srq_table->tree, srq->srqn);
 172         spin_unlock_irq(&srq_table->lock);
 173
 174 err_cmpt_put:
 175         mlx4_table_put(dev, &srq_table->cmpt_table, srq->srqn);
 176
 177 err_put:
 178         mlx4_table_put(dev, &srq_table->table, srq->srqn);
 179
 180 err_out:
 181         mlx4_bitmap_free(&srq_table->bitmap, srq->srqn);
 182
 183         return err;
 184 }
 185 EXPORT_SYMBOL_GPL(mlx4_srq_alloc);
 186
 187 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq)
 188 {
 189         struct mlx4_srq_table *srq_table = &mlx4_priv(dev)->srq_table;
 190         int err;
 191
 192         err = mlx4_HW2SW_SRQ(dev, NULL, srq->srqn);
 193         if (err)
 194                 mlx4_warn(dev, "HW2SW_SRQ failed (%d) for SRQN %06x\n", err, srq->srqn);
 195
 196         spin_lock_irq(&srq_table->lock);
 197         radix_tree_delete(&srq_table->tree, srq->srqn);
 198         spin_unlock_irq(&srq_table->lock);
 199
 200         if (atomic_dec_and_test(&srq->refcount))
 201                 complete(&srq->free);
 202         wait_for_completion(&srq->free);
 203
 204         mlx4_table_put(dev, &srq_table->table, srq->srqn);
 205         mlx4_bitmap_free(&srq_table->bitmap, srq->srqn);
 206 }
 207 EXPORT_SYMBOL_GPL(mlx4_srq_free);
 208
 209 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark)
 210 {
 211         return mlx4_ARM_SRQ(dev, srq->srqn, limit_watermark);
 212 }
 213 EXPORT_SYMBOL_GPL(mlx4_srq_arm);
 214
 215 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark)
 216 {
 217         struct mlx4_cmd_mailbox *mailbox;
 218         struct mlx4_srq_context *srq_context;
 219         int err;
 220
 221         mailbox = mlx4_alloc_cmd_mailbox(dev);
 222         if (IS_ERR(mailbox))
 223                 return PTR_ERR(mailbox);
 224
 225         srq_context = mailbox->buf;
 226
 227         err = mlx4_QUERY_SRQ(dev, mailbox, srq->srqn);
 228         if (err)
 229                 goto err_out;
 230         *limit_watermark = be16_to_cpu(srq_context->limit_watermark);
 231
 232 err_out:
 233         mlx4_free_cmd_mailbox(dev, mailbox);
 234         return err;
 235 }
 236 EXPORT_SYMBOL_GPL(mlx4_srq_query);
 237
 238 int mlx4_init_srq_table(struct mlx4_dev *dev)
 239 {
 240         struct mlx4_srq_table *srq_table = &mlx4_priv(dev)->srq_table;
 241         int err;
 242
 243         spin_lock_init(&srq_table->lock);
 244         INIT_RADIX_TREE(&srq_table->tree, GFP_ATOMIC);
 245
 246         err = mlx4_bitmap_init(&srq_table->bitmap, dev->caps.num_srqs,
 247                                dev->caps.num_srqs - 1, dev->caps.reserved_srqs);
 248         if (err)
 249                 return err;
 250
 251         return 0;
 252 }
 253
 254 void mlx4_cleanup_srq_table(struct mlx4_dev *dev)
 255 {
 256         mlx4_bitmap_cleanup(&mlx4_priv(dev)->srq_table.bitmap);
 257 }