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ia64/kvm: compilation fix. export account_system_vtime.
[pv_ops_mirror.git] / drivers / net / tokenring / 3c359.c
blob45208a0e69a095b876f2ba3fe3301f83cefcf985
1 /*
2 * 3c359.c (c) 2000 Mike Phillips (mikep@linuxtr.net) All Rights Reserved
3 *
4 * Linux driver for 3Com 3c359 Tokenlink Velocity XL PCI NIC
5 *
6 * Base Driver Olympic:
7 * Written 1999 Peter De Schrijver & Mike Phillips
8 *
9 * This software may be used and distributed according to the terms
10 * of the GNU General Public License, incorporated herein by reference.
11 *
12 * 7/17/00 - Clean up, version number 0.9.0. Ready to release to the world.
13 *
14 * 2/16/01 - Port up to kernel 2.4.2 ready for submission into the kernel.
15 * 3/05/01 - Last clean up stuff before submission.
16 * 2/15/01 - Finally, update to new pci api.
17 *
18 * To Do:
19 */
20
21 /*
22 * Technical Card Details
23 *
24 * All access to data is done with 16/8 bit transfers. The transfer
25 * method really sucks. You can only read or write one location at a time.
26 *
27 * Also, the microcode for the card must be uploaded if the card does not have
28 * the flashrom on board. This is a 28K bloat in the driver when compiled
29 * as a module.
30 *
31 * Rx is very simple, status into a ring of descriptors, dma data transfer,
32 * interrupts to tell us when a packet is received.
33 *
34 * Tx is a little more interesting. Similar scenario, descriptor and dma data
35 * transfers, but we don't have to interrupt the card to tell it another packet
36 * is ready for transmission, we are just doing simple memory writes, not io or mmio
37 * writes. The card can be set up to simply poll on the next
38 * descriptor pointer and when this value is non-zero will automatically download
39 * the next packet. The card then interrupts us when the packet is done.
40 *
41 */
42
43 #define XL_DEBUG 0
44
45 #include <linux/jiffies.h>
46 #include <linux/module.h>
47 #include <linux/kernel.h>
48 #include <linux/errno.h>
49 #include <linux/timer.h>
50 #include <linux/in.h>
51 #include <linux/ioport.h>
52 #include <linux/string.h>
53 #include <linux/proc_fs.h>
54 #include <linux/ptrace.h>
55 #include <linux/skbuff.h>
56 #include <linux/interrupt.h>
57 #include <linux/delay.h>
58 #include <linux/netdevice.h>
59 #include <linux/trdevice.h>
60 #include <linux/stddef.h>
61 #include <linux/init.h>
62 #include <linux/pci.h>
63 #include <linux/spinlock.h>
64 #include <linux/bitops.h>
65
66 #include <net/checksum.h>
67
68 #include <asm/io.h>
69 #include <asm/system.h>
70
71 #include "3c359.h"
72
73 static char version[] __devinitdata =
74 "3c359.c v1.2.0 2/17/01 - Mike Phillips (mikep@linuxtr.net)" ;
75
76 MODULE_AUTHOR("Mike Phillips <mikep@linuxtr.net>") ;
77 MODULE_DESCRIPTION("3Com 3C359 Velocity XL Token Ring Adapter Driver \n") ;
78
79 /* Module paramters */
80
81 /* Ring Speed 0,4,16
82 * 0 = Autosense
83 * 4,16 = Selected speed only, no autosense
84 * This allows the card to be the first on the ring
85 * and become the active monitor.
86 *
87 * WARNING: Some hubs will allow you to insert
88 * at the wrong speed.
89 *
90 * The adapter will _not_ fail to open if there are no
91 * active monitors on the ring, it will simply open up in
92 * its last known ringspeed if no ringspeed is specified.
93 */
94
95 static int ringspeed[XL_MAX_ADAPTERS] = {0,} ;
96
97 module_param_array(ringspeed, int, NULL, 0);
98 MODULE_PARM_DESC(ringspeed,"3c359: Ringspeed selection - 4,16 or 0") ;
99
100 /* Packet buffer size */
101
102 static int pkt_buf_sz[XL_MAX_ADAPTERS] = {0,} ;
103
104 module_param_array(pkt_buf_sz, int, NULL, 0) ;
105 MODULE_PARM_DESC(pkt_buf_sz,"3c359: Initial buffer size") ;
106 /* Message Level */
107
108 static int message_level[XL_MAX_ADAPTERS] = {0,} ;
109
110 module_param_array(message_level, int, NULL, 0) ;
111 MODULE_PARM_DESC(message_level, "3c359: Level of reported messages \n") ;
112 /*
113 * This is a real nasty way of doing this, but otherwise you
114 * will be stuck with 1555 lines of hex #'s in the code.
115 */
116
117 #include "3c359_microcode.h"
118
119 static struct pci_device_id xl_pci_tbl[] =
120 {
121 {PCI_VENDOR_ID_3COM,PCI_DEVICE_ID_3COM_3C359, PCI_ANY_ID, PCI_ANY_ID, },
122 { } /* terminate list */
123 };
124 MODULE_DEVICE_TABLE(pci,xl_pci_tbl) ;
125
126 static int xl_init(struct net_device *dev);
127 static int xl_open(struct net_device *dev);
128 static int xl_open_hw(struct net_device *dev) ;
129 static int xl_hw_reset(struct net_device *dev);
130 static int xl_xmit(struct sk_buff *skb, struct net_device *dev);
131 static void xl_dn_comp(struct net_device *dev);
132 static int xl_close(struct net_device *dev);
133 static void xl_set_rx_mode(struct net_device *dev);
134 static irqreturn_t xl_interrupt(int irq, void *dev_id);
135 static struct net_device_stats * xl_get_stats(struct net_device *dev);
136 static int xl_set_mac_address(struct net_device *dev, void *addr) ;
137 static void xl_arb_cmd(struct net_device *dev);
138 static void xl_asb_cmd(struct net_device *dev) ;
139 static void xl_srb_cmd(struct net_device *dev, int srb_cmd) ;
140 static void xl_wait_misr_flags(struct net_device *dev) ;
141 static int xl_change_mtu(struct net_device *dev, int mtu);
142 static void xl_srb_bh(struct net_device *dev) ;
143 static void xl_asb_bh(struct net_device *dev) ;
144 static void xl_reset(struct net_device *dev) ;
145 static void xl_freemem(struct net_device *dev) ;
146
147
148 /* EEProm Access Functions */
149 static u16 xl_ee_read(struct net_device *dev, int ee_addr) ;
150 static void xl_ee_write(struct net_device *dev, int ee_addr, u16 ee_value) ;
151
152 /* Debugging functions */
153 #if XL_DEBUG
154 static void print_tx_state(struct net_device *dev) ;
155 static void print_rx_state(struct net_device *dev) ;
156
157 static void print_tx_state(struct net_device *dev)
158 {
159
160 struct xl_private *xl_priv = netdev_priv(dev);
161 struct xl_tx_desc *txd ;
162 u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
163 int i ;
164
165 printk("tx_ring_head: %d, tx_ring_tail: %d, free_ent: %d \n",xl_priv->tx_ring_head,
166 xl_priv->tx_ring_tail, xl_priv->free_ring_entries) ;
167 printk("Ring , Address , FSH , DnNextPtr, Buffer, Buffer_Len \n");
168 for (i = 0; i < 16; i++) {
169 txd = &(xl_priv->xl_tx_ring[i]) ;
170 printk("%d, %08lx, %08x, %08x, %08x, %08x \n", i, virt_to_bus(txd),
171 txd->framestartheader, txd->dnnextptr, txd->buffer, txd->buffer_length ) ;
172 }
173
174 printk("DNLISTPTR = %04x \n", readl(xl_mmio + MMIO_DNLISTPTR) );
175
176 printk("DmaCtl = %04x \n", readl(xl_mmio + MMIO_DMA_CTRL) );
177 printk("Queue status = %0x \n",netif_running(dev) ) ;
178 }
179
180 static void print_rx_state(struct net_device *dev)
181 {
182
183 struct xl_private *xl_priv = netdev_priv(dev);
184 struct xl_rx_desc *rxd ;
185 u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
186 int i ;
187
188 printk("rx_ring_tail: %d \n", xl_priv->rx_ring_tail) ;
189 printk("Ring , Address , FrameState , UPNextPtr, FragAddr, Frag_Len \n");
190 for (i = 0; i < 16; i++) {
191 /* rxd = (struct xl_rx_desc *)xl_priv->rx_ring_dma_addr + (i * sizeof(struct xl_rx_desc)) ; */
192 rxd = &(xl_priv->xl_rx_ring[i]) ;
193 printk("%d, %08lx, %08x, %08x, %08x, %08x \n", i, virt_to_bus(rxd),
194 rxd->framestatus, rxd->upnextptr, rxd->upfragaddr, rxd->upfraglen ) ;
195 }
196
197 printk("UPLISTPTR = %04x \n", readl(xl_mmio + MMIO_UPLISTPTR) );
198
199 printk("DmaCtl = %04x \n", readl(xl_mmio + MMIO_DMA_CTRL) );
200 printk("Queue status = %0x \n",netif_running(dev) ) ;
201 }
202 #endif
203
204 /*
205 * Read values from the on-board EEProm. This looks very strange
206 * but you have to wait for the EEProm to get/set the value before
207 * passing/getting the next value from the nic. As with all requests
208 * on this nic it has to be done in two stages, a) tell the nic which
209 * memory address you want to access and b) pass/get the value from the nic.
210 * With the EEProm, you have to wait before and inbetween access a) and b).
211 * As this is only read at initialization time and the wait period is very
212 * small we shouldn't have to worry about scheduling issues.
213 */
214
215 static u16 xl_ee_read(struct net_device *dev, int ee_addr)
216 {
217 struct xl_private *xl_priv = netdev_priv(dev);
218 u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
219
220 /* Wait for EEProm to not be busy */
221 writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
222 while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ;
223
224 /* Tell EEProm what we want to do and where */
225 writel(IO_WORD_WRITE | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
226 writew(EEREAD + ee_addr, xl_mmio + MMIO_MACDATA) ;
227
228 /* Wait for EEProm to not be busy */
229 writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
230 while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ;
231
232 /* Tell EEProm what we want to do and where */
233 writel(IO_WORD_WRITE | EECONTROL , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
234 writew(EEREAD + ee_addr, xl_mmio + MMIO_MACDATA) ;
235
236 /* Finally read the value from the EEProm */
237 writel(IO_WORD_READ | EEDATA , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
238 return readw(xl_mmio + MMIO_MACDATA) ;
239 }
240
241 /*
242 * Write values to the onboard eeprom. As with eeprom read you need to
243 * set which location to write, wait, value to write, wait, with the
244 * added twist of having to enable eeprom writes as well.
245 */
246
247 static void xl_ee_write(struct net_device *dev, int ee_addr, u16 ee_value)
248 {
249 struct xl_private *xl_priv = netdev_priv(dev);
250 u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
251
252 /* Wait for EEProm to not be busy */
253 writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
254 while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ;
255
256 /* Enable write/erase */
257 writel(IO_WORD_WRITE | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
258 writew(EE_ENABLE_WRITE, xl_mmio + MMIO_MACDATA) ;
259
260 /* Wait for EEProm to not be busy */
261 writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
262 while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ;
263
264 /* Put the value we want to write into EEDATA */
265 writel(IO_WORD_WRITE | EEDATA, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
266 writew(ee_value, xl_mmio + MMIO_MACDATA) ;
267
268 /* Tell EEProm to write eevalue into ee_addr */
269 writel(IO_WORD_WRITE | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
270 writew(EEWRITE + ee_addr, xl_mmio + MMIO_MACDATA) ;
271
272 /* Wait for EEProm to not be busy, to ensure write gets done */
273 writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
274 while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ;
275
276 return ;
277 }
278
279 static int __devinit xl_probe(struct pci_dev *pdev,
280 const struct pci_device_id *ent)
281 {
282 struct net_device *dev ;
283 struct xl_private *xl_priv ;
284 static int card_no = -1 ;
285 int i ;
286
287 card_no++ ;
288
289 if (pci_enable_device(pdev)) {
290 return -ENODEV ;
291 }
292
293 pci_set_master(pdev);
294
295 if ((i = pci_request_regions(pdev,"3c359"))) {
296 return i ;
297 } ;
298
299 /*
300 * Allowing init_trdev to allocate the dev->priv structure will align xl_private
301 * on a 32 bytes boundary which we need for the rx/tx descriptors
302 */
303
304 dev = alloc_trdev(sizeof(struct xl_private)) ;
305 if (!dev) {
306 pci_release_regions(pdev) ;
307 return -ENOMEM ;
308 }
309 xl_priv = netdev_priv(dev);
310
311 #if XL_DEBUG
312 printk("pci_device: %p, dev:%p, dev->priv: %p, ba[0]: %10x, ba[1]:%10x\n",
313 pdev, dev, netdev_priv(dev), (unsigned int)pdev->resource[0].start, (unsigned int)pdev->resource[1].start);
314 #endif
315
316 dev->irq=pdev->irq;
317 dev->base_addr=pci_resource_start(pdev,0) ;
318 xl_priv->xl_card_name = pci_name(pdev);
319 xl_priv->xl_mmio=ioremap(pci_resource_start(pdev,1), XL_IO_SPACE);
320 xl_priv->pdev = pdev ;
321
322 if ((pkt_buf_sz[card_no] < 100) || (pkt_buf_sz[card_no] > 18000) )
323 xl_priv->pkt_buf_sz = PKT_BUF_SZ ;
324 else
325 xl_priv->pkt_buf_sz = pkt_buf_sz[card_no] ;
326
327 dev->mtu = xl_priv->pkt_buf_sz - TR_HLEN ;
328 xl_priv->xl_ring_speed = ringspeed[card_no] ;
329 xl_priv->xl_message_level = message_level[card_no] ;
330 xl_priv->xl_functional_addr[0] = xl_priv->xl_functional_addr[1] = xl_priv->xl_functional_addr[2] = xl_priv->xl_functional_addr[3] = 0 ;
331 xl_priv->xl_copy_all_options = 0 ;
332
333 if((i = xl_init(dev))) {
334 iounmap(xl_priv->xl_mmio) ;
335 free_netdev(dev) ;
336 pci_release_regions(pdev) ;
337 return i ;
338 }
339
340 dev->open=&xl_open;
341 dev->hard_start_xmit=&xl_xmit;
342 dev->change_mtu=&xl_change_mtu;
343 dev->stop=&xl_close;
344 dev->do_ioctl=NULL;
345 dev->set_multicast_list=&xl_set_rx_mode;
346 dev->get_stats=&xl_get_stats ;
347 dev->set_mac_address=&xl_set_mac_address ;
348 SET_NETDEV_DEV(dev, &pdev->dev);
349
350 pci_set_drvdata(pdev,dev) ;
351 if ((i = register_netdev(dev))) {
352 printk(KERN_ERR "3C359, register netdev failed\n") ;
353 pci_set_drvdata(pdev,NULL) ;
354 iounmap(xl_priv->xl_mmio) ;
355 free_netdev(dev) ;
356 pci_release_regions(pdev) ;
357 return i ;
358 }
359
360 printk(KERN_INFO "3C359: %s registered as: %s\n",xl_priv->xl_card_name,dev->name) ;
361
362 return 0;
363 }
364
365
366 static int __devinit xl_init(struct net_device *dev)
367 {
368 struct xl_private *xl_priv = netdev_priv(dev);
369
370 printk(KERN_INFO "%s \n", version);
371 printk(KERN_INFO "%s: I/O at %hx, MMIO at %p, using irq %d\n",
372 xl_priv->xl_card_name, (unsigned int)dev->base_addr ,xl_priv->xl_mmio, dev->irq);
373
374 spin_lock_init(&xl_priv->xl_lock) ;
375
376 return xl_hw_reset(dev) ;
377
378 }
379
380
381 /*
382 * Hardware reset. This needs to be a separate entity as we need to reset the card
383 * when we change the EEProm settings.
384 */
385
386 static int xl_hw_reset(struct net_device *dev)
387 {
388 struct xl_private *xl_priv = netdev_priv(dev);
389 u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
390 unsigned long t ;
391 u16 i ;
392 u16 result_16 ;
393 u8 result_8 ;
394 u16 start ;
395 int j ;
396
397 /*
398 * Reset the card. If the card has got the microcode on board, we have
399 * missed the initialization interrupt, so we must always do this.
400 */
401
402 writew( GLOBAL_RESET, xl_mmio + MMIO_COMMAND ) ;
403
404 /*
405 * Must wait for cmdInProgress bit (12) to clear before continuing with
406 * card configuration.
407 */
408
409 t=jiffies;
410 while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
411 schedule();
412 if (time_after(jiffies, t + 40 * HZ)) {
413 printk(KERN_ERR "%s: 3COM 3C359 Velocity XL card not responding to global reset.\n", dev->name);
414 return -ENODEV;
415 }
416 }
417
418 /*
419 * Enable pmbar by setting bit in CPAttention
420 */
421
422 writel( (IO_BYTE_READ | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
423 result_8 = readb(xl_mmio + MMIO_MACDATA) ;
424 result_8 = result_8 | CPA_PMBARVIS ;
425 writel( (IO_BYTE_WRITE | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
426 writeb(result_8, xl_mmio + MMIO_MACDATA) ;
427
428 /*
429 * Read cpHold bit in pmbar, if cleared we have got Flashrom on board.
430 * If not, we need to upload the microcode to the card
431 */
432
433 writel( (IO_WORD_READ | PMBAR),xl_mmio + MMIO_MAC_ACCESS_CMD);
434
435 #if XL_DEBUG
436 printk(KERN_INFO "Read from PMBAR = %04x \n", readw(xl_mmio + MMIO_MACDATA)) ;
437 #endif
438
439 if ( readw( (xl_mmio + MMIO_MACDATA)) & PMB_CPHOLD ) {
440
441 /* Set PmBar, privateMemoryBase bits (8:2) to 0 */
442
443 writel( (IO_WORD_READ | PMBAR),xl_mmio + MMIO_MAC_ACCESS_CMD);
444 result_16 = readw(xl_mmio + MMIO_MACDATA) ;
445 result_16 = result_16 & ~((0x7F) << 2) ;
446 writel( (IO_WORD_WRITE | PMBAR), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
447 writew(result_16,xl_mmio + MMIO_MACDATA) ;
448
449 /* Set CPAttention, memWrEn bit */
450
451 writel( (IO_BYTE_READ | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
452 result_8 = readb(xl_mmio + MMIO_MACDATA) ;
453 result_8 = result_8 | CPA_MEMWREN ;
454 writel( (IO_BYTE_WRITE | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
455 writeb(result_8, xl_mmio + MMIO_MACDATA) ;
456
457 /*
458 * Now to write the microcode into the shared ram
459 * The microcode must finish at position 0xFFFF, so we must subtract
460 * to get the start position for the code
461 */
462
463 start = (0xFFFF - (mc_size) + 1 ) ; /* Looks strange but ensures compiler only uses 16 bit unsigned int for this */
464
465 printk(KERN_INFO "3C359: Uploading Microcode: ");
466
467 for (i = start, j = 0; j < mc_size; i++, j++) {
468 writel(MEM_BYTE_WRITE | 0XD0000 | i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
469 writeb(microcode[j],xl_mmio + MMIO_MACDATA) ;
470 if (j % 1024 == 0)
471 printk(".");
472 }
473 printk("\n") ;
474
475 for (i=0;i < 16; i++) {
476 writel( (MEM_BYTE_WRITE | 0xDFFF0) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
477 writeb(microcode[mc_size - 16 + i], xl_mmio + MMIO_MACDATA) ;
478 }
479
480 /*
481 * Have to write the start address of the upload to FFF4, but
482 * the address must be >> 4. You do not want to know how long
483 * it took me to discover this.
484 */
485
486 writel(MEM_WORD_WRITE | 0xDFFF4, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
487 writew(start >> 4, xl_mmio + MMIO_MACDATA);
488
489 /* Clear the CPAttention, memWrEn Bit */
490
491 writel( (IO_BYTE_READ | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
492 result_8 = readb(xl_mmio + MMIO_MACDATA) ;
493 result_8 = result_8 & ~CPA_MEMWREN ;
494 writel( (IO_BYTE_WRITE | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
495 writeb(result_8, xl_mmio + MMIO_MACDATA) ;
496
497 /* Clear the cpHold bit in pmbar */
498
499 writel( (IO_WORD_READ | PMBAR),xl_mmio + MMIO_MAC_ACCESS_CMD);
500 result_16 = readw(xl_mmio + MMIO_MACDATA) ;
501 result_16 = result_16 & ~PMB_CPHOLD ;
502 writel( (IO_WORD_WRITE | PMBAR), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
503 writew(result_16,xl_mmio + MMIO_MACDATA) ;
504
505
506 } /* If microcode upload required */
507
508 /*
509 * The card should now go though a self test procedure and get itself ready
510 * to be opened, we must wait for an srb response with the initialization
511 * information.
512 */
513
514 #if XL_DEBUG
515 printk(KERN_INFO "%s: Microcode uploaded, must wait for the self test to complete\n", dev->name);
516 #endif
517
518 writew(SETINDENABLE | 0xFFF, xl_mmio + MMIO_COMMAND) ;
519
520 t=jiffies;
521 while ( !(readw(xl_mmio + MMIO_INTSTATUS_AUTO) & INTSTAT_SRB) ) {
522 schedule();
523 if (time_after(jiffies, t + 15 * HZ)) {
524 printk(KERN_ERR "3COM 3C359 Velocity XL card not responding.\n");
525 return -ENODEV;
526 }
527 }
528
529 /*
530 * Write the RxBufArea with D000, RxEarlyThresh, TxStartThresh,
531 * DnPriReqThresh, read the tech docs if you want to know what
532 * values they need to be.
533 */
534
535 writel(MMIO_WORD_WRITE | RXBUFAREA, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
536 writew(0xD000, xl_mmio + MMIO_MACDATA) ;
537
538 writel(MMIO_WORD_WRITE | RXEARLYTHRESH, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
539 writew(0X0020, xl_mmio + MMIO_MACDATA) ;
540
541 writew( SETTXSTARTTHRESH | 0x40 , xl_mmio + MMIO_COMMAND) ;
542
543 writeb(0x04, xl_mmio + MMIO_DNBURSTTHRESH) ;
544 writeb(0x04, xl_mmio + DNPRIREQTHRESH) ;
545
546 /*
547 * Read WRBR to provide the location of the srb block, have to use byte reads not word reads.
548 * Tech docs have this wrong !!!!
549 */
550
551 writel(MMIO_BYTE_READ | WRBR, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
552 xl_priv->srb = readb(xl_mmio + MMIO_MACDATA) << 8 ;
553 writel( (MMIO_BYTE_READ | WRBR) + 1, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
554 xl_priv->srb = xl_priv->srb | readb(xl_mmio + MMIO_MACDATA) ;
555
556 #if XL_DEBUG
557 writel(IO_WORD_READ | SWITCHSETTINGS, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
558 if ( readw(xl_mmio + MMIO_MACDATA) & 2) {
559 printk(KERN_INFO "Default ring speed 4 mbps \n") ;
560 } else {
561 printk(KERN_INFO "Default ring speed 16 mbps \n") ;
562 }
563 printk(KERN_INFO "%s: xl_priv->srb = %04x\n",xl_priv->xl_card_name, xl_priv->srb);
564 #endif
565
566 return 0;
567 }
568
569 static int xl_open(struct net_device *dev)
570 {
571 struct xl_private *xl_priv=netdev_priv(dev);
572 u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
573 u8 i ;
574 __le16 hwaddr[3] ; /* Should be u8[6] but we get word return values */
575 int open_err ;
576
577 u16 switchsettings, switchsettings_eeprom ;
578
579 if(request_irq(dev->irq, &xl_interrupt, IRQF_SHARED , "3c359", dev)) {
580 return -EAGAIN;
581 }
582
583 /*
584 * Read the information from the EEPROM that we need.
585 */
586
587 hwaddr[0] = cpu_to_le16(xl_ee_read(dev,0x10));
588 hwaddr[1] = cpu_to_le16(xl_ee_read(dev,0x11));
589 hwaddr[2] = cpu_to_le16(xl_ee_read(dev,0x12));
590
591 /* Ring speed */
592
593 switchsettings_eeprom = xl_ee_read(dev,0x08) ;
594 switchsettings = switchsettings_eeprom ;
595
596 if (xl_priv->xl_ring_speed != 0) {
597 if (xl_priv->xl_ring_speed == 4)
598 switchsettings = switchsettings | 0x02 ;
599 else
600 switchsettings = switchsettings & ~0x02 ;
601 }
602
603 /* Only write EEProm if there has been a change */
604 if (switchsettings != switchsettings_eeprom) {
605 xl_ee_write(dev,0x08,switchsettings) ;
606 /* Hardware reset after changing EEProm */
607 xl_hw_reset(dev) ;
608 }
609
610 memcpy(dev->dev_addr,hwaddr,dev->addr_len) ;
611
612 open_err = xl_open_hw(dev) ;
613
614 /*
615 * This really needs to be cleaned up with better error reporting.
616 */
617
618 if (open_err != 0) { /* Something went wrong with the open command */
619 if (open_err & 0x07) { /* Wrong speed, retry at different speed */
620 printk(KERN_WARNING "%s: Open Error, retrying at different ringspeed \n", dev->name) ;
621 switchsettings = switchsettings ^ 2 ;
622 xl_ee_write(dev,0x08,switchsettings) ;
623 xl_hw_reset(dev) ;
624 open_err = xl_open_hw(dev) ;
625 if (open_err != 0) {
626 printk(KERN_WARNING "%s: Open error returned a second time, we're bombing out now\n", dev->name);
627 free_irq(dev->irq,dev) ;
628 return -ENODEV ;
629 }
630 } else {
631 printk(KERN_WARNING "%s: Open Error = %04x\n", dev->name, open_err) ;
632 free_irq(dev->irq,dev) ;
633 return -ENODEV ;
634 }
635 }
636
637 /*
638 * Now to set up the Rx and Tx buffer structures
639 */
640 /* These MUST be on 8 byte boundaries */
641 xl_priv->xl_tx_ring = kzalloc((sizeof(struct xl_tx_desc) * XL_TX_RING_SIZE) + 7, GFP_DMA | GFP_KERNEL);
642 if (xl_priv->xl_tx_ring == NULL) {
643 printk(KERN_WARNING "%s: Not enough memory to allocate rx buffers.\n",
644 dev->name);
645 free_irq(dev->irq,dev);
646 return -ENOMEM;
647 }
648 xl_priv->xl_rx_ring = kzalloc((sizeof(struct xl_rx_desc) * XL_RX_RING_SIZE) +7, GFP_DMA | GFP_KERNEL);
649 if (xl_priv->xl_tx_ring == NULL) {
650 printk(KERN_WARNING "%s: Not enough memory to allocate rx buffers.\n",
651 dev->name);
652 free_irq(dev->irq,dev);
653 kfree(xl_priv->xl_tx_ring);
654 return -ENOMEM;
655 }
656
657 /* Setup Rx Ring */
658 for (i=0 ; i < XL_RX_RING_SIZE ; i++) {
659 struct sk_buff *skb ;
660
661 skb = dev_alloc_skb(xl_priv->pkt_buf_sz) ;
662 if (skb==NULL)
663 break ;
664
665 skb->dev = dev ;
666 xl_priv->xl_rx_ring[i].upfragaddr = cpu_to_le32(pci_map_single(xl_priv->pdev, skb->data,xl_priv->pkt_buf_sz, PCI_DMA_FROMDEVICE));
667 xl_priv->xl_rx_ring[i].upfraglen = cpu_to_le32(xl_priv->pkt_buf_sz) | RXUPLASTFRAG;
668 xl_priv->rx_ring_skb[i] = skb ;
669 }
670
671 if (i==0) {
672 printk(KERN_WARNING "%s: Not enough memory to allocate rx buffers. Adapter disabled \n",dev->name) ;
673 free_irq(dev->irq,dev) ;
674 return -EIO ;
675 }
676
677 xl_priv->rx_ring_no = i ;
678 xl_priv->rx_ring_tail = 0 ;
679 xl_priv->rx_ring_dma_addr = pci_map_single(xl_priv->pdev,xl_priv->xl_rx_ring, sizeof(struct xl_rx_desc) * XL_RX_RING_SIZE, PCI_DMA_TODEVICE) ;
680 for (i=0;i<(xl_priv->rx_ring_no-1);i++) {
681 xl_priv->xl_rx_ring[i].upnextptr = cpu_to_le32(xl_priv->rx_ring_dma_addr + (sizeof (struct xl_rx_desc) * (i+1)));
682 }
683 xl_priv->xl_rx_ring[i].upnextptr = 0 ;
684
685 writel(xl_priv->rx_ring_dma_addr, xl_mmio + MMIO_UPLISTPTR) ;
686
687 /* Setup Tx Ring */
688
689 xl_priv->tx_ring_dma_addr = pci_map_single(xl_priv->pdev,xl_priv->xl_tx_ring, sizeof(struct xl_tx_desc) * XL_TX_RING_SIZE,PCI_DMA_TODEVICE) ;
690
691 xl_priv->tx_ring_head = 1 ;
692 xl_priv->tx_ring_tail = 255 ; /* Special marker for first packet */
693 xl_priv->free_ring_entries = XL_TX_RING_SIZE ;
694
695 /*
696 * Setup the first dummy DPD entry for polling to start working.
697 */
698
699 xl_priv->xl_tx_ring[0].framestartheader = TXDPDEMPTY;
700 xl_priv->xl_tx_ring[0].buffer = 0 ;
701 xl_priv->xl_tx_ring[0].buffer_length = 0 ;
702 xl_priv->xl_tx_ring[0].dnnextptr = 0 ;
703
704 writel(xl_priv->tx_ring_dma_addr, xl_mmio + MMIO_DNLISTPTR) ;
705 writel(DNUNSTALL, xl_mmio + MMIO_COMMAND) ;
706 writel(UPUNSTALL, xl_mmio + MMIO_COMMAND) ;
707 writel(DNENABLE, xl_mmio + MMIO_COMMAND) ;
708 writeb(0x40, xl_mmio + MMIO_DNPOLL) ;
709
710 /*
711 * Enable interrupts on the card
712 */
713
714 writel(SETINTENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ;
715 writel(SETINDENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ;
716
717 netif_start_queue(dev) ;
718 return 0;
719
720 }
721
722 static int xl_open_hw(struct net_device *dev)
723 {
724 struct xl_private *xl_priv=netdev_priv(dev);
725 u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
726 u16 vsoff ;
727 char ver_str[33];
728 int open_err ;
729 int i ;
730 unsigned long t ;
731
732 /*
733 * Okay, let's build up the Open.NIC srb command
734 *
735 */
736
737 writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
738 writeb(OPEN_NIC, xl_mmio + MMIO_MACDATA) ;
739
740 /*
741 * Use this as a test byte, if it comes back with the same value, the command didn't work
742 */
743
744 writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb)+ 2, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
745 writeb(0xff,xl_mmio + MMIO_MACDATA) ;
746
747 /* Open options */
748 writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + 8, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
749 writeb(0x00, xl_mmio + MMIO_MACDATA) ;
750 writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + 9, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
751 writeb(0x00, xl_mmio + MMIO_MACDATA) ;
752
753 /*
754 * Node address, be careful here, the docs say you can just put zeros here and it will use
755 * the hardware address, it doesn't, you must include the node address in the open command.
756 */
757
758 if (xl_priv->xl_laa[0]) { /* If using a LAA address */
759 for (i=10;i<16;i++) {
760 writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
761 writeb(xl_priv->xl_laa[i-10],xl_mmio + MMIO_MACDATA) ;
762 }
763 memcpy(dev->dev_addr,xl_priv->xl_laa,dev->addr_len) ;
764 } else { /* Regular hardware address */
765 for (i=10;i<16;i++) {
766 writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
767 writeb(dev->dev_addr[i-10], xl_mmio + MMIO_MACDATA) ;
768 }
769 }
770
771 /* Default everything else to 0 */
772 for (i = 16; i < 34; i++) {
773 writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
774 writeb(0x00,xl_mmio + MMIO_MACDATA) ;
775 }
776
777 /*
778 * Set the csrb bit in the MISR register
779 */
780
781 xl_wait_misr_flags(dev) ;
782 writel(MEM_BYTE_WRITE | MF_CSRB, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
783 writeb(0xFF, xl_mmio + MMIO_MACDATA) ;
784 writel(MMIO_BYTE_WRITE | MISR_SET, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
785 writeb(MISR_CSRB , xl_mmio + MMIO_MACDATA) ;
786
787 /*
788 * Now wait for the command to run
789 */
790
791 t=jiffies;
792 while (! (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_SRB)) {
793 schedule();
794 if (time_after(jiffies, t + 40 * HZ)) {
795 printk(KERN_ERR "3COM 3C359 Velocity XL card not responding.\n");
796 break ;
797 }
798 }
799
800 /*
801 * Let's interpret the open response
802 */
803
804 writel( (MEM_BYTE_READ | 0xD0000 | xl_priv->srb)+2, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
805 if (readb(xl_mmio + MMIO_MACDATA)!=0) {
806 open_err = readb(xl_mmio + MMIO_MACDATA) << 8 ;
807 writel( (MEM_BYTE_READ | 0xD0000 | xl_priv->srb) + 7, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
808 open_err |= readb(xl_mmio + MMIO_MACDATA) ;
809 return open_err ;
810 } else {
811 writel( (MEM_WORD_READ | 0xD0000 | xl_priv->srb) + 8, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
812 xl_priv->asb = swab16(readw(xl_mmio + MMIO_MACDATA)) ;
813 printk(KERN_INFO "%s: Adapter Opened Details: ",dev->name) ;
814 printk("ASB: %04x",xl_priv->asb ) ;
815 writel( (MEM_WORD_READ | 0xD0000 | xl_priv->srb) + 10, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
816 printk(", SRB: %04x",swab16(readw(xl_mmio + MMIO_MACDATA)) ) ;
817
818 writel( (MEM_WORD_READ | 0xD0000 | xl_priv->srb) + 12, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
819 xl_priv->arb = swab16(readw(xl_mmio + MMIO_MACDATA)) ;
820 printk(", ARB: %04x \n",xl_priv->arb ) ;
821 writel( (MEM_WORD_READ | 0xD0000 | xl_priv->srb) + 14, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
822 vsoff = swab16(readw(xl_mmio + MMIO_MACDATA)) ;
823
824 /*
825 * Interesting, sending the individual characters directly to printk was causing klogd to use
826 * use 100% of processor time, so we build up the string and print that instead.
827 */
828
829 for (i=0;i<0x20;i++) {
830 writel( (MEM_BYTE_READ | 0xD0000 | vsoff) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
831 ver_str[i] = readb(xl_mmio + MMIO_MACDATA) ;
832 }
833 ver_str[i] = '\0' ;
834 printk(KERN_INFO "%s: Microcode version String: %s \n",dev->name,ver_str);
835 }
836
837 /*
838 * Issue the AckInterrupt
839 */
840 writew(ACK_INTERRUPT | SRBRACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
841
842 return 0 ;
843 }
844
845 /*
846 * There are two ways of implementing rx on the 359 NIC, either
847 * interrupt driven or polling. We are going to uses interrupts,
848 * it is the easier way of doing things.
849 *
850 * The Rx works with a ring of Rx descriptors. At initialise time the ring
851 * entries point to the next entry except for the last entry in the ring
852 * which points to 0. The card is programmed with the location of the first
853 * available descriptor and keeps reading the next_ptr until next_ptr is set
854 * to 0. Hopefully with a ring size of 16 the card will never get to read a next_ptr
855 * of 0. As the Rx interrupt is received we copy the frame up to the protocol layers
856 * and then point the end of the ring to our current position and point our current
857 * position to 0, therefore making the current position the last position on the ring.
858 * The last position on the ring therefore loops continually loops around the rx ring.
859 *
860 * rx_ring_tail is the position on the ring to process next. (Think of a snake, the head
861 * expands as the card adds new packets and we go around eating the tail processing the
862 * packets.)
863 *
864 * Undoubtably it could be streamlined and improved upon, but at the moment it works
865 * and the fast path through the routine is fine.
866 *
867 * adv_rx_ring could be inlined to increase performance, but its called a *lot* of times
868 * in xl_rx so would increase the size of the function significantly.
869 */
870
871 static void adv_rx_ring(struct net_device *dev) /* Advance rx_ring, cut down on bloat in xl_rx */
872 {
873 struct xl_private *xl_priv=netdev_priv(dev);
874 int n = xl_priv->rx_ring_tail;
875 int prev_ring_loc;
876
877 prev_ring_loc = (n + XL_RX_RING_SIZE - 1) & (XL_RX_RING_SIZE - 1);
878 xl_priv->xl_rx_ring[prev_ring_loc].upnextptr = cpu_to_le32(xl_priv->rx_ring_dma_addr + (sizeof (struct xl_rx_desc) * n));
879 xl_priv->xl_rx_ring[n].framestatus = 0;
880 xl_priv->xl_rx_ring[n].upnextptr = 0;
881 xl_priv->rx_ring_tail++;
882 xl_priv->rx_ring_tail &= (XL_RX_RING_SIZE-1);
883 }
884
885 static void xl_rx(struct net_device *dev)
886 {
887 struct xl_private *xl_priv=netdev_priv(dev);
888 u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
889 struct sk_buff *skb, *skb2 ;
890 int frame_length = 0, copy_len = 0 ;
891 int temp_ring_loc ;
892
893 /*
894 * Receive the next frame, loop around the ring until all frames
895 * have been received.
896 */
897
898 while (xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].framestatus & (RXUPDCOMPLETE | RXUPDFULL) ) { /* Descriptor to process */
899
900 if (xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].framestatus & RXUPDFULL ) { /* UpdFull, Multiple Descriptors used for the frame */
901
902 /*
903 * This is a pain, you need to go through all the descriptors until the last one
904 * for this frame to find the framelength
905 */
906
907 temp_ring_loc = xl_priv->rx_ring_tail ;
908
909 while (xl_priv->xl_rx_ring[temp_ring_loc].framestatus & RXUPDFULL ) {
910 temp_ring_loc++ ;
911 temp_ring_loc &= (XL_RX_RING_SIZE-1) ;
912 }
913
914 frame_length = le32_to_cpu(xl_priv->xl_rx_ring[temp_ring_loc].framestatus) & 0x7FFF;
915
916 skb = dev_alloc_skb(frame_length) ;
917
918 if (skb==NULL) { /* No memory for frame, still need to roll forward the rx ring */
919 printk(KERN_WARNING "%s: dev_alloc_skb failed - multi buffer !\n", dev->name) ;
920 while (xl_priv->rx_ring_tail != temp_ring_loc)
921 adv_rx_ring(dev) ;
922
923 adv_rx_ring(dev) ; /* One more time just for luck :) */
924 xl_priv->xl_stats.rx_dropped++ ;
925
926 writel(ACK_INTERRUPT | UPCOMPACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ;
927 return ;
928 }
929
930 while (xl_priv->rx_ring_tail != temp_ring_loc) {
931 copy_len = le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfraglen) & 0x7FFF;
932 frame_length -= copy_len ;
933 pci_dma_sync_single_for_cpu(xl_priv->pdev,le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr),xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE);
934 skb_copy_from_linear_data(xl_priv->rx_ring_skb[xl_priv->rx_ring_tail],
935 skb_put(skb, copy_len),
936 copy_len);
937 pci_dma_sync_single_for_device(xl_priv->pdev,le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr),xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE);
938 adv_rx_ring(dev) ;
939 }
940
941 /* Now we have found the last fragment */
942 pci_dma_sync_single_for_cpu(xl_priv->pdev,le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr),xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE);
943 skb_copy_from_linear_data(xl_priv->rx_ring_skb[xl_priv->rx_ring_tail],
944 skb_put(skb,copy_len), frame_length);
945 /* memcpy(skb_put(skb,frame_length), bus_to_virt(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr), frame_length) ; */
946 pci_dma_sync_single_for_device(xl_priv->pdev,le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr),xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE);
947 adv_rx_ring(dev) ;
948 skb->protocol = tr_type_trans(skb,dev) ;
949 netif_rx(skb) ;
950
951 } else { /* Single Descriptor Used, simply swap buffers over, fast path */
952
953 frame_length = le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].framestatus) & 0x7FFF;
954
955 skb = dev_alloc_skb(xl_priv->pkt_buf_sz) ;
956
957 if (skb==NULL) { /* Still need to fix the rx ring */
958 printk(KERN_WARNING "%s: dev_alloc_skb failed in rx, single buffer \n",dev->name) ;
959 adv_rx_ring(dev) ;
960 xl_priv->xl_stats.rx_dropped++ ;
961 writel(ACK_INTERRUPT | UPCOMPACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ;
962 return ;
963 }
964
965 skb2 = xl_priv->rx_ring_skb[xl_priv->rx_ring_tail] ;
966 pci_unmap_single(xl_priv->pdev, le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr), xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE) ;
967 skb_put(skb2, frame_length) ;
968 skb2->protocol = tr_type_trans(skb2,dev) ;
969
970 xl_priv->rx_ring_skb[xl_priv->rx_ring_tail] = skb ;
971 xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr = cpu_to_le32(pci_map_single(xl_priv->pdev,skb->data,xl_priv->pkt_buf_sz, PCI_DMA_FROMDEVICE));
972 xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfraglen = cpu_to_le32(xl_priv->pkt_buf_sz) | RXUPLASTFRAG;
973 adv_rx_ring(dev) ;
974 xl_priv->xl_stats.rx_packets++ ;
975 xl_priv->xl_stats.rx_bytes += frame_length ;
976
977 netif_rx(skb2) ;
978 } /* if multiple buffers */
979 dev->last_rx = jiffies ;
980 } /* while packet to do */
981
982 /* Clear the updComplete interrupt */
983 writel(ACK_INTERRUPT | UPCOMPACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ;
984 return ;
985 }
986
987 /*
988 * This is ruthless, it doesn't care what state the card is in it will
989 * completely reset the adapter.
990 */
991
992 static void xl_reset(struct net_device *dev)
993 {
994 struct xl_private *xl_priv=netdev_priv(dev);
995 u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
996 unsigned long t;
997
998 writew( GLOBAL_RESET, xl_mmio + MMIO_COMMAND ) ;
999
1000 /*
1001 * Must wait for cmdInProgress bit (12) to clear before continuing with
1002 * card configuration.
1003 */
1004
1005 t=jiffies;
1006 while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
1007 if (time_after(jiffies, t + 40 * HZ)) {
1008 printk(KERN_ERR "3COM 3C359 Velocity XL card not responding.\n");
1009 break ;
1010 }
1011 }
1012
1013 }
1014
1015 static void xl_freemem(struct net_device *dev)
1016 {
1017 struct xl_private *xl_priv=netdev_priv(dev);
1018 int i ;
1019
1020 for (i=0;i<XL_RX_RING_SIZE;i++) {
1021 dev_kfree_skb_irq(xl_priv->rx_ring_skb[xl_priv->rx_ring_tail]) ;
1022 pci_unmap_single(xl_priv->pdev,le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr),xl_priv->pkt_buf_sz, PCI_DMA_FROMDEVICE);
1023 xl_priv->rx_ring_tail++ ;
1024 xl_priv->rx_ring_tail &= XL_RX_RING_SIZE-1;
1025 }
1026
1027 /* unmap ring */
1028 pci_unmap_single(xl_priv->pdev,xl_priv->rx_ring_dma_addr, sizeof(struct xl_rx_desc) * XL_RX_RING_SIZE, PCI_DMA_FROMDEVICE) ;
1029
1030 pci_unmap_single(xl_priv->pdev,xl_priv->tx_ring_dma_addr, sizeof(struct xl_tx_desc) * XL_TX_RING_SIZE, PCI_DMA_TODEVICE) ;
1031
1032 kfree(xl_priv->xl_rx_ring) ;
1033 kfree(xl_priv->xl_tx_ring) ;
1034
1035 return ;
1036 }
1037
1038 static irqreturn_t xl_interrupt(int irq, void *dev_id)
1039 {
1040 struct net_device *dev = (struct net_device *)dev_id;
1041 struct xl_private *xl_priv =netdev_priv(dev);
1042 u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
1043 u16 intstatus, macstatus ;
1044
1045 intstatus = readw(xl_mmio + MMIO_INTSTATUS) ;
1046
1047 if (!(intstatus & 1)) /* We didn't generate the interrupt */
1048 return IRQ_NONE;
1049
1050 spin_lock(&xl_priv->xl_lock) ;
1051
1052 /*
1053 * Process the interrupt
1054 */
1055 /*
1056 * Something fishy going on here, we shouldn't get 0001 ints, not fatal though.
1057 */
1058 if (intstatus == 0x0001) {
1059 writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
1060 printk(KERN_INFO "%s: 00001 int received \n",dev->name) ;
1061 } else {
1062 if (intstatus & (HOSTERRINT | SRBRINT | ARBCINT | UPCOMPINT | DNCOMPINT | HARDERRINT | (1<<8) | TXUNDERRUN | ASBFINT)) {
1063
1064 /*
1065 * Host Error.
1066 * It may be possible to recover from this, but usually it means something
1067 * is seriously fubar, so we just close the adapter.
1068 */
1069
1070 if (intstatus & HOSTERRINT) {
1071 printk(KERN_WARNING "%s: Host Error, performing global reset, intstatus = %04x \n",dev->name,intstatus) ;
1072 writew( GLOBAL_RESET, xl_mmio + MMIO_COMMAND ) ;
1073 printk(KERN_WARNING "%s: Resetting hardware: \n", dev->name);
1074 netif_stop_queue(dev) ;
1075 xl_freemem(dev) ;
1076 free_irq(dev->irq,dev);
1077 xl_reset(dev) ;
1078 writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
1079 spin_unlock(&xl_priv->xl_lock) ;
1080 return IRQ_HANDLED;
1081 } /* Host Error */
1082
1083 if (intstatus & SRBRINT ) { /* Srbc interrupt */
1084 writel(ACK_INTERRUPT | SRBRACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
1085 if (xl_priv->srb_queued)
1086 xl_srb_bh(dev) ;
1087 } /* SRBR Interrupt */
1088
1089 if (intstatus & TXUNDERRUN) { /* Issue DnReset command */
1090 writel(DNRESET, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1091 while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) { /* Wait for command to run */
1092 /* !!! FIX-ME !!!!
1093 Must put a timeout check here ! */
1094 /* Empty Loop */
1095 }
1096 printk(KERN_WARNING "%s: TX Underrun received \n",dev->name) ;
1097 writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
1098 } /* TxUnderRun */
1099
1100 if (intstatus & ARBCINT ) { /* Arbc interrupt */
1101 xl_arb_cmd(dev) ;
1102 } /* Arbc */
1103
1104 if (intstatus & ASBFINT) {
1105 if (xl_priv->asb_queued == 1) {
1106 xl_asb_cmd(dev) ;
1107 } else if (xl_priv->asb_queued == 2) {
1108 xl_asb_bh(dev) ;
1109 } else {
1110 writel(ACK_INTERRUPT | LATCH_ACK | ASBFACK, xl_mmio + MMIO_COMMAND) ;
1111 }
1112 } /* Asbf */
1113
1114 if (intstatus & UPCOMPINT ) /* UpComplete */
1115 xl_rx(dev) ;
1116
1117 if (intstatus & DNCOMPINT ) /* DnComplete */
1118 xl_dn_comp(dev) ;
1119
1120 if (intstatus & HARDERRINT ) { /* Hardware error */
1121 writel(MMIO_WORD_READ | MACSTATUS, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1122 macstatus = readw(xl_mmio + MMIO_MACDATA) ;
1123 printk(KERN_WARNING "%s: MacStatusError, details: ", dev->name);
1124 if (macstatus & (1<<14))
1125 printk(KERN_WARNING "tchk error: Unrecoverable error \n") ;
1126 if (macstatus & (1<<3))
1127 printk(KERN_WARNING "eint error: Internal watchdog timer expired \n") ;
1128 if (macstatus & (1<<2))
1129 printk(KERN_WARNING "aint error: Host tried to perform invalid operation \n") ;
1130 printk(KERN_WARNING "Instatus = %02x, macstatus = %02x\n",intstatus,macstatus) ;
1131 printk(KERN_WARNING "%s: Resetting hardware: \n", dev->name);
1132 netif_stop_queue(dev) ;
1133 xl_freemem(dev) ;
1134 free_irq(dev->irq,dev);
1135 unregister_netdev(dev) ;
1136 free_netdev(dev) ;
1137 xl_reset(dev) ;
1138 writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
1139 spin_unlock(&xl_priv->xl_lock) ;
1140 return IRQ_HANDLED;
1141 }
1142 } else {
1143 printk(KERN_WARNING "%s: Received Unknown interrupt : %04x \n", dev->name, intstatus) ;
1144 writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
1145 }
1146 }
1147
1148 /* Turn interrupts back on */
1149
1150 writel( SETINDENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ;
1151 writel( SETINTENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ;
1152
1153 spin_unlock(&xl_priv->xl_lock) ;
1154 return IRQ_HANDLED;
1155 }
1156
1157 /*
1158 * Tx - Polling configuration
1159 */
1160
1161 static int xl_xmit(struct sk_buff *skb, struct net_device *dev)
1162 {
1163 struct xl_private *xl_priv=netdev_priv(dev);
1164 struct xl_tx_desc *txd ;
1165 int tx_head, tx_tail, tx_prev ;
1166 unsigned long flags ;
1167
1168 spin_lock_irqsave(&xl_priv->xl_lock,flags) ;
1169
1170 netif_stop_queue(dev) ;
1171
1172 if (xl_priv->free_ring_entries > 1 ) {
1173 /*
1174 * Set up the descriptor for the packet
1175 */
1176 tx_head = xl_priv->tx_ring_head ;
1177 tx_tail = xl_priv->tx_ring_tail ;
1178
1179 txd = &(xl_priv->xl_tx_ring[tx_head]) ;
1180 txd->dnnextptr = 0 ;
1181 txd->framestartheader = cpu_to_le32(skb->len) | TXDNINDICATE;
1182 txd->buffer = cpu_to_le32(pci_map_single(xl_priv->pdev, skb->data, skb->len, PCI_DMA_TODEVICE));
1183 txd->buffer_length = cpu_to_le32(skb->len) | TXDNFRAGLAST;
1184 xl_priv->tx_ring_skb[tx_head] = skb ;
1185 xl_priv->xl_stats.tx_packets++ ;
1186 xl_priv->xl_stats.tx_bytes += skb->len ;
1187
1188 /*
1189 * Set the nextptr of the previous descriptor equal to this descriptor, add XL_TX_RING_SIZE -1
1190 * to ensure no negative numbers in unsigned locations.
1191 */
1192
1193 tx_prev = (xl_priv->tx_ring_head + XL_TX_RING_SIZE - 1) & (XL_TX_RING_SIZE - 1) ;
1194
1195 xl_priv->tx_ring_head++ ;
1196 xl_priv->tx_ring_head &= (XL_TX_RING_SIZE - 1) ;
1197 xl_priv->free_ring_entries-- ;
1198
1199 xl_priv->xl_tx_ring[tx_prev].dnnextptr = cpu_to_le32(xl_priv->tx_ring_dma_addr + (sizeof (struct xl_tx_desc) * tx_head));
1200
1201 /* Sneaky, by doing a read on DnListPtr we can force the card to poll on the DnNextPtr */
1202 /* readl(xl_mmio + MMIO_DNLISTPTR) ; */
1203
1204 netif_wake_queue(dev) ;
1205
1206 spin_unlock_irqrestore(&xl_priv->xl_lock,flags) ;
1207
1208 return 0;
1209 } else {
1210 spin_unlock_irqrestore(&xl_priv->xl_lock,flags) ;
1211 return 1;
1212 }
1213
1214 }
1215
1216 /*
1217 * The NIC has told us that a packet has been downloaded onto the card, we must
1218 * find out which packet it has done, clear the skb and information for the packet
1219 * then advance around the ring for all tranmitted packets
1220 */
1221
1222 static void xl_dn_comp(struct net_device *dev)
1223 {
1224 struct xl_private *xl_priv=netdev_priv(dev);
1225 u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
1226 struct xl_tx_desc *txd ;
1227
1228
1229 if (xl_priv->tx_ring_tail == 255) {/* First time */
1230 xl_priv->xl_tx_ring[0].framestartheader = 0 ;
1231 xl_priv->xl_tx_ring[0].dnnextptr = 0 ;
1232 xl_priv->tx_ring_tail = 1 ;
1233 }
1234
1235 while (xl_priv->xl_tx_ring[xl_priv->tx_ring_tail].framestartheader & TXDNCOMPLETE ) {
1236 txd = &(xl_priv->xl_tx_ring[xl_priv->tx_ring_tail]) ;
1237 pci_unmap_single(xl_priv->pdev, le32_to_cpu(txd->buffer), xl_priv->tx_ring_skb[xl_priv->tx_ring_tail]->len, PCI_DMA_TODEVICE);
1238 txd->framestartheader = 0 ;
1239 txd->buffer = cpu_to_le32(0xdeadbeef);
1240 txd->buffer_length = 0 ;
1241 dev_kfree_skb_irq(xl_priv->tx_ring_skb[xl_priv->tx_ring_tail]) ;
1242 xl_priv->tx_ring_tail++ ;
1243 xl_priv->tx_ring_tail &= (XL_TX_RING_SIZE - 1) ;
1244 xl_priv->free_ring_entries++ ;
1245 }
1246
1247 netif_wake_queue(dev) ;
1248
1249 writel(ACK_INTERRUPT | DNCOMPACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ;
1250 }
1251
1252 /*
1253 * Close the adapter properly.
1254 * This srb reply cannot be handled from interrupt context as we have
1255 * to free the interrupt from the driver.
1256 */
1257
1258 static int xl_close(struct net_device *dev)
1259 {
1260 struct xl_private *xl_priv = netdev_priv(dev);
1261 u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
1262 unsigned long t ;
1263
1264 netif_stop_queue(dev) ;
1265
1266 /*
1267 * Close the adapter, need to stall the rx and tx queues.
1268 */
1269
1270 writew(DNSTALL, xl_mmio + MMIO_COMMAND) ;
1271 t=jiffies;
1272 while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
1273 schedule();
1274 if (time_after(jiffies, t + 10 * HZ)) {
1275 printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-DNSTALL not responding.\n", dev->name);
1276 break ;
1277 }
1278 }
1279 writew(DNDISABLE, xl_mmio + MMIO_COMMAND) ;
1280 t=jiffies;
1281 while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
1282 schedule();
1283 if (time_after(jiffies, t + 10 * HZ)) {
1284 printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-DNDISABLE not responding.\n", dev->name);
1285 break ;
1286 }
1287 }
1288 writew(UPSTALL, xl_mmio + MMIO_COMMAND) ;
1289 t=jiffies;
1290 while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
1291 schedule();
1292 if (time_after(jiffies, t + 10 * HZ)) {
1293 printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-UPSTALL not responding.\n", dev->name);
1294 break ;
1295 }
1296 }
1297
1298 /* Turn off interrupts, we will still get the indication though
1299 * so we can trap it
1300 */
1301
1302 writel(SETINTENABLE, xl_mmio + MMIO_COMMAND) ;
1303
1304 xl_srb_cmd(dev,CLOSE_NIC) ;
1305
1306 t=jiffies;
1307 while (!(readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_SRB)) {
1308 schedule();
1309 if (time_after(jiffies, t + 10 * HZ)) {
1310 printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-CLOSENIC not responding.\n", dev->name);
1311 break ;
1312 }
1313 }
1314 /* Read the srb response from the adapter */
1315
1316 writel(MEM_BYTE_READ | 0xd0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD);
1317 if (readb(xl_mmio + MMIO_MACDATA) != CLOSE_NIC) {
1318 printk(KERN_INFO "%s: CLOSE_NIC did not get a CLOSE_NIC response \n",dev->name) ;
1319 } else {
1320 writel((MEM_BYTE_READ | 0xd0000 | xl_priv->srb) +2, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1321 if (readb(xl_mmio + MMIO_MACDATA)==0) {
1322 printk(KERN_INFO "%s: Adapter has been closed \n",dev->name) ;
1323 writew(ACK_INTERRUPT | SRBRACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
1324
1325 xl_freemem(dev) ;
1326 free_irq(dev->irq,dev) ;
1327 } else {
1328 printk(KERN_INFO "%s: Close nic command returned error code %02x\n",dev->name, readb(xl_mmio + MMIO_MACDATA)) ;
1329 }
1330 }
1331
1332 /* Reset the upload and download logic */
1333
1334 writew(UPRESET, xl_mmio + MMIO_COMMAND) ;
1335 t=jiffies;
1336 while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
1337 schedule();
1338 if (time_after(jiffies, t + 10 * HZ)) {
1339 printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-UPRESET not responding.\n", dev->name);
1340 break ;
1341 }
1342 }
1343 writew(DNRESET, xl_mmio + MMIO_COMMAND) ;
1344 t=jiffies;
1345 while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
1346 schedule();
1347 if (time_after(jiffies, t + 10 * HZ)) {
1348 printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-DNRESET not responding.\n", dev->name);
1349 break ;
1350 }
1351 }
1352 xl_hw_reset(dev) ;
1353 return 0 ;
1354 }
1355
1356 static void xl_set_rx_mode(struct net_device *dev)
1357 {
1358 struct xl_private *xl_priv = netdev_priv(dev);
1359 struct dev_mc_list *dmi ;
1360 unsigned char dev_mc_address[4] ;
1361 u16 options ;
1362 int i ;
1363
1364 if (dev->flags & IFF_PROMISC)
1365 options = 0x0004 ;
1366 else
1367 options = 0x0000 ;
1368
1369 if (options ^ xl_priv->xl_copy_all_options) { /* Changed, must send command */
1370 xl_priv->xl_copy_all_options = options ;
1371 xl_srb_cmd(dev, SET_RECEIVE_MODE) ;
1372 return ;
1373 }
1374
1375 dev_mc_address[0] = dev_mc_address[1] = dev_mc_address[2] = dev_mc_address[3] = 0 ;
1376
1377 for (i=0,dmi=dev->mc_list;i < dev->mc_count; i++,dmi = dmi->next) {
1378 dev_mc_address[0] |= dmi->dmi_addr[2] ;
1379 dev_mc_address[1] |= dmi->dmi_addr[3] ;
1380 dev_mc_address[2] |= dmi->dmi_addr[4] ;
1381 dev_mc_address[3] |= dmi->dmi_addr[5] ;
1382 }
1383
1384 if (memcmp(xl_priv->xl_functional_addr,dev_mc_address,4) != 0) { /* Options have changed, run the command */
1385 memcpy(xl_priv->xl_functional_addr, dev_mc_address,4) ;
1386 xl_srb_cmd(dev, SET_FUNC_ADDRESS) ;
1387 }
1388 return ;
1389 }
1390
1391
1392 /*
1393 * We issued an srb command and now we must read
1394 * the response from the completed command.
1395 */
1396
1397 static void xl_srb_bh(struct net_device *dev)
1398 {
1399 struct xl_private *xl_priv = netdev_priv(dev);
1400 u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
1401 u8 srb_cmd, ret_code ;
1402 int i ;
1403
1404 writel(MEM_BYTE_READ | 0xd0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1405 srb_cmd = readb(xl_mmio + MMIO_MACDATA) ;
1406 writel((MEM_BYTE_READ | 0xd0000 | xl_priv->srb) +2, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1407 ret_code = readb(xl_mmio + MMIO_MACDATA) ;
1408
1409 /* Ret_code is standard across all commands */
1410
1411 switch (ret_code) {
1412 case 1:
1413 printk(KERN_INFO "%s: Command: %d - Invalid Command code\n",dev->name,srb_cmd) ;
1414 break ;
1415 case 4:
1416 printk(KERN_INFO "%s: Command: %d - Adapter is closed, must be open for this command \n",dev->name,srb_cmd) ;
1417 break ;
1418
1419 case 6:
1420 printk(KERN_INFO "%s: Command: %d - Options Invalid for command \n",dev->name,srb_cmd) ;
1421 break ;
1422
1423 case 0: /* Successful command execution */
1424 switch (srb_cmd) {
1425 case READ_LOG: /* Returns 14 bytes of data from the NIC */
1426 if(xl_priv->xl_message_level)
1427 printk(KERN_INFO "%s: READ.LOG 14 bytes of data ",dev->name) ;
1428 /*
1429 * We still have to read the log even if message_level = 0 and we don't want
1430 * to see it
1431 */
1432 for (i=0;i<14;i++) {
1433 writel(MEM_BYTE_READ | 0xd0000 | xl_priv->srb | i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1434 if(xl_priv->xl_message_level)
1435 printk("%02x:",readb(xl_mmio + MMIO_MACDATA)) ;
1436 }
1437 printk("\n") ;
1438 break ;
1439 case SET_FUNC_ADDRESS:
1440 if(xl_priv->xl_message_level)
1441 printk(KERN_INFO "%s: Functional Address Set \n",dev->name) ;
1442 break ;
1443 case CLOSE_NIC:
1444 if(xl_priv->xl_message_level)
1445 printk(KERN_INFO "%s: Received CLOSE_NIC interrupt in interrupt handler \n",dev->name) ;
1446 break ;
1447 case SET_MULTICAST_MODE:
1448 if(xl_priv->xl_message_level)
1449 printk(KERN_INFO "%s: Multicast options successfully changed\n",dev->name) ;
1450 break ;
1451 case SET_RECEIVE_MODE:
1452 if(xl_priv->xl_message_level) {
1453 if (xl_priv->xl_copy_all_options == 0x0004)
1454 printk(KERN_INFO "%s: Entering promiscuous mode \n", dev->name) ;
1455 else
1456 printk(KERN_INFO "%s: Entering normal receive mode \n",dev->name) ;
1457 }
1458 break ;
1459
1460 } /* switch */
1461 break ;
1462 } /* switch */
1463 return ;
1464 }
1465
1466 static struct net_device_stats * xl_get_stats(struct net_device *dev)
1467 {
1468 struct xl_private *xl_priv = netdev_priv(dev);
1469 return (struct net_device_stats *) &xl_priv->xl_stats;
1470 }
1471
1472 static int xl_set_mac_address (struct net_device *dev, void *addr)
1473 {
1474 struct sockaddr *saddr = addr ;
1475 struct xl_private *xl_priv = netdev_priv(dev);
1476
1477 if (netif_running(dev)) {
1478 printk(KERN_WARNING "%s: Cannot set mac/laa address while card is open\n", dev->name) ;
1479 return -EIO ;
1480 }
1481
1482 memcpy(xl_priv->xl_laa, saddr->sa_data,dev->addr_len) ;
1483
1484 if (xl_priv->xl_message_level) {
1485 printk(KERN_INFO "%s: MAC/LAA Set to = %x.%x.%x.%x.%x.%x\n",dev->name, xl_priv->xl_laa[0],
1486 xl_priv->xl_laa[1], xl_priv->xl_laa[2],
1487 xl_priv->xl_laa[3], xl_priv->xl_laa[4],
1488 xl_priv->xl_laa[5]);
1489 }
1490
1491 return 0 ;
1492 }
1493
1494 static void xl_arb_cmd(struct net_device *dev)
1495 {
1496 struct xl_private *xl_priv = netdev_priv(dev);
1497 u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
1498 u8 arb_cmd ;
1499 u16 lan_status, lan_status_diff ;
1500
1501 writel( ( MEM_BYTE_READ | 0xD0000 | xl_priv->arb), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1502 arb_cmd = readb(xl_mmio + MMIO_MACDATA) ;
1503
1504 if (arb_cmd == RING_STATUS_CHANGE) { /* Ring.Status.Change */
1505 writel( ( (MEM_WORD_READ | 0xD0000 | xl_priv->arb) + 6), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1506
1507 printk(KERN_INFO "%s: Ring Status Change: New Status = %04x\n", dev->name, swab16(readw(xl_mmio + MMIO_MACDATA) )) ;
1508
1509 lan_status = swab16(readw(xl_mmio + MMIO_MACDATA));
1510
1511 /* Acknowledge interrupt, this tells nic we are done with the arb */
1512 writel(ACK_INTERRUPT | ARBCACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
1513
1514 lan_status_diff = xl_priv->xl_lan_status ^ lan_status ;
1515
1516 if (lan_status_diff & (LSC_LWF | LSC_ARW | LSC_FPE | LSC_RR) ) {
1517 if (lan_status_diff & LSC_LWF)
1518 printk(KERN_WARNING "%s: Short circuit detected on the lobe\n",dev->name);
1519 if (lan_status_diff & LSC_ARW)
1520 printk(KERN_WARNING "%s: Auto removal error\n",dev->name);
1521 if (lan_status_diff & LSC_FPE)
1522 printk(KERN_WARNING "%s: FDX Protocol Error\n",dev->name);
1523 if (lan_status_diff & LSC_RR)
1524 printk(KERN_WARNING "%s: Force remove MAC frame received\n",dev->name);
1525
1526 /* Adapter has been closed by the hardware */
1527
1528 netif_stop_queue(dev);
1529 xl_freemem(dev) ;
1530 free_irq(dev->irq,dev);
1531
1532 printk(KERN_WARNING "%s: Adapter has been closed \n", dev->name) ;
1533 } /* If serious error */
1534
1535 if (xl_priv->xl_message_level) {
1536 if (lan_status_diff & LSC_SIG_LOSS)
1537 printk(KERN_WARNING "%s: No receive signal detected \n", dev->name) ;
1538 if (lan_status_diff & LSC_HARD_ERR)
1539 printk(KERN_INFO "%s: Beaconing \n",dev->name);
1540 if (lan_status_diff & LSC_SOFT_ERR)
1541 printk(KERN_WARNING "%s: Adapter transmitted Soft Error Report Mac Frame \n",dev->name);
1542 if (lan_status_diff & LSC_TRAN_BCN)
1543 printk(KERN_INFO "%s: We are tranmitting the beacon, aaah\n",dev->name);
1544 if (lan_status_diff & LSC_SS)
1545 printk(KERN_INFO "%s: Single Station on the ring \n", dev->name);
1546 if (lan_status_diff & LSC_RING_REC)
1547 printk(KERN_INFO "%s: Ring recovery ongoing\n",dev->name);
1548 if (lan_status_diff & LSC_FDX_MODE)
1549 printk(KERN_INFO "%s: Operating in FDX mode\n",dev->name);
1550 }
1551
1552 if (lan_status_diff & LSC_CO) {
1553 if (xl_priv->xl_message_level)
1554 printk(KERN_INFO "%s: Counter Overflow \n", dev->name);
1555 /* Issue READ.LOG command */
1556 xl_srb_cmd(dev, READ_LOG) ;
1557 }
1558
1559 /* There is no command in the tech docs to issue the read_sr_counters */
1560 if (lan_status_diff & LSC_SR_CO) {
1561 if (xl_priv->xl_message_level)
1562 printk(KERN_INFO "%s: Source routing counters overflow\n", dev->name);
1563 }
1564
1565 xl_priv->xl_lan_status = lan_status ;
1566
1567 } /* Lan.change.status */
1568 else if ( arb_cmd == RECEIVE_DATA) { /* Received.Data */
1569 #if XL_DEBUG
1570 printk(KERN_INFO "Received.Data \n") ;
1571 #endif
1572 writel( ((MEM_WORD_READ | 0xD0000 | xl_priv->arb) + 6), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1573 xl_priv->mac_buffer = swab16(readw(xl_mmio + MMIO_MACDATA)) ;
1574
1575 /* Now we are going to be really basic here and not do anything
1576 * with the data at all. The tech docs do not give me enough
1577 * information to calculate the buffers properly so we're
1578 * just going to tell the nic that we've dealt with the frame
1579 * anyway.
1580 */
1581
1582 dev->last_rx = jiffies ;
1583 /* Acknowledge interrupt, this tells nic we are done with the arb */
1584 writel(ACK_INTERRUPT | ARBCACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
1585
1586 /* Is the ASB free ? */
1587
1588 xl_priv->asb_queued = 0 ;
1589 writel( ((MEM_BYTE_READ | 0xD0000 | xl_priv->asb) + 2), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1590 if (readb(xl_mmio + MMIO_MACDATA) != 0xff) {
1591 xl_priv->asb_queued = 1 ;
1592
1593 xl_wait_misr_flags(dev) ;
1594
1595 writel(MEM_BYTE_WRITE | MF_ASBFR, xl_mmio + MMIO_MAC_ACCESS_CMD);
1596 writeb(0xff, xl_mmio + MMIO_MACDATA) ;
1597 writel(MMIO_BYTE_WRITE | MISR_SET, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1598 writeb(MISR_ASBFR, xl_mmio + MMIO_MACDATA) ;
1599 return ;
1600 /* Drop out and wait for the bottom half to be run */
1601 }
1602
1603 xl_asb_cmd(dev) ;
1604
1605 } else {
1606 printk(KERN_WARNING "%s: Received unknown arb (xl_priv) command: %02x \n",dev->name,arb_cmd) ;
1607 }
1608
1609 /* Acknowledge the arb interrupt */
1610
1611 writel(ACK_INTERRUPT | ARBCACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ;
1612
1613 return ;
1614 }
1615
1616
1617 /*
1618 * There is only one asb command, but we can get called from different
1619 * places.
1620 */
1621
1622 static void xl_asb_cmd(struct net_device *dev)
1623 {
1624 struct xl_private *xl_priv = netdev_priv(dev);
1625 u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
1626
1627 if (xl_priv->asb_queued == 1)
1628 writel(ACK_INTERRUPT | LATCH_ACK | ASBFACK, xl_mmio + MMIO_COMMAND) ;
1629
1630 writel(MEM_BYTE_WRITE | 0xd0000 | xl_priv->asb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1631 writeb(0x81, xl_mmio + MMIO_MACDATA) ;
1632
1633 writel(MEM_WORD_WRITE | 0xd0000 | xl_priv->asb | 6, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1634 writew(swab16(xl_priv->mac_buffer), xl_mmio + MMIO_MACDATA) ;
1635
1636 xl_wait_misr_flags(dev) ;
1637
1638 writel(MEM_BYTE_WRITE | MF_RASB, xl_mmio + MMIO_MAC_ACCESS_CMD);
1639 writeb(0xff, xl_mmio + MMIO_MACDATA) ;
1640
1641 writel(MMIO_BYTE_WRITE | MISR_SET, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1642 writeb(MISR_RASB, xl_mmio + MMIO_MACDATA) ;
1643
1644 xl_priv->asb_queued = 2 ;
1645
1646 return ;
1647 }
1648
1649 /*
1650 * This will only get called if there was an error
1651 * from the asb cmd.
1652 */
1653 static void xl_asb_bh(struct net_device *dev)
1654 {
1655 struct xl_private *xl_priv = netdev_priv(dev);
1656 u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
1657 u8 ret_code ;
1658
1659 writel(MMIO_BYTE_READ | 0xd0000 | xl_priv->asb | 2, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1660 ret_code = readb(xl_mmio + MMIO_MACDATA) ;
1661 switch (ret_code) {
1662 case 0x01:
1663 printk(KERN_INFO "%s: ASB Command, unrecognized command code \n",dev->name) ;
1664 break ;
1665 case 0x26:
1666 printk(KERN_INFO "%s: ASB Command, unexpected receive buffer \n", dev->name) ;
1667 break ;
1668 case 0x40:
1669 printk(KERN_INFO "%s: ASB Command, Invalid Station ID \n", dev->name) ;
1670 break ;
1671 }
1672 xl_priv->asb_queued = 0 ;
1673 writel(ACK_INTERRUPT | LATCH_ACK | ASBFACK, xl_mmio + MMIO_COMMAND) ;
1674 return ;
1675 }
1676
1677 /*
1678 * Issue srb commands to the nic
1679 */
1680
1681 static void xl_srb_cmd(struct net_device *dev, int srb_cmd)
1682 {
1683 struct xl_private *xl_priv = netdev_priv(dev);
1684 u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
1685
1686 switch (srb_cmd) {
1687 case READ_LOG:
1688 writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1689 writeb(READ_LOG, xl_mmio + MMIO_MACDATA) ;
1690 break;
1691
1692 case CLOSE_NIC:
1693 writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1694 writeb(CLOSE_NIC, xl_mmio + MMIO_MACDATA) ;
1695 break ;
1696
1697 case SET_RECEIVE_MODE:
1698 writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1699 writeb(SET_RECEIVE_MODE, xl_mmio + MMIO_MACDATA) ;
1700 writel(MEM_WORD_WRITE | 0xD0000 | xl_priv->srb | 4, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1701 writew(xl_priv->xl_copy_all_options, xl_mmio + MMIO_MACDATA) ;
1702 break ;
1703
1704 case SET_FUNC_ADDRESS:
1705 writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1706 writeb(SET_FUNC_ADDRESS, xl_mmio + MMIO_MACDATA) ;
1707 writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb | 6 , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1708 writeb(xl_priv->xl_functional_addr[0], xl_mmio + MMIO_MACDATA) ;
1709 writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb | 7 , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1710 writeb(xl_priv->xl_functional_addr[1], xl_mmio + MMIO_MACDATA) ;
1711 writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb | 8 , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1712 writeb(xl_priv->xl_functional_addr[2], xl_mmio + MMIO_MACDATA) ;
1713 writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb | 9 , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1714 writeb(xl_priv->xl_functional_addr[3], xl_mmio + MMIO_MACDATA) ;
1715 break ;
1716 } /* switch */
1717
1718
1719 xl_wait_misr_flags(dev) ;
1720
1721 /* Write 0xff to the CSRB flag */
1722 writel(MEM_BYTE_WRITE | MF_CSRB , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1723 writeb(0xFF, xl_mmio + MMIO_MACDATA) ;
1724 /* Set csrb bit in MISR register to process command */
1725 writel(MMIO_BYTE_WRITE | MISR_SET, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1726 writeb(MISR_CSRB, xl_mmio + MMIO_MACDATA) ;
1727 xl_priv->srb_queued = 1 ;
1728
1729 return ;
1730 }
1731
1732 /*
1733 * This is nasty, to use the MISR command you have to wait for 6 memory locations
1734 * to be zero. This is the way the driver does on other OS'es so we should be ok with
1735 * the empty loop.
1736 */
1737
1738 static void xl_wait_misr_flags(struct net_device *dev)
1739 {
1740 struct xl_private *xl_priv = netdev_priv(dev);
1741 u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
1742
1743 int i ;
1744
1745 writel(MMIO_BYTE_READ | MISR_RW, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1746 if (readb(xl_mmio + MMIO_MACDATA) != 0) { /* Misr not clear */
1747 for (i=0; i<6; i++) {
1748 writel(MEM_BYTE_READ | 0xDFFE0 | i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1749 while (readb(xl_mmio + MMIO_MACDATA) != 0 ) {} ; /* Empty Loop */
1750 }
1751 }
1752
1753 writel(MMIO_BYTE_WRITE | MISR_AND, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1754 writeb(0x80, xl_mmio + MMIO_MACDATA) ;
1755
1756 return ;
1757 }
1758
1759 /*
1760 * Change mtu size, this should work the same as olympic
1761 */
1762
1763 static int xl_change_mtu(struct net_device *dev, int mtu)
1764 {
1765 struct xl_private *xl_priv = netdev_priv(dev);
1766 u16 max_mtu ;
1767
1768 if (xl_priv->xl_ring_speed == 4)
1769 max_mtu = 4500 ;
1770 else
1771 max_mtu = 18000 ;
1772
1773 if (mtu > max_mtu)
1774 return -EINVAL ;
1775 if (mtu < 100)
1776 return -EINVAL ;
1777
1778 dev->mtu = mtu ;
1779 xl_priv->pkt_buf_sz = mtu + TR_HLEN ;
1780
1781 return 0 ;
1782 }
1783
1784 static void __devexit xl_remove_one (struct pci_dev *pdev)
1785 {
1786 struct net_device *dev = pci_get_drvdata(pdev);
1787 struct xl_private *xl_priv=netdev_priv(dev);
1788
1789 unregister_netdev(dev);
1790 iounmap(xl_priv->xl_mmio) ;
1791 pci_release_regions(pdev) ;
1792 pci_set_drvdata(pdev,NULL) ;
1793 free_netdev(dev);
1794 return ;
1795 }
1796
1797 static struct pci_driver xl_3c359_driver = {
1798 .name = "3c359",
1799 .id_table = xl_pci_tbl,
1800 .probe = xl_probe,
1801 .remove = __devexit_p(xl_remove_one),
1802 };
1803
1804 static int __init xl_pci_init (void)
1805 {
1806 return pci_register_driver(&xl_3c359_driver);
1807 }
1808
1809
1810 static void __exit xl_pci_cleanup (void)
1811 {
1812 pci_unregister_driver (&xl_3c359_driver);
1813 }
1814
1815 module_init(xl_pci_init);
1816 module_exit(xl_pci_cleanup);
1817
1818 MODULE_LICENSE("GPL") ;
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