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ia64/kvm: compilation fix. export account_system_vtime.
[pv_ops_mirror.git] / drivers / net / wireless / adm8211.c
blob5c0d2b082750d550d7025b3e6716179ea6ea274a
1
2 /*
3 * Linux device driver for ADMtek ADM8211 (IEEE 802.11b MAC/BBP)
4 *
5 * Copyright (c) 2003, Jouni Malinen <j@w1.fi>
6 * Copyright (c) 2004-2007, Michael Wu <flamingice@sourmilk.net>
7 * Some parts copyright (c) 2003 by David Young <dyoung@pobox.com>
8 * and used with permission.
9 *
10 * Much thanks to Infineon-ADMtek for their support of this driver.
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation. See README and COPYING for
15 * more details.
16 */
17
18 #include <linux/init.h>
19 #include <linux/if.h>
20 #include <linux/skbuff.h>
21 #include <linux/etherdevice.h>
22 #include <linux/pci.h>
23 #include <linux/delay.h>
24 #include <linux/crc32.h>
25 #include <linux/eeprom_93cx6.h>
26 #include <net/mac80211.h>
27
28 #include "adm8211.h"
29
30 MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
31 MODULE_AUTHOR("Jouni Malinen <j@w1.fi>");
32 MODULE_DESCRIPTION("Driver for IEEE 802.11b wireless cards based on ADMtek ADM8211");
33 MODULE_SUPPORTED_DEVICE("ADM8211");
34 MODULE_LICENSE("GPL");
35
36 static unsigned int tx_ring_size __read_mostly = 16;
37 static unsigned int rx_ring_size __read_mostly = 16;
38
39 module_param(tx_ring_size, uint, 0);
40 module_param(rx_ring_size, uint, 0);
41
42 static struct pci_device_id adm8211_pci_id_table[] __devinitdata = {
43 /* ADMtek ADM8211 */
44 { PCI_DEVICE(0x10B7, 0x6000) }, /* 3Com 3CRSHPW796 */
45 { PCI_DEVICE(0x1200, 0x8201) }, /* ? */
46 { PCI_DEVICE(0x1317, 0x8201) }, /* ADM8211A */
47 { PCI_DEVICE(0x1317, 0x8211) }, /* ADM8211B/C */
48 { 0 }
49 };
50
51 static struct ieee80211_rate adm8211_rates[] = {
52 { .bitrate = 10, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
53 { .bitrate = 20, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
54 { .bitrate = 55, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
55 { .bitrate = 110, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
56 { .bitrate = 220, .flags = IEEE80211_RATE_SHORT_PREAMBLE }, /* XX ?? */
57 };
58
59 static const struct ieee80211_channel adm8211_channels[] = {
60 { .center_freq = 2412},
61 { .center_freq = 2417},
62 { .center_freq = 2422},
63 { .center_freq = 2427},
64 { .center_freq = 2432},
65 { .center_freq = 2437},
66 { .center_freq = 2442},
67 { .center_freq = 2447},
68 { .center_freq = 2452},
69 { .center_freq = 2457},
70 { .center_freq = 2462},
71 { .center_freq = 2467},
72 { .center_freq = 2472},
73 { .center_freq = 2484},
74 };
75
76
77 static void adm8211_eeprom_register_read(struct eeprom_93cx6 *eeprom)
78 {
79 struct adm8211_priv *priv = eeprom->data;
80 u32 reg = ADM8211_CSR_READ(SPR);
81
82 eeprom->reg_data_in = reg & ADM8211_SPR_SDI;
83 eeprom->reg_data_out = reg & ADM8211_SPR_SDO;
84 eeprom->reg_data_clock = reg & ADM8211_SPR_SCLK;
85 eeprom->reg_chip_select = reg & ADM8211_SPR_SCS;
86 }
87
88 static void adm8211_eeprom_register_write(struct eeprom_93cx6 *eeprom)
89 {
90 struct adm8211_priv *priv = eeprom->data;
91 u32 reg = 0x4000 | ADM8211_SPR_SRS;
92
93 if (eeprom->reg_data_in)
94 reg |= ADM8211_SPR_SDI;
95 if (eeprom->reg_data_out)
96 reg |= ADM8211_SPR_SDO;
97 if (eeprom->reg_data_clock)
98 reg |= ADM8211_SPR_SCLK;
99 if (eeprom->reg_chip_select)
100 reg |= ADM8211_SPR_SCS;
101
102 ADM8211_CSR_WRITE(SPR, reg);
103 ADM8211_CSR_READ(SPR); /* eeprom_delay */
104 }
105
106 static int adm8211_read_eeprom(struct ieee80211_hw *dev)
107 {
108 struct adm8211_priv *priv = dev->priv;
109 unsigned int words, i;
110 struct ieee80211_chan_range chan_range;
111 u16 cr49;
112 struct eeprom_93cx6 eeprom = {
113 .data = priv,
114 .register_read = adm8211_eeprom_register_read,
115 .register_write = adm8211_eeprom_register_write
116 };
117
118 if (ADM8211_CSR_READ(CSR_TEST0) & ADM8211_CSR_TEST0_EPTYP) {
119 /* 256 * 16-bit = 512 bytes */
120 eeprom.width = PCI_EEPROM_WIDTH_93C66;
121 words = 256;
122 } else {
123 /* 64 * 16-bit = 128 bytes */
124 eeprom.width = PCI_EEPROM_WIDTH_93C46;
125 words = 64;
126 }
127
128 priv->eeprom_len = words * 2;
129 priv->eeprom = kmalloc(priv->eeprom_len, GFP_KERNEL);
130 if (!priv->eeprom)
131 return -ENOMEM;
132
133 eeprom_93cx6_multiread(&eeprom, 0, (__le16 *)priv->eeprom, words);
134
135 cr49 = le16_to_cpu(priv->eeprom->cr49);
136 priv->rf_type = (cr49 >> 3) & 0x7;
137 switch (priv->rf_type) {
138 case ADM8211_TYPE_INTERSIL:
139 case ADM8211_TYPE_RFMD:
140 case ADM8211_TYPE_MARVEL:
141 case ADM8211_TYPE_AIROHA:
142 case ADM8211_TYPE_ADMTEK:
143 break;
144
145 default:
146 if (priv->pdev->revision < ADM8211_REV_CA)
147 priv->rf_type = ADM8211_TYPE_RFMD;
148 else
149 priv->rf_type = ADM8211_TYPE_AIROHA;
150
151 printk(KERN_WARNING "%s (adm8211): Unknown RFtype %d\n",
152 pci_name(priv->pdev), (cr49 >> 3) & 0x7);
153 }
154
155 priv->bbp_type = cr49 & 0x7;
156 switch (priv->bbp_type) {
157 case ADM8211_TYPE_INTERSIL:
158 case ADM8211_TYPE_RFMD:
159 case ADM8211_TYPE_MARVEL:
160 case ADM8211_TYPE_AIROHA:
161 case ADM8211_TYPE_ADMTEK:
162 break;
163 default:
164 if (priv->pdev->revision < ADM8211_REV_CA)
165 priv->bbp_type = ADM8211_TYPE_RFMD;
166 else
167 priv->bbp_type = ADM8211_TYPE_ADMTEK;
168
169 printk(KERN_WARNING "%s (adm8211): Unknown BBPtype: %d\n",
170 pci_name(priv->pdev), cr49 >> 3);
171 }
172
173 if (priv->eeprom->country_code >= ARRAY_SIZE(cranges)) {
174 printk(KERN_WARNING "%s (adm8211): Invalid country code (%d)\n",
175 pci_name(priv->pdev), priv->eeprom->country_code);
176
177 chan_range = cranges[2];
178 } else
179 chan_range = cranges[priv->eeprom->country_code];
180
181 printk(KERN_DEBUG "%s (adm8211): Channel range: %d - %d\n",
182 pci_name(priv->pdev), (int)chan_range.min, (int)chan_range.max);
183
184 BUILD_BUG_ON(sizeof(priv->channels) != sizeof(adm8211_channels));
185
186 memcpy(priv->channels, adm8211_channels, sizeof(priv->channels));
187 priv->band.channels = priv->channels;
188 priv->band.n_channels = ARRAY_SIZE(adm8211_channels);
189 priv->band.bitrates = adm8211_rates;
190 priv->band.n_bitrates = ARRAY_SIZE(adm8211_rates);
191
192 for (i = 1; i <= ARRAY_SIZE(adm8211_channels); i++)
193 if (i < chan_range.min || i > chan_range.max)
194 priv->channels[i - 1].flags |= IEEE80211_CHAN_DISABLED;
195
196 switch (priv->eeprom->specific_bbptype) {
197 case ADM8211_BBP_RFMD3000:
198 case ADM8211_BBP_RFMD3002:
199 case ADM8211_BBP_ADM8011:
200 priv->specific_bbptype = priv->eeprom->specific_bbptype;
201 break;
202
203 default:
204 if (priv->pdev->revision < ADM8211_REV_CA)
205 priv->specific_bbptype = ADM8211_BBP_RFMD3000;
206 else
207 priv->specific_bbptype = ADM8211_BBP_ADM8011;
208
209 printk(KERN_WARNING "%s (adm8211): Unknown specific BBP: %d\n",
210 pci_name(priv->pdev), priv->eeprom->specific_bbptype);
211 }
212
213 switch (priv->eeprom->specific_rftype) {
214 case ADM8211_RFMD2948:
215 case ADM8211_RFMD2958:
216 case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
217 case ADM8211_MAX2820:
218 case ADM8211_AL2210L:
219 priv->transceiver_type = priv->eeprom->specific_rftype;
220 break;
221
222 default:
223 if (priv->pdev->revision == ADM8211_REV_BA)
224 priv->transceiver_type = ADM8211_RFMD2958_RF3000_CONTROL_POWER;
225 else if (priv->pdev->revision == ADM8211_REV_CA)
226 priv->transceiver_type = ADM8211_AL2210L;
227 else if (priv->pdev->revision == ADM8211_REV_AB)
228 priv->transceiver_type = ADM8211_RFMD2948;
229
230 printk(KERN_WARNING "%s (adm8211): Unknown transceiver: %d\n",
231 pci_name(priv->pdev), priv->eeprom->specific_rftype);
232
233 break;
234 }
235
236 printk(KERN_DEBUG "%s (adm8211): RFtype=%d BBPtype=%d Specific BBP=%d "
237 "Transceiver=%d\n", pci_name(priv->pdev), priv->rf_type,
238 priv->bbp_type, priv->specific_bbptype, priv->transceiver_type);
239
240 return 0;
241 }
242
243 static inline void adm8211_write_sram(struct ieee80211_hw *dev,
244 u32 addr, u32 data)
245 {
246 struct adm8211_priv *priv = dev->priv;
247
248 ADM8211_CSR_WRITE(WEPCTL, addr | ADM8211_WEPCTL_TABLE_WR |
249 (priv->pdev->revision < ADM8211_REV_BA ?
250 0 : ADM8211_WEPCTL_SEL_WEPTABLE ));
251 ADM8211_CSR_READ(WEPCTL);
252 msleep(1);
253
254 ADM8211_CSR_WRITE(WESK, data);
255 ADM8211_CSR_READ(WESK);
256 msleep(1);
257 }
258
259 static void adm8211_write_sram_bytes(struct ieee80211_hw *dev,
260 unsigned int addr, u8 *buf,
261 unsigned int len)
262 {
263 struct adm8211_priv *priv = dev->priv;
264 u32 reg = ADM8211_CSR_READ(WEPCTL);
265 unsigned int i;
266
267 if (priv->pdev->revision < ADM8211_REV_BA) {
268 for (i = 0; i < len; i += 2) {
269 u16 val = buf[i] | (buf[i + 1] << 8);
270 adm8211_write_sram(dev, addr + i / 2, val);
271 }
272 } else {
273 for (i = 0; i < len; i += 4) {
274 u32 val = (buf[i + 0] << 0 ) | (buf[i + 1] << 8 ) |
275 (buf[i + 2] << 16) | (buf[i + 3] << 24);
276 adm8211_write_sram(dev, addr + i / 4, val);
277 }
278 }
279
280 ADM8211_CSR_WRITE(WEPCTL, reg);
281 }
282
283 static void adm8211_clear_sram(struct ieee80211_hw *dev)
284 {
285 struct adm8211_priv *priv = dev->priv;
286 u32 reg = ADM8211_CSR_READ(WEPCTL);
287 unsigned int addr;
288
289 for (addr = 0; addr < ADM8211_SRAM_SIZE; addr++)
290 adm8211_write_sram(dev, addr, 0);
291
292 ADM8211_CSR_WRITE(WEPCTL, reg);
293 }
294
295 static int adm8211_get_stats(struct ieee80211_hw *dev,
296 struct ieee80211_low_level_stats *stats)
297 {
298 struct adm8211_priv *priv = dev->priv;
299
300 memcpy(stats, &priv->stats, sizeof(*stats));
301
302 return 0;
303 }
304
305 static int adm8211_get_tx_stats(struct ieee80211_hw *dev,
306 struct ieee80211_tx_queue_stats *stats)
307 {
308 struct adm8211_priv *priv = dev->priv;
309 struct ieee80211_tx_queue_stats_data *data = &stats->data[0];
310
311 data->len = priv->cur_tx - priv->dirty_tx;
312 data->limit = priv->tx_ring_size - 2;
313 data->count = priv->dirty_tx;
314
315 return 0;
316 }
317
318 static void adm8211_interrupt_tci(struct ieee80211_hw *dev)
319 {
320 struct adm8211_priv *priv = dev->priv;
321 unsigned int dirty_tx;
322
323 spin_lock(&priv->lock);
324
325 for (dirty_tx = priv->dirty_tx; priv->cur_tx - dirty_tx; dirty_tx++) {
326 unsigned int entry = dirty_tx % priv->tx_ring_size;
327 u32 status = le32_to_cpu(priv->tx_ring[entry].status);
328 struct ieee80211_tx_status tx_status;
329 struct adm8211_tx_ring_info *info;
330 struct sk_buff *skb;
331
332 if (status & TDES0_CONTROL_OWN ||
333 !(status & TDES0_CONTROL_DONE))
334 break;
335
336 info = &priv->tx_buffers[entry];
337 skb = info->skb;
338
339 /* TODO: check TDES0_STATUS_TUF and TDES0_STATUS_TRO */
340
341 pci_unmap_single(priv->pdev, info->mapping,
342 info->skb->len, PCI_DMA_TODEVICE);
343
344 memset(&tx_status, 0, sizeof(tx_status));
345 skb_pull(skb, sizeof(struct adm8211_tx_hdr));
346 memcpy(skb_push(skb, info->hdrlen), skb->cb, info->hdrlen);
347 memcpy(&tx_status.control, &info->tx_control,
348 sizeof(tx_status.control));
349 if (!(tx_status.control.flags & IEEE80211_TXCTL_NO_ACK)) {
350 if (status & TDES0_STATUS_ES)
351 tx_status.excessive_retries = 1;
352 else
353 tx_status.flags |= IEEE80211_TX_STATUS_ACK;
354 }
355 ieee80211_tx_status_irqsafe(dev, skb, &tx_status);
356
357 info->skb = NULL;
358 }
359
360 if (priv->cur_tx - dirty_tx < priv->tx_ring_size - 2)
361 ieee80211_wake_queue(dev, 0);
362
363 priv->dirty_tx = dirty_tx;
364 spin_unlock(&priv->lock);
365 }
366
367
368 static void adm8211_interrupt_rci(struct ieee80211_hw *dev)
369 {
370 struct adm8211_priv *priv = dev->priv;
371 unsigned int entry = priv->cur_rx % priv->rx_ring_size;
372 u32 status;
373 unsigned int pktlen;
374 struct sk_buff *skb, *newskb;
375 unsigned int limit = priv->rx_ring_size;
376 u8 rssi, rate;
377
378 while (!(priv->rx_ring[entry].status & cpu_to_le32(RDES0_STATUS_OWN))) {
379 if (!limit--)
380 break;
381
382 status = le32_to_cpu(priv->rx_ring[entry].status);
383 rate = (status & RDES0_STATUS_RXDR) >> 12;
384 rssi = le32_to_cpu(priv->rx_ring[entry].length) &
385 RDES1_STATUS_RSSI;
386
387 pktlen = status & RDES0_STATUS_FL;
388 if (pktlen > RX_PKT_SIZE) {
389 if (net_ratelimit())
390 printk(KERN_DEBUG "%s: frame too long (%d)\n",
391 wiphy_name(dev->wiphy), pktlen);
392 pktlen = RX_PKT_SIZE;
393 }
394
395 if (!priv->soft_rx_crc && status & RDES0_STATUS_ES) {
396 skb = NULL; /* old buffer will be reused */
397 /* TODO: update RX error stats */
398 /* TODO: check RDES0_STATUS_CRC*E */
399 } else if (pktlen < RX_COPY_BREAK) {
400 skb = dev_alloc_skb(pktlen);
401 if (skb) {
402 pci_dma_sync_single_for_cpu(
403 priv->pdev,
404 priv->rx_buffers[entry].mapping,
405 pktlen, PCI_DMA_FROMDEVICE);
406 memcpy(skb_put(skb, pktlen),
407 skb_tail_pointer(priv->rx_buffers[entry].skb),
408 pktlen);
409 pci_dma_sync_single_for_device(
410 priv->pdev,
411 priv->rx_buffers[entry].mapping,
412 RX_PKT_SIZE, PCI_DMA_FROMDEVICE);
413 }
414 } else {
415 newskb = dev_alloc_skb(RX_PKT_SIZE);
416 if (newskb) {
417 skb = priv->rx_buffers[entry].skb;
418 skb_put(skb, pktlen);
419 pci_unmap_single(
420 priv->pdev,
421 priv->rx_buffers[entry].mapping,
422 RX_PKT_SIZE, PCI_DMA_FROMDEVICE);
423 priv->rx_buffers[entry].skb = newskb;
424 priv->rx_buffers[entry].mapping =
425 pci_map_single(priv->pdev,
426 skb_tail_pointer(newskb),
427 RX_PKT_SIZE,
428 PCI_DMA_FROMDEVICE);
429 } else {
430 skb = NULL;
431 /* TODO: update rx dropped stats */
432 }
433
434 priv->rx_ring[entry].buffer1 =
435 cpu_to_le32(priv->rx_buffers[entry].mapping);
436 }
437
438 priv->rx_ring[entry].status = cpu_to_le32(RDES0_STATUS_OWN |
439 RDES0_STATUS_SQL);
440 priv->rx_ring[entry].length =
441 cpu_to_le32(RX_PKT_SIZE |
442 (entry == priv->rx_ring_size - 1 ?
443 RDES1_CONTROL_RER : 0));
444
445 if (skb) {
446 struct ieee80211_rx_status rx_status = {0};
447
448 if (priv->pdev->revision < ADM8211_REV_CA)
449 rx_status.ssi = rssi;
450 else
451 rx_status.ssi = 100 - rssi;
452
453 rx_status.rate_idx = rate;
454
455 rx_status.freq = adm8211_channels[priv->channel - 1].center_freq;
456 rx_status.band = IEEE80211_BAND_2GHZ;
457
458 ieee80211_rx_irqsafe(dev, skb, &rx_status);
459 }
460
461 entry = (++priv->cur_rx) % priv->rx_ring_size;
462 }
463
464 /* TODO: check LPC and update stats? */
465 }
466
467
468 static irqreturn_t adm8211_interrupt(int irq, void *dev_id)
469 {
470 #define ADM8211_INT(x) \
471 do { \
472 if (unlikely(stsr & ADM8211_STSR_ ## x)) \
473 printk(KERN_DEBUG "%s: " #x "\n", wiphy_name(dev->wiphy)); \
474 } while (0)
475
476 struct ieee80211_hw *dev = dev_id;
477 struct adm8211_priv *priv = dev->priv;
478 u32 stsr = ADM8211_CSR_READ(STSR);
479 ADM8211_CSR_WRITE(STSR, stsr);
480 if (stsr == 0xffffffff)
481 return IRQ_HANDLED;
482
483 if (!(stsr & (ADM8211_STSR_NISS | ADM8211_STSR_AISS)))
484 return IRQ_HANDLED;
485
486 if (stsr & ADM8211_STSR_RCI)
487 adm8211_interrupt_rci(dev);
488 if (stsr & ADM8211_STSR_TCI)
489 adm8211_interrupt_tci(dev);
490
491 ADM8211_INT(PCF);
492 ADM8211_INT(BCNTC);
493 ADM8211_INT(GPINT);
494 ADM8211_INT(ATIMTC);
495 ADM8211_INT(TSFTF);
496 ADM8211_INT(TSCZ);
497 ADM8211_INT(SQL);
498 ADM8211_INT(WEPTD);
499 ADM8211_INT(ATIME);
500 ADM8211_INT(TEIS);
501 ADM8211_INT(FBE);
502 ADM8211_INT(REIS);
503 ADM8211_INT(GPTT);
504 ADM8211_INT(RPS);
505 ADM8211_INT(RDU);
506 ADM8211_INT(TUF);
507 ADM8211_INT(TPS);
508
509 return IRQ_HANDLED;
510
511 #undef ADM8211_INT
512 }
513
514 #define WRITE_SYN(name,v_mask,v_shift,a_mask,a_shift,bits,prewrite,postwrite)\
515 static void adm8211_rf_write_syn_ ## name (struct ieee80211_hw *dev, \
516 u16 addr, u32 value) { \
517 struct adm8211_priv *priv = dev->priv; \
518 unsigned int i; \
519 u32 reg, bitbuf; \
520 \
521 value &= v_mask; \
522 addr &= a_mask; \
523 bitbuf = (value << v_shift) | (addr << a_shift); \
524 \
525 ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_IF_SELECT_1); \
526 ADM8211_CSR_READ(SYNRF); \
527 ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_IF_SELECT_0); \
528 ADM8211_CSR_READ(SYNRF); \
529 \
530 if (prewrite) { \
531 ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_WRITE_SYNDATA_0); \
532 ADM8211_CSR_READ(SYNRF); \
533 } \
534 \
535 for (i = 0; i <= bits; i++) { \
536 if (bitbuf & (1 << (bits - i))) \
537 reg = ADM8211_SYNRF_WRITE_SYNDATA_1; \
538 else \
539 reg = ADM8211_SYNRF_WRITE_SYNDATA_0; \
540 \
541 ADM8211_CSR_WRITE(SYNRF, reg); \
542 ADM8211_CSR_READ(SYNRF); \
543 \
544 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_WRITE_CLOCK_1); \
545 ADM8211_CSR_READ(SYNRF); \
546 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_WRITE_CLOCK_0); \
547 ADM8211_CSR_READ(SYNRF); \
548 } \
549 \
550 if (postwrite == 1) { \
551 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_IF_SELECT_0); \
552 ADM8211_CSR_READ(SYNRF); \
553 } \
554 if (postwrite == 2) { \
555 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_IF_SELECT_1); \
556 ADM8211_CSR_READ(SYNRF); \
557 } \
558 \
559 ADM8211_CSR_WRITE(SYNRF, 0); \
560 ADM8211_CSR_READ(SYNRF); \
561 }
562
563 WRITE_SYN(max2820, 0x00FFF, 0, 0x0F, 12, 15, 1, 1)
564 WRITE_SYN(al2210l, 0xFFFFF, 4, 0x0F, 0, 23, 1, 1)
565 WRITE_SYN(rfmd2958, 0x3FFFF, 0, 0x1F, 18, 23, 0, 1)
566 WRITE_SYN(rfmd2948, 0x0FFFF, 4, 0x0F, 0, 21, 0, 2)
567
568 #undef WRITE_SYN
569
570 static int adm8211_write_bbp(struct ieee80211_hw *dev, u8 addr, u8 data)
571 {
572 struct adm8211_priv *priv = dev->priv;
573 unsigned int timeout;
574 u32 reg;
575
576 timeout = 10;
577 while (timeout > 0) {
578 reg = ADM8211_CSR_READ(BBPCTL);
579 if (!(reg & (ADM8211_BBPCTL_WR | ADM8211_BBPCTL_RD)))
580 break;
581 timeout--;
582 msleep(2);
583 }
584
585 if (timeout == 0) {
586 printk(KERN_DEBUG "%s: adm8211_write_bbp(%d,%d) failed"
587 " prewrite (reg=0x%08x)\n",
588 wiphy_name(dev->wiphy), addr, data, reg);
589 return -ETIMEDOUT;
590 }
591
592 switch (priv->bbp_type) {
593 case ADM8211_TYPE_INTERSIL:
594 reg = ADM8211_BBPCTL_MMISEL; /* three wire interface */
595 break;
596 case ADM8211_TYPE_RFMD:
597 reg = (0x20 << 24) | ADM8211_BBPCTL_TXCE | ADM8211_BBPCTL_CCAP |
598 (0x01 << 18);
599 break;
600 case ADM8211_TYPE_ADMTEK:
601 reg = (0x20 << 24) | ADM8211_BBPCTL_TXCE | ADM8211_BBPCTL_CCAP |
602 (0x05 << 18);
603 break;
604 }
605 reg |= ADM8211_BBPCTL_WR | (addr << 8) | data;
606
607 ADM8211_CSR_WRITE(BBPCTL, reg);
608
609 timeout = 10;
610 while (timeout > 0) {
611 reg = ADM8211_CSR_READ(BBPCTL);
612 if (!(reg & ADM8211_BBPCTL_WR))
613 break;
614 timeout--;
615 msleep(2);
616 }
617
618 if (timeout == 0) {
619 ADM8211_CSR_WRITE(BBPCTL, ADM8211_CSR_READ(BBPCTL) &
620 ~ADM8211_BBPCTL_WR);
621 printk(KERN_DEBUG "%s: adm8211_write_bbp(%d,%d) failed"
622 " postwrite (reg=0x%08x)\n",
623 wiphy_name(dev->wiphy), addr, data, reg);
624 return -ETIMEDOUT;
625 }
626
627 return 0;
628 }
629
630 static int adm8211_rf_set_channel(struct ieee80211_hw *dev, unsigned int chan)
631 {
632 static const u32 adm8211_rfmd2958_reg5[] =
633 {0x22BD, 0x22D2, 0x22E8, 0x22FE, 0x2314, 0x232A, 0x2340,
634 0x2355, 0x236B, 0x2381, 0x2397, 0x23AD, 0x23C2, 0x23F7};
635 static const u32 adm8211_rfmd2958_reg6[] =
636 {0x05D17, 0x3A2E8, 0x2E8BA, 0x22E8B, 0x1745D, 0x0BA2E, 0x00000,
637 0x345D1, 0x28BA2, 0x1D174, 0x11745, 0x05D17, 0x3A2E8, 0x11745};
638
639 struct adm8211_priv *priv = dev->priv;
640 u8 ant_power = priv->ant_power > 0x3F ?
641 priv->eeprom->antenna_power[chan - 1] : priv->ant_power;
642 u8 tx_power = priv->tx_power > 0x3F ?
643 priv->eeprom->tx_power[chan - 1] : priv->tx_power;
644 u8 lpf_cutoff = priv->lpf_cutoff == 0xFF ?
645 priv->eeprom->lpf_cutoff[chan - 1] : priv->lpf_cutoff;
646 u8 lnags_thresh = priv->lnags_threshold == 0xFF ?
647 priv->eeprom->lnags_threshold[chan - 1] : priv->lnags_threshold;
648 u32 reg;
649
650 ADM8211_IDLE();
651
652 /* Program synthesizer to new channel */
653 switch (priv->transceiver_type) {
654 case ADM8211_RFMD2958:
655 case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
656 adm8211_rf_write_syn_rfmd2958(dev, 0x00, 0x04007);
657 adm8211_rf_write_syn_rfmd2958(dev, 0x02, 0x00033);
658
659 adm8211_rf_write_syn_rfmd2958(dev, 0x05,
660 adm8211_rfmd2958_reg5[chan - 1]);
661 adm8211_rf_write_syn_rfmd2958(dev, 0x06,
662 adm8211_rfmd2958_reg6[chan - 1]);
663 break;
664
665 case ADM8211_RFMD2948:
666 adm8211_rf_write_syn_rfmd2948(dev, SI4126_MAIN_CONF,
667 SI4126_MAIN_XINDIV2);
668 adm8211_rf_write_syn_rfmd2948(dev, SI4126_POWERDOWN,
669 SI4126_POWERDOWN_PDIB |
670 SI4126_POWERDOWN_PDRB);
671 adm8211_rf_write_syn_rfmd2948(dev, SI4126_PHASE_DET_GAIN, 0);
672 adm8211_rf_write_syn_rfmd2948(dev, SI4126_RF2_N_DIV,
673 (chan == 14 ?
674 2110 : (2033 + (chan * 5))));
675 adm8211_rf_write_syn_rfmd2948(dev, SI4126_IF_N_DIV, 1496);
676 adm8211_rf_write_syn_rfmd2948(dev, SI4126_RF2_R_DIV, 44);
677 adm8211_rf_write_syn_rfmd2948(dev, SI4126_IF_R_DIV, 44);
678 break;
679
680 case ADM8211_MAX2820:
681 adm8211_rf_write_syn_max2820(dev, 0x3,
682 (chan == 14 ? 0x054 : (0x7 + (chan * 5))));
683 break;
684
685 case ADM8211_AL2210L:
686 adm8211_rf_write_syn_al2210l(dev, 0x0,
687 (chan == 14 ? 0x229B4 : (0x22967 + (chan * 5))));
688 break;
689
690 default:
691 printk(KERN_DEBUG "%s: unsupported transceiver type %d\n",
692 wiphy_name(dev->wiphy), priv->transceiver_type);
693 break;
694 }
695
696 /* write BBP regs */
697 if (priv->bbp_type == ADM8211_TYPE_RFMD) {
698
699 /* SMC 2635W specific? adm8211b doesn't use the 2948 though.. */
700 /* TODO: remove if SMC 2635W doesn't need this */
701 if (priv->transceiver_type == ADM8211_RFMD2948) {
702 reg = ADM8211_CSR_READ(GPIO);
703 reg &= 0xfffc0000;
704 reg |= ADM8211_CSR_GPIO_EN0;
705 if (chan != 14)
706 reg |= ADM8211_CSR_GPIO_O0;
707 ADM8211_CSR_WRITE(GPIO, reg);
708 }
709
710 if (priv->transceiver_type == ADM8211_RFMD2958) {
711 /* set PCNT2 */
712 adm8211_rf_write_syn_rfmd2958(dev, 0x0B, 0x07100);
713 /* set PCNT1 P_DESIRED/MID_BIAS */
714 reg = le16_to_cpu(priv->eeprom->cr49);
715 reg >>= 13;
716 reg <<= 15;
717 reg |= ant_power << 9;
718 adm8211_rf_write_syn_rfmd2958(dev, 0x0A, reg);
719 /* set TXRX TX_GAIN */
720 adm8211_rf_write_syn_rfmd2958(dev, 0x09, 0x00050 |
721 (priv->pdev->revision < ADM8211_REV_CA ? tx_power : 0));
722 } else {
723 reg = ADM8211_CSR_READ(PLCPHD);
724 reg &= 0xff00ffff;
725 reg |= tx_power << 18;
726 ADM8211_CSR_WRITE(PLCPHD, reg);
727 }
728
729 ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_SELRF |
730 ADM8211_SYNRF_PE1 | ADM8211_SYNRF_PHYRST);
731 ADM8211_CSR_READ(SYNRF);
732 msleep(30);
733
734 /* RF3000 BBP */
735 if (priv->transceiver_type != ADM8211_RFMD2958)
736 adm8211_write_bbp(dev, RF3000_TX_VAR_GAIN__TX_LEN_EXT,
737 tx_power<<2);
738 adm8211_write_bbp(dev, RF3000_LOW_GAIN_CALIB, lpf_cutoff);
739 adm8211_write_bbp(dev, RF3000_HIGH_GAIN_CALIB, lnags_thresh);
740 adm8211_write_bbp(dev, 0x1c, priv->pdev->revision == ADM8211_REV_BA ?
741 priv->eeprom->cr28 : 0);
742 adm8211_write_bbp(dev, 0x1d, priv->eeprom->cr29);
743
744 ADM8211_CSR_WRITE(SYNRF, 0);
745
746 /* Nothing to do for ADMtek BBP */
747 } else if (priv->bbp_type != ADM8211_TYPE_ADMTEK)
748 printk(KERN_DEBUG "%s: unsupported BBP type %d\n",
749 wiphy_name(dev->wiphy), priv->bbp_type);
750
751 ADM8211_RESTORE();
752
753 /* update current channel for adhoc (and maybe AP mode) */
754 reg = ADM8211_CSR_READ(CAP0);
755 reg &= ~0xF;
756 reg |= chan;
757 ADM8211_CSR_WRITE(CAP0, reg);
758
759 return 0;
760 }
761
762 static void adm8211_update_mode(struct ieee80211_hw *dev)
763 {
764 struct adm8211_priv *priv = dev->priv;
765
766 ADM8211_IDLE();
767
768 priv->soft_rx_crc = 0;
769 switch (priv->mode) {
770 case IEEE80211_IF_TYPE_STA:
771 priv->nar &= ~(ADM8211_NAR_PR | ADM8211_NAR_EA);
772 priv->nar |= ADM8211_NAR_ST | ADM8211_NAR_SR;
773 break;
774 case IEEE80211_IF_TYPE_IBSS:
775 priv->nar &= ~ADM8211_NAR_PR;
776 priv->nar |= ADM8211_NAR_EA | ADM8211_NAR_ST | ADM8211_NAR_SR;
777
778 /* don't trust the error bits on rev 0x20 and up in adhoc */
779 if (priv->pdev->revision >= ADM8211_REV_BA)
780 priv->soft_rx_crc = 1;
781 break;
782 case IEEE80211_IF_TYPE_MNTR:
783 priv->nar &= ~(ADM8211_NAR_EA | ADM8211_NAR_ST);
784 priv->nar |= ADM8211_NAR_PR | ADM8211_NAR_SR;
785 break;
786 }
787
788 ADM8211_RESTORE();
789 }
790
791 static void adm8211_hw_init_syn(struct ieee80211_hw *dev)
792 {
793 struct adm8211_priv *priv = dev->priv;
794
795 switch (priv->transceiver_type) {
796 case ADM8211_RFMD2958:
797 case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
798 /* comments taken from ADMtek vendor driver */
799
800 /* Reset RF2958 after power on */
801 adm8211_rf_write_syn_rfmd2958(dev, 0x1F, 0x00000);
802 /* Initialize RF VCO Core Bias to maximum */
803 adm8211_rf_write_syn_rfmd2958(dev, 0x0C, 0x3001F);
804 /* Initialize IF PLL */
805 adm8211_rf_write_syn_rfmd2958(dev, 0x01, 0x29C03);
806 /* Initialize IF PLL Coarse Tuning */
807 adm8211_rf_write_syn_rfmd2958(dev, 0x03, 0x1FF6F);
808 /* Initialize RF PLL */
809 adm8211_rf_write_syn_rfmd2958(dev, 0x04, 0x29403);
810 /* Initialize RF PLL Coarse Tuning */
811 adm8211_rf_write_syn_rfmd2958(dev, 0x07, 0x1456F);
812 /* Initialize TX gain and filter BW (R9) */
813 adm8211_rf_write_syn_rfmd2958(dev, 0x09,
814 (priv->transceiver_type == ADM8211_RFMD2958 ?
815 0x10050 : 0x00050));
816 /* Initialize CAL register */
817 adm8211_rf_write_syn_rfmd2958(dev, 0x08, 0x3FFF8);
818 break;
819
820 case ADM8211_MAX2820:
821 adm8211_rf_write_syn_max2820(dev, 0x1, 0x01E);
822 adm8211_rf_write_syn_max2820(dev, 0x2, 0x001);
823 adm8211_rf_write_syn_max2820(dev, 0x3, 0x054);
824 adm8211_rf_write_syn_max2820(dev, 0x4, 0x310);
825 adm8211_rf_write_syn_max2820(dev, 0x5, 0x000);
826 break;
827
828 case ADM8211_AL2210L:
829 adm8211_rf_write_syn_al2210l(dev, 0x0, 0x0196C);
830 adm8211_rf_write_syn_al2210l(dev, 0x1, 0x007CB);
831 adm8211_rf_write_syn_al2210l(dev, 0x2, 0x3582F);
832 adm8211_rf_write_syn_al2210l(dev, 0x3, 0x010A9);
833 adm8211_rf_write_syn_al2210l(dev, 0x4, 0x77280);
834 adm8211_rf_write_syn_al2210l(dev, 0x5, 0x45641);
835 adm8211_rf_write_syn_al2210l(dev, 0x6, 0xEA130);
836 adm8211_rf_write_syn_al2210l(dev, 0x7, 0x80000);
837 adm8211_rf_write_syn_al2210l(dev, 0x8, 0x7850F);
838 adm8211_rf_write_syn_al2210l(dev, 0x9, 0xF900C);
839 adm8211_rf_write_syn_al2210l(dev, 0xA, 0x00000);
840 adm8211_rf_write_syn_al2210l(dev, 0xB, 0x00000);
841 break;
842
843 case ADM8211_RFMD2948:
844 default:
845 break;
846 }
847 }
848
849 static int adm8211_hw_init_bbp(struct ieee80211_hw *dev)
850 {
851 struct adm8211_priv *priv = dev->priv;
852 u32 reg;
853
854 /* write addresses */
855 if (priv->bbp_type == ADM8211_TYPE_INTERSIL) {
856 ADM8211_CSR_WRITE(MMIWA, 0x100E0C0A);
857 ADM8211_CSR_WRITE(MMIRD0, 0x00007C7E);
858 ADM8211_CSR_WRITE(MMIRD1, 0x00100000);
859 } else if (priv->bbp_type == ADM8211_TYPE_RFMD ||
860 priv->bbp_type == ADM8211_TYPE_ADMTEK) {
861 /* check specific BBP type */
862 switch (priv->specific_bbptype) {
863 case ADM8211_BBP_RFMD3000:
864 case ADM8211_BBP_RFMD3002:
865 ADM8211_CSR_WRITE(MMIWA, 0x00009101);
866 ADM8211_CSR_WRITE(MMIRD0, 0x00000301);
867 break;
868
869 case ADM8211_BBP_ADM8011:
870 ADM8211_CSR_WRITE(MMIWA, 0x00008903);
871 ADM8211_CSR_WRITE(MMIRD0, 0x00001716);
872
873 reg = ADM8211_CSR_READ(BBPCTL);
874 reg &= ~ADM8211_BBPCTL_TYPE;
875 reg |= 0x5 << 18;
876 ADM8211_CSR_WRITE(BBPCTL, reg);
877 break;
878 }
879
880 switch (priv->pdev->revision) {
881 case ADM8211_REV_CA:
882 if (priv->transceiver_type == ADM8211_RFMD2958 ||
883 priv->transceiver_type == ADM8211_RFMD2958_RF3000_CONTROL_POWER ||
884 priv->transceiver_type == ADM8211_RFMD2948)
885 ADM8211_CSR_WRITE(SYNCTL, 0x1 << 22);
886 else if (priv->transceiver_type == ADM8211_MAX2820 ||
887 priv->transceiver_type == ADM8211_AL2210L)
888 ADM8211_CSR_WRITE(SYNCTL, 0x3 << 22);
889 break;
890
891 case ADM8211_REV_BA:
892 reg = ADM8211_CSR_READ(MMIRD1);
893 reg &= 0x0000FFFF;
894 reg |= 0x7e100000;
895 ADM8211_CSR_WRITE(MMIRD1, reg);
896 break;
897
898 case ADM8211_REV_AB:
899 case ADM8211_REV_AF:
900 default:
901 ADM8211_CSR_WRITE(MMIRD1, 0x7e100000);
902 break;
903 }
904
905 /* For RFMD */
906 ADM8211_CSR_WRITE(MACTEST, 0x800);
907 }
908
909 adm8211_hw_init_syn(dev);
910
911 /* Set RF Power control IF pin to PE1+PHYRST# */
912 ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_SELRF |
913 ADM8211_SYNRF_PE1 | ADM8211_SYNRF_PHYRST);
914 ADM8211_CSR_READ(SYNRF);
915 msleep(20);
916
917 /* write BBP regs */
918 if (priv->bbp_type == ADM8211_TYPE_RFMD) {
919 /* RF3000 BBP */
920 /* another set:
921 * 11: c8
922 * 14: 14
923 * 15: 50 (chan 1..13; chan 14: d0)
924 * 1c: 00
925 * 1d: 84
926 */
927 adm8211_write_bbp(dev, RF3000_CCA_CTRL, 0x80);
928 /* antenna selection: diversity */
929 adm8211_write_bbp(dev, RF3000_DIVERSITY__RSSI, 0x80);
930 adm8211_write_bbp(dev, RF3000_TX_VAR_GAIN__TX_LEN_EXT, 0x74);
931 adm8211_write_bbp(dev, RF3000_LOW_GAIN_CALIB, 0x38);
932 adm8211_write_bbp(dev, RF3000_HIGH_GAIN_CALIB, 0x40);
933
934 if (priv->eeprom->major_version < 2) {
935 adm8211_write_bbp(dev, 0x1c, 0x00);
936 adm8211_write_bbp(dev, 0x1d, 0x80);
937 } else {
938 if (priv->pdev->revision == ADM8211_REV_BA)
939 adm8211_write_bbp(dev, 0x1c, priv->eeprom->cr28);
940 else
941 adm8211_write_bbp(dev, 0x1c, 0x00);
942
943 adm8211_write_bbp(dev, 0x1d, priv->eeprom->cr29);
944 }
945 } else if (priv->bbp_type == ADM8211_TYPE_ADMTEK) {
946 /* reset baseband */
947 adm8211_write_bbp(dev, 0x00, 0xFF);
948 /* antenna selection: diversity */
949 adm8211_write_bbp(dev, 0x07, 0x0A);
950
951 /* TODO: find documentation for this */
952 switch (priv->transceiver_type) {
953 case ADM8211_RFMD2958:
954 case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
955 adm8211_write_bbp(dev, 0x00, 0x00);
956 adm8211_write_bbp(dev, 0x01, 0x00);
957 adm8211_write_bbp(dev, 0x02, 0x00);
958 adm8211_write_bbp(dev, 0x03, 0x00);
959 adm8211_write_bbp(dev, 0x06, 0x0f);
960 adm8211_write_bbp(dev, 0x09, 0x00);
961 adm8211_write_bbp(dev, 0x0a, 0x00);
962 adm8211_write_bbp(dev, 0x0b, 0x00);
963 adm8211_write_bbp(dev, 0x0c, 0x00);
964 adm8211_write_bbp(dev, 0x0f, 0xAA);
965 adm8211_write_bbp(dev, 0x10, 0x8c);
966 adm8211_write_bbp(dev, 0x11, 0x43);
967 adm8211_write_bbp(dev, 0x18, 0x40);
968 adm8211_write_bbp(dev, 0x20, 0x23);
969 adm8211_write_bbp(dev, 0x21, 0x02);
970 adm8211_write_bbp(dev, 0x22, 0x28);
971 adm8211_write_bbp(dev, 0x23, 0x30);
972 adm8211_write_bbp(dev, 0x24, 0x2d);
973 adm8211_write_bbp(dev, 0x28, 0x35);
974 adm8211_write_bbp(dev, 0x2a, 0x8c);
975 adm8211_write_bbp(dev, 0x2b, 0x81);
976 adm8211_write_bbp(dev, 0x2c, 0x44);
977 adm8211_write_bbp(dev, 0x2d, 0x0A);
978 adm8211_write_bbp(dev, 0x29, 0x40);
979 adm8211_write_bbp(dev, 0x60, 0x08);
980 adm8211_write_bbp(dev, 0x64, 0x01);
981 break;
982
983 case ADM8211_MAX2820:
984 adm8211_write_bbp(dev, 0x00, 0x00);
985 adm8211_write_bbp(dev, 0x01, 0x00);
986 adm8211_write_bbp(dev, 0x02, 0x00);
987 adm8211_write_bbp(dev, 0x03, 0x00);
988 adm8211_write_bbp(dev, 0x06, 0x0f);
989 adm8211_write_bbp(dev, 0x09, 0x05);
990 adm8211_write_bbp(dev, 0x0a, 0x02);
991 adm8211_write_bbp(dev, 0x0b, 0x00);
992 adm8211_write_bbp(dev, 0x0c, 0x0f);
993 adm8211_write_bbp(dev, 0x0f, 0x55);
994 adm8211_write_bbp(dev, 0x10, 0x8d);
995 adm8211_write_bbp(dev, 0x11, 0x43);
996 adm8211_write_bbp(dev, 0x18, 0x4a);
997 adm8211_write_bbp(dev, 0x20, 0x20);
998 adm8211_write_bbp(dev, 0x21, 0x02);
999 adm8211_write_bbp(dev, 0x22, 0x23);
1000 adm8211_write_bbp(dev, 0x23, 0x30);
1001 adm8211_write_bbp(dev, 0x24, 0x2d);
1002 adm8211_write_bbp(dev, 0x2a, 0x8c);
1003 adm8211_write_bbp(dev, 0x2b, 0x81);
1004 adm8211_write_bbp(dev, 0x2c, 0x44);
1005 adm8211_write_bbp(dev, 0x29, 0x4a);
1006 adm8211_write_bbp(dev, 0x60, 0x2b);
1007 adm8211_write_bbp(dev, 0x64, 0x01);
1008 break;
1009
1010 case ADM8211_AL2210L:
1011 adm8211_write_bbp(dev, 0x00, 0x00);
1012 adm8211_write_bbp(dev, 0x01, 0x00);
1013 adm8211_write_bbp(dev, 0x02, 0x00);
1014 adm8211_write_bbp(dev, 0x03, 0x00);
1015 adm8211_write_bbp(dev, 0x06, 0x0f);
1016 adm8211_write_bbp(dev, 0x07, 0x05);
1017 adm8211_write_bbp(dev, 0x08, 0x03);
1018 adm8211_write_bbp(dev, 0x09, 0x00);
1019 adm8211_write_bbp(dev, 0x0a, 0x00);
1020 adm8211_write_bbp(dev, 0x0b, 0x00);
1021 adm8211_write_bbp(dev, 0x0c, 0x10);
1022 adm8211_write_bbp(dev, 0x0f, 0x55);
1023 adm8211_write_bbp(dev, 0x10, 0x8d);
1024 adm8211_write_bbp(dev, 0x11, 0x43);
1025 adm8211_write_bbp(dev, 0x18, 0x4a);
1026 adm8211_write_bbp(dev, 0x20, 0x20);
1027 adm8211_write_bbp(dev, 0x21, 0x02);
1028 adm8211_write_bbp(dev, 0x22, 0x23);
1029 adm8211_write_bbp(dev, 0x23, 0x30);
1030 adm8211_write_bbp(dev, 0x24, 0x2d);
1031 adm8211_write_bbp(dev, 0x2a, 0xaa);
1032 adm8211_write_bbp(dev, 0x2b, 0x81);
1033 adm8211_write_bbp(dev, 0x2c, 0x44);
1034 adm8211_write_bbp(dev, 0x29, 0xfa);
1035 adm8211_write_bbp(dev, 0x60, 0x2d);
1036 adm8211_write_bbp(dev, 0x64, 0x01);
1037 break;
1038
1039 case ADM8211_RFMD2948:
1040 break;
1041
1042 default:
1043 printk(KERN_DEBUG "%s: unsupported transceiver %d\n",
1044 wiphy_name(dev->wiphy), priv->transceiver_type);
1045 break;
1046 }
1047 } else
1048 printk(KERN_DEBUG "%s: unsupported BBP %d\n",
1049 wiphy_name(dev->wiphy), priv->bbp_type);
1050
1051 ADM8211_CSR_WRITE(SYNRF, 0);
1052
1053 /* Set RF CAL control source to MAC control */
1054 reg = ADM8211_CSR_READ(SYNCTL);
1055 reg |= ADM8211_SYNCTL_SELCAL;
1056 ADM8211_CSR_WRITE(SYNCTL, reg);
1057
1058 return 0;
1059 }
1060
1061 /* configures hw beacons/probe responses */
1062 static int adm8211_set_rate(struct ieee80211_hw *dev)
1063 {
1064 struct adm8211_priv *priv = dev->priv;
1065 u32 reg;
1066 int i = 0;
1067 u8 rate_buf[12] = {0};
1068
1069 /* write supported rates */
1070 if (priv->pdev->revision != ADM8211_REV_BA) {
1071 rate_buf[0] = ARRAY_SIZE(adm8211_rates);
1072 for (i = 0; i < ARRAY_SIZE(adm8211_rates); i++)
1073 rate_buf[i + 1] = (adm8211_rates[i].bitrate / 5) | 0x80;
1074 } else {
1075 /* workaround for rev BA specific bug */
1076 rate_buf[0] = 0x04;
1077 rate_buf[1] = 0x82;
1078 rate_buf[2] = 0x04;
1079 rate_buf[3] = 0x0b;
1080 rate_buf[4] = 0x16;
1081 }
1082
1083 adm8211_write_sram_bytes(dev, ADM8211_SRAM_SUPP_RATE, rate_buf,
1084 ARRAY_SIZE(adm8211_rates) + 1);
1085
1086 reg = ADM8211_CSR_READ(PLCPHD) & 0x00FFFFFF; /* keep bits 0-23 */
1087 reg |= 1 << 15; /* short preamble */
1088 reg |= 110 << 24;
1089 ADM8211_CSR_WRITE(PLCPHD, reg);
1090
1091 /* MTMLT = 512 TU (max TX MSDU lifetime)
1092 * BCNTSIG = plcp_signal (beacon, probe resp, and atim TX rate)
1093 * SRTYLIM = 224 (short retry limit, TX header value is default) */
1094 ADM8211_CSR_WRITE(TXLMT, (512 << 16) | (110 << 8) | (224 << 0));
1095
1096 return 0;
1097 }
1098
1099 static void adm8211_hw_init(struct ieee80211_hw *dev)
1100 {
1101 struct adm8211_priv *priv = dev->priv;
1102 u32 reg;
1103 u8 cline;
1104
1105 reg = ADM8211_CSR_READ(PAR);
1106 reg |= ADM8211_PAR_MRLE | ADM8211_PAR_MRME;
1107 reg &= ~(ADM8211_PAR_BAR | ADM8211_PAR_CAL);
1108
1109 if (!pci_set_mwi(priv->pdev)) {
1110 reg |= 0x1 << 24;
1111 pci_read_config_byte(priv->pdev, PCI_CACHE_LINE_SIZE, &cline);
1112
1113 switch (cline) {
1114 case 0x8: reg |= (0x1 << 14);
1115 break;
1116 case 0x16: reg |= (0x2 << 14);
1117 break;
1118 case 0x32: reg |= (0x3 << 14);
1119 break;
1120 default: reg |= (0x0 << 14);
1121 break;
1122 }
1123 }
1124
1125 ADM8211_CSR_WRITE(PAR, reg);
1126
1127 reg = ADM8211_CSR_READ(CSR_TEST1);
1128 reg &= ~(0xF << 28);
1129 reg |= (1 << 28) | (1 << 31);
1130 ADM8211_CSR_WRITE(CSR_TEST1, reg);
1131
1132 /* lose link after 4 lost beacons */
1133 reg = (0x04 << 21) | ADM8211_WCSR_TSFTWE | ADM8211_WCSR_LSOE;
1134 ADM8211_CSR_WRITE(WCSR, reg);
1135
1136 /* Disable APM, enable receive FIFO threshold, and set drain receive
1137 * threshold to store-and-forward */
1138 reg = ADM8211_CSR_READ(CMDR);
1139 reg &= ~(ADM8211_CMDR_APM | ADM8211_CMDR_DRT);
1140 reg |= ADM8211_CMDR_RTE | ADM8211_CMDR_DRT_SF;
1141 ADM8211_CSR_WRITE(CMDR, reg);
1142
1143 adm8211_set_rate(dev);
1144
1145 /* 4-bit values:
1146 * PWR1UP = 8 * 2 ms
1147 * PWR0PAPE = 8 us or 5 us
1148 * PWR1PAPE = 1 us or 3 us
1149 * PWR0TRSW = 5 us
1150 * PWR1TRSW = 12 us
1151 * PWR0PE2 = 13 us
1152 * PWR1PE2 = 1 us
1153 * PWR0TXPE = 8 or 6 */
1154 if (priv->pdev->revision < ADM8211_REV_CA)
1155 ADM8211_CSR_WRITE(TOFS2, 0x8815cd18);
1156 else
1157 ADM8211_CSR_WRITE(TOFS2, 0x8535cd16);
1158
1159 /* Enable store and forward for transmit */
1160 priv->nar = ADM8211_NAR_SF | ADM8211_NAR_PB;
1161 ADM8211_CSR_WRITE(NAR, priv->nar);
1162
1163 /* Reset RF */
1164 ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_RADIO);
1165 ADM8211_CSR_READ(SYNRF);
1166 msleep(10);
1167 ADM8211_CSR_WRITE(SYNRF, 0);
1168 ADM8211_CSR_READ(SYNRF);
1169 msleep(5);
1170
1171 /* Set CFP Max Duration to 0x10 TU */
1172 reg = ADM8211_CSR_READ(CFPP);
1173 reg &= ~(0xffff << 8);
1174 reg |= 0x0010 << 8;
1175 ADM8211_CSR_WRITE(CFPP, reg);
1176
1177 /* USCNT = 0x16 (number of system clocks, 22 MHz, in 1us
1178 * TUCNT = 0x3ff - Tu counter 1024 us */
1179 ADM8211_CSR_WRITE(TOFS0, (0x16 << 24) | 0x3ff);
1180
1181 /* SLOT=20 us, SIFS=110 cycles of 22 MHz (5 us),
1182 * DIFS=50 us, EIFS=100 us */
1183 if (priv->pdev->revision < ADM8211_REV_CA)
1184 ADM8211_CSR_WRITE(IFST, (20 << 23) | (110 << 15) |
1185 (50 << 9) | 100);
1186 else
1187 ADM8211_CSR_WRITE(IFST, (20 << 23) | (24 << 15) |
1188 (50 << 9) | 100);
1189
1190 /* PCNT = 1 (MAC idle time awake/sleep, unit S)
1191 * RMRD = 2346 * 8 + 1 us (max RX duration) */
1192 ADM8211_CSR_WRITE(RMD, (1 << 16) | 18769);
1193
1194 /* MART=65535 us, MIRT=256 us, TSFTOFST=0 us */
1195 ADM8211_CSR_WRITE(RSPT, 0xffffff00);
1196
1197 /* Initialize BBP (and SYN) */
1198 adm8211_hw_init_bbp(dev);
1199
1200 /* make sure interrupts are off */
1201 ADM8211_CSR_WRITE(IER, 0);
1202
1203 /* ACK interrupts */
1204 ADM8211_CSR_WRITE(STSR, ADM8211_CSR_READ(STSR));
1205
1206 /* Setup WEP (turns it off for now) */
1207 reg = ADM8211_CSR_READ(MACTEST);
1208 reg &= ~(7 << 20);
1209 ADM8211_CSR_WRITE(MACTEST, reg);
1210
1211 reg = ADM8211_CSR_READ(WEPCTL);
1212 reg &= ~ADM8211_WEPCTL_WEPENABLE;
1213 reg |= ADM8211_WEPCTL_WEPRXBYP;
1214 ADM8211_CSR_WRITE(WEPCTL, reg);
1215
1216 /* Clear the missed-packet counter. */
1217 ADM8211_CSR_READ(LPC);
1218 }
1219
1220 static int adm8211_hw_reset(struct ieee80211_hw *dev)
1221 {
1222 struct adm8211_priv *priv = dev->priv;
1223 u32 reg, tmp;
1224 int timeout = 100;
1225
1226 /* Power-on issue */
1227 /* TODO: check if this is necessary */
1228 ADM8211_CSR_WRITE(FRCTL, 0);
1229
1230 /* Reset the chip */
1231 tmp = ADM8211_CSR_READ(PAR);
1232 ADM8211_CSR_WRITE(PAR, ADM8211_PAR_SWR);
1233
1234 while ((ADM8211_CSR_READ(PAR) & ADM8211_PAR_SWR) && timeout--)
1235 msleep(50);
1236
1237 if (timeout <= 0)
1238 return -ETIMEDOUT;
1239
1240 ADM8211_CSR_WRITE(PAR, tmp);
1241
1242 if (priv->pdev->revision == ADM8211_REV_BA &&
1243 (priv->transceiver_type == ADM8211_RFMD2958_RF3000_CONTROL_POWER ||
1244 priv->transceiver_type == ADM8211_RFMD2958)) {
1245 reg = ADM8211_CSR_READ(CSR_TEST1);
1246 reg |= (1 << 4) | (1 << 5);
1247 ADM8211_CSR_WRITE(CSR_TEST1, reg);
1248 } else if (priv->pdev->revision == ADM8211_REV_CA) {
1249 reg = ADM8211_CSR_READ(CSR_TEST1);
1250 reg &= ~((1 << 4) | (1 << 5));
1251 ADM8211_CSR_WRITE(CSR_TEST1, reg);
1252 }
1253
1254 ADM8211_CSR_WRITE(FRCTL, 0);
1255
1256 reg = ADM8211_CSR_READ(CSR_TEST0);
1257 reg |= ADM8211_CSR_TEST0_EPRLD; /* EEPROM Recall */
1258 ADM8211_CSR_WRITE(CSR_TEST0, reg);
1259
1260 adm8211_clear_sram(dev);
1261
1262 return 0;
1263 }
1264
1265 static u64 adm8211_get_tsft(struct ieee80211_hw *dev)
1266 {
1267 struct adm8211_priv *priv = dev->priv;
1268 u32 tsftl;
1269 u64 tsft;
1270
1271 tsftl = ADM8211_CSR_READ(TSFTL);
1272 tsft = ADM8211_CSR_READ(TSFTH);
1273 tsft <<= 32;
1274 tsft |= tsftl;
1275
1276 return tsft;
1277 }
1278
1279 static void adm8211_set_interval(struct ieee80211_hw *dev,
1280 unsigned short bi, unsigned short li)
1281 {
1282 struct adm8211_priv *priv = dev->priv;
1283 u32 reg;
1284
1285 /* BP (beacon interval) = data->beacon_interval
1286 * LI (listen interval) = data->listen_interval (in beacon intervals) */
1287 reg = (bi << 16) | li;
1288 ADM8211_CSR_WRITE(BPLI, reg);
1289 }
1290
1291 static void adm8211_set_bssid(struct ieee80211_hw *dev, const u8 *bssid)
1292 {
1293 struct adm8211_priv *priv = dev->priv;
1294 u32 reg;
1295
1296 ADM8211_CSR_WRITE(BSSID0, le32_to_cpu(*(__le32 *)bssid));
1297 reg = ADM8211_CSR_READ(ABDA1);
1298 reg &= 0x0000ffff;
1299 reg |= (bssid[4] << 16) | (bssid[5] << 24);
1300 ADM8211_CSR_WRITE(ABDA1, reg);
1301 }
1302
1303 static int adm8211_set_ssid(struct ieee80211_hw *dev, u8 *ssid, size_t ssid_len)
1304 {
1305 struct adm8211_priv *priv = dev->priv;
1306 u8 buf[36];
1307
1308 if (ssid_len > 32)
1309 return -EINVAL;
1310
1311 memset(buf, 0, sizeof(buf));
1312 buf[0] = ssid_len;
1313 memcpy(buf + 1, ssid, ssid_len);
1314 adm8211_write_sram_bytes(dev, ADM8211_SRAM_SSID, buf, 33);
1315 /* TODO: configure beacon for adhoc? */
1316 return 0;
1317 }
1318
1319 static int adm8211_config(struct ieee80211_hw *dev, struct ieee80211_conf *conf)
1320 {
1321 struct adm8211_priv *priv = dev->priv;
1322 int channel = ieee80211_frequency_to_channel(conf->channel->center_freq);
1323
1324 if (channel != priv->channel) {
1325 priv->channel = channel;
1326 adm8211_rf_set_channel(dev, priv->channel);
1327 }
1328
1329 return 0;
1330 }
1331
1332 static int adm8211_config_interface(struct ieee80211_hw *dev,
1333 struct ieee80211_vif *vif,
1334 struct ieee80211_if_conf *conf)
1335 {
1336 struct adm8211_priv *priv = dev->priv;
1337
1338 if (memcmp(conf->bssid, priv->bssid, ETH_ALEN)) {
1339 adm8211_set_bssid(dev, conf->bssid);
1340 memcpy(priv->bssid, conf->bssid, ETH_ALEN);
1341 }
1342
1343 if (conf->ssid_len != priv->ssid_len ||
1344 memcmp(conf->ssid, priv->ssid, conf->ssid_len)) {
1345 adm8211_set_ssid(dev, conf->ssid, conf->ssid_len);
1346 priv->ssid_len = conf->ssid_len;
1347 memcpy(priv->ssid, conf->ssid, conf->ssid_len);
1348 }
1349
1350 return 0;
1351 }
1352
1353 static void adm8211_configure_filter(struct ieee80211_hw *dev,
1354 unsigned int changed_flags,
1355 unsigned int *total_flags,
1356 int mc_count, struct dev_mc_list *mclist)
1357 {
1358 static const u8 bcast[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
1359 struct adm8211_priv *priv = dev->priv;
1360 unsigned int bit_nr, new_flags;
1361 u32 mc_filter[2];
1362 int i;
1363
1364 new_flags = 0;
1365
1366 if (*total_flags & FIF_PROMISC_IN_BSS) {
1367 new_flags |= FIF_PROMISC_IN_BSS;
1368 priv->nar |= ADM8211_NAR_PR;
1369 priv->nar &= ~ADM8211_NAR_MM;
1370 mc_filter[1] = mc_filter[0] = ~0;
1371 } else if ((*total_flags & FIF_ALLMULTI) || (mc_count > 32)) {
1372 new_flags |= FIF_ALLMULTI;
1373 priv->nar &= ~ADM8211_NAR_PR;
1374 priv->nar |= ADM8211_NAR_MM;
1375 mc_filter[1] = mc_filter[0] = ~0;
1376 } else {
1377 priv->nar &= ~(ADM8211_NAR_MM | ADM8211_NAR_PR);
1378 mc_filter[1] = mc_filter[0] = 0;
1379 for (i = 0; i < mc_count; i++) {
1380 if (!mclist)
1381 break;
1382 bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
1383
1384 bit_nr &= 0x3F;
1385 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1386 mclist = mclist->next;
1387 }
1388 }
1389
1390 ADM8211_IDLE_RX();
1391
1392 ADM8211_CSR_WRITE(MAR0, mc_filter[0]);
1393 ADM8211_CSR_WRITE(MAR1, mc_filter[1]);
1394 ADM8211_CSR_READ(NAR);
1395
1396 if (priv->nar & ADM8211_NAR_PR)
1397 dev->flags |= IEEE80211_HW_RX_INCLUDES_FCS;
1398 else
1399 dev->flags &= ~IEEE80211_HW_RX_INCLUDES_FCS;
1400
1401 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
1402 adm8211_set_bssid(dev, bcast);
1403 else
1404 adm8211_set_bssid(dev, priv->bssid);
1405
1406 ADM8211_RESTORE();
1407
1408 *total_flags = new_flags;
1409 }
1410
1411 static int adm8211_add_interface(struct ieee80211_hw *dev,
1412 struct ieee80211_if_init_conf *conf)
1413 {
1414 struct adm8211_priv *priv = dev->priv;
1415 if (priv->mode != IEEE80211_IF_TYPE_MNTR)
1416 return -EOPNOTSUPP;
1417
1418 switch (conf->type) {
1419 case IEEE80211_IF_TYPE_STA:
1420 priv->mode = conf->type;
1421 break;
1422 default:
1423 return -EOPNOTSUPP;
1424 }
1425
1426 ADM8211_IDLE();
1427
1428 ADM8211_CSR_WRITE(PAR0, le32_to_cpu(*(__le32 *)conf->mac_addr));
1429 ADM8211_CSR_WRITE(PAR1, le16_to_cpu(*(__le16 *)(conf->mac_addr + 4)));
1430
1431 adm8211_update_mode(dev);
1432
1433 ADM8211_RESTORE();
1434
1435 return 0;
1436 }
1437
1438 static void adm8211_remove_interface(struct ieee80211_hw *dev,
1439 struct ieee80211_if_init_conf *conf)
1440 {
1441 struct adm8211_priv *priv = dev->priv;
1442 priv->mode = IEEE80211_IF_TYPE_MNTR;
1443 }
1444
1445 static int adm8211_init_rings(struct ieee80211_hw *dev)
1446 {
1447 struct adm8211_priv *priv = dev->priv;
1448 struct adm8211_desc *desc = NULL;
1449 struct adm8211_rx_ring_info *rx_info;
1450 struct adm8211_tx_ring_info *tx_info;
1451 unsigned int i;
1452
1453 for (i = 0; i < priv->rx_ring_size; i++) {
1454 desc = &priv->rx_ring[i];
1455 desc->status = 0;
1456 desc->length = cpu_to_le32(RX_PKT_SIZE);
1457 priv->rx_buffers[i].skb = NULL;
1458 }
1459 /* Mark the end of RX ring; hw returns to base address after this
1460 * descriptor */
1461 desc->length |= cpu_to_le32(RDES1_CONTROL_RER);
1462
1463 for (i = 0; i < priv->rx_ring_size; i++) {
1464 desc = &priv->rx_ring[i];
1465 rx_info = &priv->rx_buffers[i];
1466
1467 rx_info->skb = dev_alloc_skb(RX_PKT_SIZE);
1468 if (rx_info->skb == NULL)
1469 break;
1470 rx_info->mapping = pci_map_single(priv->pdev,
1471 skb_tail_pointer(rx_info->skb),
1472 RX_PKT_SIZE,
1473 PCI_DMA_FROMDEVICE);
1474 desc->buffer1 = cpu_to_le32(rx_info->mapping);
1475 desc->status = cpu_to_le32(RDES0_STATUS_OWN | RDES0_STATUS_SQL);
1476 }
1477
1478 /* Setup TX ring. TX buffers descriptors will be filled in as needed */
1479 for (i = 0; i < priv->tx_ring_size; i++) {
1480 desc = &priv->tx_ring[i];
1481 tx_info = &priv->tx_buffers[i];
1482
1483 tx_info->skb = NULL;
1484 tx_info->mapping = 0;
1485 desc->status = 0;
1486 }
1487 desc->length = cpu_to_le32(TDES1_CONTROL_TER);
1488
1489 priv->cur_rx = priv->cur_tx = priv->dirty_tx = 0;
1490 ADM8211_CSR_WRITE(RDB, priv->rx_ring_dma);
1491 ADM8211_CSR_WRITE(TDBD, priv->tx_ring_dma);
1492
1493 return 0;
1494 }
1495
1496 static void adm8211_free_rings(struct ieee80211_hw *dev)
1497 {
1498 struct adm8211_priv *priv = dev->priv;
1499 unsigned int i;
1500
1501 for (i = 0; i < priv->rx_ring_size; i++) {
1502 if (!priv->rx_buffers[i].skb)
1503 continue;
1504
1505 pci_unmap_single(
1506 priv->pdev,
1507 priv->rx_buffers[i].mapping,
1508 RX_PKT_SIZE, PCI_DMA_FROMDEVICE);
1509
1510 dev_kfree_skb(priv->rx_buffers[i].skb);
1511 }
1512
1513 for (i = 0; i < priv->tx_ring_size; i++) {
1514 if (!priv->tx_buffers[i].skb)
1515 continue;
1516
1517 pci_unmap_single(priv->pdev,
1518 priv->tx_buffers[i].mapping,
1519 priv->tx_buffers[i].skb->len,
1520 PCI_DMA_TODEVICE);
1521
1522 dev_kfree_skb(priv->tx_buffers[i].skb);
1523 }
1524 }
1525
1526 static int adm8211_start(struct ieee80211_hw *dev)
1527 {
1528 struct adm8211_priv *priv = dev->priv;
1529 int retval;
1530
1531 /* Power up MAC and RF chips */
1532 retval = adm8211_hw_reset(dev);
1533 if (retval) {
1534 printk(KERN_ERR "%s: hardware reset failed\n",
1535 wiphy_name(dev->wiphy));
1536 goto fail;
1537 }
1538
1539 retval = adm8211_init_rings(dev);
1540 if (retval) {
1541 printk(KERN_ERR "%s: failed to initialize rings\n",
1542 wiphy_name(dev->wiphy));
1543 goto fail;
1544 }
1545
1546 /* Init hardware */
1547 adm8211_hw_init(dev);
1548 adm8211_rf_set_channel(dev, priv->channel);
1549
1550 retval = request_irq(priv->pdev->irq, &adm8211_interrupt,
1551 IRQF_SHARED, "adm8211", dev);
1552 if (retval) {
1553 printk(KERN_ERR "%s: failed to register IRQ handler\n",
1554 wiphy_name(dev->wiphy));
1555 goto fail;
1556 }
1557
1558 ADM8211_CSR_WRITE(IER, ADM8211_IER_NIE | ADM8211_IER_AIE |
1559 ADM8211_IER_RCIE | ADM8211_IER_TCIE |
1560 ADM8211_IER_TDUIE | ADM8211_IER_GPTIE);
1561 priv->mode = IEEE80211_IF_TYPE_MNTR;
1562 adm8211_update_mode(dev);
1563 ADM8211_CSR_WRITE(RDR, 0);
1564
1565 adm8211_set_interval(dev, 100, 10);
1566 return 0;
1567
1568 fail:
1569 return retval;
1570 }
1571
1572 static void adm8211_stop(struct ieee80211_hw *dev)
1573 {
1574 struct adm8211_priv *priv = dev->priv;
1575
1576 priv->mode = IEEE80211_IF_TYPE_INVALID;
1577 priv->nar = 0;
1578 ADM8211_CSR_WRITE(NAR, 0);
1579 ADM8211_CSR_WRITE(IER, 0);
1580 ADM8211_CSR_READ(NAR);
1581
1582 free_irq(priv->pdev->irq, dev);
1583
1584 adm8211_free_rings(dev);
1585 }
1586
1587 static void adm8211_calc_durations(int *dur, int *plcp, size_t payload_len, int len,
1588 int plcp_signal, int short_preamble)
1589 {
1590 /* Alternative calculation from NetBSD: */
1591
1592 /* IEEE 802.11b durations for DSSS PHY in microseconds */
1593 #define IEEE80211_DUR_DS_LONG_PREAMBLE 144
1594 #define IEEE80211_DUR_DS_SHORT_PREAMBLE 72
1595 #define IEEE80211_DUR_DS_FAST_PLCPHDR 24
1596 #define IEEE80211_DUR_DS_SLOW_PLCPHDR 48
1597 #define IEEE80211_DUR_DS_SLOW_ACK 112
1598 #define IEEE80211_DUR_DS_FAST_ACK 56
1599 #define IEEE80211_DUR_DS_SLOW_CTS 112
1600 #define IEEE80211_DUR_DS_FAST_CTS 56
1601 #define IEEE80211_DUR_DS_SLOT 20
1602 #define IEEE80211_DUR_DS_SIFS 10
1603
1604 int remainder;
1605
1606 *dur = (80 * (24 + payload_len) + plcp_signal - 1)
1607 / plcp_signal;
1608
1609 if (plcp_signal <= PLCP_SIGNAL_2M)
1610 /* 1-2Mbps WLAN: send ACK/CTS at 1Mbps */
1611 *dur += 3 * (IEEE80211_DUR_DS_SIFS +
1612 IEEE80211_DUR_DS_SHORT_PREAMBLE +
1613 IEEE80211_DUR_DS_FAST_PLCPHDR) +
1614 IEEE80211_DUR_DS_SLOW_CTS + IEEE80211_DUR_DS_SLOW_ACK;
1615 else
1616 /* 5-11Mbps WLAN: send ACK/CTS at 2Mbps */
1617 *dur += 3 * (IEEE80211_DUR_DS_SIFS +
1618 IEEE80211_DUR_DS_SHORT_PREAMBLE +
1619 IEEE80211_DUR_DS_FAST_PLCPHDR) +
1620 IEEE80211_DUR_DS_FAST_CTS + IEEE80211_DUR_DS_FAST_ACK;
1621
1622 /* lengthen duration if long preamble */
1623 if (!short_preamble)
1624 *dur += 3 * (IEEE80211_DUR_DS_LONG_PREAMBLE -
1625 IEEE80211_DUR_DS_SHORT_PREAMBLE) +
1626 3 * (IEEE80211_DUR_DS_SLOW_PLCPHDR -
1627 IEEE80211_DUR_DS_FAST_PLCPHDR);
1628
1629
1630 *plcp = (80 * len) / plcp_signal;
1631 remainder = (80 * len) % plcp_signal;
1632 if (plcp_signal == PLCP_SIGNAL_11M &&
1633 remainder <= 30 && remainder > 0)
1634 *plcp = (*plcp | 0x8000) + 1;
1635 else if (remainder)
1636 (*plcp)++;
1637 }
1638
1639 /* Transmit skb w/adm8211_tx_hdr (802.11 header created by hardware) */
1640 static void adm8211_tx_raw(struct ieee80211_hw *dev, struct sk_buff *skb,
1641 u16 plcp_signal,
1642 struct ieee80211_tx_control *control,
1643 size_t hdrlen)
1644 {
1645 struct adm8211_priv *priv = dev->priv;
1646 unsigned long flags;
1647 dma_addr_t mapping;
1648 unsigned int entry;
1649 u32 flag;
1650
1651 mapping = pci_map_single(priv->pdev, skb->data, skb->len,
1652 PCI_DMA_TODEVICE);
1653
1654 spin_lock_irqsave(&priv->lock, flags);
1655
1656 if (priv->cur_tx - priv->dirty_tx == priv->tx_ring_size / 2)
1657 flag = TDES1_CONTROL_IC | TDES1_CONTROL_LS | TDES1_CONTROL_FS;
1658 else
1659 flag = TDES1_CONTROL_LS | TDES1_CONTROL_FS;
1660
1661 if (priv->cur_tx - priv->dirty_tx == priv->tx_ring_size - 2)
1662 ieee80211_stop_queue(dev, 0);
1663
1664 entry = priv->cur_tx % priv->tx_ring_size;
1665
1666 priv->tx_buffers[entry].skb = skb;
1667 priv->tx_buffers[entry].mapping = mapping;
1668 memcpy(&priv->tx_buffers[entry].tx_control, control, sizeof(*control));
1669 priv->tx_buffers[entry].hdrlen = hdrlen;
1670 priv->tx_ring[entry].buffer1 = cpu_to_le32(mapping);
1671
1672 if (entry == priv->tx_ring_size - 1)
1673 flag |= TDES1_CONTROL_TER;
1674 priv->tx_ring[entry].length = cpu_to_le32(flag | skb->len);
1675
1676 /* Set TX rate (SIGNAL field in PLCP PPDU format) */
1677 flag = TDES0_CONTROL_OWN | (plcp_signal << 20) | 8 /* ? */;
1678 priv->tx_ring[entry].status = cpu_to_le32(flag);
1679
1680 priv->cur_tx++;
1681
1682 spin_unlock_irqrestore(&priv->lock, flags);
1683
1684 /* Trigger transmit poll */
1685 ADM8211_CSR_WRITE(TDR, 0);
1686 }
1687
1688 /* Put adm8211_tx_hdr on skb and transmit */
1689 static int adm8211_tx(struct ieee80211_hw *dev, struct sk_buff *skb,
1690 struct ieee80211_tx_control *control)
1691 {
1692 struct adm8211_tx_hdr *txhdr;
1693 u16 fc;
1694 size_t payload_len, hdrlen;
1695 int plcp, dur, len, plcp_signal, short_preamble;
1696 struct ieee80211_hdr *hdr;
1697
1698 short_preamble = !!(control->tx_rate->flags &
1699 IEEE80211_TXCTL_SHORT_PREAMBLE);
1700 plcp_signal = control->tx_rate->bitrate;
1701
1702 hdr = (struct ieee80211_hdr *)skb->data;
1703 fc = le16_to_cpu(hdr->frame_control) & ~IEEE80211_FCTL_PROTECTED;
1704 hdrlen = ieee80211_get_hdrlen(fc);
1705 memcpy(skb->cb, skb->data, hdrlen);
1706 hdr = (struct ieee80211_hdr *)skb->cb;
1707 skb_pull(skb, hdrlen);
1708 payload_len = skb->len;
1709
1710 txhdr = (struct adm8211_tx_hdr *) skb_push(skb, sizeof(*txhdr));
1711 memset(txhdr, 0, sizeof(*txhdr));
1712 memcpy(txhdr->da, ieee80211_get_DA(hdr), ETH_ALEN);
1713 txhdr->signal = plcp_signal;
1714 txhdr->frame_body_size = cpu_to_le16(payload_len);
1715 txhdr->frame_control = hdr->frame_control;
1716
1717 len = hdrlen + payload_len + FCS_LEN;
1718 if (fc & IEEE80211_FCTL_PROTECTED)
1719 len += 8;
1720
1721 txhdr->frag = cpu_to_le16(0x0FFF);
1722 adm8211_calc_durations(&dur, &plcp, payload_len,
1723 len, plcp_signal, short_preamble);
1724 txhdr->plcp_frag_head_len = cpu_to_le16(plcp);
1725 txhdr->plcp_frag_tail_len = cpu_to_le16(plcp);
1726 txhdr->dur_frag_head = cpu_to_le16(dur);
1727 txhdr->dur_frag_tail = cpu_to_le16(dur);
1728
1729 txhdr->header_control = cpu_to_le16(ADM8211_TXHDRCTL_ENABLE_EXTEND_HEADER);
1730
1731 if (short_preamble)
1732 txhdr->header_control |= cpu_to_le16(ADM8211_TXHDRCTL_SHORT_PREAMBLE);
1733
1734 if (control->flags & IEEE80211_TXCTL_USE_RTS_CTS)
1735 txhdr->header_control |= cpu_to_le16(ADM8211_TXHDRCTL_ENABLE_RTS);
1736
1737 if (fc & IEEE80211_FCTL_PROTECTED)
1738 txhdr->header_control |= cpu_to_le16(ADM8211_TXHDRCTL_ENABLE_WEP_ENGINE);
1739
1740 txhdr->retry_limit = control->retry_limit;
1741
1742 adm8211_tx_raw(dev, skb, plcp_signal, control, hdrlen);
1743
1744 return NETDEV_TX_OK;
1745 }
1746
1747 static int adm8211_alloc_rings(struct ieee80211_hw *dev)
1748 {
1749 struct adm8211_priv *priv = dev->priv;
1750 unsigned int ring_size;
1751
1752 priv->rx_buffers = kmalloc(sizeof(*priv->rx_buffers) * priv->rx_ring_size +
1753 sizeof(*priv->tx_buffers) * priv->tx_ring_size, GFP_KERNEL);
1754 if (!priv->rx_buffers)
1755 return -ENOMEM;
1756
1757 priv->tx_buffers = (void *)priv->rx_buffers +
1758 sizeof(*priv->rx_buffers) * priv->rx_ring_size;
1759
1760 /* Allocate TX/RX descriptors */
1761 ring_size = sizeof(struct adm8211_desc) * priv->rx_ring_size +
1762 sizeof(struct adm8211_desc) * priv->tx_ring_size;
1763 priv->rx_ring = pci_alloc_consistent(priv->pdev, ring_size,
1764 &priv->rx_ring_dma);
1765
1766 if (!priv->rx_ring) {
1767 kfree(priv->rx_buffers);
1768 priv->rx_buffers = NULL;
1769 priv->tx_buffers = NULL;
1770 return -ENOMEM;
1771 }
1772
1773 priv->tx_ring = (struct adm8211_desc *)(priv->rx_ring +
1774 priv->rx_ring_size);
1775 priv->tx_ring_dma = priv->rx_ring_dma +
1776 sizeof(struct adm8211_desc) * priv->rx_ring_size;
1777
1778 return 0;
1779 }
1780
1781 static const struct ieee80211_ops adm8211_ops = {
1782 .tx = adm8211_tx,
1783 .start = adm8211_start,
1784 .stop = adm8211_stop,
1785 .add_interface = adm8211_add_interface,
1786 .remove_interface = adm8211_remove_interface,
1787 .config = adm8211_config,
1788 .config_interface = adm8211_config_interface,
1789 .configure_filter = adm8211_configure_filter,
1790 .get_stats = adm8211_get_stats,
1791 .get_tx_stats = adm8211_get_tx_stats,
1792 .get_tsf = adm8211_get_tsft
1793 };
1794
1795 static int __devinit adm8211_probe(struct pci_dev *pdev,
1796 const struct pci_device_id *id)
1797 {
1798 struct ieee80211_hw *dev;
1799 struct adm8211_priv *priv;
1800 unsigned long mem_addr, mem_len;
1801 unsigned int io_addr, io_len;
1802 int err;
1803 u32 reg;
1804 u8 perm_addr[ETH_ALEN];
1805 DECLARE_MAC_BUF(mac);
1806
1807 err = pci_enable_device(pdev);
1808 if (err) {
1809 printk(KERN_ERR "%s (adm8211): Cannot enable new PCI device\n",
1810 pci_name(pdev));
1811 return err;
1812 }
1813
1814 io_addr = pci_resource_start(pdev, 0);
1815 io_len = pci_resource_len(pdev, 0);
1816 mem_addr = pci_resource_start(pdev, 1);
1817 mem_len = pci_resource_len(pdev, 1);
1818 if (io_len < 256 || mem_len < 1024) {
1819 printk(KERN_ERR "%s (adm8211): Too short PCI resources\n",
1820 pci_name(pdev));
1821 goto err_disable_pdev;
1822 }
1823
1824
1825 /* check signature */
1826 pci_read_config_dword(pdev, 0x80 /* CR32 */, &reg);
1827 if (reg != ADM8211_SIG1 && reg != ADM8211_SIG2) {
1828 printk(KERN_ERR "%s (adm8211): Invalid signature (0x%x)\n",
1829 pci_name(pdev), reg);
1830 goto err_disable_pdev;
1831 }
1832
1833 err = pci_request_regions(pdev, "adm8211");
1834 if (err) {
1835 printk(KERN_ERR "%s (adm8211): Cannot obtain PCI resources\n",
1836 pci_name(pdev));
1837 return err; /* someone else grabbed it? don't disable it */
1838 }
1839
1840 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) ||
1841 pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) {
1842 printk(KERN_ERR "%s (adm8211): No suitable DMA available\n",
1843 pci_name(pdev));
1844 goto err_free_reg;
1845 }
1846
1847 pci_set_master(pdev);
1848
1849 dev = ieee80211_alloc_hw(sizeof(*priv), &adm8211_ops);
1850 if (!dev) {
1851 printk(KERN_ERR "%s (adm8211): ieee80211 alloc failed\n",
1852 pci_name(pdev));
1853 err = -ENOMEM;
1854 goto err_free_reg;
1855 }
1856 priv = dev->priv;
1857 priv->pdev = pdev;
1858
1859 spin_lock_init(&priv->lock);
1860
1861 SET_IEEE80211_DEV(dev, &pdev->dev);
1862
1863 pci_set_drvdata(pdev, dev);
1864
1865 priv->map = pci_iomap(pdev, 1, mem_len);
1866 if (!priv->map)
1867 priv->map = pci_iomap(pdev, 0, io_len);
1868
1869 if (!priv->map) {
1870 printk(KERN_ERR "%s (adm8211): Cannot map device memory\n",
1871 pci_name(pdev));
1872 goto err_free_dev;
1873 }
1874
1875 priv->rx_ring_size = rx_ring_size;
1876 priv->tx_ring_size = tx_ring_size;
1877
1878 if (adm8211_alloc_rings(dev)) {
1879 printk(KERN_ERR "%s (adm8211): Cannot allocate TX/RX ring\n",
1880 pci_name(pdev));
1881 goto err_iounmap;
1882 }
1883
1884 *(__le32 *)perm_addr = cpu_to_le32(ADM8211_CSR_READ(PAR0));
1885 *(__le16 *)&perm_addr[4] =
1886 cpu_to_le16(ADM8211_CSR_READ(PAR1) & 0xFFFF);
1887
1888 if (!is_valid_ether_addr(perm_addr)) {
1889 printk(KERN_WARNING "%s (adm8211): Invalid hwaddr in EEPROM!\n",
1890 pci_name(pdev));
1891 random_ether_addr(perm_addr);
1892 }
1893 SET_IEEE80211_PERM_ADDR(dev, perm_addr);
1894
1895 dev->extra_tx_headroom = sizeof(struct adm8211_tx_hdr);
1896 /* dev->flags = IEEE80211_HW_RX_INCLUDES_FCS in promisc mode */
1897
1898 dev->channel_change_time = 1000;
1899 dev->max_rssi = 100; /* FIXME: find better value */
1900
1901 dev->queues = 1; /* ADM8211C supports more, maybe ADM8211B too */
1902
1903 priv->retry_limit = 3;
1904 priv->ant_power = 0x40;
1905 priv->tx_power = 0x40;
1906 priv->lpf_cutoff = 0xFF;
1907 priv->lnags_threshold = 0xFF;
1908 priv->mode = IEEE80211_IF_TYPE_INVALID;
1909
1910 /* Power-on issue. EEPROM won't read correctly without */
1911 if (pdev->revision >= ADM8211_REV_BA) {
1912 ADM8211_CSR_WRITE(FRCTL, 0);
1913 ADM8211_CSR_READ(FRCTL);
1914 ADM8211_CSR_WRITE(FRCTL, 1);
1915 ADM8211_CSR_READ(FRCTL);
1916 msleep(100);
1917 }
1918
1919 err = adm8211_read_eeprom(dev);
1920 if (err) {
1921 printk(KERN_ERR "%s (adm8211): Can't alloc eeprom buffer\n",
1922 pci_name(pdev));
1923 goto err_free_desc;
1924 }
1925
1926 priv->channel = 1;
1927
1928 dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
1929
1930 err = ieee80211_register_hw(dev);
1931 if (err) {
1932 printk(KERN_ERR "%s (adm8211): Cannot register device\n",
1933 pci_name(pdev));
1934 goto err_free_desc;
1935 }
1936
1937 printk(KERN_INFO "%s: hwaddr %s, Rev 0x%02x\n",
1938 wiphy_name(dev->wiphy), print_mac(mac, dev->wiphy->perm_addr),
1939 pdev->revision);
1940
1941 return 0;
1942
1943 err_free_desc:
1944 pci_free_consistent(pdev,
1945 sizeof(struct adm8211_desc) * priv->rx_ring_size +
1946 sizeof(struct adm8211_desc) * priv->tx_ring_size,
1947 priv->rx_ring, priv->rx_ring_dma);
1948 kfree(priv->rx_buffers);
1949
1950 err_iounmap:
1951 pci_iounmap(pdev, priv->map);
1952
1953 err_free_dev:
1954 pci_set_drvdata(pdev, NULL);
1955 ieee80211_free_hw(dev);
1956
1957 err_free_reg:
1958 pci_release_regions(pdev);
1959
1960 err_disable_pdev:
1961 pci_disable_device(pdev);
1962 return err;
1963 }
1964
1965
1966 static void __devexit adm8211_remove(struct pci_dev *pdev)
1967 {
1968 struct ieee80211_hw *dev = pci_get_drvdata(pdev);
1969 struct adm8211_priv *priv;
1970
1971 if (!dev)
1972 return;
1973
1974 ieee80211_unregister_hw(dev);
1975
1976 priv = dev->priv;
1977
1978 pci_free_consistent(pdev,
1979 sizeof(struct adm8211_desc) * priv->rx_ring_size +
1980 sizeof(struct adm8211_desc) * priv->tx_ring_size,
1981 priv->rx_ring, priv->rx_ring_dma);
1982
1983 kfree(priv->rx_buffers);
1984 kfree(priv->eeprom);
1985 pci_iounmap(pdev, priv->map);
1986 pci_release_regions(pdev);
1987 pci_disable_device(pdev);
1988 ieee80211_free_hw(dev);
1989 }
1990
1991
1992 #ifdef CONFIG_PM
1993 static int adm8211_suspend(struct pci_dev *pdev, pm_message_t state)
1994 {
1995 struct ieee80211_hw *dev = pci_get_drvdata(pdev);
1996 struct adm8211_priv *priv = dev->priv;
1997
1998 if (priv->mode != IEEE80211_IF_TYPE_INVALID) {
1999 ieee80211_stop_queues(dev);
2000 adm8211_stop(dev);
2001 }
2002
2003 pci_save_state(pdev);
2004 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2005 return 0;
2006 }
2007
2008 static int adm8211_resume(struct pci_dev *pdev)
2009 {
2010 struct ieee80211_hw *dev = pci_get_drvdata(pdev);
2011 struct adm8211_priv *priv = dev->priv;
2012
2013 pci_set_power_state(pdev, PCI_D0);
2014 pci_restore_state(pdev);
2015
2016 if (priv->mode != IEEE80211_IF_TYPE_INVALID) {
2017 adm8211_start(dev);
2018 ieee80211_start_queues(dev);
2019 }
2020
2021 return 0;
2022 }
2023 #endif /* CONFIG_PM */
2024
2025
2026 MODULE_DEVICE_TABLE(pci, adm8211_pci_id_table);
2027
2028 /* TODO: implement enable_wake */
2029 static struct pci_driver adm8211_driver = {
2030 .name = "adm8211",
2031 .id_table = adm8211_pci_id_table,
2032 .probe = adm8211_probe,
2033 .remove = __devexit_p(adm8211_remove),
2034 #ifdef CONFIG_PM
2035 .suspend = adm8211_suspend,
2036 .resume = adm8211_resume,
2037 #endif /* CONFIG_PM */
2038 };
2039
2040
2041
2042 static int __init adm8211_init(void)
2043 {
2044 return pci_register_driver(&adm8211_driver);
2045 }
2046
2047
2048 static void __exit adm8211_exit(void)
2049 {
2050 pci_unregister_driver(&adm8211_driver);
2051 }
2052
2053
2054 module_init(adm8211_init);
2055 module_exit(adm8211_exit);
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