6 #define _b43_declare_plcp_hdr(size) \
7 struct b43_plcp_hdr##size { \
11 } __attribute__((__packed__)); \
12 } __attribute__((__packed__))
14 /* struct b43_plcp_hdr4 */
15 _b43_declare_plcp_hdr(4);
16 /* struct b43_plcp_hdr6 */
17 _b43_declare_plcp_hdr(6);
19 #undef _b43_declare_plcp_hdr
21 /* TX header for v4 firmware */
23 __le32 mac_ctl
; /* MAC TX control */
24 __le16 mac_frame_ctl
; /* Copy of the FrameControl field */
25 __le16 tx_fes_time_norm
; /* TX FES Time Normal */
26 __le16 phy_ctl
; /* PHY TX control */
27 __le16 phy_ctl1
; /* PHY TX control word 1 */
28 __le16 phy_ctl1_fb
; /* PHY TX control word 1 for fallback rates */
29 __le16 phy_ctl1_rts
; /* PHY TX control word 1 RTS */
30 __le16 phy_ctl1_rts_fb
; /* PHY TX control word 1 RTS for fallback rates */
31 __u8 phy_rate
; /* PHY rate */
32 __u8 phy_rate_rts
; /* PHY rate for RTS/CTS */
33 __u8 extra_ft
; /* Extra Frame Types */
34 __u8 chan_radio_code
; /* Channel Radio Code */
35 __u8 iv
[16]; /* Encryption IV */
36 __u8 tx_receiver
[6]; /* TX Frame Receiver address */
37 __le16 tx_fes_time_fb
; /* TX FES Time Fallback */
38 struct b43_plcp_hdr6 rts_plcp_fb
; /* RTS fallback PLCP header */
39 __le16 rts_dur_fb
; /* RTS fallback duration */
40 struct b43_plcp_hdr6 plcp_fb
; /* Fallback PLCP header */
41 __le16 dur_fb
; /* Fallback duration */
42 __le16 mimo_modelen
; /* MIMO mode length */
43 __le16 mimo_ratelen_fb
; /* MIMO fallback rate length */
44 __le32 timeout
; /* Timeout */
47 /* The new r410 format. */
49 __le16 mimo_antenna
; /* MIMO antenna select */
50 __le16 preload_size
; /* Preload size */
52 __le16 cookie
; /* TX frame cookie */
53 __le16 tx_status
; /* TX status */
54 struct b43_plcp_hdr6 rts_plcp
; /* RTS PLCP header */
55 __u8 rts_frame
[16]; /* The RTS frame (if used) */
57 struct b43_plcp_hdr6 plcp
; /* Main PLCP header */
58 } new_format
__attribute__ ((__packed__
));
60 /* The old r351 format. */
63 __le16 cookie
; /* TX frame cookie */
64 __le16 tx_status
; /* TX status */
65 struct b43_plcp_hdr6 rts_plcp
; /* RTS PLCP header */
66 __u8 rts_frame
[16]; /* The RTS frame (if used) */
68 struct b43_plcp_hdr6 plcp
; /* Main PLCP header */
69 } old_format
__attribute__ ((__packed__
));
71 } __attribute__ ((__packed__
));
72 } __attribute__ ((__packed__
));
75 #define B43_TXH_MAC_USEFBR 0x10000000 /* Use fallback rate for this AMPDU */
76 #define B43_TXH_MAC_KEYIDX 0x0FF00000 /* Security key index */
77 #define B43_TXH_MAC_KEYIDX_SHIFT 20
78 #define B43_TXH_MAC_KEYALG 0x00070000 /* Security key algorithm */
79 #define B43_TXH_MAC_KEYALG_SHIFT 16
80 #define B43_TXH_MAC_AMIC 0x00008000 /* AMIC */
81 #define B43_TXH_MAC_RIFS 0x00004000 /* Use RIFS */
82 #define B43_TXH_MAC_LIFETIME 0x00002000 /* Lifetime */
83 #define B43_TXH_MAC_FRAMEBURST 0x00001000 /* Frameburst */
84 #define B43_TXH_MAC_SENDCTS 0x00000800 /* Send CTS-to-self */
85 #define B43_TXH_MAC_AMPDU 0x00000600 /* AMPDU status */
86 #define B43_TXH_MAC_AMPDU_MPDU 0x00000000 /* Regular MPDU, not an AMPDU */
87 #define B43_TXH_MAC_AMPDU_FIRST 0x00000200 /* First MPDU or AMPDU */
88 #define B43_TXH_MAC_AMPDU_INTER 0x00000400 /* Intermediate MPDU or AMPDU */
89 #define B43_TXH_MAC_AMPDU_LAST 0x00000600 /* Last (or only) MPDU of AMPDU */
90 #define B43_TXH_MAC_40MHZ 0x00000100 /* Use 40 MHz bandwidth */
91 #define B43_TXH_MAC_5GHZ 0x00000080 /* 5GHz band */
92 #define B43_TXH_MAC_DFCS 0x00000040 /* DFCS */
93 #define B43_TXH_MAC_IGNPMQ 0x00000020 /* Ignore PMQ */
94 #define B43_TXH_MAC_HWSEQ 0x00000010 /* Use Hardware Sequence Number */
95 #define B43_TXH_MAC_STMSDU 0x00000008 /* Start MSDU */
96 #define B43_TXH_MAC_SENDRTS 0x00000004 /* Send RTS */
97 #define B43_TXH_MAC_LONGFRAME 0x00000002 /* Long frame */
98 #define B43_TXH_MAC_ACK 0x00000001 /* Immediate ACK */
100 /* Extra Frame Types */
101 #define B43_TXH_EFT_FB 0x03 /* Data frame fallback encoding */
102 #define B43_TXH_EFT_FB_CCK 0x00 /* CCK */
103 #define B43_TXH_EFT_FB_OFDM 0x01 /* OFDM */
104 #define B43_TXH_EFT_FB_EWC 0x02 /* EWC */
105 #define B43_TXH_EFT_FB_N 0x03 /* N */
106 #define B43_TXH_EFT_RTS 0x0C /* RTS/CTS encoding */
107 #define B43_TXH_EFT_RTS_CCK 0x00 /* CCK */
108 #define B43_TXH_EFT_RTS_OFDM 0x04 /* OFDM */
109 #define B43_TXH_EFT_RTS_EWC 0x08 /* EWC */
110 #define B43_TXH_EFT_RTS_N 0x0C /* N */
111 #define B43_TXH_EFT_RTSFB 0x30 /* RTS/CTS fallback encoding */
112 #define B43_TXH_EFT_RTSFB_CCK 0x00 /* CCK */
113 #define B43_TXH_EFT_RTSFB_OFDM 0x10 /* OFDM */
114 #define B43_TXH_EFT_RTSFB_EWC 0x20 /* EWC */
115 #define B43_TXH_EFT_RTSFB_N 0x30 /* N */
117 /* PHY TX control word */
118 #define B43_TXH_PHY_ENC 0x0003 /* Data frame encoding */
119 #define B43_TXH_PHY_ENC_CCK 0x0000 /* CCK */
120 #define B43_TXH_PHY_ENC_OFDM 0x0001 /* OFDM */
121 #define B43_TXH_PHY_ENC_EWC 0x0002 /* EWC */
122 #define B43_TXH_PHY_ENC_N 0x0003 /* N */
123 #define B43_TXH_PHY_SHORTPRMBL 0x0010 /* Use short preamble */
124 #define B43_TXH_PHY_ANT 0x03C0 /* Antenna selection */
125 #define B43_TXH_PHY_ANT0 0x0000 /* Use antenna 0 */
126 #define B43_TXH_PHY_ANT1 0x0040 /* Use antenna 1 */
127 #define B43_TXH_PHY_ANT01AUTO 0x00C0 /* Use antenna 0/1 auto */
128 #define B43_TXH_PHY_ANT2 0x0100 /* Use antenna 2 */
129 #define B43_TXH_PHY_ANT3 0x0200 /* Use antenna 3 */
130 #define B43_TXH_PHY_TXPWR 0xFC00 /* TX power */
131 #define B43_TXH_PHY_TXPWR_SHIFT 10
133 /* PHY TX control word 1 */
134 #define B43_TXH_PHY1_BW 0x0007 /* Bandwidth */
135 #define B43_TXH_PHY1_BW_10 0x0000 /* 10 MHz */
136 #define B43_TXH_PHY1_BW_10U 0x0001 /* 10 MHz upper */
137 #define B43_TXH_PHY1_BW_20 0x0002 /* 20 MHz */
138 #define B43_TXH_PHY1_BW_20U 0x0003 /* 20 MHz upper */
139 #define B43_TXH_PHY1_BW_40 0x0004 /* 40 MHz */
140 #define B43_TXH_PHY1_BW_40DUP 0x0005 /* 50 MHz duplicate */
141 #define B43_TXH_PHY1_MODE 0x0038 /* Mode */
142 #define B43_TXH_PHY1_MODE_SISO 0x0000 /* SISO */
143 #define B43_TXH_PHY1_MODE_CDD 0x0008 /* CDD */
144 #define B43_TXH_PHY1_MODE_STBC 0x0010 /* STBC */
145 #define B43_TXH_PHY1_MODE_SDM 0x0018 /* SDM */
146 #define B43_TXH_PHY1_CRATE 0x0700 /* Coding rate */
147 #define B43_TXH_PHY1_CRATE_1_2 0x0000 /* 1/2 */
148 #define B43_TXH_PHY1_CRATE_2_3 0x0100 /* 2/3 */
149 #define B43_TXH_PHY1_CRATE_3_4 0x0200 /* 3/4 */
150 #define B43_TXH_PHY1_CRATE_4_5 0x0300 /* 4/5 */
151 #define B43_TXH_PHY1_CRATE_5_6 0x0400 /* 5/6 */
152 #define B43_TXH_PHY1_CRATE_7_8 0x0600 /* 7/8 */
153 #define B43_TXH_PHY1_MODUL 0x3800 /* Modulation scheme */
154 #define B43_TXH_PHY1_MODUL_BPSK 0x0000 /* BPSK */
155 #define B43_TXH_PHY1_MODUL_QPSK 0x0800 /* QPSK */
156 #define B43_TXH_PHY1_MODUL_QAM16 0x1000 /* QAM16 */
157 #define B43_TXH_PHY1_MODUL_QAM64 0x1800 /* QAM64 */
158 #define B43_TXH_PHY1_MODUL_QAM256 0x2000 /* QAM256 */
161 /* r351 firmware compatibility stuff. */
163 bool b43_is_old_txhdr_format(struct b43_wldev
*dev
)
165 return (dev
->fw
.rev
<= 351);
169 size_t b43_txhdr_size(struct b43_wldev
*dev
)
171 if (b43_is_old_txhdr_format(dev
))
172 return 100 + sizeof(struct b43_plcp_hdr6
);
173 return 104 + sizeof(struct b43_plcp_hdr6
);
177 int b43_generate_txhdr(struct b43_wldev
*dev
,
179 const unsigned char *fragment_data
,
180 unsigned int fragment_len
,
181 const struct ieee80211_tx_control
*txctl
, u16 cookie
);
183 /* Transmit Status */
184 struct b43_txstatus
{
185 u16 cookie
; /* The cookie from the txhdr */
186 u16 seq
; /* Sequence number */
187 u8 phy_stat
; /* PHY TX status */
188 u8 frame_count
; /* Frame transmit count */
189 u8 rts_count
; /* RTS transmit count */
190 u8 supp_reason
; /* Suppression reason */
192 u8 pm_indicated
; /* PM mode indicated to AP */
193 u8 intermediate
; /* Intermediate status notification (not final) */
194 u8 for_ampdu
; /* Status is for an AMPDU (afterburner) */
195 u8 acked
; /* Wireless ACK received */
198 /* txstatus supp_reason values */
200 B43_TXST_SUPP_NONE
, /* Not suppressed */
201 B43_TXST_SUPP_PMQ
, /* Suppressed due to PMQ entry */
202 B43_TXST_SUPP_FLUSH
, /* Suppressed due to flush request */
203 B43_TXST_SUPP_PREV
, /* Previous fragment failed */
204 B43_TXST_SUPP_CHAN
, /* Channel mismatch */
205 B43_TXST_SUPP_LIFE
, /* Lifetime expired */
206 B43_TXST_SUPP_UNDER
, /* Buffer underflow */
207 B43_TXST_SUPP_ABNACK
, /* Afterburner NACK */
210 /* Receive header for v4 firmware. */
211 struct b43_rxhdr_fw4
{
212 __le16 frame_len
; /* Frame length */
214 __le16 phy_status0
; /* PHY RX Status 0 */
216 /* RSSI for A/B/G-PHYs */
218 __u8 jssi
; /* PHY RX Status 1: JSSI */
219 __u8 sig_qual
; /* PHY RX Status 1: Signal Quality */
220 } __attribute__ ((__packed__
));
222 /* RSSI for N-PHYs */
224 __s8 power0
; /* PHY RX Status 1: Power 0 */
225 __s8 power1
; /* PHY RX Status 1: Power 1 */
226 } __attribute__ ((__packed__
));
227 } __attribute__ ((__packed__
));
228 __le16 phy_status2
; /* PHY RX Status 2 */
229 __le16 phy_status3
; /* PHY RX Status 3 */
230 __le32 mac_status
; /* MAC RX status */
233 } __attribute__ ((__packed__
));
235 /* PHY RX Status 0 */
236 #define B43_RX_PHYST0_GAINCTL 0x4000 /* Gain Control */
237 #define B43_RX_PHYST0_PLCPHCF 0x0200
238 #define B43_RX_PHYST0_PLCPFV 0x0100
239 #define B43_RX_PHYST0_SHORTPRMBL 0x0080 /* Received with Short Preamble */
240 #define B43_RX_PHYST0_LCRS 0x0040
241 #define B43_RX_PHYST0_ANT 0x0020 /* Antenna */
242 #define B43_RX_PHYST0_UNSRATE 0x0010
243 #define B43_RX_PHYST0_CLIP 0x000C
244 #define B43_RX_PHYST0_CLIP_SHIFT 2
245 #define B43_RX_PHYST0_FTYPE 0x0003 /* Frame type */
246 #define B43_RX_PHYST0_CCK 0x0000 /* Frame type: CCK */
247 #define B43_RX_PHYST0_OFDM 0x0001 /* Frame type: OFDM */
248 #define B43_RX_PHYST0_PRE_N 0x0002 /* Pre-standard N-PHY frame */
249 #define B43_RX_PHYST0_STD_N 0x0003 /* Standard N-PHY frame */
251 /* PHY RX Status 2 */
252 #define B43_RX_PHYST2_LNAG 0xC000 /* LNA Gain */
253 #define B43_RX_PHYST2_LNAG_SHIFT 14
254 #define B43_RX_PHYST2_PNAG 0x3C00 /* PNA Gain */
255 #define B43_RX_PHYST2_PNAG_SHIFT 10
256 #define B43_RX_PHYST2_FOFF 0x03FF /* F offset */
258 /* PHY RX Status 3 */
259 #define B43_RX_PHYST3_DIGG 0x1800 /* DIG Gain */
260 #define B43_RX_PHYST3_DIGG_SHIFT 11
261 #define B43_RX_PHYST3_TRSTATE 0x0400 /* TR state */
264 #define B43_RX_MAC_RXST_VALID 0x01000000 /* PHY RXST valid */
265 #define B43_RX_MAC_TKIP_MICERR 0x00100000 /* TKIP MIC error */
266 #define B43_RX_MAC_TKIP_MICATT 0x00080000 /* TKIP MIC attempted */
267 #define B43_RX_MAC_AGGTYPE 0x00060000 /* Aggregation type */
268 #define B43_RX_MAC_AGGTYPE_SHIFT 17
269 #define B43_RX_MAC_AMSDU 0x00010000 /* A-MSDU mask */
270 #define B43_RX_MAC_BEACONSENT 0x00008000 /* Beacon sent flag */
271 #define B43_RX_MAC_KEYIDX 0x000007E0 /* Key index */
272 #define B43_RX_MAC_KEYIDX_SHIFT 5
273 #define B43_RX_MAC_DECERR 0x00000010 /* Decrypt error */
274 #define B43_RX_MAC_DEC 0x00000008 /* Decryption attempted */
275 #define B43_RX_MAC_PADDING 0x00000004 /* Pad bytes present */
276 #define B43_RX_MAC_RESP 0x00000002 /* Response frame transmitted */
277 #define B43_RX_MAC_FCSERR 0x00000001 /* FCS error */
280 #define B43_RX_CHAN_40MHZ 0x1000 /* 40 Mhz channel width */
281 #define B43_RX_CHAN_5GHZ 0x0800 /* 5 Ghz band */
282 #define B43_RX_CHAN_ID 0x07F8 /* Channel ID */
283 #define B43_RX_CHAN_ID_SHIFT 3
284 #define B43_RX_CHAN_PHYTYPE 0x0007 /* PHY type */
287 u8
b43_plcp_get_ratecode_cck(const u8 bitrate
);
288 u8
b43_plcp_get_ratecode_ofdm(const u8 bitrate
);
290 void b43_generate_plcp_hdr(struct b43_plcp_hdr4
*plcp
,
291 const u16 octets
, const u8 bitrate
);
293 void b43_rx(struct b43_wldev
*dev
, struct sk_buff
*skb
, const void *_rxhdr
);
295 void b43_handle_txstatus(struct b43_wldev
*dev
,
296 const struct b43_txstatus
*status
);
297 bool b43_fill_txstatus_report(struct ieee80211_tx_status
*report
,
298 const struct b43_txstatus
*status
);
300 void b43_tx_suspend(struct b43_wldev
*dev
);
301 void b43_tx_resume(struct b43_wldev
*dev
);
304 /* Helper functions for converting the key-table index from "firmware-format"
305 * to "raw-format" and back. The firmware API changed for this at some revision.
306 * We need to account for that here. */
307 static inline int b43_new_kidx_api(struct b43_wldev
*dev
)
309 /* FIXME: Not sure the change was at rev 351 */
310 return (dev
->fw
.rev
>= 351);
312 static inline u8
b43_kidx_to_fw(struct b43_wldev
*dev
, u8 raw_kidx
)
315 if (b43_new_kidx_api(dev
)) {
316 firmware_kidx
= raw_kidx
;
318 if (raw_kidx
>= 4) /* Is per STA key? */
319 firmware_kidx
= raw_kidx
- 4;
321 firmware_kidx
= raw_kidx
; /* TX default key */
323 return firmware_kidx
;
325 static inline u8
b43_kidx_to_raw(struct b43_wldev
*dev
, u8 firmware_kidx
)
328 if (b43_new_kidx_api(dev
))
329 raw_kidx
= firmware_kidx
;
331 raw_kidx
= firmware_kidx
+ 4; /* RX default keys or per STA keys */
335 #endif /* B43_XMIT_H_ */