ia64/kvm: compilation fix. export account_system_vtime.
[pv_ops_mirror.git] / drivers / net / wireless / b43legacy / b43legacy.h
blobded3cd31b3df40bceac4a5208414eb8cc12f55ea
1 #ifndef B43legacy_H_
2 #define B43legacy_H_
4 #include <linux/hw_random.h>
5 #include <linux/kernel.h>
6 #include <linux/spinlock.h>
7 #include <linux/interrupt.h>
8 #include <linux/stringify.h>
9 #include <linux/netdevice.h>
10 #include <linux/pci.h>
11 #include <asm/atomic.h>
12 #include <linux/io.h>
14 #include <linux/ssb/ssb.h>
15 #include <linux/ssb/ssb_driver_chipcommon.h>
17 #include <linux/wireless.h>
18 #include <net/mac80211.h>
20 #include "debugfs.h"
21 #include "leds.h"
22 #include "rfkill.h"
23 #include "phy.h"
26 /* The unique identifier of the firmware that's officially supported by this
27 * driver version. */
28 #define B43legacy_SUPPORTED_FIRMWARE_ID "FW10"
30 #define B43legacy_IRQWAIT_MAX_RETRIES 20
32 #define B43legacy_RX_MAX_SSI 60 /* best guess at max ssi */
34 /* MMIO offsets */
35 #define B43legacy_MMIO_DMA0_REASON 0x20
36 #define B43legacy_MMIO_DMA0_IRQ_MASK 0x24
37 #define B43legacy_MMIO_DMA1_REASON 0x28
38 #define B43legacy_MMIO_DMA1_IRQ_MASK 0x2C
39 #define B43legacy_MMIO_DMA2_REASON 0x30
40 #define B43legacy_MMIO_DMA2_IRQ_MASK 0x34
41 #define B43legacy_MMIO_DMA3_REASON 0x38
42 #define B43legacy_MMIO_DMA3_IRQ_MASK 0x3C
43 #define B43legacy_MMIO_DMA4_REASON 0x40
44 #define B43legacy_MMIO_DMA4_IRQ_MASK 0x44
45 #define B43legacy_MMIO_DMA5_REASON 0x48
46 #define B43legacy_MMIO_DMA5_IRQ_MASK 0x4C
47 #define B43legacy_MMIO_MACCTL 0x120 /* MAC control */
48 #define B43legacy_MMIO_MACCMD 0x124 /* MAC command */
49 #define B43legacy_MMIO_GEN_IRQ_REASON 0x128
50 #define B43legacy_MMIO_GEN_IRQ_MASK 0x12C
51 #define B43legacy_MMIO_RAM_CONTROL 0x130
52 #define B43legacy_MMIO_RAM_DATA 0x134
53 #define B43legacy_MMIO_PS_STATUS 0x140
54 #define B43legacy_MMIO_RADIO_HWENABLED_HI 0x158
55 #define B43legacy_MMIO_SHM_CONTROL 0x160
56 #define B43legacy_MMIO_SHM_DATA 0x164
57 #define B43legacy_MMIO_SHM_DATA_UNALIGNED 0x166
58 #define B43legacy_MMIO_XMITSTAT_0 0x170
59 #define B43legacy_MMIO_XMITSTAT_1 0x174
60 #define B43legacy_MMIO_REV3PLUS_TSF_LOW 0x180 /* core rev >= 3 only */
61 #define B43legacy_MMIO_REV3PLUS_TSF_HIGH 0x184 /* core rev >= 3 only */
63 /* 32-bit DMA */
64 #define B43legacy_MMIO_DMA32_BASE0 0x200
65 #define B43legacy_MMIO_DMA32_BASE1 0x220
66 #define B43legacy_MMIO_DMA32_BASE2 0x240
67 #define B43legacy_MMIO_DMA32_BASE3 0x260
68 #define B43legacy_MMIO_DMA32_BASE4 0x280
69 #define B43legacy_MMIO_DMA32_BASE5 0x2A0
70 /* 64-bit DMA */
71 #define B43legacy_MMIO_DMA64_BASE0 0x200
72 #define B43legacy_MMIO_DMA64_BASE1 0x240
73 #define B43legacy_MMIO_DMA64_BASE2 0x280
74 #define B43legacy_MMIO_DMA64_BASE3 0x2C0
75 #define B43legacy_MMIO_DMA64_BASE4 0x300
76 #define B43legacy_MMIO_DMA64_BASE5 0x340
77 /* PIO */
78 #define B43legacy_MMIO_PIO1_BASE 0x300
79 #define B43legacy_MMIO_PIO2_BASE 0x310
80 #define B43legacy_MMIO_PIO3_BASE 0x320
81 #define B43legacy_MMIO_PIO4_BASE 0x330
83 #define B43legacy_MMIO_PHY_VER 0x3E0
84 #define B43legacy_MMIO_PHY_RADIO 0x3E2
85 #define B43legacy_MMIO_PHY0 0x3E6
86 #define B43legacy_MMIO_ANTENNA 0x3E8
87 #define B43legacy_MMIO_CHANNEL 0x3F0
88 #define B43legacy_MMIO_CHANNEL_EXT 0x3F4
89 #define B43legacy_MMIO_RADIO_CONTROL 0x3F6
90 #define B43legacy_MMIO_RADIO_DATA_HIGH 0x3F8
91 #define B43legacy_MMIO_RADIO_DATA_LOW 0x3FA
92 #define B43legacy_MMIO_PHY_CONTROL 0x3FC
93 #define B43legacy_MMIO_PHY_DATA 0x3FE
94 #define B43legacy_MMIO_MACFILTER_CONTROL 0x420
95 #define B43legacy_MMIO_MACFILTER_DATA 0x422
96 #define B43legacy_MMIO_RCMTA_COUNT 0x43C /* Receive Match Transmitter Addr */
97 #define B43legacy_MMIO_RADIO_HWENABLED_LO 0x49A
98 #define B43legacy_MMIO_GPIO_CONTROL 0x49C
99 #define B43legacy_MMIO_GPIO_MASK 0x49E
100 #define B43legacy_MMIO_TSF_CFP_PRETBTT 0x612
101 #define B43legacy_MMIO_TSF_0 0x632 /* core rev < 3 only */
102 #define B43legacy_MMIO_TSF_1 0x634 /* core rev < 3 only */
103 #define B43legacy_MMIO_TSF_2 0x636 /* core rev < 3 only */
104 #define B43legacy_MMIO_TSF_3 0x638 /* core rev < 3 only */
105 #define B43legacy_MMIO_RNG 0x65A
106 #define B43legacy_MMIO_POWERUP_DELAY 0x6A8
108 /* SPROM boardflags_lo values */
109 #define B43legacy_BFL_PACTRL 0x0002
110 #define B43legacy_BFL_RSSI 0x0008
111 #define B43legacy_BFL_EXTLNA 0x1000
113 /* GPIO register offset, in both ChipCommon and PCI core. */
114 #define B43legacy_GPIO_CONTROL 0x6c
116 /* SHM Routing */
117 #define B43legacy_SHM_SHARED 0x0001
118 #define B43legacy_SHM_WIRELESS 0x0002
119 #define B43legacy_SHM_HW 0x0004
120 #define B43legacy_SHM_UCODE 0x0300
122 /* SHM Routing modifiers */
123 #define B43legacy_SHM_AUTOINC_R 0x0200 /* Read Auto-increment */
124 #define B43legacy_SHM_AUTOINC_W 0x0100 /* Write Auto-increment */
125 #define B43legacy_SHM_AUTOINC_RW (B43legacy_SHM_AUTOINC_R | \
126 B43legacy_SHM_AUTOINC_W)
128 /* Misc SHM_SHARED offsets */
129 #define B43legacy_SHM_SH_WLCOREREV 0x0016 /* 802.11 core revision */
130 #define B43legacy_SHM_SH_HOSTFLO 0x005E /* Hostflags ucode opts (low) */
131 #define B43legacy_SHM_SH_HOSTFHI 0x0060 /* Hostflags ucode opts (high) */
132 /* SHM_SHARED crypto engine */
133 #define B43legacy_SHM_SH_KEYIDXBLOCK 0x05D4 /* Key index/algorithm block */
134 /* SHM_SHARED beacon/AP variables */
135 #define B43legacy_SHM_SH_DTIMP 0x0012 /* DTIM period */
136 #define B43legacy_SHM_SH_BTL0 0x0018 /* Beacon template length 0 */
137 #define B43legacy_SHM_SH_BTL1 0x001A /* Beacon template length 1 */
138 #define B43legacy_SHM_SH_BTSFOFF 0x001C /* Beacon TSF offset */
139 #define B43legacy_SHM_SH_TIMPOS 0x001E /* TIM position in beacon */
140 #define B43legacy_SHM_SH_BEACPHYCTL 0x0054 /* Beacon PHY TX control word */
141 /* SHM_SHARED ACK/CTS control */
142 #define B43legacy_SHM_SH_ACKCTSPHYCTL 0x0022 /* ACK/CTS PHY control word */
143 /* SHM_SHARED probe response variables */
144 #define B43legacy_SHM_SH_PRTLEN 0x004A /* Probe Response template length */
145 #define B43legacy_SHM_SH_PRMAXTIME 0x0074 /* Probe Response max time */
146 #define B43legacy_SHM_SH_PRPHYCTL 0x0188 /* Probe Resp PHY TX control */
147 /* SHM_SHARED rate tables */
148 /* SHM_SHARED microcode soft registers */
149 #define B43legacy_SHM_SH_UCODEREV 0x0000 /* Microcode revision */
150 #define B43legacy_SHM_SH_UCODEPATCH 0x0002 /* Microcode patchlevel */
151 #define B43legacy_SHM_SH_UCODEDATE 0x0004 /* Microcode date */
152 #define B43legacy_SHM_SH_UCODETIME 0x0006 /* Microcode time */
153 #define B43legacy_SHM_SH_SPUWKUP 0x0094 /* pre-wakeup for synth PU in us */
154 #define B43legacy_SHM_SH_PRETBTT 0x0096 /* pre-TBTT in us */
156 #define B43legacy_UCODEFLAGS_OFFSET 0x005E
158 /* Hardware Radio Enable masks */
159 #define B43legacy_MMIO_RADIO_HWENABLED_HI_MASK (1 << 16)
160 #define B43legacy_MMIO_RADIO_HWENABLED_LO_MASK (1 << 4)
162 /* HostFlags. See b43legacy_hf_read/write() */
163 #define B43legacy_HF_SYMW 0x00000002 /* G-PHY SYM workaround */
164 #define B43legacy_HF_GDCW 0x00000020 /* G-PHY DV cancel filter */
165 #define B43legacy_HF_OFDMPABOOST 0x00000040 /* Enable PA boost OFDM */
166 #define B43legacy_HF_EDCF 0x00000100 /* on if WME/MAC suspended */
168 /* MacFilter offsets. */
169 #define B43legacy_MACFILTER_SELF 0x0000
170 #define B43legacy_MACFILTER_BSSID 0x0003
171 #define B43legacy_MACFILTER_MAC 0x0010
173 /* PHYVersioning */
174 #define B43legacy_PHYTYPE_B 0x01
175 #define B43legacy_PHYTYPE_G 0x02
177 /* PHYRegisters */
178 #define B43legacy_PHY_G_LO_CONTROL 0x0810
179 #define B43legacy_PHY_ILT_G_CTRL 0x0472
180 #define B43legacy_PHY_ILT_G_DATA1 0x0473
181 #define B43legacy_PHY_ILT_G_DATA2 0x0474
182 #define B43legacy_PHY_G_PCTL 0x0029
183 #define B43legacy_PHY_RADIO_BITFIELD 0x0401
184 #define B43legacy_PHY_G_CRS 0x0429
185 #define B43legacy_PHY_NRSSILT_CTRL 0x0803
186 #define B43legacy_PHY_NRSSILT_DATA 0x0804
188 /* RadioRegisters */
189 #define B43legacy_RADIOCTL_ID 0x01
191 /* MAC Control bitfield */
192 #define B43legacy_MACCTL_ENABLED 0x00000001 /* MAC Enabled */
193 #define B43legacy_MACCTL_PSM_RUN 0x00000002 /* Run Microcode */
194 #define B43legacy_MACCTL_PSM_JMP0 0x00000004 /* Microcode jump to 0 */
195 #define B43legacy_MACCTL_SHM_ENABLED 0x00000100 /* SHM Enabled */
196 #define B43legacy_MACCTL_IHR_ENABLED 0x00000400 /* IHR Region Enabled */
197 #define B43legacy_MACCTL_BE 0x00010000 /* Big Endian mode */
198 #define B43legacy_MACCTL_INFRA 0x00020000 /* Infrastructure mode */
199 #define B43legacy_MACCTL_AP 0x00040000 /* AccessPoint mode */
200 #define B43legacy_MACCTL_RADIOLOCK 0x00080000 /* Radio lock */
201 #define B43legacy_MACCTL_BEACPROMISC 0x00100000 /* Beacon Promiscuous */
202 #define B43legacy_MACCTL_KEEP_BADPLCP 0x00200000 /* Keep bad PLCP frames */
203 #define B43legacy_MACCTL_KEEP_CTL 0x00400000 /* Keep control frames */
204 #define B43legacy_MACCTL_KEEP_BAD 0x00800000 /* Keep bad frames (FCS) */
205 #define B43legacy_MACCTL_PROMISC 0x01000000 /* Promiscuous mode */
206 #define B43legacy_MACCTL_HWPS 0x02000000 /* Hardware Power Saving */
207 #define B43legacy_MACCTL_AWAKE 0x04000000 /* Device is awake */
208 #define B43legacy_MACCTL_TBTTHOLD 0x10000000 /* TBTT Hold */
209 #define B43legacy_MACCTL_GMODE 0x80000000 /* G Mode */
211 /* MAC Command bitfield */
212 #define B43legacy_MACCMD_BEACON0_VALID 0x00000001 /* Beacon 0 in template RAM is busy/valid */
213 #define B43legacy_MACCMD_BEACON1_VALID 0x00000002 /* Beacon 1 in template RAM is busy/valid */
214 #define B43legacy_MACCMD_DFQ_VALID 0x00000004 /* Directed frame queue valid (IBSS PS mode, ATIM) */
215 #define B43legacy_MACCMD_CCA 0x00000008 /* Clear channel assessment */
216 #define B43legacy_MACCMD_BGNOISE 0x00000010 /* Background noise */
218 /* 802.11 core specific TM State Low flags */
219 #define B43legacy_TMSLOW_GMODE 0x20000000 /* G Mode Enable */
220 #define B43legacy_TMSLOW_PLLREFSEL 0x00200000 /* PLL Freq Ref Select */
221 #define B43legacy_TMSLOW_MACPHYCLKEN 0x00100000 /* MAC PHY Clock Ctrl Enbl */
222 #define B43legacy_TMSLOW_PHYRESET 0x00080000 /* PHY Reset */
223 #define B43legacy_TMSLOW_PHYCLKEN 0x00040000 /* PHY Clock Enable */
225 /* 802.11 core specific TM State High flags */
226 #define B43legacy_TMSHIGH_FCLOCK 0x00040000 /* Fast Clock Available */
227 #define B43legacy_TMSHIGH_GPHY 0x00010000 /* G-PHY avail (rev >= 5) */
229 #define B43legacy_UCODEFLAG_AUTODIV 0x0001
231 /* Generic-Interrupt reasons. */
232 #define B43legacy_IRQ_MAC_SUSPENDED 0x00000001
233 #define B43legacy_IRQ_BEACON 0x00000002
234 #define B43legacy_IRQ_TBTT_INDI 0x00000004 /* Target Beacon Transmit Time */
235 #define B43legacy_IRQ_BEACON_TX_OK 0x00000008
236 #define B43legacy_IRQ_BEACON_CANCEL 0x00000010
237 #define B43legacy_IRQ_ATIM_END 0x00000020
238 #define B43legacy_IRQ_PMQ 0x00000040
239 #define B43legacy_IRQ_PIO_WORKAROUND 0x00000100
240 #define B43legacy_IRQ_MAC_TXERR 0x00000200
241 #define B43legacy_IRQ_PHY_TXERR 0x00000800
242 #define B43legacy_IRQ_PMEVENT 0x00001000
243 #define B43legacy_IRQ_TIMER0 0x00002000
244 #define B43legacy_IRQ_TIMER1 0x00004000
245 #define B43legacy_IRQ_DMA 0x00008000
246 #define B43legacy_IRQ_TXFIFO_FLUSH_OK 0x00010000
247 #define B43legacy_IRQ_CCA_MEASURE_OK 0x00020000
248 #define B43legacy_IRQ_NOISESAMPLE_OK 0x00040000
249 #define B43legacy_IRQ_UCODE_DEBUG 0x08000000
250 #define B43legacy_IRQ_RFKILL 0x10000000
251 #define B43legacy_IRQ_TX_OK 0x20000000
252 #define B43legacy_IRQ_PHY_G_CHANGED 0x40000000
253 #define B43legacy_IRQ_TIMEOUT 0x80000000
255 #define B43legacy_IRQ_ALL 0xFFFFFFFF
256 #define B43legacy_IRQ_MASKTEMPLATE (B43legacy_IRQ_MAC_SUSPENDED | \
257 B43legacy_IRQ_BEACON | \
258 B43legacy_IRQ_TBTT_INDI | \
259 B43legacy_IRQ_ATIM_END | \
260 B43legacy_IRQ_PMQ | \
261 B43legacy_IRQ_MAC_TXERR | \
262 B43legacy_IRQ_PHY_TXERR | \
263 B43legacy_IRQ_DMA | \
264 B43legacy_IRQ_TXFIFO_FLUSH_OK | \
265 B43legacy_IRQ_NOISESAMPLE_OK | \
266 B43legacy_IRQ_UCODE_DEBUG | \
267 B43legacy_IRQ_RFKILL | \
268 B43legacy_IRQ_TX_OK)
270 /* Device specific rate values.
271 * The actual values defined here are (rate_in_mbps * 2).
272 * Some code depends on this. Don't change it. */
273 #define B43legacy_CCK_RATE_1MB 2
274 #define B43legacy_CCK_RATE_2MB 4
275 #define B43legacy_CCK_RATE_5MB 11
276 #define B43legacy_CCK_RATE_11MB 22
277 #define B43legacy_OFDM_RATE_6MB 12
278 #define B43legacy_OFDM_RATE_9MB 18
279 #define B43legacy_OFDM_RATE_12MB 24
280 #define B43legacy_OFDM_RATE_18MB 36
281 #define B43legacy_OFDM_RATE_24MB 48
282 #define B43legacy_OFDM_RATE_36MB 72
283 #define B43legacy_OFDM_RATE_48MB 96
284 #define B43legacy_OFDM_RATE_54MB 108
285 /* Convert a b43legacy rate value to a rate in 100kbps */
286 #define B43legacy_RATE_TO_100KBPS(rate) (((rate) * 10) / 2)
289 #define B43legacy_DEFAULT_SHORT_RETRY_LIMIT 7
290 #define B43legacy_DEFAULT_LONG_RETRY_LIMIT 4
292 #define B43legacy_PHY_TX_BADNESS_LIMIT 1000
294 /* Max size of a security key */
295 #define B43legacy_SEC_KEYSIZE 16
296 /* Security algorithms. */
297 enum {
298 B43legacy_SEC_ALGO_NONE = 0, /* unencrypted, as of TX header. */
299 B43legacy_SEC_ALGO_WEP40,
300 B43legacy_SEC_ALGO_TKIP,
301 B43legacy_SEC_ALGO_AES,
302 B43legacy_SEC_ALGO_WEP104,
303 B43legacy_SEC_ALGO_AES_LEGACY,
306 /* Core Information Registers */
307 #define B43legacy_CIR_BASE 0xf00
308 #define B43legacy_CIR_SBTPSFLAG (B43legacy_CIR_BASE + 0x18)
309 #define B43legacy_CIR_SBIMSTATE (B43legacy_CIR_BASE + 0x90)
310 #define B43legacy_CIR_SBINTVEC (B43legacy_CIR_BASE + 0x94)
311 #define B43legacy_CIR_SBTMSTATELOW (B43legacy_CIR_BASE + 0x98)
312 #define B43legacy_CIR_SBTMSTATEHIGH (B43legacy_CIR_BASE + 0x9c)
313 #define B43legacy_CIR_SBIMCONFIGLOW (B43legacy_CIR_BASE + 0xa8)
314 #define B43legacy_CIR_SB_ID_HI (B43legacy_CIR_BASE + 0xfc)
316 /* sbtmstatehigh state flags */
317 #define B43legacy_SBTMSTATEHIGH_SERROR 0x00000001
318 #define B43legacy_SBTMSTATEHIGH_BUSY 0x00000004
319 #define B43legacy_SBTMSTATEHIGH_TIMEOUT 0x00000020
320 #define B43legacy_SBTMSTATEHIGH_G_PHY_AVAIL 0x00010000
321 #define B43legacy_SBTMSTATEHIGH_COREFLAGS 0x1FFF0000
322 #define B43legacy_SBTMSTATEHIGH_DMA64BIT 0x10000000
323 #define B43legacy_SBTMSTATEHIGH_GATEDCLK 0x20000000
324 #define B43legacy_SBTMSTATEHIGH_BISTFAILED 0x40000000
325 #define B43legacy_SBTMSTATEHIGH_BISTCOMPLETE 0x80000000
327 /* sbimstate flags */
328 #define B43legacy_SBIMSTATE_IB_ERROR 0x20000
329 #define B43legacy_SBIMSTATE_TIMEOUT 0x40000
331 #define PFX KBUILD_MODNAME ": "
332 #ifdef assert
333 # undef assert
334 #endif
335 #ifdef CONFIG_B43LEGACY_DEBUG
336 # define B43legacy_WARN_ON(x) WARN_ON(x)
337 # define B43legacy_BUG_ON(expr) \
338 do { \
339 if (unlikely((expr))) { \
340 printk(KERN_INFO PFX "Test (%s) failed\n", \
341 #expr); \
342 BUG_ON(expr); \
344 } while (0)
345 # define B43legacy_DEBUG 1
346 #else
347 /* This will evaluate the argument even if debugging is disabled. */
348 static inline bool __b43legacy_warn_on_dummy(bool x) { return x; }
349 # define B43legacy_WARN_ON(x) __b43legacy_warn_on_dummy(unlikely(!!(x)))
350 # define B43legacy_BUG_ON(x) do { /* nothing */ } while (0)
351 # define B43legacy_DEBUG 0
352 #endif
355 struct net_device;
356 struct pci_dev;
357 struct b43legacy_dmaring;
358 struct b43legacy_pioqueue;
360 /* The firmware file header */
361 #define B43legacy_FW_TYPE_UCODE 'u'
362 #define B43legacy_FW_TYPE_PCM 'p'
363 #define B43legacy_FW_TYPE_IV 'i'
364 struct b43legacy_fw_header {
365 /* File type */
366 u8 type;
367 /* File format version */
368 u8 ver;
369 u8 __padding[2];
370 /* Size of the data. For ucode and PCM this is in bytes.
371 * For IV this is number-of-ivs. */
372 __be32 size;
373 } __attribute__((__packed__));
375 /* Initial Value file format */
376 #define B43legacy_IV_OFFSET_MASK 0x7FFF
377 #define B43legacy_IV_32BIT 0x8000
378 struct b43legacy_iv {
379 __be16 offset_size;
380 union {
381 __be16 d16;
382 __be32 d32;
383 } data __attribute__((__packed__));
384 } __attribute__((__packed__));
386 #define B43legacy_PHYMODE(phytype) (1 << (phytype))
387 #define B43legacy_PHYMODE_B B43legacy_PHYMODE \
388 ((B43legacy_PHYTYPE_B))
389 #define B43legacy_PHYMODE_G B43legacy_PHYMODE \
390 ((B43legacy_PHYTYPE_G))
392 /* Value pair to measure the LocalOscillator. */
393 struct b43legacy_lopair {
394 s8 low;
395 s8 high;
396 u8 used:1;
398 #define B43legacy_LO_COUNT (14*4)
400 struct b43legacy_phy {
401 /* Possible PHYMODEs on this PHY */
402 u8 possible_phymodes;
403 /* GMODE bit enabled in MACCTL? */
404 bool gmode;
406 /* Analog Type */
407 u8 analog;
408 /* B43legacy_PHYTYPE_ */
409 u8 type;
410 /* PHY revision number. */
411 u8 rev;
413 u16 antenna_diversity;
414 u16 savedpctlreg;
415 /* Radio versioning */
416 u16 radio_manuf; /* Radio manufacturer */
417 u16 radio_ver; /* Radio version */
418 u8 calibrated:1;
419 u8 radio_rev; /* Radio revision */
421 bool dyn_tssi_tbl; /* tssi2dbm is kmalloc()ed. */
423 /* ACI (adjacent channel interference) flags. */
424 bool aci_enable;
425 bool aci_wlan_automatic;
426 bool aci_hw_rssi;
428 /* Radio switched on/off */
429 bool radio_on;
430 struct {
431 /* Values saved when turning the radio off.
432 * They are needed when turning it on again. */
433 bool valid;
434 u16 rfover;
435 u16 rfoverval;
436 } radio_off_context;
438 u16 minlowsig[2];
439 u16 minlowsigpos[2];
441 /* LO Measurement Data.
442 * Use b43legacy_get_lopair() to get a value.
444 struct b43legacy_lopair *_lo_pairs;
445 /* TSSI to dBm table in use */
446 const s8 *tssi2dbm;
447 /* idle TSSI value */
448 s8 idle_tssi;
449 /* Target idle TSSI */
450 int tgt_idle_tssi;
451 /* Current idle TSSI */
452 int cur_idle_tssi;
454 /* LocalOscillator control values. */
455 struct b43legacy_txpower_lo_control *lo_control;
456 /* Values from b43legacy_calc_loopback_gain() */
457 s16 max_lb_gain; /* Maximum Loopback gain in hdB */
458 s16 trsw_rx_gain; /* TRSW RX gain in hdB */
459 s16 lna_lod_gain; /* LNA lod */
460 s16 lna_gain; /* LNA */
461 s16 pga_gain; /* PGA */
463 /* Desired TX power level (in dBm). This is set by the user and
464 * adjusted in b43legacy_phy_xmitpower(). */
465 u8 power_level;
467 /* Values from b43legacy_calc_loopback_gain() */
468 u16 loopback_gain[2];
470 /* TX Power control values. */
471 /* B/G PHY */
472 struct {
473 /* Current Radio Attenuation for TXpower recalculation. */
474 u16 rfatt;
475 /* Current Baseband Attenuation for TXpower recalculation. */
476 u16 bbatt;
477 /* Current TXpower control value for TXpower recalculation. */
478 u16 txctl1;
479 u16 txctl2;
481 /* A PHY */
482 struct {
483 u16 txpwr_offset;
486 /* Current Interference Mitigation mode */
487 int interfmode;
488 /* Stack of saved values from the Interference Mitigation code.
489 * Each value in the stack is layed out as follows:
490 * bit 0-11: offset
491 * bit 12-15: register ID
492 * bit 16-32: value
493 * register ID is: 0x1 PHY, 0x2 Radio, 0x3 ILT
495 #define B43legacy_INTERFSTACK_SIZE 26
496 u32 interfstack[B43legacy_INTERFSTACK_SIZE];
498 /* Saved values from the NRSSI Slope calculation */
499 s16 nrssi[2];
500 s32 nrssislope;
501 /* In memory nrssi lookup table. */
502 s8 nrssi_lt[64];
504 /* current channel */
505 u8 channel;
507 u16 lofcal;
509 u16 initval;
511 /* PHY TX errors counter. */
512 atomic_t txerr_cnt;
514 #if B43legacy_DEBUG
515 /* Manual TX-power control enabled? */
516 bool manual_txpower_control;
517 /* PHY registers locked by b43legacy_phy_lock()? */
518 bool phy_locked;
519 #endif /* B43legacy_DEBUG */
522 /* Data structures for DMA transmission, per 80211 core. */
523 struct b43legacy_dma {
524 struct b43legacy_dmaring *tx_ring0;
525 struct b43legacy_dmaring *tx_ring1;
526 struct b43legacy_dmaring *tx_ring2;
527 struct b43legacy_dmaring *tx_ring3;
528 struct b43legacy_dmaring *tx_ring4;
529 struct b43legacy_dmaring *tx_ring5;
531 struct b43legacy_dmaring *rx_ring0;
532 struct b43legacy_dmaring *rx_ring3; /* only on core.rev < 5 */
535 /* Data structures for PIO transmission, per 80211 core. */
536 struct b43legacy_pio {
537 struct b43legacy_pioqueue *queue0;
538 struct b43legacy_pioqueue *queue1;
539 struct b43legacy_pioqueue *queue2;
540 struct b43legacy_pioqueue *queue3;
543 /* Context information for a noise calculation (Link Quality). */
544 struct b43legacy_noise_calculation {
545 u8 channel_at_start;
546 bool calculation_running;
547 u8 nr_samples;
548 s8 samples[8][4];
551 struct b43legacy_stats {
552 u8 link_noise;
553 /* Store the last TX/RX times here for updating the leds. */
554 unsigned long last_tx;
555 unsigned long last_rx;
558 struct b43legacy_key {
559 void *keyconf;
560 bool enabled;
561 u8 algorithm;
564 struct b43legacy_wldev;
566 /* Data structure for the WLAN parts (802.11 cores) of the b43legacy chip. */
567 struct b43legacy_wl {
568 /* Pointer to the active wireless device on this chip */
569 struct b43legacy_wldev *current_dev;
570 /* Pointer to the ieee80211 hardware data structure */
571 struct ieee80211_hw *hw;
573 spinlock_t irq_lock; /* locks IRQ */
574 struct mutex mutex; /* locks wireless core state */
575 spinlock_t leds_lock; /* lock for leds */
577 /* We can only have one operating interface (802.11 core)
578 * at a time. General information about this interface follows.
581 struct ieee80211_vif *vif;
582 /* MAC address (can be NULL). */
583 u8 mac_addr[ETH_ALEN];
584 /* Current BSSID (can be NULL). */
585 u8 bssid[ETH_ALEN];
586 /* Interface type. (IEEE80211_IF_TYPE_XXX) */
587 int if_type;
588 /* Is the card operating in AP, STA or IBSS mode? */
589 bool operating;
590 /* filter flags */
591 unsigned int filter_flags;
592 /* Stats about the wireless interface */
593 struct ieee80211_low_level_stats ieee_stats;
595 struct hwrng rng;
596 u8 rng_initialized;
597 char rng_name[30 + 1];
599 /* The RF-kill button */
600 struct b43legacy_rfkill rfkill;
602 /* List of all wireless devices on this chip */
603 struct list_head devlist;
604 u8 nr_devs;
606 bool radiotap_enabled;
608 /* The beacon we are currently using (AP or IBSS mode).
609 * This beacon stuff is protected by the irq_lock. */
610 struct sk_buff *current_beacon;
611 bool beacon0_uploaded;
612 bool beacon1_uploaded;
615 /* Pointers to the firmware data and meta information about it. */
616 struct b43legacy_firmware {
617 /* Microcode */
618 const struct firmware *ucode;
619 /* PCM code */
620 const struct firmware *pcm;
621 /* Initial MMIO values for the firmware */
622 const struct firmware *initvals;
623 /* Initial MMIO values for the firmware, band-specific */
624 const struct firmware *initvals_band;
625 /* Firmware revision */
626 u16 rev;
627 /* Firmware patchlevel */
628 u16 patch;
631 /* Device (802.11 core) initialization status. */
632 enum {
633 B43legacy_STAT_UNINIT = 0, /* Uninitialized. */
634 B43legacy_STAT_INITIALIZED = 1, /* Initialized, not yet started. */
635 B43legacy_STAT_STARTED = 2, /* Up and running. */
637 #define b43legacy_status(wldev) atomic_read(&(wldev)->__init_status)
638 #define b43legacy_set_status(wldev, stat) do { \
639 atomic_set(&(wldev)->__init_status, (stat)); \
640 smp_wmb(); \
641 } while (0)
643 /* *** --- HOW LOCKING WORKS IN B43legacy --- ***
645 * You should always acquire both, wl->mutex and wl->irq_lock unless:
646 * - You don't need to acquire wl->irq_lock, if the interface is stopped.
647 * - You don't need to acquire wl->mutex in the IRQ handler, IRQ tasklet
648 * and packet TX path (and _ONLY_ there.)
651 /* Data structure for one wireless device (802.11 core) */
652 struct b43legacy_wldev {
653 struct ssb_device *dev;
654 struct b43legacy_wl *wl;
656 /* The device initialization status.
657 * Use b43legacy_status() to query. */
658 atomic_t __init_status;
659 /* Saved init status for handling suspend. */
660 int suspend_init_status;
662 bool __using_pio; /* Using pio rather than dma. */
663 bool bad_frames_preempt;/* Use "Bad Frames Preemption". */
664 bool dfq_valid; /* Directed frame queue valid (IBSS PS mode, ATIM). */
665 bool short_preamble; /* TRUE if using short preamble. */
666 bool short_slot; /* TRUE if using short slot timing. */
667 bool radio_hw_enable; /* State of radio hardware enable bit. */
669 /* PHY/Radio device. */
670 struct b43legacy_phy phy;
671 union {
672 /* DMA engines. */
673 struct b43legacy_dma dma;
674 /* PIO engines. */
675 struct b43legacy_pio pio;
678 /* Various statistics about the physical device. */
679 struct b43legacy_stats stats;
681 /* The device LEDs. */
682 struct b43legacy_led led_tx;
683 struct b43legacy_led led_rx;
684 struct b43legacy_led led_assoc;
685 struct b43legacy_led led_radio;
687 /* Reason code of the last interrupt. */
688 u32 irq_reason;
689 u32 dma_reason[6];
690 /* saved irq enable/disable state bitfield. */
691 u32 irq_savedstate;
692 /* Link Quality calculation context. */
693 struct b43legacy_noise_calculation noisecalc;
694 /* if > 0 MAC is suspended. if == 0 MAC is enabled. */
695 int mac_suspended;
697 /* Interrupt Service Routine tasklet (bottom-half) */
698 struct tasklet_struct isr_tasklet;
700 /* Periodic tasks */
701 struct delayed_work periodic_work;
702 unsigned int periodic_state;
704 struct work_struct restart_work;
706 /* encryption/decryption */
707 u16 ktp; /* Key table pointer */
708 u8 max_nr_keys;
709 struct b43legacy_key key[58];
711 /* Firmware data */
712 struct b43legacy_firmware fw;
714 /* Devicelist in struct b43legacy_wl (all 802.11 cores) */
715 struct list_head list;
717 /* Debugging stuff follows. */
718 #ifdef CONFIG_B43LEGACY_DEBUG
719 struct b43legacy_dfsentry *dfsentry;
720 #endif
724 static inline
725 struct b43legacy_wl *hw_to_b43legacy_wl(struct ieee80211_hw *hw)
727 return hw->priv;
730 /* Helper function, which returns a boolean.
731 * TRUE, if PIO is used; FALSE, if DMA is used.
733 #if defined(CONFIG_B43LEGACY_DMA) && defined(CONFIG_B43LEGACY_PIO)
734 static inline
735 int b43legacy_using_pio(struct b43legacy_wldev *dev)
737 return dev->__using_pio;
739 #elif defined(CONFIG_B43LEGACY_DMA)
740 static inline
741 int b43legacy_using_pio(struct b43legacy_wldev *dev)
743 return 0;
745 #elif defined(CONFIG_B43LEGACY_PIO)
746 static inline
747 int b43legacy_using_pio(struct b43legacy_wldev *dev)
749 return 1;
751 #else
752 # error "Using neither DMA nor PIO? Confused..."
753 #endif
756 static inline
757 struct b43legacy_wldev *dev_to_b43legacy_wldev(struct device *dev)
759 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
760 return ssb_get_drvdata(ssb_dev);
763 /* Is the device operating in a specified mode (IEEE80211_IF_TYPE_XXX). */
764 static inline
765 int b43legacy_is_mode(struct b43legacy_wl *wl, int type)
767 return (wl->operating &&
768 wl->if_type == type);
771 static inline
772 bool is_bcm_board_vendor(struct b43legacy_wldev *dev)
774 return (dev->dev->bus->boardinfo.vendor == PCI_VENDOR_ID_BROADCOM);
777 static inline
778 u16 b43legacy_read16(struct b43legacy_wldev *dev, u16 offset)
780 return ssb_read16(dev->dev, offset);
783 static inline
784 void b43legacy_write16(struct b43legacy_wldev *dev, u16 offset, u16 value)
786 ssb_write16(dev->dev, offset, value);
789 static inline
790 u32 b43legacy_read32(struct b43legacy_wldev *dev, u16 offset)
792 return ssb_read32(dev->dev, offset);
795 static inline
796 void b43legacy_write32(struct b43legacy_wldev *dev, u16 offset, u32 value)
798 ssb_write32(dev->dev, offset, value);
801 static inline
802 struct b43legacy_lopair *b43legacy_get_lopair(struct b43legacy_phy *phy,
803 u16 radio_attenuation,
804 u16 baseband_attenuation)
806 return phy->_lo_pairs + (radio_attenuation
807 + 14 * (baseband_attenuation / 2));
812 /* Message printing */
813 void b43legacyinfo(struct b43legacy_wl *wl, const char *fmt, ...)
814 __attribute__((format(printf, 2, 3)));
815 void b43legacyerr(struct b43legacy_wl *wl, const char *fmt, ...)
816 __attribute__((format(printf, 2, 3)));
817 void b43legacywarn(struct b43legacy_wl *wl, const char *fmt, ...)
818 __attribute__((format(printf, 2, 3)));
819 #if B43legacy_DEBUG
820 void b43legacydbg(struct b43legacy_wl *wl, const char *fmt, ...)
821 __attribute__((format(printf, 2, 3)));
822 #else /* DEBUG */
823 # define b43legacydbg(wl, fmt...) do { /* nothing */ } while (0)
824 #endif /* DEBUG */
827 /** Limit a value between two limits */
828 #ifdef limit_value
829 # undef limit_value
830 #endif
831 #define limit_value(value, min, max) \
832 ({ \
833 typeof(value) __value = (value); \
834 typeof(value) __min = (min); \
835 typeof(value) __max = (max); \
836 if (__value < __min) \
837 __value = __min; \
838 else if (__value > __max) \
839 __value = __max; \
840 __value; \
843 /* Macros for printing a value in Q5.2 format */
844 #define Q52_FMT "%u.%u"
845 #define Q52_ARG(q52) ((q52) / 4), (((q52) & 3) * 100 / 4)
847 #endif /* B43legacy_H_ */