ia64/kvm: compilation fix. export account_system_vtime.
[pv_ops_mirror.git] / drivers / rtc / rtc-bfin.c
blob8624f55d05608cabe99e6f91a9e18220be699a13
1 /*
2 * Blackfin On-Chip Real Time Clock Driver
3 * Supports BF52[257]/BF53[123]/BF53[467]/BF54[24789]
5 * Copyright 2004-2007 Analog Devices Inc.
7 * Enter bugs at http://blackfin.uclinux.org/
9 * Licensed under the GPL-2 or later.
12 /* The biggest issue we deal with in this driver is that register writes are
13 * synced to the RTC frequency of 1Hz. So if you write to a register and
14 * attempt to write again before the first write has completed, the new write
15 * is simply discarded. This can easily be troublesome if userspace disables
16 * one event (say periodic) and then right after enables an event (say alarm).
17 * Since all events are maintained in the same interrupt mask register, if
18 * we wrote to it to disable the first event and then wrote to it again to
19 * enable the second event, that second event would not be enabled as the
20 * write would be discarded and things quickly fall apart.
22 * To keep this delay from significantly degrading performance (we, in theory,
23 * would have to sleep for up to 1 second everytime we wanted to write a
24 * register), we only check the write pending status before we start to issue
25 * a new write. We bank on the idea that it doesnt matter when the sync
26 * happens so long as we don't attempt another write before it does. The only
27 * time userspace would take this penalty is when they try and do multiple
28 * operations right after another ... but in this case, they need to take the
29 * sync penalty, so we should be OK.
31 * Also note that the RTC_ISTAT register does not suffer this penalty; its
32 * writes to clear status registers complete immediately.
35 #include <linux/bcd.h>
36 #include <linux/completion.h>
37 #include <linux/delay.h>
38 #include <linux/init.h>
39 #include <linux/interrupt.h>
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/platform_device.h>
43 #include <linux/rtc.h>
44 #include <linux/seq_file.h>
46 #include <asm/blackfin.h>
48 #define dev_dbg_stamp(dev) dev_dbg(dev, "%s:%i: here i am\n", __func__, __LINE__)
50 struct bfin_rtc {
51 struct rtc_device *rtc_dev;
52 struct rtc_time rtc_alarm;
53 u16 rtc_wrote_regs;
56 /* Bit values for the ISTAT / ICTL registers */
57 #define RTC_ISTAT_WRITE_COMPLETE 0x8000
58 #define RTC_ISTAT_WRITE_PENDING 0x4000
59 #define RTC_ISTAT_ALARM_DAY 0x0040
60 #define RTC_ISTAT_24HR 0x0020
61 #define RTC_ISTAT_HOUR 0x0010
62 #define RTC_ISTAT_MIN 0x0008
63 #define RTC_ISTAT_SEC 0x0004
64 #define RTC_ISTAT_ALARM 0x0002
65 #define RTC_ISTAT_STOPWATCH 0x0001
67 /* Shift values for RTC_STAT register */
68 #define DAY_BITS_OFF 17
69 #define HOUR_BITS_OFF 12
70 #define MIN_BITS_OFF 6
71 #define SEC_BITS_OFF 0
73 /* Some helper functions to convert between the common RTC notion of time
74 * and the internal Blackfin notion that is encoded in 32bits.
76 static inline u32 rtc_time_to_bfin(unsigned long now)
78 u32 sec = (now % 60);
79 u32 min = (now % (60 * 60)) / 60;
80 u32 hour = (now % (60 * 60 * 24)) / (60 * 60);
81 u32 days = (now / (60 * 60 * 24));
82 return (sec << SEC_BITS_OFF) +
83 (min << MIN_BITS_OFF) +
84 (hour << HOUR_BITS_OFF) +
85 (days << DAY_BITS_OFF);
87 static inline unsigned long rtc_bfin_to_time(u32 rtc_bfin)
89 return (((rtc_bfin >> SEC_BITS_OFF) & 0x003F)) +
90 (((rtc_bfin >> MIN_BITS_OFF) & 0x003F) * 60) +
91 (((rtc_bfin >> HOUR_BITS_OFF) & 0x001F) * 60 * 60) +
92 (((rtc_bfin >> DAY_BITS_OFF) & 0x7FFF) * 60 * 60 * 24);
94 static inline void rtc_bfin_to_tm(u32 rtc_bfin, struct rtc_time *tm)
96 rtc_time_to_tm(rtc_bfin_to_time(rtc_bfin), tm);
99 /**
100 * bfin_rtc_sync_pending - make sure pending writes have complete
102 * Wait for the previous write to a RTC register to complete.
103 * Unfortunately, we can't sleep here as that introduces a race condition when
104 * turning on interrupt events. Consider this:
105 * - process sets alarm
106 * - process enables alarm
107 * - process sleeps while waiting for rtc write to sync
108 * - interrupt fires while process is sleeping
109 * - interrupt acks the event by writing to ISTAT
110 * - interrupt sets the WRITE PENDING bit
111 * - interrupt handler finishes
112 * - process wakes up, sees WRITE PENDING bit set, goes to sleep
113 * - interrupt fires while process is sleeping
114 * If anyone can point out the obvious solution here, i'm listening :). This
115 * shouldn't be an issue on an SMP or preempt system as this function should
116 * only be called with the rtc lock held.
118 * Other options:
119 * - disable PREN so the sync happens at 32.768kHZ ... but this changes the
120 * inc rate for all RTC registers from 1HZ to 32.768kHZ ...
121 * - use the write complete IRQ
124 static void bfin_rtc_sync_pending_polled(void)
126 while (!(bfin_read_RTC_ISTAT() & RTC_ISTAT_WRITE_COMPLETE))
127 if (!(bfin_read_RTC_ISTAT() & RTC_ISTAT_WRITE_PENDING))
128 break;
129 bfin_write_RTC_ISTAT(RTC_ISTAT_WRITE_COMPLETE);
132 static DECLARE_COMPLETION(bfin_write_complete);
133 static void bfin_rtc_sync_pending(struct device *dev)
135 dev_dbg_stamp(dev);
136 while (bfin_read_RTC_ISTAT() & RTC_ISTAT_WRITE_PENDING)
137 wait_for_completion_timeout(&bfin_write_complete, HZ * 5);
138 dev_dbg_stamp(dev);
142 * bfin_rtc_reset - set RTC to sane/known state
144 * Initialize the RTC. Enable pre-scaler to scale RTC clock
145 * to 1Hz and clear interrupt/status registers.
147 static void bfin_rtc_reset(struct device *dev)
149 struct bfin_rtc *rtc = dev_get_drvdata(dev);
150 dev_dbg_stamp(dev);
151 bfin_rtc_sync_pending(dev);
152 bfin_write_RTC_PREN(0x1);
153 bfin_write_RTC_ICTL(RTC_ISTAT_WRITE_COMPLETE);
154 bfin_write_RTC_SWCNT(0);
155 bfin_write_RTC_ALARM(0);
156 bfin_write_RTC_ISTAT(0xFFFF);
157 rtc->rtc_wrote_regs = 0;
161 * bfin_rtc_interrupt - handle interrupt from RTC
163 * Since we handle all RTC events here, we have to make sure the requested
164 * interrupt is enabled (in RTC_ICTL) as the event status register (RTC_ISTAT)
165 * always gets updated regardless of the interrupt being enabled. So when one
166 * even we care about (e.g. stopwatch) goes off, we don't want to turn around
167 * and say that other events have happened as well (e.g. second). We do not
168 * have to worry about pending writes to the RTC_ICTL register as interrupts
169 * only fire if they are enabled in the RTC_ICTL register.
171 static irqreturn_t bfin_rtc_interrupt(int irq, void *dev_id)
173 struct device *dev = dev_id;
174 struct bfin_rtc *rtc = dev_get_drvdata(dev);
175 unsigned long events = 0;
176 bool write_complete = false;
177 u16 rtc_istat, rtc_ictl;
179 dev_dbg_stamp(dev);
181 rtc_istat = bfin_read_RTC_ISTAT();
182 rtc_ictl = bfin_read_RTC_ICTL();
184 if (rtc_istat & RTC_ISTAT_WRITE_COMPLETE) {
185 bfin_write_RTC_ISTAT(RTC_ISTAT_WRITE_COMPLETE);
186 write_complete = true;
187 complete(&bfin_write_complete);
190 if (rtc_ictl & (RTC_ISTAT_ALARM | RTC_ISTAT_ALARM_DAY)) {
191 if (rtc_istat & (RTC_ISTAT_ALARM | RTC_ISTAT_ALARM_DAY)) {
192 bfin_write_RTC_ISTAT(RTC_ISTAT_ALARM | RTC_ISTAT_ALARM_DAY);
193 events |= RTC_AF | RTC_IRQF;
197 if (rtc_ictl & RTC_ISTAT_STOPWATCH) {
198 if (rtc_istat & RTC_ISTAT_STOPWATCH) {
199 bfin_write_RTC_ISTAT(RTC_ISTAT_STOPWATCH);
200 events |= RTC_PF | RTC_IRQF;
201 bfin_write_RTC_SWCNT(rtc->rtc_dev->irq_freq);
205 if (rtc_ictl & RTC_ISTAT_SEC) {
206 if (rtc_istat & RTC_ISTAT_SEC) {
207 bfin_write_RTC_ISTAT(RTC_ISTAT_SEC);
208 events |= RTC_UF | RTC_IRQF;
212 if (events)
213 rtc_update_irq(rtc->rtc_dev, 1, events);
215 if (write_complete || events)
216 return IRQ_HANDLED;
217 else
218 return IRQ_NONE;
221 static int bfin_rtc_open(struct device *dev)
223 int ret;
225 dev_dbg_stamp(dev);
227 ret = request_irq(IRQ_RTC, bfin_rtc_interrupt, IRQF_SHARED, to_platform_device(dev)->name, dev);
228 if (!ret)
229 bfin_rtc_reset(dev);
231 return ret;
234 static void bfin_rtc_release(struct device *dev)
236 dev_dbg_stamp(dev);
237 bfin_rtc_reset(dev);
238 free_irq(IRQ_RTC, dev);
241 static void bfin_rtc_int_set(struct bfin_rtc *rtc, u16 rtc_int)
243 bfin_write_RTC_ISTAT(rtc_int);
244 bfin_write_RTC_ICTL(bfin_read_RTC_ICTL() | rtc_int);
246 static void bfin_rtc_int_clear(struct bfin_rtc *rtc, u16 rtc_int)
248 bfin_write_RTC_ICTL(bfin_read_RTC_ICTL() & rtc_int);
250 static void bfin_rtc_int_set_alarm(struct bfin_rtc *rtc)
252 /* Blackfin has different bits for whether the alarm is
253 * more than 24 hours away.
255 bfin_rtc_int_set(rtc, (rtc->rtc_alarm.tm_yday == -1 ? RTC_ISTAT_ALARM : RTC_ISTAT_ALARM_DAY));
257 static int bfin_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
259 struct bfin_rtc *rtc = dev_get_drvdata(dev);
260 int ret = 0;
262 dev_dbg_stamp(dev);
264 bfin_rtc_sync_pending(dev);
266 switch (cmd) {
267 case RTC_PIE_ON:
268 dev_dbg_stamp(dev);
269 bfin_rtc_int_set(rtc, RTC_ISTAT_STOPWATCH);
270 bfin_write_RTC_SWCNT(rtc->rtc_dev->irq_freq);
271 break;
272 case RTC_PIE_OFF:
273 dev_dbg_stamp(dev);
274 bfin_rtc_int_clear(rtc, ~RTC_ISTAT_STOPWATCH);
275 break;
277 case RTC_UIE_ON:
278 dev_dbg_stamp(dev);
279 bfin_rtc_int_set(rtc, RTC_ISTAT_SEC);
280 break;
281 case RTC_UIE_OFF:
282 dev_dbg_stamp(dev);
283 bfin_rtc_int_clear(rtc, ~RTC_ISTAT_SEC);
284 break;
286 case RTC_AIE_ON:
287 dev_dbg_stamp(dev);
288 bfin_rtc_int_set_alarm(rtc);
289 break;
290 case RTC_AIE_OFF:
291 dev_dbg_stamp(dev);
292 bfin_rtc_int_clear(rtc, ~(RTC_ISTAT_ALARM | RTC_ISTAT_ALARM_DAY));
293 break;
295 default:
296 dev_dbg_stamp(dev);
297 ret = -ENOIOCTLCMD;
300 return ret;
303 static int bfin_rtc_read_time(struct device *dev, struct rtc_time *tm)
305 struct bfin_rtc *rtc = dev_get_drvdata(dev);
307 dev_dbg_stamp(dev);
309 if (rtc->rtc_wrote_regs & 0x1)
310 bfin_rtc_sync_pending(dev);
312 rtc_bfin_to_tm(bfin_read_RTC_STAT(), tm);
314 return 0;
317 static int bfin_rtc_set_time(struct device *dev, struct rtc_time *tm)
319 struct bfin_rtc *rtc = dev_get_drvdata(dev);
320 int ret;
321 unsigned long now;
323 dev_dbg_stamp(dev);
325 ret = rtc_tm_to_time(tm, &now);
326 if (ret == 0) {
327 if (rtc->rtc_wrote_regs & 0x1)
328 bfin_rtc_sync_pending(dev);
329 bfin_write_RTC_STAT(rtc_time_to_bfin(now));
330 rtc->rtc_wrote_regs = 0x1;
333 return ret;
336 static int bfin_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
338 struct bfin_rtc *rtc = dev_get_drvdata(dev);
339 dev_dbg_stamp(dev);
340 alrm->time = rtc->rtc_alarm;
341 bfin_rtc_sync_pending(dev);
342 alrm->enabled = !!(bfin_read_RTC_ICTL() & (RTC_ISTAT_ALARM | RTC_ISTAT_ALARM_DAY));
343 return 0;
346 static int bfin_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
348 struct bfin_rtc *rtc = dev_get_drvdata(dev);
349 unsigned long rtc_alarm;
351 dev_dbg_stamp(dev);
353 if (rtc_tm_to_time(&alrm->time, &rtc_alarm))
354 return -EINVAL;
356 rtc->rtc_alarm = alrm->time;
358 bfin_rtc_sync_pending(dev);
359 bfin_write_RTC_ALARM(rtc_time_to_bfin(rtc_alarm));
360 if (alrm->enabled)
361 bfin_rtc_int_set_alarm(rtc);
363 return 0;
366 static int bfin_rtc_proc(struct device *dev, struct seq_file *seq)
368 #define yesno(x) ((x) ? "yes" : "no")
369 u16 ictl = bfin_read_RTC_ICTL();
370 dev_dbg_stamp(dev);
371 seq_printf(seq,
372 "alarm_IRQ\t: %s\n"
373 "wkalarm_IRQ\t: %s\n"
374 "seconds_IRQ\t: %s\n"
375 "periodic_IRQ\t: %s\n",
376 yesno(ictl & RTC_ISTAT_ALARM),
377 yesno(ictl & RTC_ISTAT_ALARM_DAY),
378 yesno(ictl & RTC_ISTAT_SEC),
379 yesno(ictl & RTC_ISTAT_STOPWATCH));
380 return 0;
381 #undef yesno
385 * bfin_irq_set_freq - make sure hardware supports requested freq
386 * @dev: pointer to RTC device structure
387 * @freq: requested frequency rate
389 * The Blackfin RTC can only generate periodic events at 1 per
390 * second (1 Hz), so reject any attempt at changing it.
392 static int bfin_irq_set_freq(struct device *dev, int freq)
394 dev_dbg_stamp(dev);
395 return -ENOTTY;
398 static struct rtc_class_ops bfin_rtc_ops = {
399 .open = bfin_rtc_open,
400 .release = bfin_rtc_release,
401 .ioctl = bfin_rtc_ioctl,
402 .read_time = bfin_rtc_read_time,
403 .set_time = bfin_rtc_set_time,
404 .read_alarm = bfin_rtc_read_alarm,
405 .set_alarm = bfin_rtc_set_alarm,
406 .proc = bfin_rtc_proc,
407 .irq_set_freq = bfin_irq_set_freq,
410 static int __devinit bfin_rtc_probe(struct platform_device *pdev)
412 struct bfin_rtc *rtc;
413 int ret = 0;
415 dev_dbg_stamp(&pdev->dev);
417 rtc = kzalloc(sizeof(*rtc), GFP_KERNEL);
418 if (unlikely(!rtc))
419 return -ENOMEM;
421 rtc->rtc_dev = rtc_device_register(pdev->name, &pdev->dev, &bfin_rtc_ops, THIS_MODULE);
422 if (IS_ERR(rtc)) {
423 ret = PTR_ERR(rtc->rtc_dev);
424 goto err;
426 rtc->rtc_dev->irq_freq = 1;
428 platform_set_drvdata(pdev, rtc);
430 return 0;
432 err:
433 kfree(rtc);
434 return ret;
437 static int __devexit bfin_rtc_remove(struct platform_device *pdev)
439 struct bfin_rtc *rtc = platform_get_drvdata(pdev);
441 rtc_device_unregister(rtc->rtc_dev);
442 platform_set_drvdata(pdev, NULL);
443 kfree(rtc);
445 return 0;
448 static struct platform_driver bfin_rtc_driver = {
449 .driver = {
450 .name = "rtc-bfin",
451 .owner = THIS_MODULE,
453 .probe = bfin_rtc_probe,
454 .remove = __devexit_p(bfin_rtc_remove),
457 static int __init bfin_rtc_init(void)
459 return platform_driver_register(&bfin_rtc_driver);
462 static void __exit bfin_rtc_exit(void)
464 platform_driver_unregister(&bfin_rtc_driver);
467 module_init(bfin_rtc_init);
468 module_exit(bfin_rtc_exit);
470 MODULE_DESCRIPTION("Blackfin On-Chip Real Time Clock Driver");
471 MODULE_AUTHOR("Mike Frysinger <vapier@gentoo.org>");
472 MODULE_LICENSE("GPL");
473 MODULE_ALIAS("platform:rtc-bfin");