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ia64/kvm: compilation fix. export account_system_vtime.
[pv_ops_mirror.git] / drivers / scsi / qla2xxx / qla_sup.c
blob1728ab3ccb201f19677885d488d8b12726cf094d
1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2008 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7 #include "qla_def.h"
8
9 #include <linux/delay.h>
10 #include <linux/vmalloc.h>
11 #include <asm/uaccess.h>
12
13 static uint16_t qla2x00_nvram_request(scsi_qla_host_t *, uint32_t);
14 static void qla2x00_nv_deselect(scsi_qla_host_t *);
15 static void qla2x00_nv_write(scsi_qla_host_t *, uint16_t);
16
17 /*
18 * NVRAM support routines
19 */
20
21 /**
22 * qla2x00_lock_nvram_access() -
23 * @ha: HA context
24 */
25 static void
26 qla2x00_lock_nvram_access(scsi_qla_host_t *ha)
27 {
28 uint16_t data;
29 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
30
31 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
32 data = RD_REG_WORD(&reg->nvram);
33 while (data & NVR_BUSY) {
34 udelay(100);
35 data = RD_REG_WORD(&reg->nvram);
36 }
37
38 /* Lock resource */
39 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
40 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
41 udelay(5);
42 data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
43 while ((data & BIT_0) == 0) {
44 /* Lock failed */
45 udelay(100);
46 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
47 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
48 udelay(5);
49 data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
50 }
51 }
52 }
53
54 /**
55 * qla2x00_unlock_nvram_access() -
56 * @ha: HA context
57 */
58 static void
59 qla2x00_unlock_nvram_access(scsi_qla_host_t *ha)
60 {
61 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
62
63 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
64 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0);
65 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
66 }
67 }
68
69 /**
70 * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the
71 * request routine to get the word from NVRAM.
72 * @ha: HA context
73 * @addr: Address in NVRAM to read
74 *
75 * Returns the word read from nvram @addr.
76 */
77 static uint16_t
78 qla2x00_get_nvram_word(scsi_qla_host_t *ha, uint32_t addr)
79 {
80 uint16_t data;
81 uint32_t nv_cmd;
82
83 nv_cmd = addr << 16;
84 nv_cmd |= NV_READ_OP;
85 data = qla2x00_nvram_request(ha, nv_cmd);
86
87 return (data);
88 }
89
90 /**
91 * qla2x00_write_nvram_word() - Write NVRAM data.
92 * @ha: HA context
93 * @addr: Address in NVRAM to write
94 * @data: word to program
95 */
96 static void
97 qla2x00_write_nvram_word(scsi_qla_host_t *ha, uint32_t addr, uint16_t data)
98 {
99 int count;
100 uint16_t word;
101 uint32_t nv_cmd, wait_cnt;
102 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
103
104 qla2x00_nv_write(ha, NVR_DATA_OUT);
105 qla2x00_nv_write(ha, 0);
106 qla2x00_nv_write(ha, 0);
107
108 for (word = 0; word < 8; word++)
109 qla2x00_nv_write(ha, NVR_DATA_OUT);
110
111 qla2x00_nv_deselect(ha);
112
113 /* Write data */
114 nv_cmd = (addr << 16) | NV_WRITE_OP;
115 nv_cmd |= data;
116 nv_cmd <<= 5;
117 for (count = 0; count < 27; count++) {
118 if (nv_cmd & BIT_31)
119 qla2x00_nv_write(ha, NVR_DATA_OUT);
120 else
121 qla2x00_nv_write(ha, 0);
122
123 nv_cmd <<= 1;
124 }
125
126 qla2x00_nv_deselect(ha);
127
128 /* Wait for NVRAM to become ready */
129 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
130 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
131 wait_cnt = NVR_WAIT_CNT;
132 do {
133 if (!--wait_cnt) {
134 DEBUG9_10(printk("%s(%ld): NVRAM didn't go ready...\n",
135 __func__, ha->host_no));
136 break;
137 }
138 NVRAM_DELAY();
139 word = RD_REG_WORD(&reg->nvram);
140 } while ((word & NVR_DATA_IN) == 0);
141
142 qla2x00_nv_deselect(ha);
143
144 /* Disable writes */
145 qla2x00_nv_write(ha, NVR_DATA_OUT);
146 for (count = 0; count < 10; count++)
147 qla2x00_nv_write(ha, 0);
148
149 qla2x00_nv_deselect(ha);
150 }
151
152 static int
153 qla2x00_write_nvram_word_tmo(scsi_qla_host_t *ha, uint32_t addr, uint16_t data,
154 uint32_t tmo)
155 {
156 int ret, count;
157 uint16_t word;
158 uint32_t nv_cmd;
159 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
160
161 ret = QLA_SUCCESS;
162
163 qla2x00_nv_write(ha, NVR_DATA_OUT);
164 qla2x00_nv_write(ha, 0);
165 qla2x00_nv_write(ha, 0);
166
167 for (word = 0; word < 8; word++)
168 qla2x00_nv_write(ha, NVR_DATA_OUT);
169
170 qla2x00_nv_deselect(ha);
171
172 /* Write data */
173 nv_cmd = (addr << 16) | NV_WRITE_OP;
174 nv_cmd |= data;
175 nv_cmd <<= 5;
176 for (count = 0; count < 27; count++) {
177 if (nv_cmd & BIT_31)
178 qla2x00_nv_write(ha, NVR_DATA_OUT);
179 else
180 qla2x00_nv_write(ha, 0);
181
182 nv_cmd <<= 1;
183 }
184
185 qla2x00_nv_deselect(ha);
186
187 /* Wait for NVRAM to become ready */
188 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
189 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
190 do {
191 NVRAM_DELAY();
192 word = RD_REG_WORD(&reg->nvram);
193 if (!--tmo) {
194 ret = QLA_FUNCTION_FAILED;
195 break;
196 }
197 } while ((word & NVR_DATA_IN) == 0);
198
199 qla2x00_nv_deselect(ha);
200
201 /* Disable writes */
202 qla2x00_nv_write(ha, NVR_DATA_OUT);
203 for (count = 0; count < 10; count++)
204 qla2x00_nv_write(ha, 0);
205
206 qla2x00_nv_deselect(ha);
207
208 return ret;
209 }
210
211 /**
212 * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from
213 * NVRAM.
214 * @ha: HA context
215 * @nv_cmd: NVRAM command
216 *
217 * Bit definitions for NVRAM command:
218 *
219 * Bit 26 = start bit
220 * Bit 25, 24 = opcode
221 * Bit 23-16 = address
222 * Bit 15-0 = write data
223 *
224 * Returns the word read from nvram @addr.
225 */
226 static uint16_t
227 qla2x00_nvram_request(scsi_qla_host_t *ha, uint32_t nv_cmd)
228 {
229 uint8_t cnt;
230 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
231 uint16_t data = 0;
232 uint16_t reg_data;
233
234 /* Send command to NVRAM. */
235 nv_cmd <<= 5;
236 for (cnt = 0; cnt < 11; cnt++) {
237 if (nv_cmd & BIT_31)
238 qla2x00_nv_write(ha, NVR_DATA_OUT);
239 else
240 qla2x00_nv_write(ha, 0);
241 nv_cmd <<= 1;
242 }
243
244 /* Read data from NVRAM. */
245 for (cnt = 0; cnt < 16; cnt++) {
246 WRT_REG_WORD(&reg->nvram, NVR_SELECT | NVR_CLOCK);
247 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
248 NVRAM_DELAY();
249 data <<= 1;
250 reg_data = RD_REG_WORD(&reg->nvram);
251 if (reg_data & NVR_DATA_IN)
252 data |= BIT_0;
253 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
254 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
255 NVRAM_DELAY();
256 }
257
258 /* Deselect chip. */
259 WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
260 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
261 NVRAM_DELAY();
262
263 return (data);
264 }
265
266 /**
267 * qla2x00_nv_write() - Clean NVRAM operations.
268 * @ha: HA context
269 */
270 static void
271 qla2x00_nv_deselect(scsi_qla_host_t *ha)
272 {
273 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
274
275 WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
276 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
277 NVRAM_DELAY();
278 }
279
280 /**
281 * qla2x00_nv_write() - Prepare for NVRAM read/write operation.
282 * @ha: HA context
283 * @data: Serial interface selector
284 */
285 static void
286 qla2x00_nv_write(scsi_qla_host_t *ha, uint16_t data)
287 {
288 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
289
290 WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
291 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
292 NVRAM_DELAY();
293 WRT_REG_WORD(&reg->nvram, data | NVR_SELECT| NVR_CLOCK |
294 NVR_WRT_ENABLE);
295 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
296 NVRAM_DELAY();
297 WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
298 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
299 NVRAM_DELAY();
300 }
301
302 /**
303 * qla2x00_clear_nvram_protection() -
304 * @ha: HA context
305 */
306 static int
307 qla2x00_clear_nvram_protection(scsi_qla_host_t *ha)
308 {
309 int ret, stat;
310 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
311 uint32_t word, wait_cnt;
312 uint16_t wprot, wprot_old;
313
314 /* Clear NVRAM write protection. */
315 ret = QLA_FUNCTION_FAILED;
316
317 wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
318 stat = qla2x00_write_nvram_word_tmo(ha, ha->nvram_base,
319 __constant_cpu_to_le16(0x1234), 100000);
320 wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
321 if (stat != QLA_SUCCESS || wprot != 0x1234) {
322 /* Write enable. */
323 qla2x00_nv_write(ha, NVR_DATA_OUT);
324 qla2x00_nv_write(ha, 0);
325 qla2x00_nv_write(ha, 0);
326 for (word = 0; word < 8; word++)
327 qla2x00_nv_write(ha, NVR_DATA_OUT);
328
329 qla2x00_nv_deselect(ha);
330
331 /* Enable protection register. */
332 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
333 qla2x00_nv_write(ha, NVR_PR_ENABLE);
334 qla2x00_nv_write(ha, NVR_PR_ENABLE);
335 for (word = 0; word < 8; word++)
336 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
337
338 qla2x00_nv_deselect(ha);
339
340 /* Clear protection register (ffff is cleared). */
341 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
342 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
343 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
344 for (word = 0; word < 8; word++)
345 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
346
347 qla2x00_nv_deselect(ha);
348
349 /* Wait for NVRAM to become ready. */
350 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
351 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
352 wait_cnt = NVR_WAIT_CNT;
353 do {
354 if (!--wait_cnt) {
355 DEBUG9_10(printk("%s(%ld): NVRAM didn't go "
356 "ready...\n", __func__,
357 ha->host_no));
358 break;
359 }
360 NVRAM_DELAY();
361 word = RD_REG_WORD(&reg->nvram);
362 } while ((word & NVR_DATA_IN) == 0);
363
364 if (wait_cnt)
365 ret = QLA_SUCCESS;
366 } else
367 qla2x00_write_nvram_word(ha, ha->nvram_base, wprot_old);
368
369 return ret;
370 }
371
372 static void
373 qla2x00_set_nvram_protection(scsi_qla_host_t *ha, int stat)
374 {
375 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
376 uint32_t word, wait_cnt;
377
378 if (stat != QLA_SUCCESS)
379 return;
380
381 /* Set NVRAM write protection. */
382 /* Write enable. */
383 qla2x00_nv_write(ha, NVR_DATA_OUT);
384 qla2x00_nv_write(ha, 0);
385 qla2x00_nv_write(ha, 0);
386 for (word = 0; word < 8; word++)
387 qla2x00_nv_write(ha, NVR_DATA_OUT);
388
389 qla2x00_nv_deselect(ha);
390
391 /* Enable protection register. */
392 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
393 qla2x00_nv_write(ha, NVR_PR_ENABLE);
394 qla2x00_nv_write(ha, NVR_PR_ENABLE);
395 for (word = 0; word < 8; word++)
396 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
397
398 qla2x00_nv_deselect(ha);
399
400 /* Enable protection register. */
401 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
402 qla2x00_nv_write(ha, NVR_PR_ENABLE);
403 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
404 for (word = 0; word < 8; word++)
405 qla2x00_nv_write(ha, NVR_PR_ENABLE);
406
407 qla2x00_nv_deselect(ha);
408
409 /* Wait for NVRAM to become ready. */
410 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
411 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
412 wait_cnt = NVR_WAIT_CNT;
413 do {
414 if (!--wait_cnt) {
415 DEBUG9_10(printk("%s(%ld): NVRAM didn't go ready...\n",
416 __func__, ha->host_no));
417 break;
418 }
419 NVRAM_DELAY();
420 word = RD_REG_WORD(&reg->nvram);
421 } while ((word & NVR_DATA_IN) == 0);
422 }
423
424
425 /*****************************************************************************/
426 /* Flash Manipulation Routines */
427 /*****************************************************************************/
428
429 #define OPTROM_BURST_SIZE 0x1000
430 #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
431
432 static inline uint32_t
433 flash_conf_to_access_addr(uint32_t faddr)
434 {
435 return FARX_ACCESS_FLASH_CONF | faddr;
436 }
437
438 static inline uint32_t
439 flash_data_to_access_addr(uint32_t faddr)
440 {
441 return FARX_ACCESS_FLASH_DATA | faddr;
442 }
443
444 static inline uint32_t
445 nvram_conf_to_access_addr(uint32_t naddr)
446 {
447 return FARX_ACCESS_NVRAM_CONF | naddr;
448 }
449
450 static inline uint32_t
451 nvram_data_to_access_addr(uint32_t naddr)
452 {
453 return FARX_ACCESS_NVRAM_DATA | naddr;
454 }
455
456 static uint32_t
457 qla24xx_read_flash_dword(scsi_qla_host_t *ha, uint32_t addr)
458 {
459 int rval;
460 uint32_t cnt, data;
461 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
462
463 WRT_REG_DWORD(&reg->flash_addr, addr & ~FARX_DATA_FLAG);
464 /* Wait for READ cycle to complete. */
465 rval = QLA_SUCCESS;
466 for (cnt = 3000;
467 (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) == 0 &&
468 rval == QLA_SUCCESS; cnt--) {
469 if (cnt)
470 udelay(10);
471 else
472 rval = QLA_FUNCTION_TIMEOUT;
473 cond_resched();
474 }
475
476 /* TODO: What happens if we time out? */
477 data = 0xDEADDEAD;
478 if (rval == QLA_SUCCESS)
479 data = RD_REG_DWORD(&reg->flash_data);
480
481 return data;
482 }
483
484 uint32_t *
485 qla24xx_read_flash_data(scsi_qla_host_t *ha, uint32_t *dwptr, uint32_t faddr,
486 uint32_t dwords)
487 {
488 uint32_t i;
489
490 /* Dword reads to flash. */
491 for (i = 0; i < dwords; i++, faddr++)
492 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
493 flash_data_to_access_addr(faddr)));
494
495 return dwptr;
496 }
497
498 static int
499 qla24xx_write_flash_dword(scsi_qla_host_t *ha, uint32_t addr, uint32_t data)
500 {
501 int rval;
502 uint32_t cnt;
503 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
504
505 WRT_REG_DWORD(&reg->flash_data, data);
506 RD_REG_DWORD(&reg->flash_data); /* PCI Posting. */
507 WRT_REG_DWORD(&reg->flash_addr, addr | FARX_DATA_FLAG);
508 /* Wait for Write cycle to complete. */
509 rval = QLA_SUCCESS;
510 for (cnt = 500000; (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) &&
511 rval == QLA_SUCCESS; cnt--) {
512 if (cnt)
513 udelay(10);
514 else
515 rval = QLA_FUNCTION_TIMEOUT;
516 cond_resched();
517 }
518 return rval;
519 }
520
521 static void
522 qla24xx_get_flash_manufacturer(scsi_qla_host_t *ha, uint8_t *man_id,
523 uint8_t *flash_id)
524 {
525 uint32_t ids;
526
527 ids = qla24xx_read_flash_dword(ha, flash_data_to_access_addr(0xd03ab));
528 *man_id = LSB(ids);
529 *flash_id = MSB(ids);
530
531 /* Check if man_id and flash_id are valid. */
532 if (ids != 0xDEADDEAD && (*man_id == 0 || *flash_id == 0)) {
533 /* Read information using 0x9f opcode
534 * Device ID, Mfg ID would be read in the format:
535 * <Ext Dev Info><Device ID Part2><Device ID Part 1><Mfg ID>
536 * Example: ATMEL 0x00 01 45 1F
537 * Extract MFG and Dev ID from last two bytes.
538 */
539 ids = qla24xx_read_flash_dword(ha,
540 flash_data_to_access_addr(0xd009f));
541 *man_id = LSB(ids);
542 *flash_id = MSB(ids);
543 }
544 }
545
546 void
547 qla2xxx_get_flash_info(scsi_qla_host_t *ha)
548 {
549 #define FLASH_BLK_SIZE_32K 0x8000
550 #define FLASH_BLK_SIZE_64K 0x10000
551 uint16_t cnt, chksum;
552 uint16_t *wptr;
553 struct qla_fdt_layout *fdt;
554 uint8_t man_id, flash_id;
555
556 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha))
557 return;
558
559 wptr = (uint16_t *)ha->request_ring;
560 fdt = (struct qla_fdt_layout *)ha->request_ring;
561 ha->isp_ops->read_optrom(ha, (uint8_t *)ha->request_ring,
562 FA_FLASH_DESCR_ADDR << 2, OPTROM_BURST_SIZE);
563 if (*wptr == __constant_cpu_to_le16(0xffff))
564 goto no_flash_data;
565 if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' ||
566 fdt->sig[3] != 'D')
567 goto no_flash_data;
568
569 for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1;
570 cnt++)
571 chksum += le16_to_cpu(*wptr++);
572 if (chksum) {
573 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent FDT detected: "
574 "checksum=0x%x id=%c version=0x%x.\n", chksum, fdt->sig[0],
575 le16_to_cpu(fdt->version)));
576 DEBUG9(qla2x00_dump_buffer((uint8_t *)fdt, sizeof(*fdt)));
577 goto no_flash_data;
578 }
579
580 ha->fdt_odd_index = le16_to_cpu(fdt->man_id) == 0x1f;
581 ha->fdt_wrt_disable = fdt->wrt_disable_bits;
582 ha->fdt_erase_cmd = flash_conf_to_access_addr(0x0300 | fdt->erase_cmd);
583 ha->fdt_block_size = le32_to_cpu(fdt->block_size);
584 if (fdt->unprotect_sec_cmd) {
585 ha->fdt_unprotect_sec_cmd = flash_conf_to_access_addr(0x0300 |
586 fdt->unprotect_sec_cmd);
587 ha->fdt_protect_sec_cmd = fdt->protect_sec_cmd ?
588 flash_conf_to_access_addr(0x0300 | fdt->protect_sec_cmd):
589 flash_conf_to_access_addr(0x0336);
590 }
591
592 DEBUG2(qla_printk(KERN_DEBUG, ha, "Flash[FDT]: (0x%x/0x%x) erase=0x%x "
593 "pro=%x upro=%x idx=%d wrtd=0x%x blk=0x%x.\n",
594 le16_to_cpu(fdt->man_id), le16_to_cpu(fdt->id), ha->fdt_erase_cmd,
595 ha->fdt_protect_sec_cmd, ha->fdt_unprotect_sec_cmd,
596 ha->fdt_odd_index, ha->fdt_wrt_disable, ha->fdt_block_size));
597 return;
598
599 no_flash_data:
600 qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id);
601 ha->fdt_wrt_disable = 0x9c;
602 ha->fdt_erase_cmd = flash_conf_to_access_addr(0x03d8);
603 switch (man_id) {
604 case 0xbf: /* STT flash. */
605 if (flash_id == 0x8e)
606 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
607 else
608 ha->fdt_block_size = FLASH_BLK_SIZE_32K;
609
610 if (flash_id == 0x80)
611 ha->fdt_erase_cmd = flash_conf_to_access_addr(0x0352);
612 break;
613 case 0x13: /* ST M25P80. */
614 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
615 break;
616 case 0x1f: /* Atmel 26DF081A. */
617 ha->fdt_odd_index = 1;
618 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
619 ha->fdt_erase_cmd = flash_conf_to_access_addr(0x0320);
620 ha->fdt_unprotect_sec_cmd = flash_conf_to_access_addr(0x0339);
621 ha->fdt_protect_sec_cmd = flash_conf_to_access_addr(0x0336);
622 break;
623 default:
624 /* Default to 64 kb sector size. */
625 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
626 break;
627 }
628
629 DEBUG2(qla_printk(KERN_DEBUG, ha, "Flash[MID]: (0x%x/0x%x) erase=0x%x "
630 "pro=%x upro=%x idx=%d wrtd=0x%x blk=0x%x.\n", man_id, flash_id,
631 ha->fdt_erase_cmd, ha->fdt_protect_sec_cmd,
632 ha->fdt_unprotect_sec_cmd, ha->fdt_odd_index, ha->fdt_wrt_disable,
633 ha->fdt_block_size));
634 }
635
636 static void
637 qla24xx_unprotect_flash(scsi_qla_host_t *ha)
638 {
639 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
640
641 /* Enable flash write. */
642 WRT_REG_DWORD(&reg->ctrl_status,
643 RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
644 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
645
646 if (!ha->fdt_wrt_disable)
647 return;
648
649 /* Disable flash write-protection. */
650 qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0);
651 /* Some flash parts need an additional zero-write to clear bits.*/
652 qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0);
653 }
654
655 static void
656 qla24xx_protect_flash(scsi_qla_host_t *ha)
657 {
658 uint32_t cnt;
659 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
660
661 if (!ha->fdt_wrt_disable)
662 goto skip_wrt_protect;
663
664 /* Enable flash write-protection and wait for completion. */
665 qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101),
666 ha->fdt_wrt_disable);
667 for (cnt = 300; cnt &&
668 qla24xx_read_flash_dword(ha,
669 flash_conf_to_access_addr(0x005)) & BIT_0;
670 cnt--) {
671 udelay(10);
672 }
673
674 skip_wrt_protect:
675 /* Disable flash write. */
676 WRT_REG_DWORD(&reg->ctrl_status,
677 RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
678 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
679 }
680
681 static int
682 qla24xx_write_flash_data(scsi_qla_host_t *ha, uint32_t *dwptr, uint32_t faddr,
683 uint32_t dwords)
684 {
685 int ret;
686 uint32_t liter, miter;
687 uint32_t sec_mask, rest_addr;
688 uint32_t fdata, findex;
689 dma_addr_t optrom_dma;
690 void *optrom = NULL;
691 uint32_t *s, *d;
692
693 ret = QLA_SUCCESS;
694
695 /* Prepare burst-capable write on supported ISPs. */
696 if (IS_QLA25XX(ha) && !(faddr & 0xfff) &&
697 dwords > OPTROM_BURST_DWORDS) {
698 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
699 &optrom_dma, GFP_KERNEL);
700 if (!optrom) {
701 qla_printk(KERN_DEBUG, ha,
702 "Unable to allocate memory for optrom burst write "
703 "(%x KB).\n", OPTROM_BURST_SIZE / 1024);
704 }
705 }
706
707 rest_addr = (ha->fdt_block_size >> 2) - 1;
708 sec_mask = 0x80000 - (ha->fdt_block_size >> 2);
709
710 qla24xx_unprotect_flash(ha);
711
712 for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) {
713 if (ha->fdt_odd_index) {
714 findex = faddr << 2;
715 fdata = findex & sec_mask;
716 } else {
717 findex = faddr;
718 fdata = (findex & sec_mask) << 2;
719 }
720
721 /* Are we at the beginning of a sector? */
722 if ((findex & rest_addr) == 0) {
723 /* Do sector unprotect. */
724 if (ha->fdt_unprotect_sec_cmd)
725 qla24xx_write_flash_dword(ha,
726 ha->fdt_unprotect_sec_cmd,
727 (fdata & 0xff00) | ((fdata << 16) &
728 0xff0000) | ((fdata >> 16) & 0xff));
729 ret = qla24xx_write_flash_dword(ha, ha->fdt_erase_cmd,
730 (fdata & 0xff00) |((fdata << 16) &
731 0xff0000) | ((fdata >> 16) & 0xff));
732 if (ret != QLA_SUCCESS) {
733 DEBUG9(printk("%s(%ld) Unable to flash "
734 "sector: address=%x.\n", __func__,
735 ha->host_no, faddr));
736 break;
737 }
738 }
739
740 /* Go with burst-write. */
741 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) {
742 /* Copy data to DMA'ble buffer. */
743 for (miter = 0, s = optrom, d = dwptr;
744 miter < OPTROM_BURST_DWORDS; miter++, s++, d++)
745 *s = cpu_to_le32(*d);
746
747 ret = qla2x00_load_ram(ha, optrom_dma,
748 flash_data_to_access_addr(faddr),
749 OPTROM_BURST_DWORDS);
750 if (ret != QLA_SUCCESS) {
751 qla_printk(KERN_WARNING, ha,
752 "Unable to burst-write optrom segment "
753 "(%x/%x/%llx).\n", ret,
754 flash_data_to_access_addr(faddr),
755 (unsigned long long)optrom_dma);
756 qla_printk(KERN_WARNING, ha,
757 "Reverting to slow-write.\n");
758
759 dma_free_coherent(&ha->pdev->dev,
760 OPTROM_BURST_SIZE, optrom, optrom_dma);
761 optrom = NULL;
762 } else {
763 liter += OPTROM_BURST_DWORDS - 1;
764 faddr += OPTROM_BURST_DWORDS - 1;
765 dwptr += OPTROM_BURST_DWORDS - 1;
766 continue;
767 }
768 }
769
770 ret = qla24xx_write_flash_dword(ha,
771 flash_data_to_access_addr(faddr), cpu_to_le32(*dwptr));
772 if (ret != QLA_SUCCESS) {
773 DEBUG9(printk("%s(%ld) Unable to program flash "
774 "address=%x data=%x.\n", __func__,
775 ha->host_no, faddr, *dwptr));
776 break;
777 }
778
779 /* Do sector protect. */
780 if (ha->fdt_unprotect_sec_cmd &&
781 ((faddr & rest_addr) == rest_addr))
782 qla24xx_write_flash_dword(ha,
783 ha->fdt_protect_sec_cmd,
784 (fdata & 0xff00) | ((fdata << 16) &
785 0xff0000) | ((fdata >> 16) & 0xff));
786 }
787
788 qla24xx_protect_flash(ha);
789
790 if (optrom)
791 dma_free_coherent(&ha->pdev->dev,
792 OPTROM_BURST_SIZE, optrom, optrom_dma);
793
794 return ret;
795 }
796
797 uint8_t *
798 qla2x00_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
799 uint32_t bytes)
800 {
801 uint32_t i;
802 uint16_t *wptr;
803
804 /* Word reads to NVRAM via registers. */
805 wptr = (uint16_t *)buf;
806 qla2x00_lock_nvram_access(ha);
807 for (i = 0; i < bytes >> 1; i++, naddr++)
808 wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha,
809 naddr));
810 qla2x00_unlock_nvram_access(ha);
811
812 return buf;
813 }
814
815 uint8_t *
816 qla24xx_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
817 uint32_t bytes)
818 {
819 uint32_t i;
820 uint32_t *dwptr;
821
822 /* Dword reads to flash. */
823 dwptr = (uint32_t *)buf;
824 for (i = 0; i < bytes >> 2; i++, naddr++)
825 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
826 nvram_data_to_access_addr(naddr)));
827
828 return buf;
829 }
830
831 int
832 qla2x00_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
833 uint32_t bytes)
834 {
835 int ret, stat;
836 uint32_t i;
837 uint16_t *wptr;
838 unsigned long flags;
839
840 ret = QLA_SUCCESS;
841
842 spin_lock_irqsave(&ha->hardware_lock, flags);
843 qla2x00_lock_nvram_access(ha);
844
845 /* Disable NVRAM write-protection. */
846 stat = qla2x00_clear_nvram_protection(ha);
847
848 wptr = (uint16_t *)buf;
849 for (i = 0; i < bytes >> 1; i++, naddr++) {
850 qla2x00_write_nvram_word(ha, naddr,
851 cpu_to_le16(*wptr));
852 wptr++;
853 }
854
855 /* Enable NVRAM write-protection. */
856 qla2x00_set_nvram_protection(ha, stat);
857
858 qla2x00_unlock_nvram_access(ha);
859 spin_unlock_irqrestore(&ha->hardware_lock, flags);
860
861 return ret;
862 }
863
864 int
865 qla24xx_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
866 uint32_t bytes)
867 {
868 int ret;
869 uint32_t i;
870 uint32_t *dwptr;
871 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
872 unsigned long flags;
873
874 ret = QLA_SUCCESS;
875
876 spin_lock_irqsave(&ha->hardware_lock, flags);
877 /* Enable flash write. */
878 WRT_REG_DWORD(&reg->ctrl_status,
879 RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
880 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
881
882 /* Disable NVRAM write-protection. */
883 qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
884 0);
885 qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
886 0);
887
888 /* Dword writes to flash. */
889 dwptr = (uint32_t *)buf;
890 for (i = 0; i < bytes >> 2; i++, naddr++, dwptr++) {
891 ret = qla24xx_write_flash_dword(ha,
892 nvram_data_to_access_addr(naddr),
893 cpu_to_le32(*dwptr));
894 if (ret != QLA_SUCCESS) {
895 DEBUG9(printk("%s(%ld) Unable to program "
896 "nvram address=%x data=%x.\n", __func__,
897 ha->host_no, naddr, *dwptr));
898 break;
899 }
900 }
901
902 /* Enable NVRAM write-protection. */
903 qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
904 0x8c);
905
906 /* Disable flash write. */
907 WRT_REG_DWORD(&reg->ctrl_status,
908 RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
909 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
910 spin_unlock_irqrestore(&ha->hardware_lock, flags);
911
912 return ret;
913 }
914
915 uint8_t *
916 qla25xx_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
917 uint32_t bytes)
918 {
919 uint32_t i;
920 uint32_t *dwptr;
921
922 /* Dword reads to flash. */
923 dwptr = (uint32_t *)buf;
924 for (i = 0; i < bytes >> 2; i++, naddr++)
925 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
926 flash_data_to_access_addr(FA_VPD_NVRAM_ADDR | naddr)));
927
928 return buf;
929 }
930
931 int
932 qla25xx_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
933 uint32_t bytes)
934 {
935 #define RMW_BUFFER_SIZE (64 * 1024)
936 uint8_t *dbuf;
937
938 dbuf = vmalloc(RMW_BUFFER_SIZE);
939 if (!dbuf)
940 return QLA_MEMORY_ALLOC_FAILED;
941 ha->isp_ops->read_optrom(ha, dbuf, FA_VPD_NVRAM_ADDR << 2,
942 RMW_BUFFER_SIZE);
943 memcpy(dbuf + (naddr << 2), buf, bytes);
944 ha->isp_ops->write_optrom(ha, dbuf, FA_VPD_NVRAM_ADDR << 2,
945 RMW_BUFFER_SIZE);
946 vfree(dbuf);
947
948 return QLA_SUCCESS;
949 }
950
951 static inline void
952 qla2x00_flip_colors(scsi_qla_host_t *ha, uint16_t *pflags)
953 {
954 if (IS_QLA2322(ha)) {
955 /* Flip all colors. */
956 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
957 /* Turn off. */
958 ha->beacon_color_state = 0;
959 *pflags = GPIO_LED_ALL_OFF;
960 } else {
961 /* Turn on. */
962 ha->beacon_color_state = QLA_LED_ALL_ON;
963 *pflags = GPIO_LED_RGA_ON;
964 }
965 } else {
966 /* Flip green led only. */
967 if (ha->beacon_color_state == QLA_LED_GRN_ON) {
968 /* Turn off. */
969 ha->beacon_color_state = 0;
970 *pflags = GPIO_LED_GREEN_OFF_AMBER_OFF;
971 } else {
972 /* Turn on. */
973 ha->beacon_color_state = QLA_LED_GRN_ON;
974 *pflags = GPIO_LED_GREEN_ON_AMBER_OFF;
975 }
976 }
977 }
978
979 #define PIO_REG(h, r) ((h)->pio_address + offsetof(struct device_reg_2xxx, r))
980
981 void
982 qla2x00_beacon_blink(struct scsi_qla_host *ha)
983 {
984 uint16_t gpio_enable;
985 uint16_t gpio_data;
986 uint16_t led_color = 0;
987 unsigned long flags;
988 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
989
990 spin_lock_irqsave(&ha->hardware_lock, flags);
991
992 /* Save the Original GPIOE. */
993 if (ha->pio_address) {
994 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
995 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
996 } else {
997 gpio_enable = RD_REG_WORD(&reg->gpioe);
998 gpio_data = RD_REG_WORD(&reg->gpiod);
999 }
1000
1001 /* Set the modified gpio_enable values */
1002 gpio_enable |= GPIO_LED_MASK;
1003
1004 if (ha->pio_address) {
1005 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
1006 } else {
1007 WRT_REG_WORD(&reg->gpioe, gpio_enable);
1008 RD_REG_WORD(&reg->gpioe);
1009 }
1010
1011 qla2x00_flip_colors(ha, &led_color);
1012
1013 /* Clear out any previously set LED color. */
1014 gpio_data &= ~GPIO_LED_MASK;
1015
1016 /* Set the new input LED color to GPIOD. */
1017 gpio_data |= led_color;
1018
1019 /* Set the modified gpio_data values */
1020 if (ha->pio_address) {
1021 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
1022 } else {
1023 WRT_REG_WORD(&reg->gpiod, gpio_data);
1024 RD_REG_WORD(&reg->gpiod);
1025 }
1026
1027 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1028 }
1029
1030 int
1031 qla2x00_beacon_on(struct scsi_qla_host *ha)
1032 {
1033 uint16_t gpio_enable;
1034 uint16_t gpio_data;
1035 unsigned long flags;
1036 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1037
1038 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1039 ha->fw_options[1] |= FO1_DISABLE_GPIO6_7;
1040
1041 if (qla2x00_set_fw_options(ha, ha->fw_options) != QLA_SUCCESS) {
1042 qla_printk(KERN_WARNING, ha,
1043 "Unable to update fw options (beacon on).\n");
1044 return QLA_FUNCTION_FAILED;
1045 }
1046
1047 /* Turn off LEDs. */
1048 spin_lock_irqsave(&ha->hardware_lock, flags);
1049 if (ha->pio_address) {
1050 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1051 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
1052 } else {
1053 gpio_enable = RD_REG_WORD(&reg->gpioe);
1054 gpio_data = RD_REG_WORD(&reg->gpiod);
1055 }
1056 gpio_enable |= GPIO_LED_MASK;
1057
1058 /* Set the modified gpio_enable values. */
1059 if (ha->pio_address) {
1060 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
1061 } else {
1062 WRT_REG_WORD(&reg->gpioe, gpio_enable);
1063 RD_REG_WORD(&reg->gpioe);
1064 }
1065
1066 /* Clear out previously set LED colour. */
1067 gpio_data &= ~GPIO_LED_MASK;
1068 if (ha->pio_address) {
1069 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
1070 } else {
1071 WRT_REG_WORD(&reg->gpiod, gpio_data);
1072 RD_REG_WORD(&reg->gpiod);
1073 }
1074 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1075
1076 /*
1077 * Let the per HBA timer kick off the blinking process based on
1078 * the following flags. No need to do anything else now.
1079 */
1080 ha->beacon_blink_led = 1;
1081 ha->beacon_color_state = 0;
1082
1083 return QLA_SUCCESS;
1084 }
1085
1086 int
1087 qla2x00_beacon_off(struct scsi_qla_host *ha)
1088 {
1089 int rval = QLA_SUCCESS;
1090
1091 ha->beacon_blink_led = 0;
1092
1093 /* Set the on flag so when it gets flipped it will be off. */
1094 if (IS_QLA2322(ha))
1095 ha->beacon_color_state = QLA_LED_ALL_ON;
1096 else
1097 ha->beacon_color_state = QLA_LED_GRN_ON;
1098
1099 ha->isp_ops->beacon_blink(ha); /* This turns green LED off */
1100
1101 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1102 ha->fw_options[1] &= ~FO1_DISABLE_GPIO6_7;
1103
1104 rval = qla2x00_set_fw_options(ha, ha->fw_options);
1105 if (rval != QLA_SUCCESS)
1106 qla_printk(KERN_WARNING, ha,
1107 "Unable to update fw options (beacon off).\n");
1108 return rval;
1109 }
1110
1111
1112 static inline void
1113 qla24xx_flip_colors(scsi_qla_host_t *ha, uint16_t *pflags)
1114 {
1115 /* Flip all colors. */
1116 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1117 /* Turn off. */
1118 ha->beacon_color_state = 0;
1119 *pflags = 0;
1120 } else {
1121 /* Turn on. */
1122 ha->beacon_color_state = QLA_LED_ALL_ON;
1123 *pflags = GPDX_LED_YELLOW_ON | GPDX_LED_AMBER_ON;
1124 }
1125 }
1126
1127 void
1128 qla24xx_beacon_blink(struct scsi_qla_host *ha)
1129 {
1130 uint16_t led_color = 0;
1131 uint32_t gpio_data;
1132 unsigned long flags;
1133 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1134
1135 /* Save the Original GPIOD. */
1136 spin_lock_irqsave(&ha->hardware_lock, flags);
1137 gpio_data = RD_REG_DWORD(&reg->gpiod);
1138
1139 /* Enable the gpio_data reg for update. */
1140 gpio_data |= GPDX_LED_UPDATE_MASK;
1141
1142 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1143 gpio_data = RD_REG_DWORD(&reg->gpiod);
1144
1145 /* Set the color bits. */
1146 qla24xx_flip_colors(ha, &led_color);
1147
1148 /* Clear out any previously set LED color. */
1149 gpio_data &= ~GPDX_LED_COLOR_MASK;
1150
1151 /* Set the new input LED color to GPIOD. */
1152 gpio_data |= led_color;
1153
1154 /* Set the modified gpio_data values. */
1155 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1156 gpio_data = RD_REG_DWORD(&reg->gpiod);
1157 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1158 }
1159
1160 int
1161 qla24xx_beacon_on(struct scsi_qla_host *ha)
1162 {
1163 uint32_t gpio_data;
1164 unsigned long flags;
1165 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1166
1167 if (ha->beacon_blink_led == 0) {
1168 /* Enable firmware for update */
1169 ha->fw_options[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL;
1170
1171 if (qla2x00_set_fw_options(ha, ha->fw_options) != QLA_SUCCESS)
1172 return QLA_FUNCTION_FAILED;
1173
1174 if (qla2x00_get_fw_options(ha, ha->fw_options) !=
1175 QLA_SUCCESS) {
1176 qla_printk(KERN_WARNING, ha,
1177 "Unable to update fw options (beacon on).\n");
1178 return QLA_FUNCTION_FAILED;
1179 }
1180
1181 spin_lock_irqsave(&ha->hardware_lock, flags);
1182 gpio_data = RD_REG_DWORD(&reg->gpiod);
1183
1184 /* Enable the gpio_data reg for update. */
1185 gpio_data |= GPDX_LED_UPDATE_MASK;
1186 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1187 RD_REG_DWORD(&reg->gpiod);
1188
1189 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1190 }
1191
1192 /* So all colors blink together. */
1193 ha->beacon_color_state = 0;
1194
1195 /* Let the per HBA timer kick off the blinking process. */
1196 ha->beacon_blink_led = 1;
1197
1198 return QLA_SUCCESS;
1199 }
1200
1201 int
1202 qla24xx_beacon_off(struct scsi_qla_host *ha)
1203 {
1204 uint32_t gpio_data;
1205 unsigned long flags;
1206 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1207
1208 ha->beacon_blink_led = 0;
1209 ha->beacon_color_state = QLA_LED_ALL_ON;
1210
1211 ha->isp_ops->beacon_blink(ha); /* Will flip to all off. */
1212
1213 /* Give control back to firmware. */
1214 spin_lock_irqsave(&ha->hardware_lock, flags);
1215 gpio_data = RD_REG_DWORD(&reg->gpiod);
1216
1217 /* Disable the gpio_data reg for update. */
1218 gpio_data &= ~GPDX_LED_UPDATE_MASK;
1219 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1220 RD_REG_DWORD(&reg->gpiod);
1221 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1222
1223 ha->fw_options[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL;
1224
1225 if (qla2x00_set_fw_options(ha, ha->fw_options) != QLA_SUCCESS) {
1226 qla_printk(KERN_WARNING, ha,
1227 "Unable to update fw options (beacon off).\n");
1228 return QLA_FUNCTION_FAILED;
1229 }
1230
1231 if (qla2x00_get_fw_options(ha, ha->fw_options) != QLA_SUCCESS) {
1232 qla_printk(KERN_WARNING, ha,
1233 "Unable to get fw options (beacon off).\n");
1234 return QLA_FUNCTION_FAILED;
1235 }
1236
1237 return QLA_SUCCESS;
1238 }
1239
1240
1241 /*
1242 * Flash support routines
1243 */
1244
1245 /**
1246 * qla2x00_flash_enable() - Setup flash for reading and writing.
1247 * @ha: HA context
1248 */
1249 static void
1250 qla2x00_flash_enable(scsi_qla_host_t *ha)
1251 {
1252 uint16_t data;
1253 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1254
1255 data = RD_REG_WORD(&reg->ctrl_status);
1256 data |= CSR_FLASH_ENABLE;
1257 WRT_REG_WORD(&reg->ctrl_status, data);
1258 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1259 }
1260
1261 /**
1262 * qla2x00_flash_disable() - Disable flash and allow RISC to run.
1263 * @ha: HA context
1264 */
1265 static void
1266 qla2x00_flash_disable(scsi_qla_host_t *ha)
1267 {
1268 uint16_t data;
1269 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1270
1271 data = RD_REG_WORD(&reg->ctrl_status);
1272 data &= ~(CSR_FLASH_ENABLE);
1273 WRT_REG_WORD(&reg->ctrl_status, data);
1274 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1275 }
1276
1277 /**
1278 * qla2x00_read_flash_byte() - Reads a byte from flash
1279 * @ha: HA context
1280 * @addr: Address in flash to read
1281 *
1282 * A word is read from the chip, but, only the lower byte is valid.
1283 *
1284 * Returns the byte read from flash @addr.
1285 */
1286 static uint8_t
1287 qla2x00_read_flash_byte(scsi_qla_host_t *ha, uint32_t addr)
1288 {
1289 uint16_t data;
1290 uint16_t bank_select;
1291 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1292
1293 bank_select = RD_REG_WORD(&reg->ctrl_status);
1294
1295 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1296 /* Specify 64K address range: */
1297 /* clear out Module Select and Flash Address bits [19:16]. */
1298 bank_select &= ~0xf8;
1299 bank_select |= addr >> 12 & 0xf0;
1300 bank_select |= CSR_FLASH_64K_BANK;
1301 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1302 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1303
1304 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1305 data = RD_REG_WORD(&reg->flash_data);
1306
1307 return (uint8_t)data;
1308 }
1309
1310 /* Setup bit 16 of flash address. */
1311 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1312 bank_select |= CSR_FLASH_64K_BANK;
1313 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1314 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1315 } else if (((addr & BIT_16) == 0) &&
1316 (bank_select & CSR_FLASH_64K_BANK)) {
1317 bank_select &= ~(CSR_FLASH_64K_BANK);
1318 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1319 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1320 }
1321
1322 /* Always perform IO mapped accesses to the FLASH registers. */
1323 if (ha->pio_address) {
1324 uint16_t data2;
1325
1326 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
1327 do {
1328 data = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
1329 barrier();
1330 cpu_relax();
1331 data2 = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
1332 } while (data != data2);
1333 } else {
1334 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1335 data = qla2x00_debounce_register(&reg->flash_data);
1336 }
1337
1338 return (uint8_t)data;
1339 }
1340
1341 /**
1342 * qla2x00_write_flash_byte() - Write a byte to flash
1343 * @ha: HA context
1344 * @addr: Address in flash to write
1345 * @data: Data to write
1346 */
1347 static void
1348 qla2x00_write_flash_byte(scsi_qla_host_t *ha, uint32_t addr, uint8_t data)
1349 {
1350 uint16_t bank_select;
1351 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1352
1353 bank_select = RD_REG_WORD(&reg->ctrl_status);
1354 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1355 /* Specify 64K address range: */
1356 /* clear out Module Select and Flash Address bits [19:16]. */
1357 bank_select &= ~0xf8;
1358 bank_select |= addr >> 12 & 0xf0;
1359 bank_select |= CSR_FLASH_64K_BANK;
1360 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1361 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1362
1363 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1364 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1365 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
1366 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1367
1368 return;
1369 }
1370
1371 /* Setup bit 16 of flash address. */
1372 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1373 bank_select |= CSR_FLASH_64K_BANK;
1374 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1375 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1376 } else if (((addr & BIT_16) == 0) &&
1377 (bank_select & CSR_FLASH_64K_BANK)) {
1378 bank_select &= ~(CSR_FLASH_64K_BANK);
1379 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1380 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1381 }
1382
1383 /* Always perform IO mapped accesses to the FLASH registers. */
1384 if (ha->pio_address) {
1385 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
1386 WRT_REG_WORD_PIO(PIO_REG(ha, flash_data), (uint16_t)data);
1387 } else {
1388 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1389 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1390 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
1391 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1392 }
1393 }
1394
1395 /**
1396 * qla2x00_poll_flash() - Polls flash for completion.
1397 * @ha: HA context
1398 * @addr: Address in flash to poll
1399 * @poll_data: Data to be polled
1400 * @man_id: Flash manufacturer ID
1401 * @flash_id: Flash ID
1402 *
1403 * This function polls the device until bit 7 of what is read matches data
1404 * bit 7 or until data bit 5 becomes a 1. If that hapens, the flash ROM timed
1405 * out (a fatal error). The flash book recommeds reading bit 7 again after
1406 * reading bit 5 as a 1.
1407 *
1408 * Returns 0 on success, else non-zero.
1409 */
1410 static int
1411 qla2x00_poll_flash(scsi_qla_host_t *ha, uint32_t addr, uint8_t poll_data,
1412 uint8_t man_id, uint8_t flash_id)
1413 {
1414 int status;
1415 uint8_t flash_data;
1416 uint32_t cnt;
1417
1418 status = 1;
1419
1420 /* Wait for 30 seconds for command to finish. */
1421 poll_data &= BIT_7;
1422 for (cnt = 3000000; cnt; cnt--) {
1423 flash_data = qla2x00_read_flash_byte(ha, addr);
1424 if ((flash_data & BIT_7) == poll_data) {
1425 status = 0;
1426 break;
1427 }
1428
1429 if (man_id != 0x40 && man_id != 0xda) {
1430 if ((flash_data & BIT_5) && cnt > 2)
1431 cnt = 2;
1432 }
1433 udelay(10);
1434 barrier();
1435 cond_resched();
1436 }
1437 return status;
1438 }
1439
1440 /**
1441 * qla2x00_program_flash_address() - Programs a flash address
1442 * @ha: HA context
1443 * @addr: Address in flash to program
1444 * @data: Data to be written in flash
1445 * @man_id: Flash manufacturer ID
1446 * @flash_id: Flash ID
1447 *
1448 * Returns 0 on success, else non-zero.
1449 */
1450 static int
1451 qla2x00_program_flash_address(scsi_qla_host_t *ha, uint32_t addr, uint8_t data,
1452 uint8_t man_id, uint8_t flash_id)
1453 {
1454 /* Write Program Command Sequence. */
1455 if (IS_OEM_001(ha)) {
1456 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1457 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1458 qla2x00_write_flash_byte(ha, 0xaaa, 0xa0);
1459 qla2x00_write_flash_byte(ha, addr, data);
1460 } else {
1461 if (man_id == 0xda && flash_id == 0xc1) {
1462 qla2x00_write_flash_byte(ha, addr, data);
1463 if (addr & 0x7e)
1464 return 0;
1465 } else {
1466 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1467 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1468 qla2x00_write_flash_byte(ha, 0x5555, 0xa0);
1469 qla2x00_write_flash_byte(ha, addr, data);
1470 }
1471 }
1472
1473 udelay(150);
1474
1475 /* Wait for write to complete. */
1476 return qla2x00_poll_flash(ha, addr, data, man_id, flash_id);
1477 }
1478
1479 /**
1480 * qla2x00_erase_flash() - Erase the flash.
1481 * @ha: HA context
1482 * @man_id: Flash manufacturer ID
1483 * @flash_id: Flash ID
1484 *
1485 * Returns 0 on success, else non-zero.
1486 */
1487 static int
1488 qla2x00_erase_flash(scsi_qla_host_t *ha, uint8_t man_id, uint8_t flash_id)
1489 {
1490 /* Individual Sector Erase Command Sequence */
1491 if (IS_OEM_001(ha)) {
1492 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1493 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1494 qla2x00_write_flash_byte(ha, 0xaaa, 0x80);
1495 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1496 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1497 qla2x00_write_flash_byte(ha, 0xaaa, 0x10);
1498 } else {
1499 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1500 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1501 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
1502 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1503 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1504 qla2x00_write_flash_byte(ha, 0x5555, 0x10);
1505 }
1506
1507 udelay(150);
1508
1509 /* Wait for erase to complete. */
1510 return qla2x00_poll_flash(ha, 0x00, 0x80, man_id, flash_id);
1511 }
1512
1513 /**
1514 * qla2x00_erase_flash_sector() - Erase a flash sector.
1515 * @ha: HA context
1516 * @addr: Flash sector to erase
1517 * @sec_mask: Sector address mask
1518 * @man_id: Flash manufacturer ID
1519 * @flash_id: Flash ID
1520 *
1521 * Returns 0 on success, else non-zero.
1522 */
1523 static int
1524 qla2x00_erase_flash_sector(scsi_qla_host_t *ha, uint32_t addr,
1525 uint32_t sec_mask, uint8_t man_id, uint8_t flash_id)
1526 {
1527 /* Individual Sector Erase Command Sequence */
1528 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1529 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1530 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
1531 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1532 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1533 if (man_id == 0x1f && flash_id == 0x13)
1534 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x10);
1535 else
1536 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x30);
1537
1538 udelay(150);
1539
1540 /* Wait for erase to complete. */
1541 return qla2x00_poll_flash(ha, addr, 0x80, man_id, flash_id);
1542 }
1543
1544 /**
1545 * qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip.
1546 * @man_id: Flash manufacturer ID
1547 * @flash_id: Flash ID
1548 */
1549 static void
1550 qla2x00_get_flash_manufacturer(scsi_qla_host_t *ha, uint8_t *man_id,
1551 uint8_t *flash_id)
1552 {
1553 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1554 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1555 qla2x00_write_flash_byte(ha, 0x5555, 0x90);
1556 *man_id = qla2x00_read_flash_byte(ha, 0x0000);
1557 *flash_id = qla2x00_read_flash_byte(ha, 0x0001);
1558 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1559 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1560 qla2x00_write_flash_byte(ha, 0x5555, 0xf0);
1561 }
1562
1563 static void
1564 qla2x00_read_flash_data(scsi_qla_host_t *ha, uint8_t *tmp_buf, uint32_t saddr,
1565 uint32_t length)
1566 {
1567 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1568 uint32_t midpoint, ilength;
1569 uint8_t data;
1570
1571 midpoint = length / 2;
1572
1573 WRT_REG_WORD(&reg->nvram, 0);
1574 RD_REG_WORD(&reg->nvram);
1575 for (ilength = 0; ilength < length; saddr++, ilength++, tmp_buf++) {
1576 if (ilength == midpoint) {
1577 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
1578 RD_REG_WORD(&reg->nvram);
1579 }
1580 data = qla2x00_read_flash_byte(ha, saddr);
1581 if (saddr % 100)
1582 udelay(10);
1583 *tmp_buf = data;
1584 cond_resched();
1585 }
1586 }
1587
1588 static inline void
1589 qla2x00_suspend_hba(struct scsi_qla_host *ha)
1590 {
1591 int cnt;
1592 unsigned long flags;
1593 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1594
1595 /* Suspend HBA. */
1596 scsi_block_requests(ha->host);
1597 ha->isp_ops->disable_intrs(ha);
1598 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1599
1600 /* Pause RISC. */
1601 spin_lock_irqsave(&ha->hardware_lock, flags);
1602 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
1603 RD_REG_WORD(&reg->hccr);
1604 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1605 for (cnt = 0; cnt < 30000; cnt++) {
1606 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
1607 break;
1608 udelay(100);
1609 }
1610 } else {
1611 udelay(10);
1612 }
1613 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1614 }
1615
1616 static inline void
1617 qla2x00_resume_hba(struct scsi_qla_host *ha)
1618 {
1619 /* Resume HBA. */
1620 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1621 set_bit(ISP_ABORT_NEEDED, &ha->dpc_flags);
1622 qla2xxx_wake_dpc(ha);
1623 qla2x00_wait_for_hba_online(ha);
1624 scsi_unblock_requests(ha->host);
1625 }
1626
1627 uint8_t *
1628 qla2x00_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
1629 uint32_t offset, uint32_t length)
1630 {
1631 uint32_t addr, midpoint;
1632 uint8_t *data;
1633 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1634
1635 /* Suspend HBA. */
1636 qla2x00_suspend_hba(ha);
1637
1638 /* Go with read. */
1639 midpoint = ha->optrom_size / 2;
1640
1641 qla2x00_flash_enable(ha);
1642 WRT_REG_WORD(&reg->nvram, 0);
1643 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
1644 for (addr = offset, data = buf; addr < length; addr++, data++) {
1645 if (addr == midpoint) {
1646 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
1647 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
1648 }
1649
1650 *data = qla2x00_read_flash_byte(ha, addr);
1651 }
1652 qla2x00_flash_disable(ha);
1653
1654 /* Resume HBA. */
1655 qla2x00_resume_hba(ha);
1656
1657 return buf;
1658 }
1659
1660 int
1661 qla2x00_write_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
1662 uint32_t offset, uint32_t length)
1663 {
1664
1665 int rval;
1666 uint8_t man_id, flash_id, sec_number, data;
1667 uint16_t wd;
1668 uint32_t addr, liter, sec_mask, rest_addr;
1669 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1670
1671 /* Suspend HBA. */
1672 qla2x00_suspend_hba(ha);
1673
1674 rval = QLA_SUCCESS;
1675 sec_number = 0;
1676
1677 /* Reset ISP chip. */
1678 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
1679 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
1680
1681 /* Go with write. */
1682 qla2x00_flash_enable(ha);
1683 do { /* Loop once to provide quick error exit */
1684 /* Structure of flash memory based on manufacturer */
1685 if (IS_OEM_001(ha)) {
1686 /* OEM variant with special flash part. */
1687 man_id = flash_id = 0;
1688 rest_addr = 0xffff;
1689 sec_mask = 0x10000;
1690 goto update_flash;
1691 }
1692 qla2x00_get_flash_manufacturer(ha, &man_id, &flash_id);
1693 switch (man_id) {
1694 case 0x20: /* ST flash. */
1695 if (flash_id == 0xd2 || flash_id == 0xe3) {
1696 /*
1697 * ST m29w008at part - 64kb sector size with
1698 * 32kb,8kb,8kb,16kb sectors at memory address
1699 * 0xf0000.
1700 */
1701 rest_addr = 0xffff;
1702 sec_mask = 0x10000;
1703 break;
1704 }
1705 /*
1706 * ST m29w010b part - 16kb sector size
1707 * Default to 16kb sectors
1708 */
1709 rest_addr = 0x3fff;
1710 sec_mask = 0x1c000;
1711 break;
1712 case 0x40: /* Mostel flash. */
1713 /* Mostel v29c51001 part - 512 byte sector size. */
1714 rest_addr = 0x1ff;
1715 sec_mask = 0x1fe00;
1716 break;
1717 case 0xbf: /* SST flash. */
1718 /* SST39sf10 part - 4kb sector size. */
1719 rest_addr = 0xfff;
1720 sec_mask = 0x1f000;
1721 break;
1722 case 0xda: /* Winbond flash. */
1723 /* Winbond W29EE011 part - 256 byte sector size. */
1724 rest_addr = 0x7f;
1725 sec_mask = 0x1ff80;
1726 break;
1727 case 0xc2: /* Macronix flash. */
1728 /* 64k sector size. */
1729 if (flash_id == 0x38 || flash_id == 0x4f) {
1730 rest_addr = 0xffff;
1731 sec_mask = 0x10000;
1732 break;
1733 }
1734 /* Fall through... */
1735
1736 case 0x1f: /* Atmel flash. */
1737 /* 512k sector size. */
1738 if (flash_id == 0x13) {
1739 rest_addr = 0x7fffffff;
1740 sec_mask = 0x80000000;
1741 break;
1742 }
1743 /* Fall through... */
1744
1745 case 0x01: /* AMD flash. */
1746 if (flash_id == 0x38 || flash_id == 0x40 ||
1747 flash_id == 0x4f) {
1748 /* Am29LV081 part - 64kb sector size. */
1749 /* Am29LV002BT part - 64kb sector size. */
1750 rest_addr = 0xffff;
1751 sec_mask = 0x10000;
1752 break;
1753 } else if (flash_id == 0x3e) {
1754 /*
1755 * Am29LV008b part - 64kb sector size with
1756 * 32kb,8kb,8kb,16kb sector at memory address
1757 * h0xf0000.
1758 */
1759 rest_addr = 0xffff;
1760 sec_mask = 0x10000;
1761 break;
1762 } else if (flash_id == 0x20 || flash_id == 0x6e) {
1763 /*
1764 * Am29LV010 part or AM29f010 - 16kb sector
1765 * size.
1766 */
1767 rest_addr = 0x3fff;
1768 sec_mask = 0x1c000;
1769 break;
1770 } else if (flash_id == 0x6d) {
1771 /* Am29LV001 part - 8kb sector size. */
1772 rest_addr = 0x1fff;
1773 sec_mask = 0x1e000;
1774 break;
1775 }
1776 default:
1777 /* Default to 16 kb sector size. */
1778 rest_addr = 0x3fff;
1779 sec_mask = 0x1c000;
1780 break;
1781 }
1782
1783 update_flash:
1784 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1785 if (qla2x00_erase_flash(ha, man_id, flash_id)) {
1786 rval = QLA_FUNCTION_FAILED;
1787 break;
1788 }
1789 }
1790
1791 for (addr = offset, liter = 0; liter < length; liter++,
1792 addr++) {
1793 data = buf[liter];
1794 /* Are we at the beginning of a sector? */
1795 if ((addr & rest_addr) == 0) {
1796 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1797 if (addr >= 0x10000UL) {
1798 if (((addr >> 12) & 0xf0) &&
1799 ((man_id == 0x01 &&
1800 flash_id == 0x3e) ||
1801 (man_id == 0x20 &&
1802 flash_id == 0xd2))) {
1803 sec_number++;
1804 if (sec_number == 1) {
1805 rest_addr =
1806 0x7fff;
1807 sec_mask =
1808 0x18000;
1809 } else if (
1810 sec_number == 2 ||
1811 sec_number == 3) {
1812 rest_addr =
1813 0x1fff;
1814 sec_mask =
1815 0x1e000;
1816 } else if (
1817 sec_number == 4) {
1818 rest_addr =
1819 0x3fff;
1820 sec_mask =
1821 0x1c000;
1822 }
1823 }
1824 }
1825 } else if (addr == ha->optrom_size / 2) {
1826 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
1827 RD_REG_WORD(&reg->nvram);
1828 }
1829
1830 if (flash_id == 0xda && man_id == 0xc1) {
1831 qla2x00_write_flash_byte(ha, 0x5555,
1832 0xaa);
1833 qla2x00_write_flash_byte(ha, 0x2aaa,
1834 0x55);
1835 qla2x00_write_flash_byte(ha, 0x5555,
1836 0xa0);
1837 } else if (!IS_QLA2322(ha) && !IS_QLA6322(ha)) {
1838 /* Then erase it */
1839 if (qla2x00_erase_flash_sector(ha,
1840 addr, sec_mask, man_id,
1841 flash_id)) {
1842 rval = QLA_FUNCTION_FAILED;
1843 break;
1844 }
1845 if (man_id == 0x01 && flash_id == 0x6d)
1846 sec_number++;
1847 }
1848 }
1849
1850 if (man_id == 0x01 && flash_id == 0x6d) {
1851 if (sec_number == 1 &&
1852 addr == (rest_addr - 1)) {
1853 rest_addr = 0x0fff;
1854 sec_mask = 0x1f000;
1855 } else if (sec_number == 3 && (addr & 0x7ffe)) {
1856 rest_addr = 0x3fff;
1857 sec_mask = 0x1c000;
1858 }
1859 }
1860
1861 if (qla2x00_program_flash_address(ha, addr, data,
1862 man_id, flash_id)) {
1863 rval = QLA_FUNCTION_FAILED;
1864 break;
1865 }
1866 cond_resched();
1867 }
1868 } while (0);
1869 qla2x00_flash_disable(ha);
1870
1871 /* Resume HBA. */
1872 qla2x00_resume_hba(ha);
1873
1874 return rval;
1875 }
1876
1877 uint8_t *
1878 qla24xx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
1879 uint32_t offset, uint32_t length)
1880 {
1881 /* Suspend HBA. */
1882 scsi_block_requests(ha->host);
1883 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1884
1885 /* Go with read. */
1886 qla24xx_read_flash_data(ha, (uint32_t *)buf, offset >> 2, length >> 2);
1887
1888 /* Resume HBA. */
1889 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1890 scsi_unblock_requests(ha->host);
1891
1892 return buf;
1893 }
1894
1895 int
1896 qla24xx_write_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
1897 uint32_t offset, uint32_t length)
1898 {
1899 int rval;
1900
1901 /* Suspend HBA. */
1902 scsi_block_requests(ha->host);
1903 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1904
1905 /* Go with write. */
1906 rval = qla24xx_write_flash_data(ha, (uint32_t *)buf, offset >> 2,
1907 length >> 2);
1908
1909 /* Resume HBA -- RISC reset needed. */
1910 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1911 set_bit(ISP_ABORT_NEEDED, &ha->dpc_flags);
1912 qla2xxx_wake_dpc(ha);
1913 qla2x00_wait_for_hba_online(ha);
1914 scsi_unblock_requests(ha->host);
1915
1916 return rval;
1917 }
1918
1919 uint8_t *
1920 qla25xx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
1921 uint32_t offset, uint32_t length)
1922 {
1923 int rval;
1924 dma_addr_t optrom_dma;
1925 void *optrom;
1926 uint8_t *pbuf;
1927 uint32_t faddr, left, burst;
1928
1929 if (offset & 0xfff)
1930 goto slow_read;
1931 if (length < OPTROM_BURST_SIZE)
1932 goto slow_read;
1933
1934 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
1935 &optrom_dma, GFP_KERNEL);
1936 if (!optrom) {
1937 qla_printk(KERN_DEBUG, ha,
1938 "Unable to allocate memory for optrom burst read "
1939 "(%x KB).\n", OPTROM_BURST_SIZE / 1024);
1940
1941 goto slow_read;
1942 }
1943
1944 pbuf = buf;
1945 faddr = offset >> 2;
1946 left = length >> 2;
1947 burst = OPTROM_BURST_DWORDS;
1948 while (left != 0) {
1949 if (burst > left)
1950 burst = left;
1951
1952 rval = qla2x00_dump_ram(ha, optrom_dma,
1953 flash_data_to_access_addr(faddr), burst);
1954 if (rval) {
1955 qla_printk(KERN_WARNING, ha,
1956 "Unable to burst-read optrom segment "
1957 "(%x/%x/%llx).\n", rval,
1958 flash_data_to_access_addr(faddr),
1959 (unsigned long long)optrom_dma);
1960 qla_printk(KERN_WARNING, ha,
1961 "Reverting to slow-read.\n");
1962
1963 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
1964 optrom, optrom_dma);
1965 goto slow_read;
1966 }
1967
1968 memcpy(pbuf, optrom, burst * 4);
1969
1970 left -= burst;
1971 faddr += burst;
1972 pbuf += burst * 4;
1973 }
1974
1975 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, optrom,
1976 optrom_dma);
1977
1978 return buf;
1979
1980 slow_read:
1981 return qla24xx_read_optrom_data(ha, buf, offset, length);
1982 }
1983
1984 /**
1985 * qla2x00_get_fcode_version() - Determine an FCODE image's version.
1986 * @ha: HA context
1987 * @pcids: Pointer to the FCODE PCI data structure
1988 *
1989 * The process of retrieving the FCODE version information is at best
1990 * described as interesting.
1991 *
1992 * Within the first 100h bytes of the image an ASCII string is present
1993 * which contains several pieces of information including the FCODE
1994 * version. Unfortunately it seems the only reliable way to retrieve
1995 * the version is by scanning for another sentinel within the string,
1996 * the FCODE build date:
1997 *
1998 * ... 2.00.02 10/17/02 ...
1999 *
2000 * Returns QLA_SUCCESS on successful retrieval of version.
2001 */
2002 static void
2003 qla2x00_get_fcode_version(scsi_qla_host_t *ha, uint32_t pcids)
2004 {
2005 int ret = QLA_FUNCTION_FAILED;
2006 uint32_t istart, iend, iter, vend;
2007 uint8_t do_next, rbyte, *vbyte;
2008
2009 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2010
2011 /* Skip the PCI data structure. */
2012 istart = pcids +
2013 ((qla2x00_read_flash_byte(ha, pcids + 0x0B) << 8) |
2014 qla2x00_read_flash_byte(ha, pcids + 0x0A));
2015 iend = istart + 0x100;
2016 do {
2017 /* Scan for the sentinel date string...eeewww. */
2018 do_next = 0;
2019 iter = istart;
2020 while ((iter < iend) && !do_next) {
2021 iter++;
2022 if (qla2x00_read_flash_byte(ha, iter) == '/') {
2023 if (qla2x00_read_flash_byte(ha, iter + 2) ==
2024 '/')
2025 do_next++;
2026 else if (qla2x00_read_flash_byte(ha,
2027 iter + 3) == '/')
2028 do_next++;
2029 }
2030 }
2031 if (!do_next)
2032 break;
2033
2034 /* Backtrack to previous ' ' (space). */
2035 do_next = 0;
2036 while ((iter > istart) && !do_next) {
2037 iter--;
2038 if (qla2x00_read_flash_byte(ha, iter) == ' ')
2039 do_next++;
2040 }
2041 if (!do_next)
2042 break;
2043
2044 /*
2045 * Mark end of version tag, and find previous ' ' (space) or
2046 * string length (recent FCODE images -- major hack ahead!!!).
2047 */
2048 vend = iter - 1;
2049 do_next = 0;
2050 while ((iter > istart) && !do_next) {
2051 iter--;
2052 rbyte = qla2x00_read_flash_byte(ha, iter);
2053 if (rbyte == ' ' || rbyte == 0xd || rbyte == 0x10)
2054 do_next++;
2055 }
2056 if (!do_next)
2057 break;
2058
2059 /* Mark beginning of version tag, and copy data. */
2060 iter++;
2061 if ((vend - iter) &&
2062 ((vend - iter) < sizeof(ha->fcode_revision))) {
2063 vbyte = ha->fcode_revision;
2064 while (iter <= vend) {
2065 *vbyte++ = qla2x00_read_flash_byte(ha, iter);
2066 iter++;
2067 }
2068 ret = QLA_SUCCESS;
2069 }
2070 } while (0);
2071
2072 if (ret != QLA_SUCCESS)
2073 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2074 }
2075
2076 int
2077 qla2x00_get_flash_version(scsi_qla_host_t *ha, void *mbuf)
2078 {
2079 int ret = QLA_SUCCESS;
2080 uint8_t code_type, last_image;
2081 uint32_t pcihdr, pcids;
2082 uint8_t *dbyte;
2083 uint16_t *dcode;
2084
2085 if (!ha->pio_address || !mbuf)
2086 return QLA_FUNCTION_FAILED;
2087
2088 memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2089 memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2090 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2091 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2092
2093 qla2x00_flash_enable(ha);
2094
2095 /* Begin with first PCI expansion ROM header. */
2096 pcihdr = 0;
2097 last_image = 1;
2098 do {
2099 /* Verify PCI expansion ROM header. */
2100 if (qla2x00_read_flash_byte(ha, pcihdr) != 0x55 ||
2101 qla2x00_read_flash_byte(ha, pcihdr + 0x01) != 0xaa) {
2102 /* No signature */
2103 DEBUG2(printk("scsi(%ld): No matching ROM "
2104 "signature.\n", ha->host_no));
2105 ret = QLA_FUNCTION_FAILED;
2106 break;
2107 }
2108
2109 /* Locate PCI data structure. */
2110 pcids = pcihdr +
2111 ((qla2x00_read_flash_byte(ha, pcihdr + 0x19) << 8) |
2112 qla2x00_read_flash_byte(ha, pcihdr + 0x18));
2113
2114 /* Validate signature of PCI data structure. */
2115 if (qla2x00_read_flash_byte(ha, pcids) != 'P' ||
2116 qla2x00_read_flash_byte(ha, pcids + 0x1) != 'C' ||
2117 qla2x00_read_flash_byte(ha, pcids + 0x2) != 'I' ||
2118 qla2x00_read_flash_byte(ha, pcids + 0x3) != 'R') {
2119 /* Incorrect header. */
2120 DEBUG2(printk("%s(): PCI data struct not found "
2121 "pcir_adr=%x.\n", __func__, pcids));
2122 ret = QLA_FUNCTION_FAILED;
2123 break;
2124 }
2125
2126 /* Read version */
2127 code_type = qla2x00_read_flash_byte(ha, pcids + 0x14);
2128 switch (code_type) {
2129 case ROM_CODE_TYPE_BIOS:
2130 /* Intel x86, PC-AT compatible. */
2131 ha->bios_revision[0] =
2132 qla2x00_read_flash_byte(ha, pcids + 0x12);
2133 ha->bios_revision[1] =
2134 qla2x00_read_flash_byte(ha, pcids + 0x13);
2135 DEBUG3(printk("%s(): read BIOS %d.%d.\n", __func__,
2136 ha->bios_revision[1], ha->bios_revision[0]));
2137 break;
2138 case ROM_CODE_TYPE_FCODE:
2139 /* Open Firmware standard for PCI (FCode). */
2140 /* Eeeewww... */
2141 qla2x00_get_fcode_version(ha, pcids);
2142 break;
2143 case ROM_CODE_TYPE_EFI:
2144 /* Extensible Firmware Interface (EFI). */
2145 ha->efi_revision[0] =
2146 qla2x00_read_flash_byte(ha, pcids + 0x12);
2147 ha->efi_revision[1] =
2148 qla2x00_read_flash_byte(ha, pcids + 0x13);
2149 DEBUG3(printk("%s(): read EFI %d.%d.\n", __func__,
2150 ha->efi_revision[1], ha->efi_revision[0]));
2151 break;
2152 default:
2153 DEBUG2(printk("%s(): Unrecognized code type %x at "
2154 "pcids %x.\n", __func__, code_type, pcids));
2155 break;
2156 }
2157
2158 last_image = qla2x00_read_flash_byte(ha, pcids + 0x15) & BIT_7;
2159
2160 /* Locate next PCI expansion ROM. */
2161 pcihdr += ((qla2x00_read_flash_byte(ha, pcids + 0x11) << 8) |
2162 qla2x00_read_flash_byte(ha, pcids + 0x10)) * 512;
2163 } while (!last_image);
2164
2165 if (IS_QLA2322(ha)) {
2166 /* Read firmware image information. */
2167 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2168 dbyte = mbuf;
2169 memset(dbyte, 0, 8);
2170 dcode = (uint16_t *)dbyte;
2171
2172 qla2x00_read_flash_data(ha, dbyte, FA_RISC_CODE_ADDR * 4 + 10,
2173 8);
2174 DEBUG3(printk("%s(%ld): dumping fw ver from flash:\n",
2175 __func__, ha->host_no));
2176 DEBUG3(qla2x00_dump_buffer((uint8_t *)dbyte, 8));
2177
2178 if ((dcode[0] == 0xffff && dcode[1] == 0xffff &&
2179 dcode[2] == 0xffff && dcode[3] == 0xffff) ||
2180 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2181 dcode[3] == 0)) {
2182 DEBUG2(printk("%s(): Unrecognized fw revision at "
2183 "%x.\n", __func__, FA_RISC_CODE_ADDR * 4));
2184 } else {
2185 /* values are in big endian */
2186 ha->fw_revision[0] = dbyte[0] << 16 | dbyte[1];
2187 ha->fw_revision[1] = dbyte[2] << 16 | dbyte[3];
2188 ha->fw_revision[2] = dbyte[4] << 16 | dbyte[5];
2189 }
2190 }
2191
2192 qla2x00_flash_disable(ha);
2193
2194 return ret;
2195 }
2196
2197 int
2198 qla24xx_get_flash_version(scsi_qla_host_t *ha, void *mbuf)
2199 {
2200 int ret = QLA_SUCCESS;
2201 uint32_t pcihdr, pcids;
2202 uint32_t *dcode;
2203 uint8_t *bcode;
2204 uint8_t code_type, last_image;
2205 int i;
2206
2207 if (!mbuf)
2208 return QLA_FUNCTION_FAILED;
2209
2210 memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2211 memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2212 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2213 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2214
2215 dcode = mbuf;
2216
2217 /* Begin with first PCI expansion ROM header. */
2218 pcihdr = 0;
2219 last_image = 1;
2220 do {
2221 /* Verify PCI expansion ROM header. */
2222 qla24xx_read_flash_data(ha, dcode, pcihdr >> 2, 0x20);
2223 bcode = mbuf + (pcihdr % 4);
2224 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) {
2225 /* No signature */
2226 DEBUG2(printk("scsi(%ld): No matching ROM "
2227 "signature.\n", ha->host_no));
2228 ret = QLA_FUNCTION_FAILED;
2229 break;
2230 }
2231
2232 /* Locate PCI data structure. */
2233 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
2234
2235 qla24xx_read_flash_data(ha, dcode, pcids >> 2, 0x20);
2236 bcode = mbuf + (pcihdr % 4);
2237
2238 /* Validate signature of PCI data structure. */
2239 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
2240 bcode[0x2] != 'I' || bcode[0x3] != 'R') {
2241 /* Incorrect header. */
2242 DEBUG2(printk("%s(): PCI data struct not found "
2243 "pcir_adr=%x.\n", __func__, pcids));
2244 ret = QLA_FUNCTION_FAILED;
2245 break;
2246 }
2247
2248 /* Read version */
2249 code_type = bcode[0x14];
2250 switch (code_type) {
2251 case ROM_CODE_TYPE_BIOS:
2252 /* Intel x86, PC-AT compatible. */
2253 ha->bios_revision[0] = bcode[0x12];
2254 ha->bios_revision[1] = bcode[0x13];
2255 DEBUG3(printk("%s(): read BIOS %d.%d.\n", __func__,
2256 ha->bios_revision[1], ha->bios_revision[0]));
2257 break;
2258 case ROM_CODE_TYPE_FCODE:
2259 /* Open Firmware standard for PCI (FCode). */
2260 ha->fcode_revision[0] = bcode[0x12];
2261 ha->fcode_revision[1] = bcode[0x13];
2262 DEBUG3(printk("%s(): read FCODE %d.%d.\n", __func__,
2263 ha->fcode_revision[1], ha->fcode_revision[0]));
2264 break;
2265 case ROM_CODE_TYPE_EFI:
2266 /* Extensible Firmware Interface (EFI). */
2267 ha->efi_revision[0] = bcode[0x12];
2268 ha->efi_revision[1] = bcode[0x13];
2269 DEBUG3(printk("%s(): read EFI %d.%d.\n", __func__,
2270 ha->efi_revision[1], ha->efi_revision[0]));
2271 break;
2272 default:
2273 DEBUG2(printk("%s(): Unrecognized code type %x at "
2274 "pcids %x.\n", __func__, code_type, pcids));
2275 break;
2276 }
2277
2278 last_image = bcode[0x15] & BIT_7;
2279
2280 /* Locate next PCI expansion ROM. */
2281 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
2282 } while (!last_image);
2283
2284 /* Read firmware image information. */
2285 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2286 dcode = mbuf;
2287
2288 qla24xx_read_flash_data(ha, dcode, FA_RISC_CODE_ADDR + 4, 4);
2289 for (i = 0; i < 4; i++)
2290 dcode[i] = be32_to_cpu(dcode[i]);
2291
2292 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
2293 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
2294 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2295 dcode[3] == 0)) {
2296 DEBUG2(printk("%s(): Unrecognized fw version at %x.\n",
2297 __func__, FA_RISC_CODE_ADDR));
2298 } else {
2299 ha->fw_revision[0] = dcode[0];
2300 ha->fw_revision[1] = dcode[1];
2301 ha->fw_revision[2] = dcode[2];
2302 ha->fw_revision[3] = dcode[3];
2303 }
2304
2305 return ret;
2306 }
2307
2308 static int
2309 qla2xxx_hw_event_store(scsi_qla_host_t *ha, uint32_t *fdata)
2310 {
2311 uint32_t d[2], faddr;
2312
2313 /* Locate first empty entry. */
2314 for (;;) {
2315 if (ha->hw_event_ptr >=
2316 ha->hw_event_start + FA_HW_EVENT_SIZE) {
2317 DEBUG2(qla_printk(KERN_WARNING, ha,
2318 "HW event -- Log Full!\n"));
2319 return QLA_MEMORY_ALLOC_FAILED;
2320 }
2321
2322 qla24xx_read_flash_data(ha, d, ha->hw_event_ptr, 2);
2323 faddr = flash_data_to_access_addr(ha->hw_event_ptr);
2324 ha->hw_event_ptr += FA_HW_EVENT_ENTRY_SIZE;
2325 if (d[0] == __constant_cpu_to_le32(0xffffffff) &&
2326 d[1] == __constant_cpu_to_le32(0xffffffff)) {
2327 qla24xx_unprotect_flash(ha);
2328
2329 qla24xx_write_flash_dword(ha, faddr++,
2330 cpu_to_le32(jiffies));
2331 qla24xx_write_flash_dword(ha, faddr++, 0);
2332 qla24xx_write_flash_dword(ha, faddr++, *fdata++);
2333 qla24xx_write_flash_dword(ha, faddr++, *fdata);
2334
2335 qla24xx_protect_flash(ha);
2336 break;
2337 }
2338 }
2339 return QLA_SUCCESS;
2340 }
2341
2342 int
2343 qla2xxx_hw_event_log(scsi_qla_host_t *ha, uint16_t code, uint16_t d1,
2344 uint16_t d2, uint16_t d3)
2345 {
2346 #define QMARK(a, b, c, d) \
2347 cpu_to_le32(LSB(a) << 24 | LSB(b) << 16 | LSB(c) << 8 | LSB(d))
2348
2349 int rval;
2350 uint32_t marker[2], fdata[4];
2351
2352 if (ha->hw_event_start == 0)
2353 return QLA_FUNCTION_FAILED;
2354
2355 DEBUG2(qla_printk(KERN_WARNING, ha,
2356 "HW event -- code=%x, d1=%x, d2=%x, d3=%x.\n", code, d1, d2, d3));
2357
2358 /* If marker not already found, locate or write. */
2359 if (!ha->flags.hw_event_marker_found) {
2360 /* Create marker. */
2361 marker[0] = QMARK('L', ha->fw_major_version,
2362 ha->fw_minor_version, ha->fw_subminor_version);
2363 marker[1] = QMARK(QLA_DRIVER_MAJOR_VER, QLA_DRIVER_MINOR_VER,
2364 QLA_DRIVER_PATCH_VER, QLA_DRIVER_BETA_VER);
2365
2366 /* Locate marker. */
2367 ha->hw_event_ptr = ha->hw_event_start;
2368 for (;;) {
2369 qla24xx_read_flash_data(ha, fdata, ha->hw_event_ptr,
2370 4);
2371 if (fdata[0] == __constant_cpu_to_le32(0xffffffff) &&
2372 fdata[1] == __constant_cpu_to_le32(0xffffffff))
2373 break;
2374 ha->hw_event_ptr += FA_HW_EVENT_ENTRY_SIZE;
2375 if (ha->hw_event_ptr >=
2376 ha->hw_event_start + FA_HW_EVENT_SIZE) {
2377 DEBUG2(qla_printk(KERN_WARNING, ha,
2378 "HW event -- Log Full!\n"));
2379 return QLA_MEMORY_ALLOC_FAILED;
2380 }
2381 if (fdata[2] == marker[0] && fdata[3] == marker[1]) {
2382 ha->flags.hw_event_marker_found = 1;
2383 break;
2384 }
2385 }
2386 /* No marker, write it. */
2387 if (!ha->flags.hw_event_marker_found) {
2388 rval = qla2xxx_hw_event_store(ha, marker);
2389 if (rval != QLA_SUCCESS) {
2390 DEBUG2(qla_printk(KERN_WARNING, ha,
2391 "HW event -- Failed marker write=%x.!\n",
2392 rval));
2393 return rval;
2394 }
2395 ha->flags.hw_event_marker_found = 1;
2396 }
2397 }
2398
2399 /* Store error. */
2400 fdata[0] = cpu_to_le32(code << 16 | d1);
2401 fdata[1] = cpu_to_le32(d2 << 16 | d3);
2402 rval = qla2xxx_hw_event_store(ha, fdata);
2403 if (rval != QLA_SUCCESS) {
2404 DEBUG2(qla_printk(KERN_WARNING, ha,
2405 "HW event -- Failed error write=%x.!\n",
2406 rval));
2407 }
2408
2409 return rval;
2410 }
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