include/asm-powerpc/cputable.h

   1 #ifndef __ASM_POWERPC_CPUTABLE_H
   2 #define __ASM_POWERPC_CPUTABLE_H
   3
   4 #include <asm/asm-compat.h>
   5
   6 #define PPC_FEATURE_32                  0x80000000
   7 #define PPC_FEATURE_64                  0x40000000
   8 #define PPC_FEATURE_601_INSTR           0x20000000
   9 #define PPC_FEATURE_HAS_ALTIVEC         0x10000000
  10 #define PPC_FEATURE_HAS_FPU             0x08000000
  11 #define PPC_FEATURE_HAS_MMU             0x04000000
  12 #define PPC_FEATURE_HAS_4xxMAC          0x02000000
  13 #define PPC_FEATURE_UNIFIED_CACHE       0x01000000
  14 #define PPC_FEATURE_HAS_SPE             0x00800000
  15 #define PPC_FEATURE_HAS_EFP_SINGLE      0x00400000
  16 #define PPC_FEATURE_HAS_EFP_DOUBLE      0x00200000
  17 #define PPC_FEATURE_NO_TB               0x00100000
  18 #define PPC_FEATURE_POWER4              0x00080000
  19 #define PPC_FEATURE_POWER5              0x00040000
  20 #define PPC_FEATURE_POWER5_PLUS         0x00020000
  21 #define PPC_FEATURE_CELL                0x00010000
  22 #define PPC_FEATURE_BOOKE               0x00008000
  23 #define PPC_FEATURE_SMT                 0x00004000
  24 #define PPC_FEATURE_ICACHE_SNOOP        0x00002000
  25 #define PPC_FEATURE_ARCH_2_05           0x00001000
  26 #define PPC_FEATURE_PA6T                0x00000800
  27 #define PPC_FEATURE_HAS_DFP             0x00000400
  28 #define PPC_FEATURE_POWER6_EXT          0x00000200
  29
  30 #define PPC_FEATURE_TRUE_LE             0x00000002
  31 #define PPC_FEATURE_PPC_LE              0x00000001
  32
  33 #ifdef __KERNEL__
  34 #ifndef __ASSEMBLY__
  35
  36 /* This structure can grow, it's real size is used by head.S code
  37  * via the mkdefs mechanism.
  38  */
  39 struct cpu_spec;
  40
  41 typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
  42 typedef void (*cpu_restore_t)(void);
  43
  44 enum powerpc_oprofile_type {
  45         PPC_OPROFILE_INVALID = 0,
  46         PPC_OPROFILE_RS64 = 1,
  47         PPC_OPROFILE_POWER4 = 2,
  48         PPC_OPROFILE_G4 = 3,
  49         PPC_OPROFILE_FSL_EMB = 4,
  50         PPC_OPROFILE_CELL = 5,
  51         PPC_OPROFILE_PA6T = 6,
  52 };
  53
  54 enum powerpc_pmc_type {
  55         PPC_PMC_DEFAULT = 0,
  56         PPC_PMC_IBM = 1,
  57         PPC_PMC_PA6T = 2,
  58 };
  59
  60 struct pt_regs;
  61
  62 extern int machine_check_generic(struct pt_regs *regs);
  63 extern int machine_check_4xx(struct pt_regs *regs);
  64 extern int machine_check_440A(struct pt_regs *regs);
  65 extern int machine_check_e500(struct pt_regs *regs);
  66 extern int machine_check_e200(struct pt_regs *regs);
  67
  68 /* NOTE WELL: Update identify_cpu() if fields are added or removed! */
  69 struct cpu_spec {
  70         /* CPU is matched via (PVR & pvr_mask) == pvr_value */
  71         unsigned int    pvr_mask;
  72         unsigned int    pvr_value;
  73
  74         char            *cpu_name;
  75         unsigned long   cpu_features;           /* Kernel features */
  76         unsigned int    cpu_user_features;      /* Userland features */
  77
  78         /* cache line sizes */
  79         unsigned int    icache_bsize;
  80         unsigned int    dcache_bsize;
  81
  82         /* number of performance monitor counters */
  83         unsigned int    num_pmcs;
  84         enum powerpc_pmc_type pmc_type;
  85
  86         /* this is called to initialize various CPU bits like L1 cache,
  87          * BHT, SPD, etc... from head.S before branching to identify_machine
  88          */
  89         cpu_setup_t     cpu_setup;
  90         /* Used to restore cpu setup on secondary processors and at resume */
  91         cpu_restore_t   cpu_restore;
  92
  93         /* Used by oprofile userspace to select the right counters */
  94         char            *oprofile_cpu_type;
  95
  96         /* Processor specific oprofile operations */
  97         enum powerpc_oprofile_type oprofile_type;
  98
  99         /* Bit locations inside the mmcra change */
 100         unsigned long   oprofile_mmcra_sihv;
 101         unsigned long   oprofile_mmcra_sipr;
 102
 103         /* Bits to clear during an oprofile exception */
 104         unsigned long   oprofile_mmcra_clear;
 105
 106         /* Name of processor class, for the ELF AT_PLATFORM entry */
 107         char            *platform;
 108
 109         /* Processor specific machine check handling. Return negative
 110          * if the error is fatal, 1 if it was fully recovered and 0 to
 111          * pass up (not CPU originated) */
 112         int             (*machine_check)(struct pt_regs *regs);
 113 };
 114
 115 extern struct cpu_spec          *cur_cpu_spec;
 116
 117 extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
 118
 119 extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
 120 extern void do_feature_fixups(unsigned long value, void *fixup_start,
 121                               void *fixup_end);
 122
 123 #endif /* __ASSEMBLY__ */
 124
 125 /* CPU kernel features */
 126
 127 /* Retain the 32b definitions all use bottom half of word */
 128 #define CPU_FTR_COHERENT_ICACHE         ASM_CONST(0x0000000000000001)
 129 #define CPU_FTR_L2CR                    ASM_CONST(0x0000000000000002)
 130 #define CPU_FTR_SPEC7450                ASM_CONST(0x0000000000000004)
 131 #define CPU_FTR_ALTIVEC                 ASM_CONST(0x0000000000000008)
 132 #define CPU_FTR_TAU                     ASM_CONST(0x0000000000000010)
 133 #define CPU_FTR_CAN_DOZE                ASM_CONST(0x0000000000000020)
 134 #define CPU_FTR_USE_TB                  ASM_CONST(0x0000000000000040)
 135 #define CPU_FTR_604_PERF_MON            ASM_CONST(0x0000000000000080)
 136 #define CPU_FTR_601                     ASM_CONST(0x0000000000000100)
 137 #define CPU_FTR_HPTE_TABLE              ASM_CONST(0x0000000000000200)
 138 #define CPU_FTR_CAN_NAP                 ASM_CONST(0x0000000000000400)
 139 #define CPU_FTR_L3CR                    ASM_CONST(0x0000000000000800)
 140 #define CPU_FTR_L3_DISABLE_NAP          ASM_CONST(0x0000000000001000)
 141 #define CPU_FTR_NAP_DISABLE_L2_PR       ASM_CONST(0x0000000000002000)
 142 #define CPU_FTR_DUAL_PLL_750FX          ASM_CONST(0x0000000000004000)
 143 #define CPU_FTR_NO_DPM                  ASM_CONST(0x0000000000008000)
 144 #define CPU_FTR_HAS_HIGH_BATS           ASM_CONST(0x0000000000010000)
 145 #define CPU_FTR_NEED_COHERENT           ASM_CONST(0x0000000000020000)
 146 #define CPU_FTR_NO_BTIC                 ASM_CONST(0x0000000000040000)
 147 #define CPU_FTR_BIG_PHYS                ASM_CONST(0x0000000000080000)
 148 #define CPU_FTR_NODSISRALIGN            ASM_CONST(0x0000000000100000)
 149 #define CPU_FTR_PPC_LE                  ASM_CONST(0x0000000000200000)
 150 #define CPU_FTR_REAL_LE                 ASM_CONST(0x0000000000400000)
 151 #define CPU_FTR_FPU_UNAVAILABLE         ASM_CONST(0x0000000000800000)
 152 #define CPU_FTR_UNIFIED_ID_CACHE        ASM_CONST(0x0000000001000000)
 153 #define CPU_FTR_SPE                     ASM_CONST(0x0000000002000000)
 154 #define CPU_FTR_NEED_PAIRED_STWCX       ASM_CONST(0x0000000004000000)
 155
 156 /*
 157  * Add the 64-bit processor unique features in the top half of the word;
 158  * on 32-bit, make the names available but defined to be 0.
 159  */
 160 #ifdef __powerpc64__
 161 #define LONG_ASM_CONST(x)               ASM_CONST(x)
 162 #else
 163 #define LONG_ASM_CONST(x)               0
 164 #endif
 165
 166 #define CPU_FTR_SLB                     LONG_ASM_CONST(0x0000000100000000)
 167 #define CPU_FTR_16M_PAGE                LONG_ASM_CONST(0x0000000200000000)
 168 #define CPU_FTR_TLBIEL                  LONG_ASM_CONST(0x0000000400000000)
 169 #define CPU_FTR_NOEXECUTE               LONG_ASM_CONST(0x0000000800000000)
 170 #define CPU_FTR_IABR                    LONG_ASM_CONST(0x0000002000000000)
 171 #define CPU_FTR_MMCRA                   LONG_ASM_CONST(0x0000004000000000)
 172 #define CPU_FTR_CTRL                    LONG_ASM_CONST(0x0000008000000000)
 173 #define CPU_FTR_SMT                     LONG_ASM_CONST(0x0000010000000000)
 174 #define CPU_FTR_LOCKLESS_TLBIE          LONG_ASM_CONST(0x0000040000000000)
 175 #define CPU_FTR_CI_LARGE_PAGE           LONG_ASM_CONST(0x0000100000000000)
 176 #define CPU_FTR_PAUSE_ZERO              LONG_ASM_CONST(0x0000200000000000)
 177 #define CPU_FTR_PURR                    LONG_ASM_CONST(0x0000400000000000)
 178 #define CPU_FTR_CELL_TB_BUG             LONG_ASM_CONST(0x0000800000000000)
 179 #define CPU_FTR_SPURR                   LONG_ASM_CONST(0x0001000000000000)
 180 #define CPU_FTR_DSCR                    LONG_ASM_CONST(0x0002000000000000)
 181 #define CPU_FTR_1T_SEGMENT              LONG_ASM_CONST(0x0004000000000000)
 182 #define CPU_FTR_NO_SLBIE_B              LONG_ASM_CONST(0x0008000000000000)
 183
 184 #ifndef __ASSEMBLY__
 185
 186 #define CPU_FTR_PPCAS_ARCH_V2   (CPU_FTR_SLB | \
 187                                  CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
 188                                  CPU_FTR_NODSISRALIGN | CPU_FTR_16M_PAGE)
 189
 190 /* We only set the altivec features if the kernel was compiled with altivec
 191  * support
 192  */
 193 #ifdef CONFIG_ALTIVEC
 194 #define CPU_FTR_ALTIVEC_COMP    CPU_FTR_ALTIVEC
 195 #define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
 196 #else
 197 #define CPU_FTR_ALTIVEC_COMP    0
 198 #define PPC_FEATURE_HAS_ALTIVEC_COMP    0
 199 #endif
 200
 201 /* We only set the spe features if the kernel was compiled with spe
 202  * support
 203  */
 204 #ifdef CONFIG_SPE
 205 #define CPU_FTR_SPE_COMP        CPU_FTR_SPE
 206 #define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE
 207 #define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE
 208 #define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE
 209 #else
 210 #define CPU_FTR_SPE_COMP        0
 211 #define PPC_FEATURE_HAS_SPE_COMP    0
 212 #define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
 213 #define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
 214 #endif
 215
 216 /* We need to mark all pages as being coherent if we're SMP or we have a
 217  * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
 218  * require it for PCI "streaming/prefetch" to work properly.
 219  */
 220 #if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
 221         || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260)
 222 #define CPU_FTR_COMMON                  CPU_FTR_NEED_COHERENT
 223 #else
 224 #define CPU_FTR_COMMON                  0
 225 #endif
 226
 227 /* The powersave features NAP & DOZE seems to confuse BDI when
 228    debugging. So if a BDI is used, disable theses
 229  */
 230 #ifndef CONFIG_BDI_SWITCH
 231 #define CPU_FTR_MAYBE_CAN_DOZE  CPU_FTR_CAN_DOZE
 232 #define CPU_FTR_MAYBE_CAN_NAP   CPU_FTR_CAN_NAP
 233 #else
 234 #define CPU_FTR_MAYBE_CAN_DOZE  0
 235 #define CPU_FTR_MAYBE_CAN_NAP   0
 236 #endif
 237
 238 #define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
 239                      !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
 240                      !defined(CONFIG_BOOKE))
 241
 242 #define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE | \
 243         CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE)
 244 #define CPU_FTRS_603    (CPU_FTR_COMMON | \
 245             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
 246             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
 247 #define CPU_FTRS_604    (CPU_FTR_COMMON | \
 248             CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE | \
 249             CPU_FTR_PPC_LE)
 250 #define CPU_FTRS_740_NOTAU      (CPU_FTR_COMMON | \
 251             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
 252             CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
 253 #define CPU_FTRS_740    (CPU_FTR_COMMON | \
 254             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
 255             CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
 256             CPU_FTR_PPC_LE)
 257 #define CPU_FTRS_750    (CPU_FTR_COMMON | \
 258             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
 259             CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
 260             CPU_FTR_PPC_LE)
 261 #define CPU_FTRS_750CL  (CPU_FTRS_750 | CPU_FTR_HAS_HIGH_BATS)
 262 #define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
 263 #define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM)
 264 #define CPU_FTRS_750FX  (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | \
 265                 CPU_FTR_HAS_HIGH_BATS)
 266 #define CPU_FTRS_750GX  (CPU_FTRS_750FX)
 267 #define CPU_FTRS_7400_NOTAU     (CPU_FTR_COMMON | \
 268             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
 269             CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
 270             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
 271 #define CPU_FTRS_7400   (CPU_FTR_COMMON | \
 272             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
 273             CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
 274             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
 275 #define CPU_FTRS_7450_20        (CPU_FTR_COMMON | \
 276             CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 277             CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
 278             CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
 279 #define CPU_FTRS_7450_21        (CPU_FTR_COMMON | \
 280             CPU_FTR_USE_TB | \
 281             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 282             CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
 283             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
 284             CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
 285 #define CPU_FTRS_7450_23        (CPU_FTR_COMMON | \
 286             CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
 287             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 288             CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
 289             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
 290 #define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \
 291             CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
 292             CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
 293             CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | \
 294             CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
 295 #define CPU_FTRS_7455_20        (CPU_FTR_COMMON | \
 296             CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
 297             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 298             CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
 299             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
 300             CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
 301 #define CPU_FTRS_7455   (CPU_FTR_COMMON | \
 302             CPU_FTR_USE_TB | \
 303             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 304             CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
 305             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
 306             CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
 307 #define CPU_FTRS_7447_10        (CPU_FTR_COMMON | \
 308             CPU_FTR_USE_TB | \
 309             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 310             CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
 311             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
 312             CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \
 313             CPU_FTR_NEED_PAIRED_STWCX)
 314 #define CPU_FTRS_7447   (CPU_FTR_COMMON | \
 315             CPU_FTR_USE_TB | \
 316             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 317             CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
 318             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
 319             CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
 320 #define CPU_FTRS_7447A  (CPU_FTR_COMMON | \
 321             CPU_FTR_USE_TB | \
 322             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 323             CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
 324             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
 325             CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
 326 #define CPU_FTRS_7448   (CPU_FTR_COMMON | \
 327             CPU_FTR_USE_TB | \
 328             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 329             CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
 330             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
 331             CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
 332 #define CPU_FTRS_82XX   (CPU_FTR_COMMON | \
 333             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
 334 #define CPU_FTRS_G2_LE  (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
 335             CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS)
 336 #define CPU_FTRS_E300   (CPU_FTR_MAYBE_CAN_DOZE | \
 337             CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
 338             CPU_FTR_COMMON)
 339 #define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \
 340             CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
 341             CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
 342 #define CPU_FTRS_CLASSIC32      (CPU_FTR_COMMON | \
 343             CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE)
 344 #define CPU_FTRS_8XX    (CPU_FTR_USE_TB)
 345 #define CPU_FTRS_40X    (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
 346 #define CPU_FTRS_44X    (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
 347 #define CPU_FTRS_E200   (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
 348             CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
 349             CPU_FTR_UNIFIED_ID_CACHE)
 350 #define CPU_FTRS_E500   (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
 351             CPU_FTR_NODSISRALIGN)
 352 #define CPU_FTRS_E500_2 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
 353             CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN)
 354 #define CPU_FTRS_GENERIC_32     (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
 355
 356 /* 64-bit CPUs */
 357 #define CPU_FTRS_POWER3 (CPU_FTR_USE_TB | \
 358             CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | CPU_FTR_PPC_LE)
 359 #define CPU_FTRS_RS64   (CPU_FTR_USE_TB | \
 360             CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | \
 361             CPU_FTR_MMCRA | CPU_FTR_CTRL)
 362 #define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | \
 363             CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
 364             CPU_FTR_MMCRA)
 365 #define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | \
 366             CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
 367             CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA)
 368 #define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | \
 369             CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
 370             CPU_FTR_MMCRA | CPU_FTR_SMT | \
 371             CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
 372             CPU_FTR_PURR)
 373 #define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | \
 374             CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
 375             CPU_FTR_MMCRA | CPU_FTR_SMT | \
 376             CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
 377             CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
 378             CPU_FTR_DSCR)
 379 #define CPU_FTRS_CELL   (CPU_FTR_USE_TB | \
 380             CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
 381             CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
 382             CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE | CPU_FTR_CELL_TB_BUG)
 383 #define CPU_FTRS_PA6T (CPU_FTR_USE_TB | \
 384             CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
 385             CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \
 386             CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_NO_SLBIE_B)
 387 #define CPU_FTRS_COMPATIBLE     (CPU_FTR_USE_TB | \
 388             CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2)
 389
 390 #ifdef __powerpc64__
 391 #define CPU_FTRS_POSSIBLE       \
 392             (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 |        \
 393             CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 |       \
 394             CPU_FTRS_CELL | CPU_FTRS_PA6T | CPU_FTR_1T_SEGMENT)
 395 #else
 396 enum {
 397         CPU_FTRS_POSSIBLE =
 398 #if CLASSIC_PPC
 399             CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
 400             CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
 401             CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
 402             CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
 403             CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
 404             CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
 405             CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
 406             CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
 407             CPU_FTRS_CLASSIC32 |
 408 #else
 409             CPU_FTRS_GENERIC_32 |
 410 #endif
 411 #ifdef CONFIG_8xx
 412             CPU_FTRS_8XX |
 413 #endif
 414 #ifdef CONFIG_40x
 415             CPU_FTRS_40X |
 416 #endif
 417 #ifdef CONFIG_44x
 418             CPU_FTRS_44X |
 419 #endif
 420 #ifdef CONFIG_E200
 421             CPU_FTRS_E200 |
 422 #endif
 423 #ifdef CONFIG_E500
 424             CPU_FTRS_E500 | CPU_FTRS_E500_2 |
 425 #endif
 426             0,
 427 };
 428 #endif /* __powerpc64__ */
 429
 430 #ifdef __powerpc64__
 431 #define CPU_FTRS_ALWAYS         \
 432             (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 &        \
 433             CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 &       \
 434             CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE)
 435 #else
 436 enum {
 437         CPU_FTRS_ALWAYS =
 438 #if CLASSIC_PPC
 439             CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
 440             CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
 441             CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
 442             CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
 443             CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
 444             CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
 445             CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
 446             CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
 447             CPU_FTRS_CLASSIC32 &
 448 #else
 449             CPU_FTRS_GENERIC_32 &
 450 #endif
 451 #ifdef CONFIG_8xx
 452             CPU_FTRS_8XX &
 453 #endif
 454 #ifdef CONFIG_40x
 455             CPU_FTRS_40X &
 456 #endif
 457 #ifdef CONFIG_44x
 458             CPU_FTRS_44X &
 459 #endif
 460 #ifdef CONFIG_E200
 461             CPU_FTRS_E200 &
 462 #endif
 463 #ifdef CONFIG_E500
 464             CPU_FTRS_E500 & CPU_FTRS_E500_2 &
 465 #endif
 466             CPU_FTRS_POSSIBLE,
 467 };
 468 #endif /* __powerpc64__ */
 469
 470 static inline int cpu_has_feature(unsigned long feature)
 471 {
 472         return (CPU_FTRS_ALWAYS & feature) ||
 473                (CPU_FTRS_POSSIBLE
 474                 & cur_cpu_spec->cpu_features
 475                 & feature);
 476 }
 477
 478 #endif /* !__ASSEMBLY__ */
 479
 480 #ifdef __ASSEMBLY__
 481
 482 #define BEGIN_FTR_SECTION_NESTED(label) label:
 483 #define BEGIN_FTR_SECTION               BEGIN_FTR_SECTION_NESTED(97)
 484 #define END_FTR_SECTION_NESTED(msk, val, label) \
 485         MAKE_FTR_SECTION_ENTRY(msk, val, label, __ftr_fixup)
 486 #define END_FTR_SECTION(msk, val)               \
 487         END_FTR_SECTION_NESTED(msk, val, 97)
 488
 489 #define END_FTR_SECTION_IFSET(msk)      END_FTR_SECTION((msk), (msk))
 490 #define END_FTR_SECTION_IFCLR(msk)      END_FTR_SECTION((msk), 0)
 491 #endif /* __ASSEMBLY__ */
 492
 493 #endif /* __KERNEL__ */
 494 #endif /* __ASM_POWERPC_CPUTABLE_H */