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ia64/kvm: compilation fix. export account_system_vtime.
[pv_ops_mirror.git] / sound / pci / hda / hda_intel.c
blobb3a618eb42cdf5b4a45bc861312b974b7ce00581
1 /*
2 *
3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
37 #include <asm/io.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/moduleparam.h>
44 #include <linux/init.h>
45 #include <linux/slab.h>
46 #include <linux/pci.h>
47 #include <linux/mutex.h>
48 #include <sound/core.h>
49 #include <sound/initval.h>
50 #include "hda_codec.h"
51
52
53 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
54 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
55 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
56 static char *model[SNDRV_CARDS];
57 static int position_fix[SNDRV_CARDS];
58 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
59 static int single_cmd;
60 static int enable_msi;
61
62 module_param_array(index, int, NULL, 0444);
63 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
64 module_param_array(id, charp, NULL, 0444);
65 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
66 module_param_array(enable, bool, NULL, 0444);
67 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
68 module_param_array(model, charp, NULL, 0444);
69 MODULE_PARM_DESC(model, "Use the given board model.");
70 module_param_array(position_fix, int, NULL, 0444);
71 MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
72 "(0 = auto, 1 = none, 2 = POSBUF, 3 = FIFO size).");
73 module_param_array(probe_mask, int, NULL, 0444);
74 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
75 module_param(single_cmd, bool, 0444);
76 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
77 "(for debugging only).");
78 module_param(enable_msi, int, 0444);
79 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
80
81 #ifdef CONFIG_SND_HDA_POWER_SAVE
82 /* power_save option is defined in hda_codec.c */
83
84 /* reset the HD-audio controller in power save mode.
85 * this may give more power-saving, but will take longer time to
86 * wake up.
87 */
88 static int power_save_controller = 1;
89 module_param(power_save_controller, bool, 0644);
90 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
91 #endif
92
93 MODULE_LICENSE("GPL");
94 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
95 "{Intel, ICH6M},"
96 "{Intel, ICH7},"
97 "{Intel, ESB2},"
98 "{Intel, ICH8},"
99 "{Intel, ICH9},"
100 "{Intel, ICH10},"
101 "{Intel, SCH},"
102 "{ATI, SB450},"
103 "{ATI, SB600},"
104 "{ATI, RS600},"
105 "{ATI, RS690},"
106 "{ATI, RS780},"
107 "{ATI, R600},"
108 "{ATI, RV630},"
109 "{ATI, RV610},"
110 "{ATI, RV670},"
111 "{ATI, RV635},"
112 "{ATI, RV620},"
113 "{ATI, RV770},"
114 "{VIA, VT8251},"
115 "{VIA, VT8237A},"
116 "{SiS, SIS966},"
117 "{ULI, M5461}}");
118 MODULE_DESCRIPTION("Intel HDA driver");
119
120 #define SFX "hda-intel: "
121
122
123 /*
124 * registers
125 */
126 #define ICH6_REG_GCAP 0x00
127 #define ICH6_REG_VMIN 0x02
128 #define ICH6_REG_VMAJ 0x03
129 #define ICH6_REG_OUTPAY 0x04
130 #define ICH6_REG_INPAY 0x06
131 #define ICH6_REG_GCTL 0x08
132 #define ICH6_REG_WAKEEN 0x0c
133 #define ICH6_REG_STATESTS 0x0e
134 #define ICH6_REG_GSTS 0x10
135 #define ICH6_REG_INTCTL 0x20
136 #define ICH6_REG_INTSTS 0x24
137 #define ICH6_REG_WALCLK 0x30
138 #define ICH6_REG_SYNC 0x34
139 #define ICH6_REG_CORBLBASE 0x40
140 #define ICH6_REG_CORBUBASE 0x44
141 #define ICH6_REG_CORBWP 0x48
142 #define ICH6_REG_CORBRP 0x4A
143 #define ICH6_REG_CORBCTL 0x4c
144 #define ICH6_REG_CORBSTS 0x4d
145 #define ICH6_REG_CORBSIZE 0x4e
146
147 #define ICH6_REG_RIRBLBASE 0x50
148 #define ICH6_REG_RIRBUBASE 0x54
149 #define ICH6_REG_RIRBWP 0x58
150 #define ICH6_REG_RINTCNT 0x5a
151 #define ICH6_REG_RIRBCTL 0x5c
152 #define ICH6_REG_RIRBSTS 0x5d
153 #define ICH6_REG_RIRBSIZE 0x5e
154
155 #define ICH6_REG_IC 0x60
156 #define ICH6_REG_IR 0x64
157 #define ICH6_REG_IRS 0x68
158 #define ICH6_IRS_VALID (1<<1)
159 #define ICH6_IRS_BUSY (1<<0)
160
161 #define ICH6_REG_DPLBASE 0x70
162 #define ICH6_REG_DPUBASE 0x74
163 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
164
165 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
166 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
167
168 /* stream register offsets from stream base */
169 #define ICH6_REG_SD_CTL 0x00
170 #define ICH6_REG_SD_STS 0x03
171 #define ICH6_REG_SD_LPIB 0x04
172 #define ICH6_REG_SD_CBL 0x08
173 #define ICH6_REG_SD_LVI 0x0c
174 #define ICH6_REG_SD_FIFOW 0x0e
175 #define ICH6_REG_SD_FIFOSIZE 0x10
176 #define ICH6_REG_SD_FORMAT 0x12
177 #define ICH6_REG_SD_BDLPL 0x18
178 #define ICH6_REG_SD_BDLPU 0x1c
179
180 /* PCI space */
181 #define ICH6_PCIREG_TCSEL 0x44
182
183 /*
184 * other constants
185 */
186
187 /* max number of SDs */
188 /* ICH, ATI and VIA have 4 playback and 4 capture */
189 #define ICH6_NUM_CAPTURE 4
190 #define ICH6_NUM_PLAYBACK 4
191
192 /* ULI has 6 playback and 5 capture */
193 #define ULI_NUM_CAPTURE 5
194 #define ULI_NUM_PLAYBACK 6
195
196 /* ATI HDMI has 1 playback and 0 capture */
197 #define ATIHDMI_NUM_CAPTURE 0
198 #define ATIHDMI_NUM_PLAYBACK 1
199
200 /* this number is statically defined for simplicity */
201 #define MAX_AZX_DEV 16
202
203 /* max number of fragments - we may use more if allocating more pages for BDL */
204 #define BDL_SIZE 4096
205 #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
206 #define AZX_MAX_FRAG 32
207 /* max buffer size - no h/w limit, you can increase as you like */
208 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
209 /* max number of PCM devics per card */
210 #define AZX_MAX_PCMS 8
211
212 /* RIRB int mask: overrun[2], response[0] */
213 #define RIRB_INT_RESPONSE 0x01
214 #define RIRB_INT_OVERRUN 0x04
215 #define RIRB_INT_MASK 0x05
216
217 /* STATESTS int mask: SD2,SD1,SD0 */
218 #define AZX_MAX_CODECS 3
219 #define STATESTS_INT_MASK 0x07
220
221 /* SD_CTL bits */
222 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
223 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
224 #define SD_CTL_STRIPE (3 << 16) /* stripe control */
225 #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
226 #define SD_CTL_DIR (1 << 19) /* bi-directional stream */
227 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
228 #define SD_CTL_STREAM_TAG_SHIFT 20
229
230 /* SD_CTL and SD_STS */
231 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
232 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
233 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
234 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
235 SD_INT_COMPLETE)
236
237 /* SD_STS */
238 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
239
240 /* INTCTL and INTSTS */
241 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
242 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
243 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
244
245 /* GCTL unsolicited response enable bit */
246 #define ICH6_GCTL_UREN (1<<8)
247
248 /* GCTL reset bit */
249 #define ICH6_GCTL_RESET (1<<0)
250
251 /* CORB/RIRB control, read/write pointer */
252 #define ICH6_RBCTL_DMA_EN 0x02 /* enable DMA */
253 #define ICH6_RBCTL_IRQ_EN 0x01 /* enable IRQ */
254 #define ICH6_RBRWP_CLR 0x8000 /* read/write pointer clear */
255 /* below are so far hardcoded - should read registers in future */
256 #define ICH6_MAX_CORB_ENTRIES 256
257 #define ICH6_MAX_RIRB_ENTRIES 256
258
259 /* position fix mode */
260 enum {
261 POS_FIX_AUTO,
262 POS_FIX_NONE,
263 POS_FIX_POSBUF,
264 POS_FIX_FIFO,
265 };
266
267 /* Defines for ATI HD Audio support in SB450 south bridge */
268 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
269 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
270
271 /* Defines for Nvidia HDA support */
272 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
273 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
274
275 /* Defines for Intel SCH HDA snoop control */
276 #define INTEL_SCH_HDA_DEVC 0x78
277 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
278
279
280 /*
281 */
282
283 struct azx_dev {
284 struct snd_dma_buffer bdl; /* BDL buffer */
285 u32 *posbuf; /* position buffer pointer */
286
287 unsigned int bufsize; /* size of the play buffer in bytes */
288 unsigned int frags; /* number for period in the play buffer */
289 unsigned int fifo_size; /* FIFO size */
290
291 void __iomem *sd_addr; /* stream descriptor pointer */
292
293 u32 sd_int_sta_mask; /* stream int status mask */
294
295 /* pcm support */
296 struct snd_pcm_substream *substream; /* assigned substream,
297 * set in PCM open
298 */
299 unsigned int format_val; /* format value to be set in the
300 * controller and the codec
301 */
302 unsigned char stream_tag; /* assigned stream */
303 unsigned char index; /* stream index */
304 /* for sanity check of position buffer */
305 unsigned int period_intr;
306
307 unsigned int opened :1;
308 unsigned int running :1;
309 };
310
311 /* CORB/RIRB */
312 struct azx_rb {
313 u32 *buf; /* CORB/RIRB buffer
314 * Each CORB entry is 4byte, RIRB is 8byte
315 */
316 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
317 /* for RIRB */
318 unsigned short rp, wp; /* read/write pointers */
319 int cmds; /* number of pending requests */
320 u32 res; /* last read value */
321 };
322
323 struct azx {
324 struct snd_card *card;
325 struct pci_dev *pci;
326
327 /* chip type specific */
328 int driver_type;
329 int playback_streams;
330 int playback_index_offset;
331 int capture_streams;
332 int capture_index_offset;
333 int num_streams;
334
335 /* pci resources */
336 unsigned long addr;
337 void __iomem *remap_addr;
338 int irq;
339
340 /* locks */
341 spinlock_t reg_lock;
342 struct mutex open_mutex;
343
344 /* streams (x num_streams) */
345 struct azx_dev *azx_dev;
346
347 /* PCM */
348 struct snd_pcm *pcm[AZX_MAX_PCMS];
349
350 /* HD codec */
351 unsigned short codec_mask;
352 struct hda_bus *bus;
353
354 /* CORB/RIRB */
355 struct azx_rb corb;
356 struct azx_rb rirb;
357
358 /* CORB/RIRB and position buffers */
359 struct snd_dma_buffer rb;
360 struct snd_dma_buffer posbuf;
361
362 /* flags */
363 int position_fix;
364 unsigned int running :1;
365 unsigned int initialized :1;
366 unsigned int single_cmd :1;
367 unsigned int polling_mode :1;
368 unsigned int msi :1;
369
370 /* for debugging */
371 unsigned int last_cmd; /* last issued command (to sync) */
372 };
373
374 /* driver types */
375 enum {
376 AZX_DRIVER_ICH,
377 AZX_DRIVER_SCH,
378 AZX_DRIVER_ATI,
379 AZX_DRIVER_ATIHDMI,
380 AZX_DRIVER_VIA,
381 AZX_DRIVER_SIS,
382 AZX_DRIVER_ULI,
383 AZX_DRIVER_NVIDIA,
384 };
385
386 static char *driver_short_names[] __devinitdata = {
387 [AZX_DRIVER_ICH] = "HDA Intel",
388 [AZX_DRIVER_SCH] = "HDA Intel MID",
389 [AZX_DRIVER_ATI] = "HDA ATI SB",
390 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
391 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
392 [AZX_DRIVER_SIS] = "HDA SIS966",
393 [AZX_DRIVER_ULI] = "HDA ULI M5461",
394 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
395 };
396
397 /*
398 * macros for easy use
399 */
400 #define azx_writel(chip,reg,value) \
401 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
402 #define azx_readl(chip,reg) \
403 readl((chip)->remap_addr + ICH6_REG_##reg)
404 #define azx_writew(chip,reg,value) \
405 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
406 #define azx_readw(chip,reg) \
407 readw((chip)->remap_addr + ICH6_REG_##reg)
408 #define azx_writeb(chip,reg,value) \
409 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
410 #define azx_readb(chip,reg) \
411 readb((chip)->remap_addr + ICH6_REG_##reg)
412
413 #define azx_sd_writel(dev,reg,value) \
414 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
415 #define azx_sd_readl(dev,reg) \
416 readl((dev)->sd_addr + ICH6_REG_##reg)
417 #define azx_sd_writew(dev,reg,value) \
418 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
419 #define azx_sd_readw(dev,reg) \
420 readw((dev)->sd_addr + ICH6_REG_##reg)
421 #define azx_sd_writeb(dev,reg,value) \
422 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
423 #define azx_sd_readb(dev,reg) \
424 readb((dev)->sd_addr + ICH6_REG_##reg)
425
426 /* for pcm support */
427 #define get_azx_dev(substream) (substream->runtime->private_data)
428
429 /* Get the upper 32bit of the given dma_addr_t
430 * Compiler should optimize and eliminate the code if dma_addr_t is 32bit
431 */
432 #define upper_32bit(addr) (sizeof(addr) > 4 ? (u32)((addr) >> 32) : (u32)0)
433
434 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
435
436 /*
437 * Interface for HD codec
438 */
439
440 /*
441 * CORB / RIRB interface
442 */
443 static int azx_alloc_cmd_io(struct azx *chip)
444 {
445 int err;
446
447 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
448 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
449 snd_dma_pci_data(chip->pci),
450 PAGE_SIZE, &chip->rb);
451 if (err < 0) {
452 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
453 return err;
454 }
455 return 0;
456 }
457
458 static void azx_init_cmd_io(struct azx *chip)
459 {
460 /* CORB set up */
461 chip->corb.addr = chip->rb.addr;
462 chip->corb.buf = (u32 *)chip->rb.area;
463 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
464 azx_writel(chip, CORBUBASE, upper_32bit(chip->corb.addr));
465
466 /* set the corb size to 256 entries (ULI requires explicitly) */
467 azx_writeb(chip, CORBSIZE, 0x02);
468 /* set the corb write pointer to 0 */
469 azx_writew(chip, CORBWP, 0);
470 /* reset the corb hw read pointer */
471 azx_writew(chip, CORBRP, ICH6_RBRWP_CLR);
472 /* enable corb dma */
473 azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN);
474
475 /* RIRB set up */
476 chip->rirb.addr = chip->rb.addr + 2048;
477 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
478 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
479 azx_writel(chip, RIRBUBASE, upper_32bit(chip->rirb.addr));
480
481 /* set the rirb size to 256 entries (ULI requires explicitly) */
482 azx_writeb(chip, RIRBSIZE, 0x02);
483 /* reset the rirb hw write pointer */
484 azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
485 /* set N=1, get RIRB response interrupt for new entry */
486 azx_writew(chip, RINTCNT, 1);
487 /* enable rirb dma and response irq */
488 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
489 chip->rirb.rp = chip->rirb.cmds = 0;
490 }
491
492 static void azx_free_cmd_io(struct azx *chip)
493 {
494 /* disable ringbuffer DMAs */
495 azx_writeb(chip, RIRBCTL, 0);
496 azx_writeb(chip, CORBCTL, 0);
497 }
498
499 /* send a command */
500 static int azx_corb_send_cmd(struct hda_codec *codec, u32 val)
501 {
502 struct azx *chip = codec->bus->private_data;
503 unsigned int wp;
504
505 /* add command to corb */
506 wp = azx_readb(chip, CORBWP);
507 wp++;
508 wp %= ICH6_MAX_CORB_ENTRIES;
509
510 spin_lock_irq(&chip->reg_lock);
511 chip->rirb.cmds++;
512 chip->corb.buf[wp] = cpu_to_le32(val);
513 azx_writel(chip, CORBWP, wp);
514 spin_unlock_irq(&chip->reg_lock);
515
516 return 0;
517 }
518
519 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
520
521 /* retrieve RIRB entry - called from interrupt handler */
522 static void azx_update_rirb(struct azx *chip)
523 {
524 unsigned int rp, wp;
525 u32 res, res_ex;
526
527 wp = azx_readb(chip, RIRBWP);
528 if (wp == chip->rirb.wp)
529 return;
530 chip->rirb.wp = wp;
531
532 while (chip->rirb.rp != wp) {
533 chip->rirb.rp++;
534 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
535
536 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
537 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
538 res = le32_to_cpu(chip->rirb.buf[rp]);
539 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
540 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
541 else if (chip->rirb.cmds) {
542 chip->rirb.res = res;
543 smp_wmb();
544 chip->rirb.cmds--;
545 }
546 }
547 }
548
549 /* receive a response */
550 static unsigned int azx_rirb_get_response(struct hda_codec *codec)
551 {
552 struct azx *chip = codec->bus->private_data;
553 unsigned long timeout;
554
555 again:
556 timeout = jiffies + msecs_to_jiffies(1000);
557 for (;;) {
558 if (chip->polling_mode) {
559 spin_lock_irq(&chip->reg_lock);
560 azx_update_rirb(chip);
561 spin_unlock_irq(&chip->reg_lock);
562 }
563 if (!chip->rirb.cmds) {
564 smp_rmb();
565 return chip->rirb.res; /* the last value */
566 }
567 if (time_after(jiffies, timeout))
568 break;
569 if (codec->bus->needs_damn_long_delay)
570 msleep(2); /* temporary workaround */
571 else {
572 udelay(10);
573 cond_resched();
574 }
575 }
576
577 if (chip->msi) {
578 snd_printk(KERN_WARNING "hda_intel: No response from codec, "
579 "disabling MSI: last cmd=0x%08x\n", chip->last_cmd);
580 free_irq(chip->irq, chip);
581 chip->irq = -1;
582 pci_disable_msi(chip->pci);
583 chip->msi = 0;
584 if (azx_acquire_irq(chip, 1) < 0)
585 return -1;
586 goto again;
587 }
588
589 if (!chip->polling_mode) {
590 snd_printk(KERN_WARNING "hda_intel: azx_get_response timeout, "
591 "switching to polling mode: last cmd=0x%08x\n",
592 chip->last_cmd);
593 chip->polling_mode = 1;
594 goto again;
595 }
596
597 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
598 "switching to single_cmd mode: last cmd=0x%08x\n",
599 chip->last_cmd);
600 chip->rirb.rp = azx_readb(chip, RIRBWP);
601 chip->rirb.cmds = 0;
602 /* switch to single_cmd mode */
603 chip->single_cmd = 1;
604 azx_free_cmd_io(chip);
605 return -1;
606 }
607
608 /*
609 * Use the single immediate command instead of CORB/RIRB for simplicity
610 *
611 * Note: according to Intel, this is not preferred use. The command was
612 * intended for the BIOS only, and may get confused with unsolicited
613 * responses. So, we shouldn't use it for normal operation from the
614 * driver.
615 * I left the codes, however, for debugging/testing purposes.
616 */
617
618 /* send a command */
619 static int azx_single_send_cmd(struct hda_codec *codec, u32 val)
620 {
621 struct azx *chip = codec->bus->private_data;
622 int timeout = 50;
623
624 while (timeout--) {
625 /* check ICB busy bit */
626 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
627 /* Clear IRV valid bit */
628 azx_writew(chip, IRS, azx_readw(chip, IRS) |
629 ICH6_IRS_VALID);
630 azx_writel(chip, IC, val);
631 azx_writew(chip, IRS, azx_readw(chip, IRS) |
632 ICH6_IRS_BUSY);
633 return 0;
634 }
635 udelay(1);
636 }
637 if (printk_ratelimit())
638 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
639 azx_readw(chip, IRS), val);
640 return -EIO;
641 }
642
643 /* receive a response */
644 static unsigned int azx_single_get_response(struct hda_codec *codec)
645 {
646 struct azx *chip = codec->bus->private_data;
647 int timeout = 50;
648
649 while (timeout--) {
650 /* check IRV busy bit */
651 if (azx_readw(chip, IRS) & ICH6_IRS_VALID)
652 return azx_readl(chip, IR);
653 udelay(1);
654 }
655 if (printk_ratelimit())
656 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
657 azx_readw(chip, IRS));
658 return (unsigned int)-1;
659 }
660
661 /*
662 * The below are the main callbacks from hda_codec.
663 *
664 * They are just the skeleton to call sub-callbacks according to the
665 * current setting of chip->single_cmd.
666 */
667
668 /* send a command */
669 static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid,
670 int direct, unsigned int verb,
671 unsigned int para)
672 {
673 struct azx *chip = codec->bus->private_data;
674 u32 val;
675
676 val = (u32)(codec->addr & 0x0f) << 28;
677 val |= (u32)direct << 27;
678 val |= (u32)nid << 20;
679 val |= verb << 8;
680 val |= para;
681 chip->last_cmd = val;
682
683 if (chip->single_cmd)
684 return azx_single_send_cmd(codec, val);
685 else
686 return azx_corb_send_cmd(codec, val);
687 }
688
689 /* get a response */
690 static unsigned int azx_get_response(struct hda_codec *codec)
691 {
692 struct azx *chip = codec->bus->private_data;
693 if (chip->single_cmd)
694 return azx_single_get_response(codec);
695 else
696 return azx_rirb_get_response(codec);
697 }
698
699 #ifdef CONFIG_SND_HDA_POWER_SAVE
700 static void azx_power_notify(struct hda_codec *codec);
701 #endif
702
703 /* reset codec link */
704 static int azx_reset(struct azx *chip)
705 {
706 int count;
707
708 /* clear STATESTS */
709 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
710
711 /* reset controller */
712 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
713
714 count = 50;
715 while (azx_readb(chip, GCTL) && --count)
716 msleep(1);
717
718 /* delay for >= 100us for codec PLL to settle per spec
719 * Rev 0.9 section 5.5.1
720 */
721 msleep(1);
722
723 /* Bring controller out of reset */
724 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
725
726 count = 50;
727 while (!azx_readb(chip, GCTL) && --count)
728 msleep(1);
729
730 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
731 msleep(1);
732
733 /* check to see if controller is ready */
734 if (!azx_readb(chip, GCTL)) {
735 snd_printd("azx_reset: controller not ready!\n");
736 return -EBUSY;
737 }
738
739 /* Accept unsolicited responses */
740 azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN);
741
742 /* detect codecs */
743 if (!chip->codec_mask) {
744 chip->codec_mask = azx_readw(chip, STATESTS);
745 snd_printdd("codec_mask = 0x%x\n", chip->codec_mask);
746 }
747
748 return 0;
749 }
750
751
752 /*
753 * Lowlevel interface
754 */
755
756 /* enable interrupts */
757 static void azx_int_enable(struct azx *chip)
758 {
759 /* enable controller CIE and GIE */
760 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
761 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
762 }
763
764 /* disable interrupts */
765 static void azx_int_disable(struct azx *chip)
766 {
767 int i;
768
769 /* disable interrupts in stream descriptor */
770 for (i = 0; i < chip->num_streams; i++) {
771 struct azx_dev *azx_dev = &chip->azx_dev[i];
772 azx_sd_writeb(azx_dev, SD_CTL,
773 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
774 }
775
776 /* disable SIE for all streams */
777 azx_writeb(chip, INTCTL, 0);
778
779 /* disable controller CIE and GIE */
780 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
781 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
782 }
783
784 /* clear interrupts */
785 static void azx_int_clear(struct azx *chip)
786 {
787 int i;
788
789 /* clear stream status */
790 for (i = 0; i < chip->num_streams; i++) {
791 struct azx_dev *azx_dev = &chip->azx_dev[i];
792 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
793 }
794
795 /* clear STATESTS */
796 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
797
798 /* clear rirb status */
799 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
800
801 /* clear int status */
802 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
803 }
804
805 /* start a stream */
806 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
807 {
808 /* enable SIE */
809 azx_writeb(chip, INTCTL,
810 azx_readb(chip, INTCTL) | (1 << azx_dev->index));
811 /* set DMA start and interrupt mask */
812 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
813 SD_CTL_DMA_START | SD_INT_MASK);
814 }
815
816 /* stop a stream */
817 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
818 {
819 /* stop DMA */
820 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
821 ~(SD_CTL_DMA_START | SD_INT_MASK));
822 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
823 /* disable SIE */
824 azx_writeb(chip, INTCTL,
825 azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
826 }
827
828
829 /*
830 * reset and start the controller registers
831 */
832 static void azx_init_chip(struct azx *chip)
833 {
834 if (chip->initialized)
835 return;
836
837 /* reset controller */
838 azx_reset(chip);
839
840 /* initialize interrupts */
841 azx_int_clear(chip);
842 azx_int_enable(chip);
843
844 /* initialize the codec command I/O */
845 if (!chip->single_cmd)
846 azx_init_cmd_io(chip);
847
848 /* program the position buffer */
849 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
850 azx_writel(chip, DPUBASE, upper_32bit(chip->posbuf.addr));
851
852 chip->initialized = 1;
853 }
854
855 /*
856 * initialize the PCI registers
857 */
858 /* update bits in a PCI register byte */
859 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
860 unsigned char mask, unsigned char val)
861 {
862 unsigned char data;
863
864 pci_read_config_byte(pci, reg, &data);
865 data &= ~mask;
866 data |= (val & mask);
867 pci_write_config_byte(pci, reg, data);
868 }
869
870 static void azx_init_pci(struct azx *chip)
871 {
872 unsigned short snoop;
873
874 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
875 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
876 * Ensuring these bits are 0 clears playback static on some HD Audio
877 * codecs
878 */
879 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
880
881 switch (chip->driver_type) {
882 case AZX_DRIVER_ATI:
883 /* For ATI SB450 azalia HD audio, we need to enable snoop */
884 update_pci_byte(chip->pci,
885 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
886 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
887 break;
888 case AZX_DRIVER_NVIDIA:
889 /* For NVIDIA HDA, enable snoop */
890 update_pci_byte(chip->pci,
891 NVIDIA_HDA_TRANSREG_ADDR,
892 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
893 break;
894 case AZX_DRIVER_SCH:
895 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
896 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
897 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, \
898 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
899 pci_read_config_word(chip->pci,
900 INTEL_SCH_HDA_DEVC, &snoop);
901 snd_printdd("HDA snoop disabled, enabling ... %s\n",\
902 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) \
903 ? "Failed" : "OK");
904 }
905 break;
906
907 }
908 }
909
910
911 /*
912 * interrupt handler
913 */
914 static irqreturn_t azx_interrupt(int irq, void *dev_id)
915 {
916 struct azx *chip = dev_id;
917 struct azx_dev *azx_dev;
918 u32 status;
919 int i;
920
921 spin_lock(&chip->reg_lock);
922
923 status = azx_readl(chip, INTSTS);
924 if (status == 0) {
925 spin_unlock(&chip->reg_lock);
926 return IRQ_NONE;
927 }
928
929 for (i = 0; i < chip->num_streams; i++) {
930 azx_dev = &chip->azx_dev[i];
931 if (status & azx_dev->sd_int_sta_mask) {
932 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
933 if (azx_dev->substream && azx_dev->running) {
934 azx_dev->period_intr++;
935 spin_unlock(&chip->reg_lock);
936 snd_pcm_period_elapsed(azx_dev->substream);
937 spin_lock(&chip->reg_lock);
938 }
939 }
940 }
941
942 /* clear rirb int */
943 status = azx_readb(chip, RIRBSTS);
944 if (status & RIRB_INT_MASK) {
945 if (!chip->single_cmd && (status & RIRB_INT_RESPONSE))
946 azx_update_rirb(chip);
947 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
948 }
949
950 #if 0
951 /* clear state status int */
952 if (azx_readb(chip, STATESTS) & 0x04)
953 azx_writeb(chip, STATESTS, 0x04);
954 #endif
955 spin_unlock(&chip->reg_lock);
956
957 return IRQ_HANDLED;
958 }
959
960
961 /*
962 * set up BDL entries
963 */
964 static int azx_setup_periods(struct snd_pcm_substream *substream,
965 struct azx_dev *azx_dev)
966 {
967 struct snd_sg_buf *sgbuf = snd_pcm_substream_sgbuf(substream);
968 u32 *bdl;
969 int i, ofs, periods, period_bytes;
970
971 /* reset BDL address */
972 azx_sd_writel(azx_dev, SD_BDLPL, 0);
973 azx_sd_writel(azx_dev, SD_BDLPU, 0);
974
975 period_bytes = snd_pcm_lib_period_bytes(substream);
976 periods = azx_dev->bufsize / period_bytes;
977
978 /* program the initial BDL entries */
979 bdl = (u32 *)azx_dev->bdl.area;
980 ofs = 0;
981 azx_dev->frags = 0;
982 for (i = 0; i < periods; i++) {
983 int size, rest;
984 if (i >= AZX_MAX_BDL_ENTRIES) {
985 snd_printk(KERN_ERR "Too many BDL entries: "
986 "buffer=%d, period=%d\n",
987 azx_dev->bufsize, period_bytes);
988 /* reset */
989 azx_sd_writel(azx_dev, SD_BDLPL, 0);
990 azx_sd_writel(azx_dev, SD_BDLPU, 0);
991 return -EINVAL;
992 }
993 rest = period_bytes;
994 do {
995 dma_addr_t addr = snd_pcm_sgbuf_get_addr(sgbuf, ofs);
996 /* program the address field of the BDL entry */
997 bdl[0] = cpu_to_le32((u32)addr);
998 bdl[1] = cpu_to_le32(upper_32bit(addr));
999 /* program the size field of the BDL entry */
1000 size = PAGE_SIZE - (ofs % PAGE_SIZE);
1001 if (rest < size)
1002 size = rest;
1003 bdl[2] = cpu_to_le32(size);
1004 /* program the IOC to enable interrupt
1005 * only when the whole fragment is processed
1006 */
1007 rest -= size;
1008 bdl[3] = rest ? 0 : cpu_to_le32(0x01);
1009 bdl += 4;
1010 azx_dev->frags++;
1011 ofs += size;
1012 } while (rest > 0);
1013 }
1014 return 0;
1015 }
1016
1017 /*
1018 * set up the SD for streaming
1019 */
1020 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1021 {
1022 unsigned char val;
1023 int timeout;
1024
1025 /* make sure the run bit is zero for SD */
1026 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1027 ~SD_CTL_DMA_START);
1028 /* reset stream */
1029 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1030 SD_CTL_STREAM_RESET);
1031 udelay(3);
1032 timeout = 300;
1033 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1034 --timeout)
1035 ;
1036 val &= ~SD_CTL_STREAM_RESET;
1037 azx_sd_writeb(azx_dev, SD_CTL, val);
1038 udelay(3);
1039
1040 timeout = 300;
1041 /* waiting for hardware to report that the stream is out of reset */
1042 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1043 --timeout)
1044 ;
1045
1046 /* program the stream_tag */
1047 azx_sd_writel(azx_dev, SD_CTL,
1048 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1049 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1050
1051 /* program the length of samples in cyclic buffer */
1052 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1053
1054 /* program the stream format */
1055 /* this value needs to be the same as the one programmed */
1056 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1057
1058 /* program the stream LVI (last valid index) of the BDL */
1059 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1060
1061 /* program the BDL address */
1062 /* lower BDL address */
1063 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1064 /* upper BDL address */
1065 azx_sd_writel(azx_dev, SD_BDLPU, upper_32bit(azx_dev->bdl.addr));
1066
1067 /* enable the position buffer */
1068 if (chip->position_fix == POS_FIX_POSBUF ||
1069 chip->position_fix == POS_FIX_AUTO) {
1070 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1071 azx_writel(chip, DPLBASE,
1072 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1073 }
1074
1075 /* set the interrupt enable bits in the descriptor control register */
1076 azx_sd_writel(azx_dev, SD_CTL,
1077 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1078
1079 return 0;
1080 }
1081
1082
1083 /*
1084 * Codec initialization
1085 */
1086
1087 static unsigned int azx_max_codecs[] __devinitdata = {
1088 [AZX_DRIVER_ICH] = 3,
1089 [AZX_DRIVER_SCH] = 3,
1090 [AZX_DRIVER_ATI] = 4,
1091 [AZX_DRIVER_ATIHDMI] = 4,
1092 [AZX_DRIVER_VIA] = 3, /* FIXME: correct? */
1093 [AZX_DRIVER_SIS] = 3, /* FIXME: correct? */
1094 [AZX_DRIVER_ULI] = 3, /* FIXME: correct? */
1095 [AZX_DRIVER_NVIDIA] = 3, /* FIXME: correct? */
1096 };
1097
1098 static int __devinit azx_codec_create(struct azx *chip, const char *model,
1099 unsigned int codec_probe_mask)
1100 {
1101 struct hda_bus_template bus_temp;
1102 int c, codecs, audio_codecs, err;
1103
1104 memset(&bus_temp, 0, sizeof(bus_temp));
1105 bus_temp.private_data = chip;
1106 bus_temp.modelname = model;
1107 bus_temp.pci = chip->pci;
1108 bus_temp.ops.command = azx_send_cmd;
1109 bus_temp.ops.get_response = azx_get_response;
1110 #ifdef CONFIG_SND_HDA_POWER_SAVE
1111 bus_temp.ops.pm_notify = azx_power_notify;
1112 #endif
1113
1114 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1115 if (err < 0)
1116 return err;
1117
1118 codecs = audio_codecs = 0;
1119 for (c = 0; c < AZX_MAX_CODECS; c++) {
1120 if ((chip->codec_mask & (1 << c)) & codec_probe_mask) {
1121 struct hda_codec *codec;
1122 err = snd_hda_codec_new(chip->bus, c, &codec);
1123 if (err < 0)
1124 continue;
1125 codecs++;
1126 if (codec->afg)
1127 audio_codecs++;
1128 }
1129 }
1130 if (!audio_codecs) {
1131 /* probe additional slots if no codec is found */
1132 for (; c < azx_max_codecs[chip->driver_type]; c++) {
1133 if ((chip->codec_mask & (1 << c)) & codec_probe_mask) {
1134 err = snd_hda_codec_new(chip->bus, c, NULL);
1135 if (err < 0)
1136 continue;
1137 codecs++;
1138 }
1139 }
1140 }
1141 if (!codecs) {
1142 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1143 return -ENXIO;
1144 }
1145
1146 return 0;
1147 }
1148
1149
1150 /*
1151 * PCM support
1152 */
1153
1154 /* assign a stream for the PCM */
1155 static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
1156 {
1157 int dev, i, nums;
1158 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1159 dev = chip->playback_index_offset;
1160 nums = chip->playback_streams;
1161 } else {
1162 dev = chip->capture_index_offset;
1163 nums = chip->capture_streams;
1164 }
1165 for (i = 0; i < nums; i++, dev++)
1166 if (!chip->azx_dev[dev].opened) {
1167 chip->azx_dev[dev].opened = 1;
1168 return &chip->azx_dev[dev];
1169 }
1170 return NULL;
1171 }
1172
1173 /* release the assigned stream */
1174 static inline void azx_release_device(struct azx_dev *azx_dev)
1175 {
1176 azx_dev->opened = 0;
1177 }
1178
1179 static struct snd_pcm_hardware azx_pcm_hw = {
1180 .info = (SNDRV_PCM_INFO_MMAP |
1181 SNDRV_PCM_INFO_INTERLEAVED |
1182 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1183 SNDRV_PCM_INFO_MMAP_VALID |
1184 /* No full-resume yet implemented */
1185 /* SNDRV_PCM_INFO_RESUME |*/
1186 SNDRV_PCM_INFO_PAUSE |
1187 SNDRV_PCM_INFO_SYNC_START),
1188 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1189 .rates = SNDRV_PCM_RATE_48000,
1190 .rate_min = 48000,
1191 .rate_max = 48000,
1192 .channels_min = 2,
1193 .channels_max = 2,
1194 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1195 .period_bytes_min = 128,
1196 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1197 .periods_min = 2,
1198 .periods_max = AZX_MAX_FRAG,
1199 .fifo_size = 0,
1200 };
1201
1202 struct azx_pcm {
1203 struct azx *chip;
1204 struct hda_codec *codec;
1205 struct hda_pcm_stream *hinfo[2];
1206 };
1207
1208 static int azx_pcm_open(struct snd_pcm_substream *substream)
1209 {
1210 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1211 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1212 struct azx *chip = apcm->chip;
1213 struct azx_dev *azx_dev;
1214 struct snd_pcm_runtime *runtime = substream->runtime;
1215 unsigned long flags;
1216 int err;
1217
1218 mutex_lock(&chip->open_mutex);
1219 azx_dev = azx_assign_device(chip, substream->stream);
1220 if (azx_dev == NULL) {
1221 mutex_unlock(&chip->open_mutex);
1222 return -EBUSY;
1223 }
1224 runtime->hw = azx_pcm_hw;
1225 runtime->hw.channels_min = hinfo->channels_min;
1226 runtime->hw.channels_max = hinfo->channels_max;
1227 runtime->hw.formats = hinfo->formats;
1228 runtime->hw.rates = hinfo->rates;
1229 snd_pcm_limit_hw_rates(runtime);
1230 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1231 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1232 128);
1233 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1234 128);
1235 snd_hda_power_up(apcm->codec);
1236 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1237 if (err < 0) {
1238 azx_release_device(azx_dev);
1239 snd_hda_power_down(apcm->codec);
1240 mutex_unlock(&chip->open_mutex);
1241 return err;
1242 }
1243 spin_lock_irqsave(&chip->reg_lock, flags);
1244 azx_dev->substream = substream;
1245 azx_dev->running = 0;
1246 spin_unlock_irqrestore(&chip->reg_lock, flags);
1247
1248 runtime->private_data = azx_dev;
1249 snd_pcm_set_sync(substream);
1250 mutex_unlock(&chip->open_mutex);
1251 return 0;
1252 }
1253
1254 static int azx_pcm_close(struct snd_pcm_substream *substream)
1255 {
1256 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1257 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1258 struct azx *chip = apcm->chip;
1259 struct azx_dev *azx_dev = get_azx_dev(substream);
1260 unsigned long flags;
1261
1262 mutex_lock(&chip->open_mutex);
1263 spin_lock_irqsave(&chip->reg_lock, flags);
1264 azx_dev->substream = NULL;
1265 azx_dev->running = 0;
1266 spin_unlock_irqrestore(&chip->reg_lock, flags);
1267 azx_release_device(azx_dev);
1268 hinfo->ops.close(hinfo, apcm->codec, substream);
1269 snd_hda_power_down(apcm->codec);
1270 mutex_unlock(&chip->open_mutex);
1271 return 0;
1272 }
1273
1274 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1275 struct snd_pcm_hw_params *hw_params)
1276 {
1277 return snd_pcm_lib_malloc_pages(substream,
1278 params_buffer_bytes(hw_params));
1279 }
1280
1281 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1282 {
1283 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1284 struct azx_dev *azx_dev = get_azx_dev(substream);
1285 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1286
1287 /* reset BDL address */
1288 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1289 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1290 azx_sd_writel(azx_dev, SD_CTL, 0);
1291
1292 hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1293
1294 return snd_pcm_lib_free_pages(substream);
1295 }
1296
1297 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1298 {
1299 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1300 struct azx *chip = apcm->chip;
1301 struct azx_dev *azx_dev = get_azx_dev(substream);
1302 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1303 struct snd_pcm_runtime *runtime = substream->runtime;
1304
1305 azx_dev->bufsize = snd_pcm_lib_buffer_bytes(substream);
1306 azx_dev->format_val = snd_hda_calc_stream_format(runtime->rate,
1307 runtime->channels,
1308 runtime->format,
1309 hinfo->maxbps);
1310 if (!azx_dev->format_val) {
1311 snd_printk(KERN_ERR SFX
1312 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1313 runtime->rate, runtime->channels, runtime->format);
1314 return -EINVAL;
1315 }
1316
1317 snd_printdd("azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1318 azx_dev->bufsize, azx_dev->format_val);
1319 if (azx_setup_periods(substream, azx_dev) < 0)
1320 return -EINVAL;
1321 azx_setup_controller(chip, azx_dev);
1322 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1323 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1324 else
1325 azx_dev->fifo_size = 0;
1326
1327 return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1328 azx_dev->format_val, substream);
1329 }
1330
1331 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1332 {
1333 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1334 struct azx *chip = apcm->chip;
1335 struct azx_dev *azx_dev;
1336 struct snd_pcm_substream *s;
1337 int start, nsync = 0, sbits = 0;
1338 int nwait, timeout;
1339
1340 switch (cmd) {
1341 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1342 case SNDRV_PCM_TRIGGER_RESUME:
1343 case SNDRV_PCM_TRIGGER_START:
1344 start = 1;
1345 break;
1346 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1347 case SNDRV_PCM_TRIGGER_SUSPEND:
1348 case SNDRV_PCM_TRIGGER_STOP:
1349 start = 0;
1350 break;
1351 default:
1352 return -EINVAL;
1353 }
1354
1355 snd_pcm_group_for_each_entry(s, substream) {
1356 if (s->pcm->card != substream->pcm->card)
1357 continue;
1358 azx_dev = get_azx_dev(s);
1359 sbits |= 1 << azx_dev->index;
1360 nsync++;
1361 snd_pcm_trigger_done(s, substream);
1362 }
1363
1364 spin_lock(&chip->reg_lock);
1365 if (nsync > 1) {
1366 /* first, set SYNC bits of corresponding streams */
1367 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1368 }
1369 snd_pcm_group_for_each_entry(s, substream) {
1370 if (s->pcm->card != substream->pcm->card)
1371 continue;
1372 azx_dev = get_azx_dev(s);
1373 if (start)
1374 azx_stream_start(chip, azx_dev);
1375 else
1376 azx_stream_stop(chip, azx_dev);
1377 azx_dev->running = start;
1378 }
1379 spin_unlock(&chip->reg_lock);
1380 if (start) {
1381 if (nsync == 1)
1382 return 0;
1383 /* wait until all FIFOs get ready */
1384 for (timeout = 5000; timeout; timeout--) {
1385 nwait = 0;
1386 snd_pcm_group_for_each_entry(s, substream) {
1387 if (s->pcm->card != substream->pcm->card)
1388 continue;
1389 azx_dev = get_azx_dev(s);
1390 if (!(azx_sd_readb(azx_dev, SD_STS) &
1391 SD_STS_FIFO_READY))
1392 nwait++;
1393 }
1394 if (!nwait)
1395 break;
1396 cpu_relax();
1397 }
1398 } else {
1399 /* wait until all RUN bits are cleared */
1400 for (timeout = 5000; timeout; timeout--) {
1401 nwait = 0;
1402 snd_pcm_group_for_each_entry(s, substream) {
1403 if (s->pcm->card != substream->pcm->card)
1404 continue;
1405 azx_dev = get_azx_dev(s);
1406 if (azx_sd_readb(azx_dev, SD_CTL) &
1407 SD_CTL_DMA_START)
1408 nwait++;
1409 }
1410 if (!nwait)
1411 break;
1412 cpu_relax();
1413 }
1414 }
1415 if (nsync > 1) {
1416 spin_lock(&chip->reg_lock);
1417 /* reset SYNC bits */
1418 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1419 spin_unlock(&chip->reg_lock);
1420 }
1421 return 0;
1422 }
1423
1424 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1425 {
1426 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1427 struct azx *chip = apcm->chip;
1428 struct azx_dev *azx_dev = get_azx_dev(substream);
1429 unsigned int pos;
1430
1431 if (chip->position_fix == POS_FIX_POSBUF ||
1432 chip->position_fix == POS_FIX_AUTO) {
1433 /* use the position buffer */
1434 pos = le32_to_cpu(*azx_dev->posbuf);
1435 if (chip->position_fix == POS_FIX_AUTO &&
1436 azx_dev->period_intr == 1 && !pos) {
1437 printk(KERN_WARNING
1438 "hda-intel: Invalid position buffer, "
1439 "using LPIB read method instead.\n");
1440 chip->position_fix = POS_FIX_NONE;
1441 goto read_lpib;
1442 }
1443 } else {
1444 read_lpib:
1445 /* read LPIB */
1446 pos = azx_sd_readl(azx_dev, SD_LPIB);
1447 if (chip->position_fix == POS_FIX_FIFO)
1448 pos += azx_dev->fifo_size;
1449 }
1450 if (pos >= azx_dev->bufsize)
1451 pos = 0;
1452 return bytes_to_frames(substream->runtime, pos);
1453 }
1454
1455 static struct snd_pcm_ops azx_pcm_ops = {
1456 .open = azx_pcm_open,
1457 .close = azx_pcm_close,
1458 .ioctl = snd_pcm_lib_ioctl,
1459 .hw_params = azx_pcm_hw_params,
1460 .hw_free = azx_pcm_hw_free,
1461 .prepare = azx_pcm_prepare,
1462 .trigger = azx_pcm_trigger,
1463 .pointer = azx_pcm_pointer,
1464 .page = snd_pcm_sgbuf_ops_page,
1465 };
1466
1467 static void azx_pcm_free(struct snd_pcm *pcm)
1468 {
1469 kfree(pcm->private_data);
1470 }
1471
1472 static int __devinit create_codec_pcm(struct azx *chip, struct hda_codec *codec,
1473 struct hda_pcm *cpcm)
1474 {
1475 int err;
1476 struct snd_pcm *pcm;
1477 struct azx_pcm *apcm;
1478
1479 /* if no substreams are defined for both playback and capture,
1480 * it's just a placeholder. ignore it.
1481 */
1482 if (!cpcm->stream[0].substreams && !cpcm->stream[1].substreams)
1483 return 0;
1484
1485 snd_assert(cpcm->name, return -EINVAL);
1486
1487 err = snd_pcm_new(chip->card, cpcm->name, cpcm->device,
1488 cpcm->stream[0].substreams,
1489 cpcm->stream[1].substreams,
1490 &pcm);
1491 if (err < 0)
1492 return err;
1493 strcpy(pcm->name, cpcm->name);
1494 apcm = kmalloc(sizeof(*apcm), GFP_KERNEL);
1495 if (apcm == NULL)
1496 return -ENOMEM;
1497 apcm->chip = chip;
1498 apcm->codec = codec;
1499 apcm->hinfo[0] = &cpcm->stream[0];
1500 apcm->hinfo[1] = &cpcm->stream[1];
1501 pcm->private_data = apcm;
1502 pcm->private_free = azx_pcm_free;
1503 if (cpcm->stream[0].substreams)
1504 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &azx_pcm_ops);
1505 if (cpcm->stream[1].substreams)
1506 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &azx_pcm_ops);
1507 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1508 snd_dma_pci_data(chip->pci),
1509 1024 * 64, 1024 * 1024);
1510 chip->pcm[cpcm->device] = pcm;
1511 return 0;
1512 }
1513
1514 static int __devinit azx_pcm_create(struct azx *chip)
1515 {
1516 static const char *dev_name[HDA_PCM_NTYPES] = {
1517 "Audio", "SPDIF", "HDMI", "Modem"
1518 };
1519 /* starting device index for each PCM type */
1520 static int dev_idx[HDA_PCM_NTYPES] = {
1521 [HDA_PCM_TYPE_AUDIO] = 0,
1522 [HDA_PCM_TYPE_SPDIF] = 1,
1523 [HDA_PCM_TYPE_HDMI] = 3,
1524 [HDA_PCM_TYPE_MODEM] = 6
1525 };
1526 /* normal audio device indices; not linear to keep compatibility */
1527 static int audio_idx[4] = { 0, 2, 4, 5 };
1528 struct hda_codec *codec;
1529 int c, err;
1530 int num_devs[HDA_PCM_NTYPES];
1531
1532 err = snd_hda_build_pcms(chip->bus);
1533 if (err < 0)
1534 return err;
1535
1536 /* create audio PCMs */
1537 memset(num_devs, 0, sizeof(num_devs));
1538 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1539 for (c = 0; c < codec->num_pcms; c++) {
1540 struct hda_pcm *cpcm = &codec->pcm_info[c];
1541 int type = cpcm->pcm_type;
1542 switch (type) {
1543 case HDA_PCM_TYPE_AUDIO:
1544 if (num_devs[type] >= ARRAY_SIZE(audio_idx)) {
1545 snd_printk(KERN_WARNING
1546 "Too many audio devices\n");
1547 continue;
1548 }
1549 cpcm->device = audio_idx[num_devs[type]];
1550 break;
1551 case HDA_PCM_TYPE_SPDIF:
1552 case HDA_PCM_TYPE_HDMI:
1553 case HDA_PCM_TYPE_MODEM:
1554 if (num_devs[type]) {
1555 snd_printk(KERN_WARNING
1556 "%s already defined\n",
1557 dev_name[type]);
1558 continue;
1559 }
1560 cpcm->device = dev_idx[type];
1561 break;
1562 default:
1563 snd_printk(KERN_WARNING
1564 "Invalid PCM type %d\n", type);
1565 continue;
1566 }
1567 num_devs[type]++;
1568 err = create_codec_pcm(chip, codec, cpcm);
1569 if (err < 0)
1570 return err;
1571 }
1572 }
1573 return 0;
1574 }
1575
1576 /*
1577 * mixer creation - all stuff is implemented in hda module
1578 */
1579 static int __devinit azx_mixer_create(struct azx *chip)
1580 {
1581 return snd_hda_build_controls(chip->bus);
1582 }
1583
1584
1585 /*
1586 * initialize SD streams
1587 */
1588 static int __devinit azx_init_stream(struct azx *chip)
1589 {
1590 int i;
1591
1592 /* initialize each stream (aka device)
1593 * assign the starting bdl address to each stream (device)
1594 * and initialize
1595 */
1596 for (i = 0; i < chip->num_streams; i++) {
1597 struct azx_dev *azx_dev = &chip->azx_dev[i];
1598 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1599 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1600 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1601 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1602 azx_dev->sd_int_sta_mask = 1 << i;
1603 /* stream tag: must be non-zero and unique */
1604 azx_dev->index = i;
1605 azx_dev->stream_tag = i + 1;
1606 }
1607
1608 return 0;
1609 }
1610
1611 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
1612 {
1613 if (request_irq(chip->pci->irq, azx_interrupt,
1614 chip->msi ? 0 : IRQF_SHARED,
1615 "HDA Intel", chip)) {
1616 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
1617 "disabling device\n", chip->pci->irq);
1618 if (do_disconnect)
1619 snd_card_disconnect(chip->card);
1620 return -1;
1621 }
1622 chip->irq = chip->pci->irq;
1623 pci_intx(chip->pci, !chip->msi);
1624 return 0;
1625 }
1626
1627
1628 static void azx_stop_chip(struct azx *chip)
1629 {
1630 if (!chip->initialized)
1631 return;
1632
1633 /* disable interrupts */
1634 azx_int_disable(chip);
1635 azx_int_clear(chip);
1636
1637 /* disable CORB/RIRB */
1638 azx_free_cmd_io(chip);
1639
1640 /* disable position buffer */
1641 azx_writel(chip, DPLBASE, 0);
1642 azx_writel(chip, DPUBASE, 0);
1643
1644 chip->initialized = 0;
1645 }
1646
1647 #ifdef CONFIG_SND_HDA_POWER_SAVE
1648 /* power-up/down the controller */
1649 static void azx_power_notify(struct hda_codec *codec)
1650 {
1651 struct azx *chip = codec->bus->private_data;
1652 struct hda_codec *c;
1653 int power_on = 0;
1654
1655 list_for_each_entry(c, &codec->bus->codec_list, list) {
1656 if (c->power_on) {
1657 power_on = 1;
1658 break;
1659 }
1660 }
1661 if (power_on)
1662 azx_init_chip(chip);
1663 else if (chip->running && power_save_controller)
1664 azx_stop_chip(chip);
1665 }
1666 #endif /* CONFIG_SND_HDA_POWER_SAVE */
1667
1668 #ifdef CONFIG_PM
1669 /*
1670 * power management
1671 */
1672 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
1673 {
1674 struct snd_card *card = pci_get_drvdata(pci);
1675 struct azx *chip = card->private_data;
1676 int i;
1677
1678 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1679 for (i = 0; i < AZX_MAX_PCMS; i++)
1680 snd_pcm_suspend_all(chip->pcm[i]);
1681 if (chip->initialized)
1682 snd_hda_suspend(chip->bus, state);
1683 azx_stop_chip(chip);
1684 if (chip->irq >= 0) {
1685 free_irq(chip->irq, chip);
1686 chip->irq = -1;
1687 }
1688 if (chip->msi)
1689 pci_disable_msi(chip->pci);
1690 pci_disable_device(pci);
1691 pci_save_state(pci);
1692 pci_set_power_state(pci, pci_choose_state(pci, state));
1693 return 0;
1694 }
1695
1696 static int azx_resume(struct pci_dev *pci)
1697 {
1698 struct snd_card *card = pci_get_drvdata(pci);
1699 struct azx *chip = card->private_data;
1700
1701 pci_set_power_state(pci, PCI_D0);
1702 pci_restore_state(pci);
1703 if (pci_enable_device(pci) < 0) {
1704 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
1705 "disabling device\n");
1706 snd_card_disconnect(card);
1707 return -EIO;
1708 }
1709 pci_set_master(pci);
1710 if (chip->msi)
1711 if (pci_enable_msi(pci) < 0)
1712 chip->msi = 0;
1713 if (azx_acquire_irq(chip, 1) < 0)
1714 return -EIO;
1715 azx_init_pci(chip);
1716
1717 if (snd_hda_codecs_inuse(chip->bus))
1718 azx_init_chip(chip);
1719
1720 snd_hda_resume(chip->bus);
1721 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1722 return 0;
1723 }
1724 #endif /* CONFIG_PM */
1725
1726
1727 /*
1728 * destructor
1729 */
1730 static int azx_free(struct azx *chip)
1731 {
1732 int i;
1733
1734 if (chip->initialized) {
1735 for (i = 0; i < chip->num_streams; i++)
1736 azx_stream_stop(chip, &chip->azx_dev[i]);
1737 azx_stop_chip(chip);
1738 }
1739
1740 if (chip->irq >= 0)
1741 free_irq(chip->irq, (void*)chip);
1742 if (chip->msi)
1743 pci_disable_msi(chip->pci);
1744 if (chip->remap_addr)
1745 iounmap(chip->remap_addr);
1746
1747 if (chip->azx_dev) {
1748 for (i = 0; i < chip->num_streams; i++)
1749 if (chip->azx_dev[i].bdl.area)
1750 snd_dma_free_pages(&chip->azx_dev[i].bdl);
1751 }
1752 if (chip->rb.area)
1753 snd_dma_free_pages(&chip->rb);
1754 if (chip->posbuf.area)
1755 snd_dma_free_pages(&chip->posbuf);
1756 pci_release_regions(chip->pci);
1757 pci_disable_device(chip->pci);
1758 kfree(chip->azx_dev);
1759 kfree(chip);
1760
1761 return 0;
1762 }
1763
1764 static int azx_dev_free(struct snd_device *device)
1765 {
1766 return azx_free(device->device_data);
1767 }
1768
1769 /*
1770 * white/black-listing for position_fix
1771 */
1772 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
1773 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_NONE),
1774 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_NONE),
1775 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_NONE),
1776 {}
1777 };
1778
1779 static int __devinit check_position_fix(struct azx *chip, int fix)
1780 {
1781 const struct snd_pci_quirk *q;
1782
1783 if (fix == POS_FIX_AUTO) {
1784 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1785 if (q) {
1786 printk(KERN_INFO
1787 "hda_intel: position_fix set to %d "
1788 "for device %04x:%04x\n",
1789 q->value, q->subvendor, q->subdevice);
1790 return q->value;
1791 }
1792 }
1793 return fix;
1794 }
1795
1796 /*
1797 * black-lists for probe_mask
1798 */
1799 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
1800 /* Thinkpad often breaks the controller communication when accessing
1801 * to the non-working (or non-existing) modem codec slot.
1802 */
1803 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1804 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1805 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1806 {}
1807 };
1808
1809 static void __devinit check_probe_mask(struct azx *chip, int dev)
1810 {
1811 const struct snd_pci_quirk *q;
1812
1813 if (probe_mask[dev] == -1) {
1814 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1815 if (q) {
1816 printk(KERN_INFO
1817 "hda_intel: probe_mask set to 0x%x "
1818 "for device %04x:%04x\n",
1819 q->value, q->subvendor, q->subdevice);
1820 probe_mask[dev] = q->value;
1821 }
1822 }
1823 }
1824
1825
1826 /*
1827 * constructor
1828 */
1829 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
1830 int dev, int driver_type,
1831 struct azx **rchip)
1832 {
1833 struct azx *chip;
1834 int i, err;
1835 unsigned short gcap;
1836 static struct snd_device_ops ops = {
1837 .dev_free = azx_dev_free,
1838 };
1839
1840 *rchip = NULL;
1841
1842 err = pci_enable_device(pci);
1843 if (err < 0)
1844 return err;
1845
1846 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1847 if (!chip) {
1848 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
1849 pci_disable_device(pci);
1850 return -ENOMEM;
1851 }
1852
1853 spin_lock_init(&chip->reg_lock);
1854 mutex_init(&chip->open_mutex);
1855 chip->card = card;
1856 chip->pci = pci;
1857 chip->irq = -1;
1858 chip->driver_type = driver_type;
1859 chip->msi = enable_msi;
1860
1861 chip->position_fix = check_position_fix(chip, position_fix[dev]);
1862 check_probe_mask(chip, dev);
1863
1864 chip->single_cmd = single_cmd;
1865
1866 #if BITS_PER_LONG != 64
1867 /* Fix up base address on ULI M5461 */
1868 if (chip->driver_type == AZX_DRIVER_ULI) {
1869 u16 tmp3;
1870 pci_read_config_word(pci, 0x40, &tmp3);
1871 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1872 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1873 }
1874 #endif
1875
1876 err = pci_request_regions(pci, "ICH HD audio");
1877 if (err < 0) {
1878 kfree(chip);
1879 pci_disable_device(pci);
1880 return err;
1881 }
1882
1883 chip->addr = pci_resource_start(pci, 0);
1884 chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci,0));
1885 if (chip->remap_addr == NULL) {
1886 snd_printk(KERN_ERR SFX "ioremap error\n");
1887 err = -ENXIO;
1888 goto errout;
1889 }
1890
1891 if (chip->msi)
1892 if (pci_enable_msi(pci) < 0)
1893 chip->msi = 0;
1894
1895 if (azx_acquire_irq(chip, 0) < 0) {
1896 err = -EBUSY;
1897 goto errout;
1898 }
1899
1900 pci_set_master(pci);
1901 synchronize_irq(chip->irq);
1902
1903 gcap = azx_readw(chip, GCAP);
1904 snd_printdd("chipset global capabilities = 0x%x\n", gcap);
1905
1906 /* allow 64bit DMA address if supported by H/W */
1907 if ((gcap & 0x01) && !pci_set_dma_mask(pci, DMA_64BIT_MASK))
1908 pci_set_consistent_dma_mask(pci, DMA_64BIT_MASK);
1909
1910 /* read number of streams from GCAP register instead of using
1911 * hardcoded value
1912 */
1913 chip->capture_streams = (gcap >> 8) & 0x0f;
1914 chip->playback_streams = (gcap >> 12) & 0x0f;
1915 if (!chip->playback_streams && !chip->capture_streams) {
1916 /* gcap didn't give any info, switching to old method */
1917
1918 switch (chip->driver_type) {
1919 case AZX_DRIVER_ULI:
1920 chip->playback_streams = ULI_NUM_PLAYBACK;
1921 chip->capture_streams = ULI_NUM_CAPTURE;
1922 break;
1923 case AZX_DRIVER_ATIHDMI:
1924 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1925 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1926 break;
1927 default:
1928 chip->playback_streams = ICH6_NUM_PLAYBACK;
1929 chip->capture_streams = ICH6_NUM_CAPTURE;
1930 break;
1931 }
1932 }
1933 chip->capture_index_offset = 0;
1934 chip->playback_index_offset = chip->capture_streams;
1935 chip->num_streams = chip->playback_streams + chip->capture_streams;
1936 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
1937 GFP_KERNEL);
1938 if (!chip->azx_dev) {
1939 snd_printk(KERN_ERR "cannot malloc azx_dev\n");
1940 goto errout;
1941 }
1942
1943 for (i = 0; i < chip->num_streams; i++) {
1944 /* allocate memory for the BDL for each stream */
1945 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
1946 snd_dma_pci_data(chip->pci),
1947 BDL_SIZE, &chip->azx_dev[i].bdl);
1948 if (err < 0) {
1949 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
1950 goto errout;
1951 }
1952 }
1953 /* allocate memory for the position buffer */
1954 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
1955 snd_dma_pci_data(chip->pci),
1956 chip->num_streams * 8, &chip->posbuf);
1957 if (err < 0) {
1958 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
1959 goto errout;
1960 }
1961 /* allocate CORB/RIRB */
1962 if (!chip->single_cmd) {
1963 err = azx_alloc_cmd_io(chip);
1964 if (err < 0)
1965 goto errout;
1966 }
1967
1968 /* initialize streams */
1969 azx_init_stream(chip);
1970
1971 /* initialize chip */
1972 azx_init_pci(chip);
1973 azx_init_chip(chip);
1974
1975 /* codec detection */
1976 if (!chip->codec_mask) {
1977 snd_printk(KERN_ERR SFX "no codecs found!\n");
1978 err = -ENODEV;
1979 goto errout;
1980 }
1981
1982 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1983 if (err <0) {
1984 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
1985 goto errout;
1986 }
1987
1988 strcpy(card->driver, "HDA-Intel");
1989 strcpy(card->shortname, driver_short_names[chip->driver_type]);
1990 sprintf(card->longname, "%s at 0x%lx irq %i",
1991 card->shortname, chip->addr, chip->irq);
1992
1993 *rchip = chip;
1994 return 0;
1995
1996 errout:
1997 azx_free(chip);
1998 return err;
1999 }
2000
2001 static void power_down_all_codecs(struct azx *chip)
2002 {
2003 #ifdef CONFIG_SND_HDA_POWER_SAVE
2004 /* The codecs were powered up in snd_hda_codec_new().
2005 * Now all initialization done, so turn them down if possible
2006 */
2007 struct hda_codec *codec;
2008 list_for_each_entry(codec, &chip->bus->codec_list, list) {
2009 snd_hda_power_down(codec);
2010 }
2011 #endif
2012 }
2013
2014 static int __devinit azx_probe(struct pci_dev *pci,
2015 const struct pci_device_id *pci_id)
2016 {
2017 static int dev;
2018 struct snd_card *card;
2019 struct azx *chip;
2020 int err;
2021
2022 if (dev >= SNDRV_CARDS)
2023 return -ENODEV;
2024 if (!enable[dev]) {
2025 dev++;
2026 return -ENOENT;
2027 }
2028
2029 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2030 if (!card) {
2031 snd_printk(KERN_ERR SFX "Error creating card!\n");
2032 return -ENOMEM;
2033 }
2034
2035 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2036 if (err < 0) {
2037 snd_card_free(card);
2038 return err;
2039 }
2040 card->private_data = chip;
2041
2042 /* create codec instances */
2043 err = azx_codec_create(chip, model[dev], probe_mask[dev]);
2044 if (err < 0) {
2045 snd_card_free(card);
2046 return err;
2047 }
2048
2049 /* create PCM streams */
2050 err = azx_pcm_create(chip);
2051 if (err < 0) {
2052 snd_card_free(card);
2053 return err;
2054 }
2055
2056 /* create mixer controls */
2057 err = azx_mixer_create(chip);
2058 if (err < 0) {
2059 snd_card_free(card);
2060 return err;
2061 }
2062
2063 snd_card_set_dev(card, &pci->dev);
2064
2065 err = snd_card_register(card);
2066 if (err < 0) {
2067 snd_card_free(card);
2068 return err;
2069 }
2070
2071 pci_set_drvdata(pci, card);
2072 chip->running = 1;
2073 power_down_all_codecs(chip);
2074
2075 dev++;
2076 return err;
2077 }
2078
2079 static void __devexit azx_remove(struct pci_dev *pci)
2080 {
2081 snd_card_free(pci_get_drvdata(pci));
2082 pci_set_drvdata(pci, NULL);
2083 }
2084
2085 /* PCI IDs */
2086 static struct pci_device_id azx_ids[] = {
2087 /* ICH 6..10 */
2088 { PCI_DEVICE(0x8086, 0x2668), .driver_data = AZX_DRIVER_ICH },
2089 { PCI_DEVICE(0x8086, 0x27d8), .driver_data = AZX_DRIVER_ICH },
2090 { PCI_DEVICE(0x8086, 0x269a), .driver_data = AZX_DRIVER_ICH },
2091 { PCI_DEVICE(0x8086, 0x284b), .driver_data = AZX_DRIVER_ICH },
2092 { PCI_DEVICE(0x8086, 0x293e), .driver_data = AZX_DRIVER_ICH },
2093 { PCI_DEVICE(0x8086, 0x293f), .driver_data = AZX_DRIVER_ICH },
2094 { PCI_DEVICE(0x8086, 0x3a3e), .driver_data = AZX_DRIVER_ICH },
2095 { PCI_DEVICE(0x8086, 0x3a6e), .driver_data = AZX_DRIVER_ICH },
2096 /* SCH */
2097 { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
2098 /* ATI SB 450/600 */
2099 { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2100 { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2101 /* ATI HDMI */
2102 { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2103 { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2104 { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
2105 { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2106 { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2107 { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2108 { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2109 { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2110 { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2111 { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2112 { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2113 { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2114 { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2115 /* VIA VT8251/VT8237A */
2116 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2117 /* SIS966 */
2118 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2119 /* ULI M5461 */
2120 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2121 /* NVIDIA MCP */
2122 { PCI_DEVICE(0x10de, 0x026c), .driver_data = AZX_DRIVER_NVIDIA },
2123 { PCI_DEVICE(0x10de, 0x0371), .driver_data = AZX_DRIVER_NVIDIA },
2124 { PCI_DEVICE(0x10de, 0x03e4), .driver_data = AZX_DRIVER_NVIDIA },
2125 { PCI_DEVICE(0x10de, 0x03f0), .driver_data = AZX_DRIVER_NVIDIA },
2126 { PCI_DEVICE(0x10de, 0x044a), .driver_data = AZX_DRIVER_NVIDIA },
2127 { PCI_DEVICE(0x10de, 0x044b), .driver_data = AZX_DRIVER_NVIDIA },
2128 { PCI_DEVICE(0x10de, 0x055c), .driver_data = AZX_DRIVER_NVIDIA },
2129 { PCI_DEVICE(0x10de, 0x055d), .driver_data = AZX_DRIVER_NVIDIA },
2130 { PCI_DEVICE(0x10de, 0x0774), .driver_data = AZX_DRIVER_NVIDIA },
2131 { PCI_DEVICE(0x10de, 0x0775), .driver_data = AZX_DRIVER_NVIDIA },
2132 { PCI_DEVICE(0x10de, 0x0776), .driver_data = AZX_DRIVER_NVIDIA },
2133 { PCI_DEVICE(0x10de, 0x0777), .driver_data = AZX_DRIVER_NVIDIA },
2134 { PCI_DEVICE(0x10de, 0x07fc), .driver_data = AZX_DRIVER_NVIDIA },
2135 { PCI_DEVICE(0x10de, 0x07fd), .driver_data = AZX_DRIVER_NVIDIA },
2136 { PCI_DEVICE(0x10de, 0x0ac0), .driver_data = AZX_DRIVER_NVIDIA },
2137 { PCI_DEVICE(0x10de, 0x0ac1), .driver_data = AZX_DRIVER_NVIDIA },
2138 { PCI_DEVICE(0x10de, 0x0ac2), .driver_data = AZX_DRIVER_NVIDIA },
2139 { PCI_DEVICE(0x10de, 0x0ac3), .driver_data = AZX_DRIVER_NVIDIA },
2140 { PCI_DEVICE(0x10de, 0x0bd4), .driver_data = AZX_DRIVER_NVIDIA },
2141 { PCI_DEVICE(0x10de, 0x0bd5), .driver_data = AZX_DRIVER_NVIDIA },
2142 { PCI_DEVICE(0x10de, 0x0bd6), .driver_data = AZX_DRIVER_NVIDIA },
2143 { PCI_DEVICE(0x10de, 0x0bd7), .driver_data = AZX_DRIVER_NVIDIA },
2144 { 0, }
2145 };
2146 MODULE_DEVICE_TABLE(pci, azx_ids);
2147
2148 /* pci_driver definition */
2149 static struct pci_driver driver = {
2150 .name = "HDA Intel",
2151 .id_table = azx_ids,
2152 .probe = azx_probe,
2153 .remove = __devexit_p(azx_remove),
2154 #ifdef CONFIG_PM
2155 .suspend = azx_suspend,
2156 .resume = azx_resume,
2157 #endif
2158 };
2159
2160 static int __init alsa_card_azx_init(void)
2161 {
2162 return pci_register_driver(&driver);
2163 }
2164
2165 static void __exit alsa_card_azx_exit(void)
2166 {
2167 pci_unregister_driver(&driver);
2168 }
2169
2170 module_init(alsa_card_azx_init)
2171 module_exit(alsa_card_azx_exit)
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