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remove unused TIF_NOTIFY_RESUME flag
[pv_ops_mirror.git] / drivers / net / 8139cp.c
blobe970e64bf96698916a1caaac8c5000471ed6cc18
1 /* 8139cp.c: A Linux PCI Ethernet driver for the RealTek 8139C+ chips. */
2 /*
3 Copyright 2001-2004 Jeff Garzik <jgarzik@pobox.com>
4
5 Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com) [tg3.c]
6 Copyright (C) 2000, 2001 David S. Miller (davem@redhat.com) [sungem.c]
7 Copyright 2001 Manfred Spraul [natsemi.c]
8 Copyright 1999-2001 by Donald Becker. [natsemi.c]
9 Written 1997-2001 by Donald Becker. [8139too.c]
10 Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. [acenic.c]
11
12 This software may be used and distributed according to the terms of
13 the GNU General Public License (GPL), incorporated herein by reference.
14 Drivers based on or derived from this code fall under the GPL and must
15 retain the authorship, copyright and license notice. This file is not
16 a complete program and may only be used when the entire operating
17 system is licensed under the GPL.
18
19 See the file COPYING in this distribution for more information.
20
21 Contributors:
22
23 Wake-on-LAN support - Felipe Damasio <felipewd@terra.com.br>
24 PCI suspend/resume - Felipe Damasio <felipewd@terra.com.br>
25 LinkChg interrupt - Felipe Damasio <felipewd@terra.com.br>
26
27 TODO:
28 * Test Tx checksumming thoroughly
29
30 Low priority TODO:
31 * Complete reset on PciErr
32 * Consider Rx interrupt mitigation using TimerIntr
33 * Investigate using skb->priority with h/w VLAN priority
34 * Investigate using High Priority Tx Queue with skb->priority
35 * Adjust Rx FIFO threshold and Max Rx DMA burst on Rx FIFO error
36 * Adjust Tx FIFO threshold and Max Tx DMA burst on Tx FIFO error
37 * Implement Tx software interrupt mitigation via
38 Tx descriptor bit
39 * The real minimum of CP_MIN_MTU is 4 bytes. However,
40 for this to be supported, one must(?) turn on packet padding.
41 * Support external MII transceivers (patch available)
42
43 NOTES:
44 * TX checksumming is considered experimental. It is off by
45 default, use ethtool to turn it on.
46
47 */
48
49 #define DRV_NAME "8139cp"
50 #define DRV_VERSION "1.3"
51 #define DRV_RELDATE "Mar 22, 2004"
52
53
54 #include <linux/module.h>
55 #include <linux/moduleparam.h>
56 #include <linux/kernel.h>
57 #include <linux/compiler.h>
58 #include <linux/netdevice.h>
59 #include <linux/etherdevice.h>
60 #include <linux/init.h>
61 #include <linux/pci.h>
62 #include <linux/dma-mapping.h>
63 #include <linux/delay.h>
64 #include <linux/ethtool.h>
65 #include <linux/mii.h>
66 #include <linux/if_vlan.h>
67 #include <linux/crc32.h>
68 #include <linux/in.h>
69 #include <linux/ip.h>
70 #include <linux/tcp.h>
71 #include <linux/udp.h>
72 #include <linux/cache.h>
73 #include <asm/io.h>
74 #include <asm/irq.h>
75 #include <asm/uaccess.h>
76
77 /* VLAN tagging feature enable/disable */
78 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
79 #define CP_VLAN_TAG_USED 1
80 #define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
81 do { (tx_desc)->opts2 = (vlan_tag_value); } while (0)
82 #else
83 #define CP_VLAN_TAG_USED 0
84 #define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
85 do { (tx_desc)->opts2 = 0; } while (0)
86 #endif
87
88 /* These identify the driver base version and may not be removed. */
89 static char version[] =
90 KERN_INFO DRV_NAME ": 10/100 PCI Ethernet driver v" DRV_VERSION " (" DRV_RELDATE ")\n";
91
92 MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
93 MODULE_DESCRIPTION("RealTek RTL-8139C+ series 10/100 PCI Ethernet driver");
94 MODULE_VERSION(DRV_VERSION);
95 MODULE_LICENSE("GPL");
96
97 static int debug = -1;
98 module_param(debug, int, 0);
99 MODULE_PARM_DESC (debug, "8139cp: bitmapped message enable number");
100
101 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
102 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
103 static int multicast_filter_limit = 32;
104 module_param(multicast_filter_limit, int, 0);
105 MODULE_PARM_DESC (multicast_filter_limit, "8139cp: maximum number of filtered multicast addresses");
106
107 #define PFX DRV_NAME ": "
108
109 #define CP_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
110 NETIF_MSG_PROBE | \
111 NETIF_MSG_LINK)
112 #define CP_NUM_STATS 14 /* struct cp_dma_stats, plus one */
113 #define CP_STATS_SIZE 64 /* size in bytes of DMA stats block */
114 #define CP_REGS_SIZE (0xff + 1)
115 #define CP_REGS_VER 1 /* version 1 */
116 #define CP_RX_RING_SIZE 64
117 #define CP_TX_RING_SIZE 64
118 #define CP_RING_BYTES \
119 ((sizeof(struct cp_desc) * CP_RX_RING_SIZE) + \
120 (sizeof(struct cp_desc) * CP_TX_RING_SIZE) + \
121 CP_STATS_SIZE)
122 #define NEXT_TX(N) (((N) + 1) & (CP_TX_RING_SIZE - 1))
123 #define NEXT_RX(N) (((N) + 1) & (CP_RX_RING_SIZE - 1))
124 #define TX_BUFFS_AVAIL(CP) \
125 (((CP)->tx_tail <= (CP)->tx_head) ? \
126 (CP)->tx_tail + (CP_TX_RING_SIZE - 1) - (CP)->tx_head : \
127 (CP)->tx_tail - (CP)->tx_head - 1)
128
129 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
130 #define RX_OFFSET 2
131 #define CP_INTERNAL_PHY 32
132
133 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
134 #define RX_FIFO_THRESH 5 /* Rx buffer level before first PCI xfer. */
135 #define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 */
136 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
137 #define TX_EARLY_THRESH 256 /* Early Tx threshold, in bytes */
138
139 /* Time in jiffies before concluding the transmitter is hung. */
140 #define TX_TIMEOUT (6*HZ)
141
142 /* hardware minimum and maximum for a single frame's data payload */
143 #define CP_MIN_MTU 60 /* TODO: allow lower, but pad */
144 #define CP_MAX_MTU 4096
145
146 enum {
147 /* NIC register offsets */
148 MAC0 = 0x00, /* Ethernet hardware address. */
149 MAR0 = 0x08, /* Multicast filter. */
150 StatsAddr = 0x10, /* 64-bit start addr of 64-byte DMA stats blk */
151 TxRingAddr = 0x20, /* 64-bit start addr of Tx ring */
152 HiTxRingAddr = 0x28, /* 64-bit start addr of high priority Tx ring */
153 Cmd = 0x37, /* Command register */
154 IntrMask = 0x3C, /* Interrupt mask */
155 IntrStatus = 0x3E, /* Interrupt status */
156 TxConfig = 0x40, /* Tx configuration */
157 ChipVersion = 0x43, /* 8-bit chip version, inside TxConfig */
158 RxConfig = 0x44, /* Rx configuration */
159 RxMissed = 0x4C, /* 24 bits valid, write clears */
160 Cfg9346 = 0x50, /* EEPROM select/control; Cfg reg [un]lock */
161 Config1 = 0x52, /* Config1 */
162 Config3 = 0x59, /* Config3 */
163 Config4 = 0x5A, /* Config4 */
164 MultiIntr = 0x5C, /* Multiple interrupt select */
165 BasicModeCtrl = 0x62, /* MII BMCR */
166 BasicModeStatus = 0x64, /* MII BMSR */
167 NWayAdvert = 0x66, /* MII ADVERTISE */
168 NWayLPAR = 0x68, /* MII LPA */
169 NWayExpansion = 0x6A, /* MII Expansion */
170 Config5 = 0xD8, /* Config5 */
171 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
172 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
173 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
174 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
175 RxRingAddr = 0xE4, /* 64-bit start addr of Rx ring */
176 TxThresh = 0xEC, /* Early Tx threshold */
177 OldRxBufAddr = 0x30, /* DMA address of Rx ring buffer (C mode) */
178 OldTSD0 = 0x10, /* DMA address of first Tx desc (C mode) */
179
180 /* Tx and Rx status descriptors */
181 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
182 RingEnd = (1 << 30), /* End of descriptor ring */
183 FirstFrag = (1 << 29), /* First segment of a packet */
184 LastFrag = (1 << 28), /* Final segment of a packet */
185 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
186 MSSShift = 16, /* MSS value position */
187 MSSMask = 0xfff, /* MSS value: 11 bits */
188 TxError = (1 << 23), /* Tx error summary */
189 RxError = (1 << 20), /* Rx error summary */
190 IPCS = (1 << 18), /* Calculate IP checksum */
191 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
192 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
193 TxVlanTag = (1 << 17), /* Add VLAN tag */
194 RxVlanTagged = (1 << 16), /* Rx VLAN tag available */
195 IPFail = (1 << 15), /* IP checksum failed */
196 UDPFail = (1 << 14), /* UDP/IP checksum failed */
197 TCPFail = (1 << 13), /* TCP/IP checksum failed */
198 NormalTxPoll = (1 << 6), /* One or more normal Tx packets to send */
199 PID1 = (1 << 17), /* 2 protocol id bits: 0==non-IP, */
200 PID0 = (1 << 16), /* 1==UDP/IP, 2==TCP/IP, 3==IP */
201 RxProtoTCP = 1,
202 RxProtoUDP = 2,
203 RxProtoIP = 3,
204 TxFIFOUnder = (1 << 25), /* Tx FIFO underrun */
205 TxOWC = (1 << 22), /* Tx Out-of-window collision */
206 TxLinkFail = (1 << 21), /* Link failed during Tx of packet */
207 TxMaxCol = (1 << 20), /* Tx aborted due to excessive collisions */
208 TxColCntShift = 16, /* Shift, to get 4-bit Tx collision cnt */
209 TxColCntMask = 0x01 | 0x02 | 0x04 | 0x08, /* 4-bit collision count */
210 RxErrFrame = (1 << 27), /* Rx frame alignment error */
211 RxMcast = (1 << 26), /* Rx multicast packet rcv'd */
212 RxErrCRC = (1 << 18), /* Rx CRC error */
213 RxErrRunt = (1 << 19), /* Rx error, packet < 64 bytes */
214 RxErrLong = (1 << 21), /* Rx error, packet > 4096 bytes */
215 RxErrFIFO = (1 << 22), /* Rx error, FIFO overflowed, pkt bad */
216
217 /* StatsAddr register */
218 DumpStats = (1 << 3), /* Begin stats dump */
219
220 /* RxConfig register */
221 RxCfgFIFOShift = 13, /* Shift, to get Rx FIFO thresh value */
222 RxCfgDMAShift = 8, /* Shift, to get Rx Max DMA value */
223 AcceptErr = 0x20, /* Accept packets with CRC errors */
224 AcceptRunt = 0x10, /* Accept runt (<64 bytes) packets */
225 AcceptBroadcast = 0x08, /* Accept broadcast packets */
226 AcceptMulticast = 0x04, /* Accept multicast packets */
227 AcceptMyPhys = 0x02, /* Accept pkts with our MAC as dest */
228 AcceptAllPhys = 0x01, /* Accept all pkts w/ physical dest */
229
230 /* IntrMask / IntrStatus registers */
231 PciErr = (1 << 15), /* System error on the PCI bus */
232 TimerIntr = (1 << 14), /* Asserted when TCTR reaches TimerInt value */
233 LenChg = (1 << 13), /* Cable length change */
234 SWInt = (1 << 8), /* Software-requested interrupt */
235 TxEmpty = (1 << 7), /* No Tx descriptors available */
236 RxFIFOOvr = (1 << 6), /* Rx FIFO Overflow */
237 LinkChg = (1 << 5), /* Packet underrun, or link change */
238 RxEmpty = (1 << 4), /* No Rx descriptors available */
239 TxErr = (1 << 3), /* Tx error */
240 TxOK = (1 << 2), /* Tx packet sent */
241 RxErr = (1 << 1), /* Rx error */
242 RxOK = (1 << 0), /* Rx packet received */
243 IntrResvd = (1 << 10), /* reserved, according to RealTek engineers,
244 but hardware likes to raise it */
245
246 IntrAll = PciErr | TimerIntr | LenChg | SWInt | TxEmpty |
247 RxFIFOOvr | LinkChg | RxEmpty | TxErr | TxOK |
248 RxErr | RxOK | IntrResvd,
249
250 /* C mode command register */
251 CmdReset = (1 << 4), /* Enable to reset; self-clearing */
252 RxOn = (1 << 3), /* Rx mode enable */
253 TxOn = (1 << 2), /* Tx mode enable */
254
255 /* C+ mode command register */
256 RxVlanOn = (1 << 6), /* Rx VLAN de-tagging enable */
257 RxChkSum = (1 << 5), /* Rx checksum offload enable */
258 PCIDAC = (1 << 4), /* PCI Dual Address Cycle (64-bit PCI) */
259 PCIMulRW = (1 << 3), /* Enable PCI read/write multiple */
260 CpRxOn = (1 << 1), /* Rx mode enable */
261 CpTxOn = (1 << 0), /* Tx mode enable */
262
263 /* Cfg9436 EEPROM control register */
264 Cfg9346_Lock = 0x00, /* Lock ConfigX/MII register access */
265 Cfg9346_Unlock = 0xC0, /* Unlock ConfigX/MII register access */
266
267 /* TxConfig register */
268 IFG = (1 << 25) | (1 << 24), /* standard IEEE interframe gap */
269 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
270
271 /* Early Tx Threshold register */
272 TxThreshMask = 0x3f, /* Mask bits 5-0 */
273 TxThreshMax = 2048, /* Max early Tx threshold */
274
275 /* Config1 register */
276 DriverLoaded = (1 << 5), /* Software marker, driver is loaded */
277 LWACT = (1 << 4), /* LWAKE active mode */
278 PMEnable = (1 << 0), /* Enable various PM features of chip */
279
280 /* Config3 register */
281 PARMEnable = (1 << 6), /* Enable auto-loading of PHY parms */
282 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
283 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
284
285 /* Config4 register */
286 LWPTN = (1 << 1), /* LWAKE Pattern */
287 LWPME = (1 << 4), /* LANWAKE vs PMEB */
288
289 /* Config5 register */
290 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
291 MWF = (1 << 5), /* Accept Multicast wakeup frame */
292 UWF = (1 << 4), /* Accept Unicast wakeup frame */
293 LANWake = (1 << 1), /* Enable LANWake signal */
294 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
295
296 cp_norx_intr_mask = PciErr | LinkChg | TxOK | TxErr | TxEmpty,
297 cp_rx_intr_mask = RxOK | RxErr | RxEmpty | RxFIFOOvr,
298 cp_intr_mask = cp_rx_intr_mask | cp_norx_intr_mask,
299 };
300
301 static const unsigned int cp_rx_config =
302 (RX_FIFO_THRESH << RxCfgFIFOShift) |
303 (RX_DMA_BURST << RxCfgDMAShift);
304
305 struct cp_desc {
306 u32 opts1;
307 u32 opts2;
308 u64 addr;
309 };
310
311 struct cp_dma_stats {
312 u64 tx_ok;
313 u64 rx_ok;
314 u64 tx_err;
315 u32 rx_err;
316 u16 rx_fifo;
317 u16 frame_align;
318 u32 tx_ok_1col;
319 u32 tx_ok_mcol;
320 u64 rx_ok_phys;
321 u64 rx_ok_bcast;
322 u32 rx_ok_mcast;
323 u16 tx_abort;
324 u16 tx_underrun;
325 } __attribute__((packed));
326
327 struct cp_extra_stats {
328 unsigned long rx_frags;
329 };
330
331 struct cp_private {
332 void __iomem *regs;
333 struct net_device *dev;
334 spinlock_t lock;
335 u32 msg_enable;
336
337 struct pci_dev *pdev;
338 u32 rx_config;
339 u16 cpcmd;
340
341 struct net_device_stats net_stats;
342 struct cp_extra_stats cp_stats;
343
344 unsigned rx_head ____cacheline_aligned;
345 unsigned rx_tail;
346 struct cp_desc *rx_ring;
347 struct sk_buff *rx_skb[CP_RX_RING_SIZE];
348
349 unsigned tx_head ____cacheline_aligned;
350 unsigned tx_tail;
351 struct cp_desc *tx_ring;
352 struct sk_buff *tx_skb[CP_TX_RING_SIZE];
353
354 unsigned rx_buf_sz;
355 unsigned wol_enabled : 1; /* Is Wake-on-LAN enabled? */
356
357 #if CP_VLAN_TAG_USED
358 struct vlan_group *vlgrp;
359 #endif
360 dma_addr_t ring_dma;
361
362 struct mii_if_info mii_if;
363 };
364
365 #define cpr8(reg) readb(cp->regs + (reg))
366 #define cpr16(reg) readw(cp->regs + (reg))
367 #define cpr32(reg) readl(cp->regs + (reg))
368 #define cpw8(reg,val) writeb((val), cp->regs + (reg))
369 #define cpw16(reg,val) writew((val), cp->regs + (reg))
370 #define cpw32(reg,val) writel((val), cp->regs + (reg))
371 #define cpw8_f(reg,val) do { \
372 writeb((val), cp->regs + (reg)); \
373 readb(cp->regs + (reg)); \
374 } while (0)
375 #define cpw16_f(reg,val) do { \
376 writew((val), cp->regs + (reg)); \
377 readw(cp->regs + (reg)); \
378 } while (0)
379 #define cpw32_f(reg,val) do { \
380 writel((val), cp->regs + (reg)); \
381 readl(cp->regs + (reg)); \
382 } while (0)
383
384
385 static void __cp_set_rx_mode (struct net_device *dev);
386 static void cp_tx (struct cp_private *cp);
387 static void cp_clean_rings (struct cp_private *cp);
388 #ifdef CONFIG_NET_POLL_CONTROLLER
389 static void cp_poll_controller(struct net_device *dev);
390 #endif
391 static int cp_get_eeprom_len(struct net_device *dev);
392 static int cp_get_eeprom(struct net_device *dev,
393 struct ethtool_eeprom *eeprom, u8 *data);
394 static int cp_set_eeprom(struct net_device *dev,
395 struct ethtool_eeprom *eeprom, u8 *data);
396
397 static struct pci_device_id cp_pci_tbl[] = {
398 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139), },
399 { PCI_DEVICE(PCI_VENDOR_ID_TTTECH, PCI_DEVICE_ID_TTTECH_MC322), },
400 { },
401 };
402 MODULE_DEVICE_TABLE(pci, cp_pci_tbl);
403
404 static struct {
405 const char str[ETH_GSTRING_LEN];
406 } ethtool_stats_keys[] = {
407 { "tx_ok" },
408 { "rx_ok" },
409 { "tx_err" },
410 { "rx_err" },
411 { "rx_fifo" },
412 { "frame_align" },
413 { "tx_ok_1col" },
414 { "tx_ok_mcol" },
415 { "rx_ok_phys" },
416 { "rx_ok_bcast" },
417 { "rx_ok_mcast" },
418 { "tx_abort" },
419 { "tx_underrun" },
420 { "rx_frags" },
421 };
422
423
424 #if CP_VLAN_TAG_USED
425 static void cp_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
426 {
427 struct cp_private *cp = netdev_priv(dev);
428 unsigned long flags;
429
430 spin_lock_irqsave(&cp->lock, flags);
431 cp->vlgrp = grp;
432 if (grp)
433 cp->cpcmd |= RxVlanOn;
434 else
435 cp->cpcmd &= ~RxVlanOn;
436
437 cpw16(CpCmd, cp->cpcmd);
438 spin_unlock_irqrestore(&cp->lock, flags);
439 }
440 #endif /* CP_VLAN_TAG_USED */
441
442 static inline void cp_set_rxbufsize (struct cp_private *cp)
443 {
444 unsigned int mtu = cp->dev->mtu;
445
446 if (mtu > ETH_DATA_LEN)
447 /* MTU + ethernet header + FCS + optional VLAN tag */
448 cp->rx_buf_sz = mtu + ETH_HLEN + 8;
449 else
450 cp->rx_buf_sz = PKT_BUF_SZ;
451 }
452
453 static inline void cp_rx_skb (struct cp_private *cp, struct sk_buff *skb,
454 struct cp_desc *desc)
455 {
456 skb->protocol = eth_type_trans (skb, cp->dev);
457
458 cp->net_stats.rx_packets++;
459 cp->net_stats.rx_bytes += skb->len;
460 cp->dev->last_rx = jiffies;
461
462 #if CP_VLAN_TAG_USED
463 if (cp->vlgrp && (desc->opts2 & RxVlanTagged)) {
464 vlan_hwaccel_receive_skb(skb, cp->vlgrp,
465 be16_to_cpu(desc->opts2 & 0xffff));
466 } else
467 #endif
468 netif_receive_skb(skb);
469 }
470
471 static void cp_rx_err_acct (struct cp_private *cp, unsigned rx_tail,
472 u32 status, u32 len)
473 {
474 if (netif_msg_rx_err (cp))
475 printk (KERN_DEBUG
476 "%s: rx err, slot %d status 0x%x len %d\n",
477 cp->dev->name, rx_tail, status, len);
478 cp->net_stats.rx_errors++;
479 if (status & RxErrFrame)
480 cp->net_stats.rx_frame_errors++;
481 if (status & RxErrCRC)
482 cp->net_stats.rx_crc_errors++;
483 if ((status & RxErrRunt) || (status & RxErrLong))
484 cp->net_stats.rx_length_errors++;
485 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag))
486 cp->net_stats.rx_length_errors++;
487 if (status & RxErrFIFO)
488 cp->net_stats.rx_fifo_errors++;
489 }
490
491 static inline unsigned int cp_rx_csum_ok (u32 status)
492 {
493 unsigned int protocol = (status >> 16) & 0x3;
494
495 if (likely((protocol == RxProtoTCP) && (!(status & TCPFail))))
496 return 1;
497 else if ((protocol == RxProtoUDP) && (!(status & UDPFail)))
498 return 1;
499 else if ((protocol == RxProtoIP) && (!(status & IPFail)))
500 return 1;
501 return 0;
502 }
503
504 static int cp_rx_poll (struct net_device *dev, int *budget)
505 {
506 struct cp_private *cp = netdev_priv(dev);
507 unsigned rx_tail = cp->rx_tail;
508 unsigned rx_work = dev->quota;
509 unsigned rx;
510
511 rx_status_loop:
512 rx = 0;
513 cpw16(IntrStatus, cp_rx_intr_mask);
514
515 while (1) {
516 u32 status, len;
517 dma_addr_t mapping;
518 struct sk_buff *skb, *new_skb;
519 struct cp_desc *desc;
520 unsigned buflen;
521
522 skb = cp->rx_skb[rx_tail];
523 BUG_ON(!skb);
524
525 desc = &cp->rx_ring[rx_tail];
526 status = le32_to_cpu(desc->opts1);
527 if (status & DescOwn)
528 break;
529
530 len = (status & 0x1fff) - 4;
531 mapping = le64_to_cpu(desc->addr);
532
533 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag)) {
534 /* we don't support incoming fragmented frames.
535 * instead, we attempt to ensure that the
536 * pre-allocated RX skbs are properly sized such
537 * that RX fragments are never encountered
538 */
539 cp_rx_err_acct(cp, rx_tail, status, len);
540 cp->net_stats.rx_dropped++;
541 cp->cp_stats.rx_frags++;
542 goto rx_next;
543 }
544
545 if (status & (RxError | RxErrFIFO)) {
546 cp_rx_err_acct(cp, rx_tail, status, len);
547 goto rx_next;
548 }
549
550 if (netif_msg_rx_status(cp))
551 printk(KERN_DEBUG "%s: rx slot %d status 0x%x len %d\n",
552 dev->name, rx_tail, status, len);
553
554 buflen = cp->rx_buf_sz + RX_OFFSET;
555 new_skb = dev_alloc_skb (buflen);
556 if (!new_skb) {
557 cp->net_stats.rx_dropped++;
558 goto rx_next;
559 }
560
561 skb_reserve(new_skb, RX_OFFSET);
562
563 pci_unmap_single(cp->pdev, mapping,
564 buflen, PCI_DMA_FROMDEVICE);
565
566 /* Handle checksum offloading for incoming packets. */
567 if (cp_rx_csum_ok(status))
568 skb->ip_summed = CHECKSUM_UNNECESSARY;
569 else
570 skb->ip_summed = CHECKSUM_NONE;
571
572 skb_put(skb, len);
573
574 mapping = pci_map_single(cp->pdev, new_skb->data, buflen,
575 PCI_DMA_FROMDEVICE);
576 cp->rx_skb[rx_tail] = new_skb;
577
578 cp_rx_skb(cp, skb, desc);
579 rx++;
580
581 rx_next:
582 cp->rx_ring[rx_tail].opts2 = 0;
583 cp->rx_ring[rx_tail].addr = cpu_to_le64(mapping);
584 if (rx_tail == (CP_RX_RING_SIZE - 1))
585 desc->opts1 = cpu_to_le32(DescOwn | RingEnd |
586 cp->rx_buf_sz);
587 else
588 desc->opts1 = cpu_to_le32(DescOwn | cp->rx_buf_sz);
589 rx_tail = NEXT_RX(rx_tail);
590
591 if (!rx_work--)
592 break;
593 }
594
595 cp->rx_tail = rx_tail;
596
597 dev->quota -= rx;
598 *budget -= rx;
599
600 /* if we did not reach work limit, then we're done with
601 * this round of polling
602 */
603 if (rx_work) {
604 unsigned long flags;
605
606 if (cpr16(IntrStatus) & cp_rx_intr_mask)
607 goto rx_status_loop;
608
609 local_irq_save(flags);
610 cpw16_f(IntrMask, cp_intr_mask);
611 __netif_rx_complete(dev);
612 local_irq_restore(flags);
613
614 return 0; /* done */
615 }
616
617 return 1; /* not done */
618 }
619
620 static irqreturn_t cp_interrupt (int irq, void *dev_instance)
621 {
622 struct net_device *dev = dev_instance;
623 struct cp_private *cp;
624 u16 status;
625
626 if (unlikely(dev == NULL))
627 return IRQ_NONE;
628 cp = netdev_priv(dev);
629
630 status = cpr16(IntrStatus);
631 if (!status || (status == 0xFFFF))
632 return IRQ_NONE;
633
634 if (netif_msg_intr(cp))
635 printk(KERN_DEBUG "%s: intr, status %04x cmd %02x cpcmd %04x\n",
636 dev->name, status, cpr8(Cmd), cpr16(CpCmd));
637
638 cpw16(IntrStatus, status & ~cp_rx_intr_mask);
639
640 spin_lock(&cp->lock);
641
642 /* close possible race's with dev_close */
643 if (unlikely(!netif_running(dev))) {
644 cpw16(IntrMask, 0);
645 spin_unlock(&cp->lock);
646 return IRQ_HANDLED;
647 }
648
649 if (status & (RxOK | RxErr | RxEmpty | RxFIFOOvr))
650 if (netif_rx_schedule_prep(dev)) {
651 cpw16_f(IntrMask, cp_norx_intr_mask);
652 __netif_rx_schedule(dev);
653 }
654
655 if (status & (TxOK | TxErr | TxEmpty | SWInt))
656 cp_tx(cp);
657 if (status & LinkChg)
658 mii_check_media(&cp->mii_if, netif_msg_link(cp), false);
659
660 spin_unlock(&cp->lock);
661
662 if (status & PciErr) {
663 u16 pci_status;
664
665 pci_read_config_word(cp->pdev, PCI_STATUS, &pci_status);
666 pci_write_config_word(cp->pdev, PCI_STATUS, pci_status);
667 printk(KERN_ERR "%s: PCI bus error, status=%04x, PCI status=%04x\n",
668 dev->name, status, pci_status);
669
670 /* TODO: reset hardware */
671 }
672
673 return IRQ_HANDLED;
674 }
675
676 #ifdef CONFIG_NET_POLL_CONTROLLER
677 /*
678 * Polling receive - used by netconsole and other diagnostic tools
679 * to allow network i/o with interrupts disabled.
680 */
681 static void cp_poll_controller(struct net_device *dev)
682 {
683 disable_irq(dev->irq);
684 cp_interrupt(dev->irq, dev);
685 enable_irq(dev->irq);
686 }
687 #endif
688
689 static void cp_tx (struct cp_private *cp)
690 {
691 unsigned tx_head = cp->tx_head;
692 unsigned tx_tail = cp->tx_tail;
693
694 while (tx_tail != tx_head) {
695 struct cp_desc *txd = cp->tx_ring + tx_tail;
696 struct sk_buff *skb;
697 u32 status;
698
699 rmb();
700 status = le32_to_cpu(txd->opts1);
701 if (status & DescOwn)
702 break;
703
704 skb = cp->tx_skb[tx_tail];
705 BUG_ON(!skb);
706
707 pci_unmap_single(cp->pdev, le64_to_cpu(txd->addr),
708 le32_to_cpu(txd->opts1) & 0xffff,
709 PCI_DMA_TODEVICE);
710
711 if (status & LastFrag) {
712 if (status & (TxError | TxFIFOUnder)) {
713 if (netif_msg_tx_err(cp))
714 printk(KERN_DEBUG "%s: tx err, status 0x%x\n",
715 cp->dev->name, status);
716 cp->net_stats.tx_errors++;
717 if (status & TxOWC)
718 cp->net_stats.tx_window_errors++;
719 if (status & TxMaxCol)
720 cp->net_stats.tx_aborted_errors++;
721 if (status & TxLinkFail)
722 cp->net_stats.tx_carrier_errors++;
723 if (status & TxFIFOUnder)
724 cp->net_stats.tx_fifo_errors++;
725 } else {
726 cp->net_stats.collisions +=
727 ((status >> TxColCntShift) & TxColCntMask);
728 cp->net_stats.tx_packets++;
729 cp->net_stats.tx_bytes += skb->len;
730 if (netif_msg_tx_done(cp))
731 printk(KERN_DEBUG "%s: tx done, slot %d\n", cp->dev->name, tx_tail);
732 }
733 dev_kfree_skb_irq(skb);
734 }
735
736 cp->tx_skb[tx_tail] = NULL;
737
738 tx_tail = NEXT_TX(tx_tail);
739 }
740
741 cp->tx_tail = tx_tail;
742
743 if (TX_BUFFS_AVAIL(cp) > (MAX_SKB_FRAGS + 1))
744 netif_wake_queue(cp->dev);
745 }
746
747 static int cp_start_xmit (struct sk_buff *skb, struct net_device *dev)
748 {
749 struct cp_private *cp = netdev_priv(dev);
750 unsigned entry;
751 u32 eor, flags;
752 unsigned long intr_flags;
753 #if CP_VLAN_TAG_USED
754 u32 vlan_tag = 0;
755 #endif
756 int mss = 0;
757
758 spin_lock_irqsave(&cp->lock, intr_flags);
759
760 /* This is a hard error, log it. */
761 if (TX_BUFFS_AVAIL(cp) <= (skb_shinfo(skb)->nr_frags + 1)) {
762 netif_stop_queue(dev);
763 spin_unlock_irqrestore(&cp->lock, intr_flags);
764 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
765 dev->name);
766 return 1;
767 }
768
769 #if CP_VLAN_TAG_USED
770 if (cp->vlgrp && vlan_tx_tag_present(skb))
771 vlan_tag = TxVlanTag | cpu_to_be16(vlan_tx_tag_get(skb));
772 #endif
773
774 entry = cp->tx_head;
775 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
776 if (dev->features & NETIF_F_TSO)
777 mss = skb_shinfo(skb)->gso_size;
778
779 if (skb_shinfo(skb)->nr_frags == 0) {
780 struct cp_desc *txd = &cp->tx_ring[entry];
781 u32 len;
782 dma_addr_t mapping;
783
784 len = skb->len;
785 mapping = pci_map_single(cp->pdev, skb->data, len, PCI_DMA_TODEVICE);
786 CP_VLAN_TX_TAG(txd, vlan_tag);
787 txd->addr = cpu_to_le64(mapping);
788 wmb();
789
790 flags = eor | len | DescOwn | FirstFrag | LastFrag;
791
792 if (mss)
793 flags |= LargeSend | ((mss & MSSMask) << MSSShift);
794 else if (skb->ip_summed == CHECKSUM_PARTIAL) {
795 const struct iphdr *ip = ip_hdr(skb);
796 if (ip->protocol == IPPROTO_TCP)
797 flags |= IPCS | TCPCS;
798 else if (ip->protocol == IPPROTO_UDP)
799 flags |= IPCS | UDPCS;
800 else
801 WARN_ON(1); /* we need a WARN() */
802 }
803
804 txd->opts1 = cpu_to_le32(flags);
805 wmb();
806
807 cp->tx_skb[entry] = skb;
808 entry = NEXT_TX(entry);
809 } else {
810 struct cp_desc *txd;
811 u32 first_len, first_eor;
812 dma_addr_t first_mapping;
813 int frag, first_entry = entry;
814 const struct iphdr *ip = ip_hdr(skb);
815
816 /* We must give this initial chunk to the device last.
817 * Otherwise we could race with the device.
818 */
819 first_eor = eor;
820 first_len = skb_headlen(skb);
821 first_mapping = pci_map_single(cp->pdev, skb->data,
822 first_len, PCI_DMA_TODEVICE);
823 cp->tx_skb[entry] = skb;
824 entry = NEXT_TX(entry);
825
826 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
827 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
828 u32 len;
829 u32 ctrl;
830 dma_addr_t mapping;
831
832 len = this_frag->size;
833 mapping = pci_map_single(cp->pdev,
834 ((void *) page_address(this_frag->page) +
835 this_frag->page_offset),
836 len, PCI_DMA_TODEVICE);
837 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
838
839 ctrl = eor | len | DescOwn;
840
841 if (mss)
842 ctrl |= LargeSend |
843 ((mss & MSSMask) << MSSShift);
844 else if (skb->ip_summed == CHECKSUM_PARTIAL) {
845 if (ip->protocol == IPPROTO_TCP)
846 ctrl |= IPCS | TCPCS;
847 else if (ip->protocol == IPPROTO_UDP)
848 ctrl |= IPCS | UDPCS;
849 else
850 BUG();
851 }
852
853 if (frag == skb_shinfo(skb)->nr_frags - 1)
854 ctrl |= LastFrag;
855
856 txd = &cp->tx_ring[entry];
857 CP_VLAN_TX_TAG(txd, vlan_tag);
858 txd->addr = cpu_to_le64(mapping);
859 wmb();
860
861 txd->opts1 = cpu_to_le32(ctrl);
862 wmb();
863
864 cp->tx_skb[entry] = skb;
865 entry = NEXT_TX(entry);
866 }
867
868 txd = &cp->tx_ring[first_entry];
869 CP_VLAN_TX_TAG(txd, vlan_tag);
870 txd->addr = cpu_to_le64(first_mapping);
871 wmb();
872
873 if (skb->ip_summed == CHECKSUM_PARTIAL) {
874 if (ip->protocol == IPPROTO_TCP)
875 txd->opts1 = cpu_to_le32(first_eor | first_len |
876 FirstFrag | DescOwn |
877 IPCS | TCPCS);
878 else if (ip->protocol == IPPROTO_UDP)
879 txd->opts1 = cpu_to_le32(first_eor | first_len |
880 FirstFrag | DescOwn |
881 IPCS | UDPCS);
882 else
883 BUG();
884 } else
885 txd->opts1 = cpu_to_le32(first_eor | first_len |
886 FirstFrag | DescOwn);
887 wmb();
888 }
889 cp->tx_head = entry;
890 if (netif_msg_tx_queued(cp))
891 printk(KERN_DEBUG "%s: tx queued, slot %d, skblen %d\n",
892 dev->name, entry, skb->len);
893 if (TX_BUFFS_AVAIL(cp) <= (MAX_SKB_FRAGS + 1))
894 netif_stop_queue(dev);
895
896 spin_unlock_irqrestore(&cp->lock, intr_flags);
897
898 cpw8(TxPoll, NormalTxPoll);
899 dev->trans_start = jiffies;
900
901 return 0;
902 }
903
904 /* Set or clear the multicast filter for this adaptor.
905 This routine is not state sensitive and need not be SMP locked. */
906
907 static void __cp_set_rx_mode (struct net_device *dev)
908 {
909 struct cp_private *cp = netdev_priv(dev);
910 u32 mc_filter[2]; /* Multicast hash filter */
911 int i, rx_mode;
912 u32 tmp;
913
914 /* Note: do not reorder, GCC is clever about common statements. */
915 if (dev->flags & IFF_PROMISC) {
916 /* Unconditionally log net taps. */
917 rx_mode =
918 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
919 AcceptAllPhys;
920 mc_filter[1] = mc_filter[0] = 0xffffffff;
921 } else if ((dev->mc_count > multicast_filter_limit)
922 || (dev->flags & IFF_ALLMULTI)) {
923 /* Too many to filter perfectly -- accept all multicasts. */
924 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
925 mc_filter[1] = mc_filter[0] = 0xffffffff;
926 } else {
927 struct dev_mc_list *mclist;
928 rx_mode = AcceptBroadcast | AcceptMyPhys;
929 mc_filter[1] = mc_filter[0] = 0;
930 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
931 i++, mclist = mclist->next) {
932 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
933
934 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
935 rx_mode |= AcceptMulticast;
936 }
937 }
938
939 /* We can safely update without stopping the chip. */
940 tmp = cp_rx_config | rx_mode;
941 if (cp->rx_config != tmp) {
942 cpw32_f (RxConfig, tmp);
943 cp->rx_config = tmp;
944 }
945 cpw32_f (MAR0 + 0, mc_filter[0]);
946 cpw32_f (MAR0 + 4, mc_filter[1]);
947 }
948
949 static void cp_set_rx_mode (struct net_device *dev)
950 {
951 unsigned long flags;
952 struct cp_private *cp = netdev_priv(dev);
953
954 spin_lock_irqsave (&cp->lock, flags);
955 __cp_set_rx_mode(dev);
956 spin_unlock_irqrestore (&cp->lock, flags);
957 }
958
959 static void __cp_get_stats(struct cp_private *cp)
960 {
961 /* only lower 24 bits valid; write any value to clear */
962 cp->net_stats.rx_missed_errors += (cpr32 (RxMissed) & 0xffffff);
963 cpw32 (RxMissed, 0);
964 }
965
966 static struct net_device_stats *cp_get_stats(struct net_device *dev)
967 {
968 struct cp_private *cp = netdev_priv(dev);
969 unsigned long flags;
970
971 /* The chip only need report frame silently dropped. */
972 spin_lock_irqsave(&cp->lock, flags);
973 if (netif_running(dev) && netif_device_present(dev))
974 __cp_get_stats(cp);
975 spin_unlock_irqrestore(&cp->lock, flags);
976
977 return &cp->net_stats;
978 }
979
980 static void cp_stop_hw (struct cp_private *cp)
981 {
982 cpw16(IntrStatus, ~(cpr16(IntrStatus)));
983 cpw16_f(IntrMask, 0);
984 cpw8(Cmd, 0);
985 cpw16_f(CpCmd, 0);
986 cpw16_f(IntrStatus, ~(cpr16(IntrStatus)));
987
988 cp->rx_tail = 0;
989 cp->tx_head = cp->tx_tail = 0;
990 }
991
992 static void cp_reset_hw (struct cp_private *cp)
993 {
994 unsigned work = 1000;
995
996 cpw8(Cmd, CmdReset);
997
998 while (work--) {
999 if (!(cpr8(Cmd) & CmdReset))
1000 return;
1001
1002 schedule_timeout_uninterruptible(10);
1003 }
1004
1005 printk(KERN_ERR "%s: hardware reset timeout\n", cp->dev->name);
1006 }
1007
1008 static inline void cp_start_hw (struct cp_private *cp)
1009 {
1010 cpw16(CpCmd, cp->cpcmd);
1011 cpw8(Cmd, RxOn | TxOn);
1012 }
1013
1014 static void cp_init_hw (struct cp_private *cp)
1015 {
1016 struct net_device *dev = cp->dev;
1017 dma_addr_t ring_dma;
1018
1019 cp_reset_hw(cp);
1020
1021 cpw8_f (Cfg9346, Cfg9346_Unlock);
1022
1023 /* Restore our idea of the MAC address. */
1024 cpw32_f (MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
1025 cpw32_f (MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
1026
1027 cp_start_hw(cp);
1028 cpw8(TxThresh, 0x06); /* XXX convert magic num to a constant */
1029
1030 __cp_set_rx_mode(dev);
1031 cpw32_f (TxConfig, IFG | (TX_DMA_BURST << TxDMAShift));
1032
1033 cpw8(Config1, cpr8(Config1) | DriverLoaded | PMEnable);
1034 /* Disable Wake-on-LAN. Can be turned on with ETHTOOL_SWOL */
1035 cpw8(Config3, PARMEnable);
1036 cp->wol_enabled = 0;
1037
1038 cpw8(Config5, cpr8(Config5) & PMEStatus);
1039
1040 cpw32_f(HiTxRingAddr, 0);
1041 cpw32_f(HiTxRingAddr + 4, 0);
1042
1043 ring_dma = cp->ring_dma;
1044 cpw32_f(RxRingAddr, ring_dma & 0xffffffff);
1045 cpw32_f(RxRingAddr + 4, (ring_dma >> 16) >> 16);
1046
1047 ring_dma += sizeof(struct cp_desc) * CP_RX_RING_SIZE;
1048 cpw32_f(TxRingAddr, ring_dma & 0xffffffff);
1049 cpw32_f(TxRingAddr + 4, (ring_dma >> 16) >> 16);
1050
1051 cpw16(MultiIntr, 0);
1052
1053 cpw16_f(IntrMask, cp_intr_mask);
1054
1055 cpw8_f(Cfg9346, Cfg9346_Lock);
1056 }
1057
1058 static int cp_refill_rx (struct cp_private *cp)
1059 {
1060 unsigned i;
1061
1062 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1063 struct sk_buff *skb;
1064 dma_addr_t mapping;
1065
1066 skb = dev_alloc_skb(cp->rx_buf_sz + RX_OFFSET);
1067 if (!skb)
1068 goto err_out;
1069
1070 skb_reserve(skb, RX_OFFSET);
1071
1072 mapping = pci_map_single(cp->pdev, skb->data, cp->rx_buf_sz,
1073 PCI_DMA_FROMDEVICE);
1074 cp->rx_skb[i] = skb;
1075
1076 cp->rx_ring[i].opts2 = 0;
1077 cp->rx_ring[i].addr = cpu_to_le64(mapping);
1078 if (i == (CP_RX_RING_SIZE - 1))
1079 cp->rx_ring[i].opts1 =
1080 cpu_to_le32(DescOwn | RingEnd | cp->rx_buf_sz);
1081 else
1082 cp->rx_ring[i].opts1 =
1083 cpu_to_le32(DescOwn | cp->rx_buf_sz);
1084 }
1085
1086 return 0;
1087
1088 err_out:
1089 cp_clean_rings(cp);
1090 return -ENOMEM;
1091 }
1092
1093 static void cp_init_rings_index (struct cp_private *cp)
1094 {
1095 cp->rx_tail = 0;
1096 cp->tx_head = cp->tx_tail = 0;
1097 }
1098
1099 static int cp_init_rings (struct cp_private *cp)
1100 {
1101 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1102 cp->tx_ring[CP_TX_RING_SIZE - 1].opts1 = cpu_to_le32(RingEnd);
1103
1104 cp_init_rings_index(cp);
1105
1106 return cp_refill_rx (cp);
1107 }
1108
1109 static int cp_alloc_rings (struct cp_private *cp)
1110 {
1111 void *mem;
1112
1113 mem = pci_alloc_consistent(cp->pdev, CP_RING_BYTES, &cp->ring_dma);
1114 if (!mem)
1115 return -ENOMEM;
1116
1117 cp->rx_ring = mem;
1118 cp->tx_ring = &cp->rx_ring[CP_RX_RING_SIZE];
1119
1120 return cp_init_rings(cp);
1121 }
1122
1123 static void cp_clean_rings (struct cp_private *cp)
1124 {
1125 struct cp_desc *desc;
1126 unsigned i;
1127
1128 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1129 if (cp->rx_skb[i]) {
1130 desc = cp->rx_ring + i;
1131 pci_unmap_single(cp->pdev, le64_to_cpu(desc->addr),
1132 cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1133 dev_kfree_skb(cp->rx_skb[i]);
1134 }
1135 }
1136
1137 for (i = 0; i < CP_TX_RING_SIZE; i++) {
1138 if (cp->tx_skb[i]) {
1139 struct sk_buff *skb = cp->tx_skb[i];
1140
1141 desc = cp->tx_ring + i;
1142 pci_unmap_single(cp->pdev, le64_to_cpu(desc->addr),
1143 le32_to_cpu(desc->opts1) & 0xffff,
1144 PCI_DMA_TODEVICE);
1145 if (le32_to_cpu(desc->opts1) & LastFrag)
1146 dev_kfree_skb(skb);
1147 cp->net_stats.tx_dropped++;
1148 }
1149 }
1150
1151 memset(cp->rx_ring, 0, sizeof(struct cp_desc) * CP_RX_RING_SIZE);
1152 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1153
1154 memset(cp->rx_skb, 0, sizeof(struct sk_buff *) * CP_RX_RING_SIZE);
1155 memset(cp->tx_skb, 0, sizeof(struct sk_buff *) * CP_TX_RING_SIZE);
1156 }
1157
1158 static void cp_free_rings (struct cp_private *cp)
1159 {
1160 cp_clean_rings(cp);
1161 pci_free_consistent(cp->pdev, CP_RING_BYTES, cp->rx_ring, cp->ring_dma);
1162 cp->rx_ring = NULL;
1163 cp->tx_ring = NULL;
1164 }
1165
1166 static int cp_open (struct net_device *dev)
1167 {
1168 struct cp_private *cp = netdev_priv(dev);
1169 int rc;
1170
1171 if (netif_msg_ifup(cp))
1172 printk(KERN_DEBUG "%s: enabling interface\n", dev->name);
1173
1174 rc = cp_alloc_rings(cp);
1175 if (rc)
1176 return rc;
1177
1178 cp_init_hw(cp);
1179
1180 rc = request_irq(dev->irq, cp_interrupt, IRQF_SHARED, dev->name, dev);
1181 if (rc)
1182 goto err_out_hw;
1183
1184 netif_carrier_off(dev);
1185 mii_check_media(&cp->mii_if, netif_msg_link(cp), true);
1186 netif_start_queue(dev);
1187
1188 return 0;
1189
1190 err_out_hw:
1191 cp_stop_hw(cp);
1192 cp_free_rings(cp);
1193 return rc;
1194 }
1195
1196 static int cp_close (struct net_device *dev)
1197 {
1198 struct cp_private *cp = netdev_priv(dev);
1199 unsigned long flags;
1200
1201 if (netif_msg_ifdown(cp))
1202 printk(KERN_DEBUG "%s: disabling interface\n", dev->name);
1203
1204 spin_lock_irqsave(&cp->lock, flags);
1205
1206 netif_stop_queue(dev);
1207 netif_carrier_off(dev);
1208
1209 cp_stop_hw(cp);
1210
1211 spin_unlock_irqrestore(&cp->lock, flags);
1212
1213 synchronize_irq(dev->irq);
1214 free_irq(dev->irq, dev);
1215
1216 cp_free_rings(cp);
1217 return 0;
1218 }
1219
1220 static void cp_tx_timeout(struct net_device *dev)
1221 {
1222 struct cp_private *cp = netdev_priv(dev);
1223 unsigned long flags;
1224 int rc;
1225
1226 printk(KERN_WARNING "%s: Transmit timeout, status %2x %4x %4x %4x\n",
1227 dev->name, cpr8(Cmd), cpr16(CpCmd),
1228 cpr16(IntrStatus), cpr16(IntrMask));
1229
1230 spin_lock_irqsave(&cp->lock, flags);
1231
1232 cp_stop_hw(cp);
1233 cp_clean_rings(cp);
1234 rc = cp_init_rings(cp);
1235 cp_start_hw(cp);
1236
1237 netif_wake_queue(dev);
1238
1239 spin_unlock_irqrestore(&cp->lock, flags);
1240
1241 return;
1242 }
1243
1244 #ifdef BROKEN
1245 static int cp_change_mtu(struct net_device *dev, int new_mtu)
1246 {
1247 struct cp_private *cp = netdev_priv(dev);
1248 int rc;
1249 unsigned long flags;
1250
1251 /* check for invalid MTU, according to hardware limits */
1252 if (new_mtu < CP_MIN_MTU || new_mtu > CP_MAX_MTU)
1253 return -EINVAL;
1254
1255 /* if network interface not up, no need for complexity */
1256 if (!netif_running(dev)) {
1257 dev->mtu = new_mtu;
1258 cp_set_rxbufsize(cp); /* set new rx buf size */
1259 return 0;
1260 }
1261
1262 spin_lock_irqsave(&cp->lock, flags);
1263
1264 cp_stop_hw(cp); /* stop h/w and free rings */
1265 cp_clean_rings(cp);
1266
1267 dev->mtu = new_mtu;
1268 cp_set_rxbufsize(cp); /* set new rx buf size */
1269
1270 rc = cp_init_rings(cp); /* realloc and restart h/w */
1271 cp_start_hw(cp);
1272
1273 spin_unlock_irqrestore(&cp->lock, flags);
1274
1275 return rc;
1276 }
1277 #endif /* BROKEN */
1278
1279 static const char mii_2_8139_map[8] = {
1280 BasicModeCtrl,
1281 BasicModeStatus,
1282 0,
1283 0,
1284 NWayAdvert,
1285 NWayLPAR,
1286 NWayExpansion,
1287 0
1288 };
1289
1290 static int mdio_read(struct net_device *dev, int phy_id, int location)
1291 {
1292 struct cp_private *cp = netdev_priv(dev);
1293
1294 return location < 8 && mii_2_8139_map[location] ?
1295 readw(cp->regs + mii_2_8139_map[location]) : 0;
1296 }
1297
1298
1299 static void mdio_write(struct net_device *dev, int phy_id, int location,
1300 int value)
1301 {
1302 struct cp_private *cp = netdev_priv(dev);
1303
1304 if (location == 0) {
1305 cpw8(Cfg9346, Cfg9346_Unlock);
1306 cpw16(BasicModeCtrl, value);
1307 cpw8(Cfg9346, Cfg9346_Lock);
1308 } else if (location < 8 && mii_2_8139_map[location])
1309 cpw16(mii_2_8139_map[location], value);
1310 }
1311
1312 /* Set the ethtool Wake-on-LAN settings */
1313 static int netdev_set_wol (struct cp_private *cp,
1314 const struct ethtool_wolinfo *wol)
1315 {
1316 u8 options;
1317
1318 options = cpr8 (Config3) & ~(LinkUp | MagicPacket);
1319 /* If WOL is being disabled, no need for complexity */
1320 if (wol->wolopts) {
1321 if (wol->wolopts & WAKE_PHY) options |= LinkUp;
1322 if (wol->wolopts & WAKE_MAGIC) options |= MagicPacket;
1323 }
1324
1325 cpw8 (Cfg9346, Cfg9346_Unlock);
1326 cpw8 (Config3, options);
1327 cpw8 (Cfg9346, Cfg9346_Lock);
1328
1329 options = 0; /* Paranoia setting */
1330 options = cpr8 (Config5) & ~(UWF | MWF | BWF);
1331 /* If WOL is being disabled, no need for complexity */
1332 if (wol->wolopts) {
1333 if (wol->wolopts & WAKE_UCAST) options |= UWF;
1334 if (wol->wolopts & WAKE_BCAST) options |= BWF;
1335 if (wol->wolopts & WAKE_MCAST) options |= MWF;
1336 }
1337
1338 cpw8 (Config5, options);
1339
1340 cp->wol_enabled = (wol->wolopts) ? 1 : 0;
1341
1342 return 0;
1343 }
1344
1345 /* Get the ethtool Wake-on-LAN settings */
1346 static void netdev_get_wol (struct cp_private *cp,
1347 struct ethtool_wolinfo *wol)
1348 {
1349 u8 options;
1350
1351 wol->wolopts = 0; /* Start from scratch */
1352 wol->supported = WAKE_PHY | WAKE_BCAST | WAKE_MAGIC |
1353 WAKE_MCAST | WAKE_UCAST;
1354 /* We don't need to go on if WOL is disabled */
1355 if (!cp->wol_enabled) return;
1356
1357 options = cpr8 (Config3);
1358 if (options & LinkUp) wol->wolopts |= WAKE_PHY;
1359 if (options & MagicPacket) wol->wolopts |= WAKE_MAGIC;
1360
1361 options = 0; /* Paranoia setting */
1362 options = cpr8 (Config5);
1363 if (options & UWF) wol->wolopts |= WAKE_UCAST;
1364 if (options & BWF) wol->wolopts |= WAKE_BCAST;
1365 if (options & MWF) wol->wolopts |= WAKE_MCAST;
1366 }
1367
1368 static void cp_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1369 {
1370 struct cp_private *cp = netdev_priv(dev);
1371
1372 strcpy (info->driver, DRV_NAME);
1373 strcpy (info->version, DRV_VERSION);
1374 strcpy (info->bus_info, pci_name(cp->pdev));
1375 }
1376
1377 static int cp_get_regs_len(struct net_device *dev)
1378 {
1379 return CP_REGS_SIZE;
1380 }
1381
1382 static int cp_get_stats_count (struct net_device *dev)
1383 {
1384 return CP_NUM_STATS;
1385 }
1386
1387 static int cp_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1388 {
1389 struct cp_private *cp = netdev_priv(dev);
1390 int rc;
1391 unsigned long flags;
1392
1393 spin_lock_irqsave(&cp->lock, flags);
1394 rc = mii_ethtool_gset(&cp->mii_if, cmd);
1395 spin_unlock_irqrestore(&cp->lock, flags);
1396
1397 return rc;
1398 }
1399
1400 static int cp_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1401 {
1402 struct cp_private *cp = netdev_priv(dev);
1403 int rc;
1404 unsigned long flags;
1405
1406 spin_lock_irqsave(&cp->lock, flags);
1407 rc = mii_ethtool_sset(&cp->mii_if, cmd);
1408 spin_unlock_irqrestore(&cp->lock, flags);
1409
1410 return rc;
1411 }
1412
1413 static int cp_nway_reset(struct net_device *dev)
1414 {
1415 struct cp_private *cp = netdev_priv(dev);
1416 return mii_nway_restart(&cp->mii_if);
1417 }
1418
1419 static u32 cp_get_msglevel(struct net_device *dev)
1420 {
1421 struct cp_private *cp = netdev_priv(dev);
1422 return cp->msg_enable;
1423 }
1424
1425 static void cp_set_msglevel(struct net_device *dev, u32 value)
1426 {
1427 struct cp_private *cp = netdev_priv(dev);
1428 cp->msg_enable = value;
1429 }
1430
1431 static u32 cp_get_rx_csum(struct net_device *dev)
1432 {
1433 struct cp_private *cp = netdev_priv(dev);
1434 return (cpr16(CpCmd) & RxChkSum) ? 1 : 0;
1435 }
1436
1437 static int cp_set_rx_csum(struct net_device *dev, u32 data)
1438 {
1439 struct cp_private *cp = netdev_priv(dev);
1440 u16 cmd = cp->cpcmd, newcmd;
1441
1442 newcmd = cmd;
1443
1444 if (data)
1445 newcmd |= RxChkSum;
1446 else
1447 newcmd &= ~RxChkSum;
1448
1449 if (newcmd != cmd) {
1450 unsigned long flags;
1451
1452 spin_lock_irqsave(&cp->lock, flags);
1453 cp->cpcmd = newcmd;
1454 cpw16_f(CpCmd, newcmd);
1455 spin_unlock_irqrestore(&cp->lock, flags);
1456 }
1457
1458 return 0;
1459 }
1460
1461 static void cp_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1462 void *p)
1463 {
1464 struct cp_private *cp = netdev_priv(dev);
1465 unsigned long flags;
1466
1467 if (regs->len < CP_REGS_SIZE)
1468 return /* -EINVAL */;
1469
1470 regs->version = CP_REGS_VER;
1471
1472 spin_lock_irqsave(&cp->lock, flags);
1473 memcpy_fromio(p, cp->regs, CP_REGS_SIZE);
1474 spin_unlock_irqrestore(&cp->lock, flags);
1475 }
1476
1477 static void cp_get_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1478 {
1479 struct cp_private *cp = netdev_priv(dev);
1480 unsigned long flags;
1481
1482 spin_lock_irqsave (&cp->lock, flags);
1483 netdev_get_wol (cp, wol);
1484 spin_unlock_irqrestore (&cp->lock, flags);
1485 }
1486
1487 static int cp_set_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1488 {
1489 struct cp_private *cp = netdev_priv(dev);
1490 unsigned long flags;
1491 int rc;
1492
1493 spin_lock_irqsave (&cp->lock, flags);
1494 rc = netdev_set_wol (cp, wol);
1495 spin_unlock_irqrestore (&cp->lock, flags);
1496
1497 return rc;
1498 }
1499
1500 static void cp_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
1501 {
1502 switch (stringset) {
1503 case ETH_SS_STATS:
1504 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
1505 break;
1506 default:
1507 BUG();
1508 break;
1509 }
1510 }
1511
1512 static void cp_get_ethtool_stats (struct net_device *dev,
1513 struct ethtool_stats *estats, u64 *tmp_stats)
1514 {
1515 struct cp_private *cp = netdev_priv(dev);
1516 struct cp_dma_stats *nic_stats;
1517 dma_addr_t dma;
1518 int i;
1519
1520 nic_stats = pci_alloc_consistent(cp->pdev, sizeof(*nic_stats), &dma);
1521 if (!nic_stats)
1522 return;
1523
1524 /* begin NIC statistics dump */
1525 cpw32(StatsAddr + 4, (u64)dma >> 32);
1526 cpw32(StatsAddr, ((u64)dma & DMA_32BIT_MASK) | DumpStats);
1527 cpr32(StatsAddr);
1528
1529 for (i = 0; i < 1000; i++) {
1530 if ((cpr32(StatsAddr) & DumpStats) == 0)
1531 break;
1532 udelay(10);
1533 }
1534 cpw32(StatsAddr, 0);
1535 cpw32(StatsAddr + 4, 0);
1536 cpr32(StatsAddr);
1537
1538 i = 0;
1539 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_ok);
1540 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok);
1541 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_err);
1542 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_err);
1543 tmp_stats[i++] = le16_to_cpu(nic_stats->rx_fifo);
1544 tmp_stats[i++] = le16_to_cpu(nic_stats->frame_align);
1545 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_1col);
1546 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_mcol);
1547 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_phys);
1548 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_bcast);
1549 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_ok_mcast);
1550 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_abort);
1551 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_underrun);
1552 tmp_stats[i++] = cp->cp_stats.rx_frags;
1553 BUG_ON(i != CP_NUM_STATS);
1554
1555 pci_free_consistent(cp->pdev, sizeof(*nic_stats), nic_stats, dma);
1556 }
1557
1558 static const struct ethtool_ops cp_ethtool_ops = {
1559 .get_drvinfo = cp_get_drvinfo,
1560 .get_regs_len = cp_get_regs_len,
1561 .get_stats_count = cp_get_stats_count,
1562 .get_settings = cp_get_settings,
1563 .set_settings = cp_set_settings,
1564 .nway_reset = cp_nway_reset,
1565 .get_link = ethtool_op_get_link,
1566 .get_msglevel = cp_get_msglevel,
1567 .set_msglevel = cp_set_msglevel,
1568 .get_rx_csum = cp_get_rx_csum,
1569 .set_rx_csum = cp_set_rx_csum,
1570 .get_tx_csum = ethtool_op_get_tx_csum,
1571 .set_tx_csum = ethtool_op_set_tx_csum, /* local! */
1572 .get_sg = ethtool_op_get_sg,
1573 .set_sg = ethtool_op_set_sg,
1574 .get_tso = ethtool_op_get_tso,
1575 .set_tso = ethtool_op_set_tso,
1576 .get_regs = cp_get_regs,
1577 .get_wol = cp_get_wol,
1578 .set_wol = cp_set_wol,
1579 .get_strings = cp_get_strings,
1580 .get_ethtool_stats = cp_get_ethtool_stats,
1581 .get_perm_addr = ethtool_op_get_perm_addr,
1582 .get_eeprom_len = cp_get_eeprom_len,
1583 .get_eeprom = cp_get_eeprom,
1584 .set_eeprom = cp_set_eeprom,
1585 };
1586
1587 static int cp_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1588 {
1589 struct cp_private *cp = netdev_priv(dev);
1590 int rc;
1591 unsigned long flags;
1592
1593 if (!netif_running(dev))
1594 return -EINVAL;
1595
1596 spin_lock_irqsave(&cp->lock, flags);
1597 rc = generic_mii_ioctl(&cp->mii_if, if_mii(rq), cmd, NULL);
1598 spin_unlock_irqrestore(&cp->lock, flags);
1599 return rc;
1600 }
1601
1602 /* Serial EEPROM section. */
1603
1604 /* EEPROM_Ctrl bits. */
1605 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1606 #define EE_CS 0x08 /* EEPROM chip select. */
1607 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1608 #define EE_WRITE_0 0x00
1609 #define EE_WRITE_1 0x02
1610 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1611 #define EE_ENB (0x80 | EE_CS)
1612
1613 /* Delay between EEPROM clock transitions.
1614 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1615 */
1616
1617 #define eeprom_delay() readl(ee_addr)
1618
1619 /* The EEPROM commands include the alway-set leading bit. */
1620 #define EE_EXTEND_CMD (4)
1621 #define EE_WRITE_CMD (5)
1622 #define EE_READ_CMD (6)
1623 #define EE_ERASE_CMD (7)
1624
1625 #define EE_EWDS_ADDR (0)
1626 #define EE_WRAL_ADDR (1)
1627 #define EE_ERAL_ADDR (2)
1628 #define EE_EWEN_ADDR (3)
1629
1630 #define CP_EEPROM_MAGIC PCI_DEVICE_ID_REALTEK_8139
1631
1632 static void eeprom_cmd_start(void __iomem *ee_addr)
1633 {
1634 writeb (EE_ENB & ~EE_CS, ee_addr);
1635 writeb (EE_ENB, ee_addr);
1636 eeprom_delay ();
1637 }
1638
1639 static void eeprom_cmd(void __iomem *ee_addr, int cmd, int cmd_len)
1640 {
1641 int i;
1642
1643 /* Shift the command bits out. */
1644 for (i = cmd_len - 1; i >= 0; i--) {
1645 int dataval = (cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1646 writeb (EE_ENB | dataval, ee_addr);
1647 eeprom_delay ();
1648 writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
1649 eeprom_delay ();
1650 }
1651 writeb (EE_ENB, ee_addr);
1652 eeprom_delay ();
1653 }
1654
1655 static void eeprom_cmd_end(void __iomem *ee_addr)
1656 {
1657 writeb (~EE_CS, ee_addr);
1658 eeprom_delay ();
1659 }
1660
1661 static void eeprom_extend_cmd(void __iomem *ee_addr, int extend_cmd,
1662 int addr_len)
1663 {
1664 int cmd = (EE_EXTEND_CMD << addr_len) | (extend_cmd << (addr_len - 2));
1665
1666 eeprom_cmd_start(ee_addr);
1667 eeprom_cmd(ee_addr, cmd, 3 + addr_len);
1668 eeprom_cmd_end(ee_addr);
1669 }
1670
1671 static u16 read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1672 {
1673 int i;
1674 u16 retval = 0;
1675 void __iomem *ee_addr = ioaddr + Cfg9346;
1676 int read_cmd = location | (EE_READ_CMD << addr_len);
1677
1678 eeprom_cmd_start(ee_addr);
1679 eeprom_cmd(ee_addr, read_cmd, 3 + addr_len);
1680
1681 for (i = 16; i > 0; i--) {
1682 writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
1683 eeprom_delay ();
1684 retval =
1685 (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
1686 0);
1687 writeb (EE_ENB, ee_addr);
1688 eeprom_delay ();
1689 }
1690
1691 eeprom_cmd_end(ee_addr);
1692
1693 return retval;
1694 }
1695
1696 static void write_eeprom(void __iomem *ioaddr, int location, u16 val,
1697 int addr_len)
1698 {
1699 int i;
1700 void __iomem *ee_addr = ioaddr + Cfg9346;
1701 int write_cmd = location | (EE_WRITE_CMD << addr_len);
1702
1703 eeprom_extend_cmd(ee_addr, EE_EWEN_ADDR, addr_len);
1704
1705 eeprom_cmd_start(ee_addr);
1706 eeprom_cmd(ee_addr, write_cmd, 3 + addr_len);
1707 eeprom_cmd(ee_addr, val, 16);
1708 eeprom_cmd_end(ee_addr);
1709
1710 eeprom_cmd_start(ee_addr);
1711 for (i = 0; i < 20000; i++)
1712 if (readb(ee_addr) & EE_DATA_READ)
1713 break;
1714 eeprom_cmd_end(ee_addr);
1715
1716 eeprom_extend_cmd(ee_addr, EE_EWDS_ADDR, addr_len);
1717 }
1718
1719 static int cp_get_eeprom_len(struct net_device *dev)
1720 {
1721 struct cp_private *cp = netdev_priv(dev);
1722 int size;
1723
1724 spin_lock_irq(&cp->lock);
1725 size = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 256 : 128;
1726 spin_unlock_irq(&cp->lock);
1727
1728 return size;
1729 }
1730
1731 static int cp_get_eeprom(struct net_device *dev,
1732 struct ethtool_eeprom *eeprom, u8 *data)
1733 {
1734 struct cp_private *cp = netdev_priv(dev);
1735 unsigned int addr_len;
1736 u16 val;
1737 u32 offset = eeprom->offset >> 1;
1738 u32 len = eeprom->len;
1739 u32 i = 0;
1740
1741 eeprom->magic = CP_EEPROM_MAGIC;
1742
1743 spin_lock_irq(&cp->lock);
1744
1745 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
1746
1747 if (eeprom->offset & 1) {
1748 val = read_eeprom(cp->regs, offset, addr_len);
1749 data[i++] = (u8)(val >> 8);
1750 offset++;
1751 }
1752
1753 while (i < len - 1) {
1754 val = read_eeprom(cp->regs, offset, addr_len);
1755 data[i++] = (u8)val;
1756 data[i++] = (u8)(val >> 8);
1757 offset++;
1758 }
1759
1760 if (i < len) {
1761 val = read_eeprom(cp->regs, offset, addr_len);
1762 data[i] = (u8)val;
1763 }
1764
1765 spin_unlock_irq(&cp->lock);
1766 return 0;
1767 }
1768
1769 static int cp_set_eeprom(struct net_device *dev,
1770 struct ethtool_eeprom *eeprom, u8 *data)
1771 {
1772 struct cp_private *cp = netdev_priv(dev);
1773 unsigned int addr_len;
1774 u16 val;
1775 u32 offset = eeprom->offset >> 1;
1776 u32 len = eeprom->len;
1777 u32 i = 0;
1778
1779 if (eeprom->magic != CP_EEPROM_MAGIC)
1780 return -EINVAL;
1781
1782 spin_lock_irq(&cp->lock);
1783
1784 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
1785
1786 if (eeprom->offset & 1) {
1787 val = read_eeprom(cp->regs, offset, addr_len) & 0xff;
1788 val |= (u16)data[i++] << 8;
1789 write_eeprom(cp->regs, offset, val, addr_len);
1790 offset++;
1791 }
1792
1793 while (i < len - 1) {
1794 val = (u16)data[i++];
1795 val |= (u16)data[i++] << 8;
1796 write_eeprom(cp->regs, offset, val, addr_len);
1797 offset++;
1798 }
1799
1800 if (i < len) {
1801 val = read_eeprom(cp->regs, offset, addr_len) & 0xff00;
1802 val |= (u16)data[i];
1803 write_eeprom(cp->regs, offset, val, addr_len);
1804 }
1805
1806 spin_unlock_irq(&cp->lock);
1807 return 0;
1808 }
1809
1810 /* Put the board into D3cold state and wait for WakeUp signal */
1811 static void cp_set_d3_state (struct cp_private *cp)
1812 {
1813 pci_enable_wake (cp->pdev, 0, 1); /* Enable PME# generation */
1814 pci_set_power_state (cp->pdev, PCI_D3hot);
1815 }
1816
1817 static int cp_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1818 {
1819 struct net_device *dev;
1820 struct cp_private *cp;
1821 int rc;
1822 void __iomem *regs;
1823 resource_size_t pciaddr;
1824 unsigned int addr_len, i, pci_using_dac;
1825
1826 #ifndef MODULE
1827 static int version_printed;
1828 if (version_printed++ == 0)
1829 printk("%s", version);
1830 #endif
1831
1832 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
1833 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision < 0x20) {
1834 dev_err(&pdev->dev,
1835 "This (id %04x:%04x rev %02x) is not an 8139C+ compatible chip\n",
1836 pdev->vendor, pdev->device, pdev->revision);
1837 dev_err(&pdev->dev, "Try the \"8139too\" driver instead.\n");
1838 return -ENODEV;
1839 }
1840
1841 dev = alloc_etherdev(sizeof(struct cp_private));
1842 if (!dev)
1843 return -ENOMEM;
1844 SET_MODULE_OWNER(dev);
1845 SET_NETDEV_DEV(dev, &pdev->dev);
1846
1847 cp = netdev_priv(dev);
1848 cp->pdev = pdev;
1849 cp->dev = dev;
1850 cp->msg_enable = (debug < 0 ? CP_DEF_MSG_ENABLE : debug);
1851 spin_lock_init (&cp->lock);
1852 cp->mii_if.dev = dev;
1853 cp->mii_if.mdio_read = mdio_read;
1854 cp->mii_if.mdio_write = mdio_write;
1855 cp->mii_if.phy_id = CP_INTERNAL_PHY;
1856 cp->mii_if.phy_id_mask = 0x1f;
1857 cp->mii_if.reg_num_mask = 0x1f;
1858 cp_set_rxbufsize(cp);
1859
1860 rc = pci_enable_device(pdev);
1861 if (rc)
1862 goto err_out_free;
1863
1864 rc = pci_set_mwi(pdev);
1865 if (rc)
1866 goto err_out_disable;
1867
1868 rc = pci_request_regions(pdev, DRV_NAME);
1869 if (rc)
1870 goto err_out_mwi;
1871
1872 pciaddr = pci_resource_start(pdev, 1);
1873 if (!pciaddr) {
1874 rc = -EIO;
1875 dev_err(&pdev->dev, "no MMIO resource\n");
1876 goto err_out_res;
1877 }
1878 if (pci_resource_len(pdev, 1) < CP_REGS_SIZE) {
1879 rc = -EIO;
1880 dev_err(&pdev->dev, "MMIO resource (%llx) too small\n",
1881 (unsigned long long)pci_resource_len(pdev, 1));
1882 goto err_out_res;
1883 }
1884
1885 /* Configure DMA attributes. */
1886 if ((sizeof(dma_addr_t) > 4) &&
1887 !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) &&
1888 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1889 pci_using_dac = 1;
1890 } else {
1891 pci_using_dac = 0;
1892
1893 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1894 if (rc) {
1895 dev_err(&pdev->dev,
1896 "No usable DMA configuration, aborting.\n");
1897 goto err_out_res;
1898 }
1899 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1900 if (rc) {
1901 dev_err(&pdev->dev,
1902 "No usable consistent DMA configuration, "
1903 "aborting.\n");
1904 goto err_out_res;
1905 }
1906 }
1907
1908 cp->cpcmd = (pci_using_dac ? PCIDAC : 0) |
1909 PCIMulRW | RxChkSum | CpRxOn | CpTxOn;
1910
1911 regs = ioremap(pciaddr, CP_REGS_SIZE);
1912 if (!regs) {
1913 rc = -EIO;
1914 dev_err(&pdev->dev, "Cannot map PCI MMIO (%Lx@%Lx)\n",
1915 (unsigned long long)pci_resource_len(pdev, 1),
1916 (unsigned long long)pciaddr);
1917 goto err_out_res;
1918 }
1919 dev->base_addr = (unsigned long) regs;
1920 cp->regs = regs;
1921
1922 cp_stop_hw(cp);
1923
1924 /* read MAC address from EEPROM */
1925 addr_len = read_eeprom (regs, 0, 8) == 0x8129 ? 8 : 6;
1926 for (i = 0; i < 3; i++)
1927 ((u16 *) (dev->dev_addr))[i] =
1928 le16_to_cpu (read_eeprom (regs, i + 7, addr_len));
1929 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1930
1931 dev->open = cp_open;
1932 dev->stop = cp_close;
1933 dev->set_multicast_list = cp_set_rx_mode;
1934 dev->hard_start_xmit = cp_start_xmit;
1935 dev->get_stats = cp_get_stats;
1936 dev->do_ioctl = cp_ioctl;
1937 dev->poll = cp_rx_poll;
1938 #ifdef CONFIG_NET_POLL_CONTROLLER
1939 dev->poll_controller = cp_poll_controller;
1940 #endif
1941 dev->weight = 16; /* arbitrary? from NAPI_HOWTO.txt. */
1942 #ifdef BROKEN
1943 dev->change_mtu = cp_change_mtu;
1944 #endif
1945 dev->ethtool_ops = &cp_ethtool_ops;
1946 dev->tx_timeout = cp_tx_timeout;
1947 dev->watchdog_timeo = TX_TIMEOUT;
1948
1949 #if CP_VLAN_TAG_USED
1950 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1951 dev->vlan_rx_register = cp_vlan_rx_register;
1952 #endif
1953
1954 if (pci_using_dac)
1955 dev->features |= NETIF_F_HIGHDMA;
1956
1957 #if 0 /* disabled by default until verified */
1958 dev->features |= NETIF_F_TSO;
1959 #endif
1960
1961 dev->irq = pdev->irq;
1962
1963 rc = register_netdev(dev);
1964 if (rc)
1965 goto err_out_iomap;
1966
1967 printk (KERN_INFO "%s: RTL-8139C+ at 0x%lx, "
1968 "%02x:%02x:%02x:%02x:%02x:%02x, "
1969 "IRQ %d\n",
1970 dev->name,
1971 dev->base_addr,
1972 dev->dev_addr[0], dev->dev_addr[1],
1973 dev->dev_addr[2], dev->dev_addr[3],
1974 dev->dev_addr[4], dev->dev_addr[5],
1975 dev->irq);
1976
1977 pci_set_drvdata(pdev, dev);
1978
1979 /* enable busmastering and memory-write-invalidate */
1980 pci_set_master(pdev);
1981
1982 if (cp->wol_enabled)
1983 cp_set_d3_state (cp);
1984
1985 return 0;
1986
1987 err_out_iomap:
1988 iounmap(regs);
1989 err_out_res:
1990 pci_release_regions(pdev);
1991 err_out_mwi:
1992 pci_clear_mwi(pdev);
1993 err_out_disable:
1994 pci_disable_device(pdev);
1995 err_out_free:
1996 free_netdev(dev);
1997 return rc;
1998 }
1999
2000 static void cp_remove_one (struct pci_dev *pdev)
2001 {
2002 struct net_device *dev = pci_get_drvdata(pdev);
2003 struct cp_private *cp = netdev_priv(dev);
2004
2005 unregister_netdev(dev);
2006 iounmap(cp->regs);
2007 if (cp->wol_enabled)
2008 pci_set_power_state (pdev, PCI_D0);
2009 pci_release_regions(pdev);
2010 pci_clear_mwi(pdev);
2011 pci_disable_device(pdev);
2012 pci_set_drvdata(pdev, NULL);
2013 free_netdev(dev);
2014 }
2015
2016 #ifdef CONFIG_PM
2017 static int cp_suspend (struct pci_dev *pdev, pm_message_t state)
2018 {
2019 struct net_device *dev = pci_get_drvdata(pdev);
2020 struct cp_private *cp = netdev_priv(dev);
2021 unsigned long flags;
2022
2023 if (!netif_running(dev))
2024 return 0;
2025
2026 netif_device_detach (dev);
2027 netif_stop_queue (dev);
2028
2029 spin_lock_irqsave (&cp->lock, flags);
2030
2031 /* Disable Rx and Tx */
2032 cpw16 (IntrMask, 0);
2033 cpw8 (Cmd, cpr8 (Cmd) & (~RxOn | ~TxOn));
2034
2035 spin_unlock_irqrestore (&cp->lock, flags);
2036
2037 pci_save_state(pdev);
2038 pci_enable_wake(pdev, pci_choose_state(pdev, state), cp->wol_enabled);
2039 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2040
2041 return 0;
2042 }
2043
2044 static int cp_resume (struct pci_dev *pdev)
2045 {
2046 struct net_device *dev = pci_get_drvdata (pdev);
2047 struct cp_private *cp = netdev_priv(dev);
2048 unsigned long flags;
2049
2050 if (!netif_running(dev))
2051 return 0;
2052
2053 netif_device_attach (dev);
2054
2055 pci_set_power_state(pdev, PCI_D0);
2056 pci_restore_state(pdev);
2057 pci_enable_wake(pdev, PCI_D0, 0);
2058
2059 /* FIXME: sh*t may happen if the Rx ring buffer is depleted */
2060 cp_init_rings_index (cp);
2061 cp_init_hw (cp);
2062 netif_start_queue (dev);
2063
2064 spin_lock_irqsave (&cp->lock, flags);
2065
2066 mii_check_media(&cp->mii_if, netif_msg_link(cp), false);
2067
2068 spin_unlock_irqrestore (&cp->lock, flags);
2069
2070 return 0;
2071 }
2072 #endif /* CONFIG_PM */
2073
2074 static struct pci_driver cp_driver = {
2075 .name = DRV_NAME,
2076 .id_table = cp_pci_tbl,
2077 .probe = cp_init_one,
2078 .remove = cp_remove_one,
2079 #ifdef CONFIG_PM
2080 .resume = cp_resume,
2081 .suspend = cp_suspend,
2082 #endif
2083 };
2084
2085 static int __init cp_init (void)
2086 {
2087 #ifdef MODULE
2088 printk("%s", version);
2089 #endif
2090 return pci_register_driver(&cp_driver);
2091 }
2092
2093 static void __exit cp_exit (void)
2094 {
2095 pci_unregister_driver (&cp_driver);
2096 }
2097
2098 module_init(cp_init);
2099 module_exit(cp_exit);
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