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remove unused TIF_NOTIFY_RESUME flag
[pv_ops_mirror.git] / drivers / net / sundance.c
blobaf0c9831074c62c4c9d14d4fad624fcd81bd0391
1 /* sundance.c: A Linux device driver for the Sundance ST201 "Alta". */
2 /*
3 Written 1999-2000 by Donald Becker.
4
5 This software may be used and distributed according to the terms of
6 the GNU General Public License (GPL), incorporated herein by reference.
7 Drivers based on or derived from this code fall under the GPL and must
8 retain the authorship, copyright and license notice. This file is not
9 a complete program and may only be used when the entire operating
10 system is licensed under the GPL.
11
12 The author may be reached as becker@scyld.com, or C/O
13 Scyld Computing Corporation
14 410 Severn Ave., Suite 210
15 Annapolis MD 21403
16
17 Support and updates available at
18 http://www.scyld.com/network/sundance.html
19 [link no longer provides useful info -jgarzik]
20 Archives of the mailing list are still available at
21 http://www.beowulf.org/pipermail/netdrivers/
22
23 */
24
25 #define DRV_NAME "sundance"
26 #define DRV_VERSION "1.2"
27 #define DRV_RELDATE "11-Sep-2006"
28
29
30 /* The user-configurable values.
31 These may be modified when a driver module is loaded.*/
32 static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
33 /* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
34 Typical is a 64 element hash table based on the Ethernet CRC. */
35 static const int multicast_filter_limit = 32;
36
37 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
38 Setting to > 1518 effectively disables this feature.
39 This chip can receive into offset buffers, so the Alpha does not
40 need a copy-align. */
41 static int rx_copybreak;
42 static int flowctrl=1;
43
44 /* media[] specifies the media type the NIC operates at.
45 autosense Autosensing active media.
46 10mbps_hd 10Mbps half duplex.
47 10mbps_fd 10Mbps full duplex.
48 100mbps_hd 100Mbps half duplex.
49 100mbps_fd 100Mbps full duplex.
50 0 Autosensing active media.
51 1 10Mbps half duplex.
52 2 10Mbps full duplex.
53 3 100Mbps half duplex.
54 4 100Mbps full duplex.
55 */
56 #define MAX_UNITS 8
57 static char *media[MAX_UNITS];
58
59
60 /* Operational parameters that are set at compile time. */
61
62 /* Keep the ring sizes a power of two for compile efficiency.
63 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
64 Making the Tx ring too large decreases the effectiveness of channel
65 bonding and packet priority, and more than 128 requires modifying the
66 Tx error recovery.
67 Large receive rings merely waste memory. */
68 #define TX_RING_SIZE 32
69 #define TX_QUEUE_LEN (TX_RING_SIZE - 1) /* Limit ring entries actually used. */
70 #define RX_RING_SIZE 64
71 #define RX_BUDGET 32
72 #define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct netdev_desc)
73 #define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct netdev_desc)
74
75 /* Operational parameters that usually are not changed. */
76 /* Time in jiffies before concluding the transmitter is hung. */
77 #define TX_TIMEOUT (4*HZ)
78 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
79
80 /* Include files, designed to support most kernel versions 2.0.0 and later. */
81 #include <linux/module.h>
82 #include <linux/kernel.h>
83 #include <linux/string.h>
84 #include <linux/timer.h>
85 #include <linux/errno.h>
86 #include <linux/ioport.h>
87 #include <linux/slab.h>
88 #include <linux/interrupt.h>
89 #include <linux/pci.h>
90 #include <linux/netdevice.h>
91 #include <linux/etherdevice.h>
92 #include <linux/skbuff.h>
93 #include <linux/init.h>
94 #include <linux/bitops.h>
95 #include <asm/uaccess.h>
96 #include <asm/processor.h> /* Processor type for cache alignment. */
97 #include <asm/io.h>
98 #include <linux/delay.h>
99 #include <linux/spinlock.h>
100 #ifndef _COMPAT_WITH_OLD_KERNEL
101 #include <linux/crc32.h>
102 #include <linux/ethtool.h>
103 #include <linux/mii.h>
104 #else
105 #include "crc32.h"
106 #include "ethtool.h"
107 #include "mii.h"
108 #include "compat.h"
109 #endif
110
111 /* These identify the driver base version and may not be removed. */
112 static char version[] =
113 KERN_INFO DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " Written by Donald Becker\n";
114
115 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
116 MODULE_DESCRIPTION("Sundance Alta Ethernet driver");
117 MODULE_LICENSE("GPL");
118
119 module_param(debug, int, 0);
120 module_param(rx_copybreak, int, 0);
121 module_param_array(media, charp, NULL, 0);
122 module_param(flowctrl, int, 0);
123 MODULE_PARM_DESC(debug, "Sundance Alta debug level (0-5)");
124 MODULE_PARM_DESC(rx_copybreak, "Sundance Alta copy breakpoint for copy-only-tiny-frames");
125 MODULE_PARM_DESC(flowctrl, "Sundance Alta flow control [0|1]");
126
127 /*
128 Theory of Operation
129
130 I. Board Compatibility
131
132 This driver is designed for the Sundance Technologies "Alta" ST201 chip.
133
134 II. Board-specific settings
135
136 III. Driver operation
137
138 IIIa. Ring buffers
139
140 This driver uses two statically allocated fixed-size descriptor lists
141 formed into rings by a branch from the final descriptor to the beginning of
142 the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
143 Some chips explicitly use only 2^N sized rings, while others use a
144 'next descriptor' pointer that the driver forms into rings.
145
146 IIIb/c. Transmit/Receive Structure
147
148 This driver uses a zero-copy receive and transmit scheme.
149 The driver allocates full frame size skbuffs for the Rx ring buffers at
150 open() time and passes the skb->data field to the chip as receive data
151 buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
152 a fresh skbuff is allocated and the frame is copied to the new skbuff.
153 When the incoming frame is larger, the skbuff is passed directly up the
154 protocol stack. Buffers consumed this way are replaced by newly allocated
155 skbuffs in a later phase of receives.
156
157 The RX_COPYBREAK value is chosen to trade-off the memory wasted by
158 using a full-sized skbuff for small frames vs. the copying costs of larger
159 frames. New boards are typically used in generously configured machines
160 and the underfilled buffers have negligible impact compared to the benefit of
161 a single allocation size, so the default value of zero results in never
162 copying packets. When copying is done, the cost is usually mitigated by using
163 a combined copy/checksum routine. Copying also preloads the cache, which is
164 most useful with small frames.
165
166 A subtle aspect of the operation is that the IP header at offset 14 in an
167 ethernet frame isn't longword aligned for further processing.
168 Unaligned buffers are permitted by the Sundance hardware, so
169 frames are received into the skbuff at an offset of "+2", 16-byte aligning
170 the IP header.
171
172 IIId. Synchronization
173
174 The driver runs as two independent, single-threaded flows of control. One
175 is the send-packet routine, which enforces single-threaded use by the
176 dev->tbusy flag. The other thread is the interrupt handler, which is single
177 threaded by the hardware and interrupt handling software.
178
179 The send packet thread has partial control over the Tx ring and 'dev->tbusy'
180 flag. It sets the tbusy flag whenever it's queuing a Tx packet. If the next
181 queue slot is empty, it clears the tbusy flag when finished otherwise it sets
182 the 'lp->tx_full' flag.
183
184 The interrupt handler has exclusive control over the Rx ring and records stats
185 from the Tx ring. After reaping the stats, it marks the Tx queue entry as
186 empty by incrementing the dirty_tx mark. Iff the 'lp->tx_full' flag is set, it
187 clears both the tx_full and tbusy flags.
188
189 IV. Notes
190
191 IVb. References
192
193 The Sundance ST201 datasheet, preliminary version.
194 The Kendin KS8723 datasheet, preliminary version.
195 The ICplus IP100 datasheet, preliminary version.
196 http://www.scyld.com/expert/100mbps.html
197 http://www.scyld.com/expert/NWay.html
198
199 IVc. Errata
200
201 */
202
203 /* Work-around for Kendin chip bugs. */
204 #ifndef CONFIG_SUNDANCE_MMIO
205 #define USE_IO_OPS 1
206 #endif
207
208 static const struct pci_device_id sundance_pci_tbl[] = {
209 { 0x1186, 0x1002, 0x1186, 0x1002, 0, 0, 0 },
210 { 0x1186, 0x1002, 0x1186, 0x1003, 0, 0, 1 },
211 { 0x1186, 0x1002, 0x1186, 0x1012, 0, 0, 2 },
212 { 0x1186, 0x1002, 0x1186, 0x1040, 0, 0, 3 },
213 { 0x1186, 0x1002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
214 { 0x13F0, 0x0201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5 },
215 { 0x13F0, 0x0200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6 },
216 { }
217 };
218 MODULE_DEVICE_TABLE(pci, sundance_pci_tbl);
219
220 enum {
221 netdev_io_size = 128
222 };
223
224 struct pci_id_info {
225 const char *name;
226 };
227 static const struct pci_id_info pci_id_tbl[] __devinitdata = {
228 {"D-Link DFE-550TX FAST Ethernet Adapter"},
229 {"D-Link DFE-550FX 100Mbps Fiber-optics Adapter"},
230 {"D-Link DFE-580TX 4 port Server Adapter"},
231 {"D-Link DFE-530TXS FAST Ethernet Adapter"},
232 {"D-Link DL10050-based FAST Ethernet Adapter"},
233 {"Sundance Technology Alta"},
234 {"IC Plus Corporation IP100A FAST Ethernet Adapter"},
235 { } /* terminate list. */
236 };
237
238 /* This driver was written to use PCI memory space, however x86-oriented
239 hardware often uses I/O space accesses. */
240
241 /* Offsets to the device registers.
242 Unlike software-only systems, device drivers interact with complex hardware.
243 It's not useful to define symbolic names for every register bit in the
244 device. The name can only partially document the semantics and make
245 the driver longer and more difficult to read.
246 In general, only the important configuration values or bits changed
247 multiple times should be defined symbolically.
248 */
249 enum alta_offsets {
250 DMACtrl = 0x00,
251 TxListPtr = 0x04,
252 TxDMABurstThresh = 0x08,
253 TxDMAUrgentThresh = 0x09,
254 TxDMAPollPeriod = 0x0a,
255 RxDMAStatus = 0x0c,
256 RxListPtr = 0x10,
257 DebugCtrl0 = 0x1a,
258 DebugCtrl1 = 0x1c,
259 RxDMABurstThresh = 0x14,
260 RxDMAUrgentThresh = 0x15,
261 RxDMAPollPeriod = 0x16,
262 LEDCtrl = 0x1a,
263 ASICCtrl = 0x30,
264 EEData = 0x34,
265 EECtrl = 0x36,
266 FlashAddr = 0x40,
267 FlashData = 0x44,
268 TxStatus = 0x46,
269 TxFrameId = 0x47,
270 DownCounter = 0x18,
271 IntrClear = 0x4a,
272 IntrEnable = 0x4c,
273 IntrStatus = 0x4e,
274 MACCtrl0 = 0x50,
275 MACCtrl1 = 0x52,
276 StationAddr = 0x54,
277 MaxFrameSize = 0x5A,
278 RxMode = 0x5c,
279 MIICtrl = 0x5e,
280 MulticastFilter0 = 0x60,
281 MulticastFilter1 = 0x64,
282 RxOctetsLow = 0x68,
283 RxOctetsHigh = 0x6a,
284 TxOctetsLow = 0x6c,
285 TxOctetsHigh = 0x6e,
286 TxFramesOK = 0x70,
287 RxFramesOK = 0x72,
288 StatsCarrierError = 0x74,
289 StatsLateColl = 0x75,
290 StatsMultiColl = 0x76,
291 StatsOneColl = 0x77,
292 StatsTxDefer = 0x78,
293 RxMissed = 0x79,
294 StatsTxXSDefer = 0x7a,
295 StatsTxAbort = 0x7b,
296 StatsBcastTx = 0x7c,
297 StatsBcastRx = 0x7d,
298 StatsMcastTx = 0x7e,
299 StatsMcastRx = 0x7f,
300 /* Aliased and bogus values! */
301 RxStatus = 0x0c,
302 };
303 enum ASICCtrl_HiWord_bit {
304 GlobalReset = 0x0001,
305 RxReset = 0x0002,
306 TxReset = 0x0004,
307 DMAReset = 0x0008,
308 FIFOReset = 0x0010,
309 NetworkReset = 0x0020,
310 HostReset = 0x0040,
311 ResetBusy = 0x0400,
312 };
313
314 /* Bits in the interrupt status/mask registers. */
315 enum intr_status_bits {
316 IntrSummary=0x0001, IntrPCIErr=0x0002, IntrMACCtrl=0x0008,
317 IntrTxDone=0x0004, IntrRxDone=0x0010, IntrRxStart=0x0020,
318 IntrDrvRqst=0x0040,
319 StatsMax=0x0080, LinkChange=0x0100,
320 IntrTxDMADone=0x0200, IntrRxDMADone=0x0400,
321 };
322
323 /* Bits in the RxMode register. */
324 enum rx_mode_bits {
325 AcceptAllIPMulti=0x20, AcceptMultiHash=0x10, AcceptAll=0x08,
326 AcceptBroadcast=0x04, AcceptMulticast=0x02, AcceptMyPhys=0x01,
327 };
328 /* Bits in MACCtrl. */
329 enum mac_ctrl0_bits {
330 EnbFullDuplex=0x20, EnbRcvLargeFrame=0x40,
331 EnbFlowCtrl=0x100, EnbPassRxCRC=0x200,
332 };
333 enum mac_ctrl1_bits {
334 StatsEnable=0x0020, StatsDisable=0x0040, StatsEnabled=0x0080,
335 TxEnable=0x0100, TxDisable=0x0200, TxEnabled=0x0400,
336 RxEnable=0x0800, RxDisable=0x1000, RxEnabled=0x2000,
337 };
338
339 /* The Rx and Tx buffer descriptors. */
340 /* Note that using only 32 bit fields simplifies conversion to big-endian
341 architectures. */
342 struct netdev_desc {
343 u32 next_desc;
344 u32 status;
345 struct desc_frag { u32 addr, length; } frag[1];
346 };
347
348 /* Bits in netdev_desc.status */
349 enum desc_status_bits {
350 DescOwn=0x8000,
351 DescEndPacket=0x4000,
352 DescEndRing=0x2000,
353 LastFrag=0x80000000,
354 DescIntrOnTx=0x8000,
355 DescIntrOnDMADone=0x80000000,
356 DisableAlign = 0x00000001,
357 };
358
359 #define PRIV_ALIGN 15 /* Required alignment mask */
360 /* Use __attribute__((aligned (L1_CACHE_BYTES))) to maintain alignment
361 within the structure. */
362 #define MII_CNT 4
363 struct netdev_private {
364 /* Descriptor rings first for alignment. */
365 struct netdev_desc *rx_ring;
366 struct netdev_desc *tx_ring;
367 struct sk_buff* rx_skbuff[RX_RING_SIZE];
368 struct sk_buff* tx_skbuff[TX_RING_SIZE];
369 dma_addr_t tx_ring_dma;
370 dma_addr_t rx_ring_dma;
371 struct net_device_stats stats;
372 struct timer_list timer; /* Media monitoring timer. */
373 /* Frequently used values: keep some adjacent for cache effect. */
374 spinlock_t lock;
375 spinlock_t rx_lock; /* Group with Tx control cache line. */
376 int msg_enable;
377 int chip_id;
378 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
379 unsigned int rx_buf_sz; /* Based on MTU+slack. */
380 struct netdev_desc *last_tx; /* Last Tx descriptor used. */
381 unsigned int cur_tx, dirty_tx;
382 /* These values are keep track of the transceiver/media in use. */
383 unsigned int flowctrl:1;
384 unsigned int default_port:4; /* Last dev->if_port value. */
385 unsigned int an_enable:1;
386 unsigned int speed;
387 struct tasklet_struct rx_tasklet;
388 struct tasklet_struct tx_tasklet;
389 int budget;
390 int cur_task;
391 /* Multicast and receive mode. */
392 spinlock_t mcastlock; /* SMP lock multicast updates. */
393 u16 mcast_filter[4];
394 /* MII transceiver section. */
395 struct mii_if_info mii_if;
396 int mii_preamble_required;
397 unsigned char phys[MII_CNT]; /* MII device addresses, only first one used. */
398 struct pci_dev *pci_dev;
399 void __iomem *base;
400 };
401
402 /* The station address location in the EEPROM. */
403 #define EEPROM_SA_OFFSET 0x10
404 #define DEFAULT_INTR (IntrRxDMADone | IntrPCIErr | \
405 IntrDrvRqst | IntrTxDone | StatsMax | \
406 LinkChange)
407
408 static int change_mtu(struct net_device *dev, int new_mtu);
409 static int eeprom_read(void __iomem *ioaddr, int location);
410 static int mdio_read(struct net_device *dev, int phy_id, int location);
411 static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
412 static int netdev_open(struct net_device *dev);
413 static void check_duplex(struct net_device *dev);
414 static void netdev_timer(unsigned long data);
415 static void tx_timeout(struct net_device *dev);
416 static void init_ring(struct net_device *dev);
417 static int start_tx(struct sk_buff *skb, struct net_device *dev);
418 static int reset_tx (struct net_device *dev);
419 static irqreturn_t intr_handler(int irq, void *dev_instance);
420 static void rx_poll(unsigned long data);
421 static void tx_poll(unsigned long data);
422 static void refill_rx (struct net_device *dev);
423 static void netdev_error(struct net_device *dev, int intr_status);
424 static void netdev_error(struct net_device *dev, int intr_status);
425 static void set_rx_mode(struct net_device *dev);
426 static int __set_mac_addr(struct net_device *dev);
427 static struct net_device_stats *get_stats(struct net_device *dev);
428 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
429 static int netdev_close(struct net_device *dev);
430 static const struct ethtool_ops ethtool_ops;
431
432 static void sundance_reset(struct net_device *dev, unsigned long reset_cmd)
433 {
434 struct netdev_private *np = netdev_priv(dev);
435 void __iomem *ioaddr = np->base + ASICCtrl;
436 int countdown;
437
438 /* ST201 documentation states ASICCtrl is a 32bit register */
439 iowrite32 (reset_cmd | ioread32 (ioaddr), ioaddr);
440 /* ST201 documentation states reset can take up to 1 ms */
441 countdown = 10 + 1;
442 while (ioread32 (ioaddr) & (ResetBusy << 16)) {
443 if (--countdown == 0) {
444 printk(KERN_WARNING "%s : reset not completed !!\n", dev->name);
445 break;
446 }
447 udelay(100);
448 }
449 }
450
451 static int __devinit sundance_probe1 (struct pci_dev *pdev,
452 const struct pci_device_id *ent)
453 {
454 struct net_device *dev;
455 struct netdev_private *np;
456 static int card_idx;
457 int chip_idx = ent->driver_data;
458 int irq;
459 int i;
460 void __iomem *ioaddr;
461 u16 mii_ctl;
462 void *ring_space;
463 dma_addr_t ring_dma;
464 #ifdef USE_IO_OPS
465 int bar = 0;
466 #else
467 int bar = 1;
468 #endif
469 int phy, phy_idx = 0;
470
471
472 /* when built into the kernel, we only print version if device is found */
473 #ifndef MODULE
474 static int printed_version;
475 if (!printed_version++)
476 printk(version);
477 #endif
478
479 if (pci_enable_device(pdev))
480 return -EIO;
481 pci_set_master(pdev);
482
483 irq = pdev->irq;
484
485 dev = alloc_etherdev(sizeof(*np));
486 if (!dev)
487 return -ENOMEM;
488 SET_MODULE_OWNER(dev);
489 SET_NETDEV_DEV(dev, &pdev->dev);
490
491 if (pci_request_regions(pdev, DRV_NAME))
492 goto err_out_netdev;
493
494 ioaddr = pci_iomap(pdev, bar, netdev_io_size);
495 if (!ioaddr)
496 goto err_out_res;
497
498 for (i = 0; i < 3; i++)
499 ((u16 *)dev->dev_addr)[i] =
500 le16_to_cpu(eeprom_read(ioaddr, i + EEPROM_SA_OFFSET));
501 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
502
503 dev->base_addr = (unsigned long)ioaddr;
504 dev->irq = irq;
505
506 np = netdev_priv(dev);
507 np->base = ioaddr;
508 np->pci_dev = pdev;
509 np->chip_id = chip_idx;
510 np->msg_enable = (1 << debug) - 1;
511 spin_lock_init(&np->lock);
512 tasklet_init(&np->rx_tasklet, rx_poll, (unsigned long)dev);
513 tasklet_init(&np->tx_tasklet, tx_poll, (unsigned long)dev);
514
515 ring_space = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &ring_dma);
516 if (!ring_space)
517 goto err_out_cleardev;
518 np->tx_ring = (struct netdev_desc *)ring_space;
519 np->tx_ring_dma = ring_dma;
520
521 ring_space = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &ring_dma);
522 if (!ring_space)
523 goto err_out_unmap_tx;
524 np->rx_ring = (struct netdev_desc *)ring_space;
525 np->rx_ring_dma = ring_dma;
526
527 np->mii_if.dev = dev;
528 np->mii_if.mdio_read = mdio_read;
529 np->mii_if.mdio_write = mdio_write;
530 np->mii_if.phy_id_mask = 0x1f;
531 np->mii_if.reg_num_mask = 0x1f;
532
533 /* The chip-specific entries in the device structure. */
534 dev->open = &netdev_open;
535 dev->hard_start_xmit = &start_tx;
536 dev->stop = &netdev_close;
537 dev->get_stats = &get_stats;
538 dev->set_multicast_list = &set_rx_mode;
539 dev->do_ioctl = &netdev_ioctl;
540 SET_ETHTOOL_OPS(dev, &ethtool_ops);
541 dev->tx_timeout = &tx_timeout;
542 dev->watchdog_timeo = TX_TIMEOUT;
543 dev->change_mtu = &change_mtu;
544 pci_set_drvdata(pdev, dev);
545
546 i = register_netdev(dev);
547 if (i)
548 goto err_out_unmap_rx;
549
550 printk(KERN_INFO "%s: %s at %p, ",
551 dev->name, pci_id_tbl[chip_idx].name, ioaddr);
552 for (i = 0; i < 5; i++)
553 printk("%2.2x:", dev->dev_addr[i]);
554 printk("%2.2x, IRQ %d.\n", dev->dev_addr[i], irq);
555
556 np->phys[0] = 1; /* Default setting */
557 np->mii_preamble_required++;
558 /*
559 * It seems some phys doesn't deal well with address 0 being accessed
560 * first, so leave address zero to the end of the loop (32 & 31).
561 */
562 for (phy = 1; phy <= 32 && phy_idx < MII_CNT; phy++) {
563 int phyx = phy & 0x1f;
564 int mii_status = mdio_read(dev, phyx, MII_BMSR);
565 if (mii_status != 0xffff && mii_status != 0x0000) {
566 np->phys[phy_idx++] = phyx;
567 np->mii_if.advertising = mdio_read(dev, phyx, MII_ADVERTISE);
568 if ((mii_status & 0x0040) == 0)
569 np->mii_preamble_required++;
570 printk(KERN_INFO "%s: MII PHY found at address %d, status "
571 "0x%4.4x advertising %4.4x.\n",
572 dev->name, phyx, mii_status, np->mii_if.advertising);
573 }
574 }
575 np->mii_preamble_required--;
576
577 if (phy_idx == 0) {
578 printk(KERN_INFO "%s: No MII transceiver found, aborting. ASIC status %x\n",
579 dev->name, ioread32(ioaddr + ASICCtrl));
580 goto err_out_unregister;
581 }
582
583 np->mii_if.phy_id = np->phys[0];
584
585 /* Parse override configuration */
586 np->an_enable = 1;
587 if (card_idx < MAX_UNITS) {
588 if (media[card_idx] != NULL) {
589 np->an_enable = 0;
590 if (strcmp (media[card_idx], "100mbps_fd") == 0 ||
591 strcmp (media[card_idx], "4") == 0) {
592 np->speed = 100;
593 np->mii_if.full_duplex = 1;
594 } else if (strcmp (media[card_idx], "100mbps_hd") == 0
595 || strcmp (media[card_idx], "3") == 0) {
596 np->speed = 100;
597 np->mii_if.full_duplex = 0;
598 } else if (strcmp (media[card_idx], "10mbps_fd") == 0 ||
599 strcmp (media[card_idx], "2") == 0) {
600 np->speed = 10;
601 np->mii_if.full_duplex = 1;
602 } else if (strcmp (media[card_idx], "10mbps_hd") == 0 ||
603 strcmp (media[card_idx], "1") == 0) {
604 np->speed = 10;
605 np->mii_if.full_duplex = 0;
606 } else {
607 np->an_enable = 1;
608 }
609 }
610 if (flowctrl == 1)
611 np->flowctrl = 1;
612 }
613
614 /* Fibre PHY? */
615 if (ioread32 (ioaddr + ASICCtrl) & 0x80) {
616 /* Default 100Mbps Full */
617 if (np->an_enable) {
618 np->speed = 100;
619 np->mii_if.full_duplex = 1;
620 np->an_enable = 0;
621 }
622 }
623 /* Reset PHY */
624 mdio_write (dev, np->phys[0], MII_BMCR, BMCR_RESET);
625 mdelay (300);
626 /* If flow control enabled, we need to advertise it.*/
627 if (np->flowctrl)
628 mdio_write (dev, np->phys[0], MII_ADVERTISE, np->mii_if.advertising | 0x0400);
629 mdio_write (dev, np->phys[0], MII_BMCR, BMCR_ANENABLE|BMCR_ANRESTART);
630 /* Force media type */
631 if (!np->an_enable) {
632 mii_ctl = 0;
633 mii_ctl |= (np->speed == 100) ? BMCR_SPEED100 : 0;
634 mii_ctl |= (np->mii_if.full_duplex) ? BMCR_FULLDPLX : 0;
635 mdio_write (dev, np->phys[0], MII_BMCR, mii_ctl);
636 printk (KERN_INFO "Override speed=%d, %s duplex\n",
637 np->speed, np->mii_if.full_duplex ? "Full" : "Half");
638
639 }
640
641 /* Perhaps move the reset here? */
642 /* Reset the chip to erase previous misconfiguration. */
643 if (netif_msg_hw(np))
644 printk("ASIC Control is %x.\n", ioread32(ioaddr + ASICCtrl));
645 sundance_reset(dev, 0x00ff << 16);
646 if (netif_msg_hw(np))
647 printk("ASIC Control is now %x.\n", ioread32(ioaddr + ASICCtrl));
648
649 card_idx++;
650 return 0;
651
652 err_out_unregister:
653 unregister_netdev(dev);
654 err_out_unmap_rx:
655 pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
656 err_out_unmap_tx:
657 pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
658 err_out_cleardev:
659 pci_set_drvdata(pdev, NULL);
660 pci_iounmap(pdev, ioaddr);
661 err_out_res:
662 pci_release_regions(pdev);
663 err_out_netdev:
664 free_netdev (dev);
665 return -ENODEV;
666 }
667
668 static int change_mtu(struct net_device *dev, int new_mtu)
669 {
670 if ((new_mtu < 68) || (new_mtu > 8191)) /* Set by RxDMAFrameLen */
671 return -EINVAL;
672 if (netif_running(dev))
673 return -EBUSY;
674 dev->mtu = new_mtu;
675 return 0;
676 }
677
678 #define eeprom_delay(ee_addr) ioread32(ee_addr)
679 /* Read the EEPROM and MII Management Data I/O (MDIO) interfaces. */
680 static int __devinit eeprom_read(void __iomem *ioaddr, int location)
681 {
682 int boguscnt = 10000; /* Typical 1900 ticks. */
683 iowrite16(0x0200 | (location & 0xff), ioaddr + EECtrl);
684 do {
685 eeprom_delay(ioaddr + EECtrl);
686 if (! (ioread16(ioaddr + EECtrl) & 0x8000)) {
687 return ioread16(ioaddr + EEData);
688 }
689 } while (--boguscnt > 0);
690 return 0;
691 }
692
693 /* MII transceiver control section.
694 Read and write the MII registers using software-generated serial
695 MDIO protocol. See the MII specifications or DP83840A data sheet
696 for details.
697
698 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
699 met by back-to-back 33Mhz PCI cycles. */
700 #define mdio_delay() ioread8(mdio_addr)
701
702 enum mii_reg_bits {
703 MDIO_ShiftClk=0x0001, MDIO_Data=0x0002, MDIO_EnbOutput=0x0004,
704 };
705 #define MDIO_EnbIn (0)
706 #define MDIO_WRITE0 (MDIO_EnbOutput)
707 #define MDIO_WRITE1 (MDIO_Data | MDIO_EnbOutput)
708
709 /* Generate the preamble required for initial synchronization and
710 a few older transceivers. */
711 static void mdio_sync(void __iomem *mdio_addr)
712 {
713 int bits = 32;
714
715 /* Establish sync by sending at least 32 logic ones. */
716 while (--bits >= 0) {
717 iowrite8(MDIO_WRITE1, mdio_addr);
718 mdio_delay();
719 iowrite8(MDIO_WRITE1 | MDIO_ShiftClk, mdio_addr);
720 mdio_delay();
721 }
722 }
723
724 static int mdio_read(struct net_device *dev, int phy_id, int location)
725 {
726 struct netdev_private *np = netdev_priv(dev);
727 void __iomem *mdio_addr = np->base + MIICtrl;
728 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
729 int i, retval = 0;
730
731 if (np->mii_preamble_required)
732 mdio_sync(mdio_addr);
733
734 /* Shift the read command bits out. */
735 for (i = 15; i >= 0; i--) {
736 int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
737
738 iowrite8(dataval, mdio_addr);
739 mdio_delay();
740 iowrite8(dataval | MDIO_ShiftClk, mdio_addr);
741 mdio_delay();
742 }
743 /* Read the two transition, 16 data, and wire-idle bits. */
744 for (i = 19; i > 0; i--) {
745 iowrite8(MDIO_EnbIn, mdio_addr);
746 mdio_delay();
747 retval = (retval << 1) | ((ioread8(mdio_addr) & MDIO_Data) ? 1 : 0);
748 iowrite8(MDIO_EnbIn | MDIO_ShiftClk, mdio_addr);
749 mdio_delay();
750 }
751 return (retval>>1) & 0xffff;
752 }
753
754 static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
755 {
756 struct netdev_private *np = netdev_priv(dev);
757 void __iomem *mdio_addr = np->base + MIICtrl;
758 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location<<18) | value;
759 int i;
760
761 if (np->mii_preamble_required)
762 mdio_sync(mdio_addr);
763
764 /* Shift the command bits out. */
765 for (i = 31; i >= 0; i--) {
766 int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
767
768 iowrite8(dataval, mdio_addr);
769 mdio_delay();
770 iowrite8(dataval | MDIO_ShiftClk, mdio_addr);
771 mdio_delay();
772 }
773 /* Clear out extra bits. */
774 for (i = 2; i > 0; i--) {
775 iowrite8(MDIO_EnbIn, mdio_addr);
776 mdio_delay();
777 iowrite8(MDIO_EnbIn | MDIO_ShiftClk, mdio_addr);
778 mdio_delay();
779 }
780 return;
781 }
782
783 static int netdev_open(struct net_device *dev)
784 {
785 struct netdev_private *np = netdev_priv(dev);
786 void __iomem *ioaddr = np->base;
787 unsigned long flags;
788 int i;
789
790 /* Do we need to reset the chip??? */
791
792 i = request_irq(dev->irq, &intr_handler, IRQF_SHARED, dev->name, dev);
793 if (i)
794 return i;
795
796 if (netif_msg_ifup(np))
797 printk(KERN_DEBUG "%s: netdev_open() irq %d.\n",
798 dev->name, dev->irq);
799 init_ring(dev);
800
801 iowrite32(np->rx_ring_dma, ioaddr + RxListPtr);
802 /* The Tx list pointer is written as packets are queued. */
803
804 /* Initialize other registers. */
805 __set_mac_addr(dev);
806 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
807 iowrite16(dev->mtu + 18, ioaddr + MaxFrameSize);
808 #else
809 iowrite16(dev->mtu + 14, ioaddr + MaxFrameSize);
810 #endif
811 if (dev->mtu > 2047)
812 iowrite32(ioread32(ioaddr + ASICCtrl) | 0x0C, ioaddr + ASICCtrl);
813
814 /* Configure the PCI bus bursts and FIFO thresholds. */
815
816 if (dev->if_port == 0)
817 dev->if_port = np->default_port;
818
819 spin_lock_init(&np->mcastlock);
820
821 set_rx_mode(dev);
822 iowrite16(0, ioaddr + IntrEnable);
823 iowrite16(0, ioaddr + DownCounter);
824 /* Set the chip to poll every N*320nsec. */
825 iowrite8(100, ioaddr + RxDMAPollPeriod);
826 iowrite8(127, ioaddr + TxDMAPollPeriod);
827 /* Fix DFE-580TX packet drop issue */
828 if (np->pci_dev->revision >= 0x14)
829 iowrite8(0x01, ioaddr + DebugCtrl1);
830 netif_start_queue(dev);
831
832 spin_lock_irqsave(&np->lock, flags);
833 reset_tx(dev);
834 spin_unlock_irqrestore(&np->lock, flags);
835
836 iowrite16 (StatsEnable | RxEnable | TxEnable, ioaddr + MACCtrl1);
837
838 if (netif_msg_ifup(np))
839 printk(KERN_DEBUG "%s: Done netdev_open(), status: Rx %x Tx %x "
840 "MAC Control %x, %4.4x %4.4x.\n",
841 dev->name, ioread32(ioaddr + RxStatus), ioread8(ioaddr + TxStatus),
842 ioread32(ioaddr + MACCtrl0),
843 ioread16(ioaddr + MACCtrl1), ioread16(ioaddr + MACCtrl0));
844
845 /* Set the timer to check for link beat. */
846 init_timer(&np->timer);
847 np->timer.expires = jiffies + 3*HZ;
848 np->timer.data = (unsigned long)dev;
849 np->timer.function = &netdev_timer; /* timer handler */
850 add_timer(&np->timer);
851
852 /* Enable interrupts by setting the interrupt mask. */
853 iowrite16(DEFAULT_INTR, ioaddr + IntrEnable);
854
855 return 0;
856 }
857
858 static void check_duplex(struct net_device *dev)
859 {
860 struct netdev_private *np = netdev_priv(dev);
861 void __iomem *ioaddr = np->base;
862 int mii_lpa = mdio_read(dev, np->phys[0], MII_LPA);
863 int negotiated = mii_lpa & np->mii_if.advertising;
864 int duplex;
865
866 /* Force media */
867 if (!np->an_enable || mii_lpa == 0xffff) {
868 if (np->mii_if.full_duplex)
869 iowrite16 (ioread16 (ioaddr + MACCtrl0) | EnbFullDuplex,
870 ioaddr + MACCtrl0);
871 return;
872 }
873
874 /* Autonegotiation */
875 duplex = (negotiated & 0x0100) || (negotiated & 0x01C0) == 0x0040;
876 if (np->mii_if.full_duplex != duplex) {
877 np->mii_if.full_duplex = duplex;
878 if (netif_msg_link(np))
879 printk(KERN_INFO "%s: Setting %s-duplex based on MII #%d "
880 "negotiated capability %4.4x.\n", dev->name,
881 duplex ? "full" : "half", np->phys[0], negotiated);
882 iowrite16(ioread16(ioaddr + MACCtrl0) | duplex ? 0x20 : 0, ioaddr + MACCtrl0);
883 }
884 }
885
886 static void netdev_timer(unsigned long data)
887 {
888 struct net_device *dev = (struct net_device *)data;
889 struct netdev_private *np = netdev_priv(dev);
890 void __iomem *ioaddr = np->base;
891 int next_tick = 10*HZ;
892
893 if (netif_msg_timer(np)) {
894 printk(KERN_DEBUG "%s: Media selection timer tick, intr status %4.4x, "
895 "Tx %x Rx %x.\n",
896 dev->name, ioread16(ioaddr + IntrEnable),
897 ioread8(ioaddr + TxStatus), ioread32(ioaddr + RxStatus));
898 }
899 check_duplex(dev);
900 np->timer.expires = jiffies + next_tick;
901 add_timer(&np->timer);
902 }
903
904 static void tx_timeout(struct net_device *dev)
905 {
906 struct netdev_private *np = netdev_priv(dev);
907 void __iomem *ioaddr = np->base;
908 unsigned long flag;
909
910 netif_stop_queue(dev);
911 tasklet_disable(&np->tx_tasklet);
912 iowrite16(0, ioaddr + IntrEnable);
913 printk(KERN_WARNING "%s: Transmit timed out, TxStatus %2.2x "
914 "TxFrameId %2.2x,"
915 " resetting...\n", dev->name, ioread8(ioaddr + TxStatus),
916 ioread8(ioaddr + TxFrameId));
917
918 {
919 int i;
920 for (i=0; i<TX_RING_SIZE; i++) {
921 printk(KERN_DEBUG "%02x %08llx %08x %08x(%02x) %08x %08x\n", i,
922 (unsigned long long)(np->tx_ring_dma + i*sizeof(*np->tx_ring)),
923 le32_to_cpu(np->tx_ring[i].next_desc),
924 le32_to_cpu(np->tx_ring[i].status),
925 (le32_to_cpu(np->tx_ring[i].status) >> 2) & 0xff,
926 le32_to_cpu(np->tx_ring[i].frag[0].addr),
927 le32_to_cpu(np->tx_ring[i].frag[0].length));
928 }
929 printk(KERN_DEBUG "TxListPtr=%08x netif_queue_stopped=%d\n",
930 ioread32(np->base + TxListPtr),
931 netif_queue_stopped(dev));
932 printk(KERN_DEBUG "cur_tx=%d(%02x) dirty_tx=%d(%02x)\n",
933 np->cur_tx, np->cur_tx % TX_RING_SIZE,
934 np->dirty_tx, np->dirty_tx % TX_RING_SIZE);
935 printk(KERN_DEBUG "cur_rx=%d dirty_rx=%d\n", np->cur_rx, np->dirty_rx);
936 printk(KERN_DEBUG "cur_task=%d\n", np->cur_task);
937 }
938 spin_lock_irqsave(&np->lock, flag);
939
940 /* Stop and restart the chip's Tx processes . */
941 reset_tx(dev);
942 spin_unlock_irqrestore(&np->lock, flag);
943
944 dev->if_port = 0;
945
946 dev->trans_start = jiffies;
947 np->stats.tx_errors++;
948 if (np->cur_tx - np->dirty_tx < TX_QUEUE_LEN - 4) {
949 netif_wake_queue(dev);
950 }
951 iowrite16(DEFAULT_INTR, ioaddr + IntrEnable);
952 tasklet_enable(&np->tx_tasklet);
953 }
954
955
956 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
957 static void init_ring(struct net_device *dev)
958 {
959 struct netdev_private *np = netdev_priv(dev);
960 int i;
961
962 np->cur_rx = np->cur_tx = 0;
963 np->dirty_rx = np->dirty_tx = 0;
964 np->cur_task = 0;
965
966 np->rx_buf_sz = (dev->mtu <= 1520 ? PKT_BUF_SZ : dev->mtu + 16);
967
968 /* Initialize all Rx descriptors. */
969 for (i = 0; i < RX_RING_SIZE; i++) {
970 np->rx_ring[i].next_desc = cpu_to_le32(np->rx_ring_dma +
971 ((i+1)%RX_RING_SIZE)*sizeof(*np->rx_ring));
972 np->rx_ring[i].status = 0;
973 np->rx_ring[i].frag[0].length = 0;
974 np->rx_skbuff[i] = NULL;
975 }
976
977 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
978 for (i = 0; i < RX_RING_SIZE; i++) {
979 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz);
980 np->rx_skbuff[i] = skb;
981 if (skb == NULL)
982 break;
983 skb->dev = dev; /* Mark as being used by this device. */
984 skb_reserve(skb, 2); /* 16 byte align the IP header. */
985 np->rx_ring[i].frag[0].addr = cpu_to_le32(
986 pci_map_single(np->pci_dev, skb->data, np->rx_buf_sz,
987 PCI_DMA_FROMDEVICE));
988 np->rx_ring[i].frag[0].length = cpu_to_le32(np->rx_buf_sz | LastFrag);
989 }
990 np->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
991
992 for (i = 0; i < TX_RING_SIZE; i++) {
993 np->tx_skbuff[i] = NULL;
994 np->tx_ring[i].status = 0;
995 }
996 return;
997 }
998
999 static void tx_poll (unsigned long data)
1000 {
1001 struct net_device *dev = (struct net_device *)data;
1002 struct netdev_private *np = netdev_priv(dev);
1003 unsigned head = np->cur_task % TX_RING_SIZE;
1004 struct netdev_desc *txdesc =
1005 &np->tx_ring[(np->cur_tx - 1) % TX_RING_SIZE];
1006
1007 /* Chain the next pointer */
1008 for (; np->cur_tx - np->cur_task > 0; np->cur_task++) {
1009 int entry = np->cur_task % TX_RING_SIZE;
1010 txdesc = &np->tx_ring[entry];
1011 if (np->last_tx) {
1012 np->last_tx->next_desc = cpu_to_le32(np->tx_ring_dma +
1013 entry*sizeof(struct netdev_desc));
1014 }
1015 np->last_tx = txdesc;
1016 }
1017 /* Indicate the latest descriptor of tx ring */
1018 txdesc->status |= cpu_to_le32(DescIntrOnTx);
1019
1020 if (ioread32 (np->base + TxListPtr) == 0)
1021 iowrite32 (np->tx_ring_dma + head * sizeof(struct netdev_desc),
1022 np->base + TxListPtr);
1023 return;
1024 }
1025
1026 static int
1027 start_tx (struct sk_buff *skb, struct net_device *dev)
1028 {
1029 struct netdev_private *np = netdev_priv(dev);
1030 struct netdev_desc *txdesc;
1031 unsigned entry;
1032
1033 /* Calculate the next Tx descriptor entry. */
1034 entry = np->cur_tx % TX_RING_SIZE;
1035 np->tx_skbuff[entry] = skb;
1036 txdesc = &np->tx_ring[entry];
1037
1038 txdesc->next_desc = 0;
1039 txdesc->status = cpu_to_le32 ((entry << 2) | DisableAlign);
1040 txdesc->frag[0].addr = cpu_to_le32 (pci_map_single (np->pci_dev, skb->data,
1041 skb->len,
1042 PCI_DMA_TODEVICE));
1043 txdesc->frag[0].length = cpu_to_le32 (skb->len | LastFrag);
1044
1045 /* Increment cur_tx before tasklet_schedule() */
1046 np->cur_tx++;
1047 mb();
1048 /* Schedule a tx_poll() task */
1049 tasklet_schedule(&np->tx_tasklet);
1050
1051 /* On some architectures: explicitly flush cache lines here. */
1052 if (np->cur_tx - np->dirty_tx < TX_QUEUE_LEN - 1
1053 && !netif_queue_stopped(dev)) {
1054 /* do nothing */
1055 } else {
1056 netif_stop_queue (dev);
1057 }
1058 dev->trans_start = jiffies;
1059 if (netif_msg_tx_queued(np)) {
1060 printk (KERN_DEBUG
1061 "%s: Transmit frame #%d queued in slot %d.\n",
1062 dev->name, np->cur_tx, entry);
1063 }
1064 return 0;
1065 }
1066
1067 /* Reset hardware tx and free all of tx buffers */
1068 static int
1069 reset_tx (struct net_device *dev)
1070 {
1071 struct netdev_private *np = netdev_priv(dev);
1072 void __iomem *ioaddr = np->base;
1073 struct sk_buff *skb;
1074 int i;
1075 int irq = in_interrupt();
1076
1077 /* Reset tx logic, TxListPtr will be cleaned */
1078 iowrite16 (TxDisable, ioaddr + MACCtrl1);
1079 sundance_reset(dev, (NetworkReset|FIFOReset|DMAReset|TxReset) << 16);
1080
1081 /* free all tx skbuff */
1082 for (i = 0; i < TX_RING_SIZE; i++) {
1083 np->tx_ring[i].next_desc = 0;
1084
1085 skb = np->tx_skbuff[i];
1086 if (skb) {
1087 pci_unmap_single(np->pci_dev,
1088 np->tx_ring[i].frag[0].addr, skb->len,
1089 PCI_DMA_TODEVICE);
1090 if (irq)
1091 dev_kfree_skb_irq (skb);
1092 else
1093 dev_kfree_skb (skb);
1094 np->tx_skbuff[i] = NULL;
1095 np->stats.tx_dropped++;
1096 }
1097 }
1098 np->cur_tx = np->dirty_tx = 0;
1099 np->cur_task = 0;
1100
1101 np->last_tx = NULL;
1102 iowrite8(127, ioaddr + TxDMAPollPeriod);
1103
1104 iowrite16 (StatsEnable | RxEnable | TxEnable, ioaddr + MACCtrl1);
1105 return 0;
1106 }
1107
1108 /* The interrupt handler cleans up after the Tx thread,
1109 and schedule a Rx thread work */
1110 static irqreturn_t intr_handler(int irq, void *dev_instance)
1111 {
1112 struct net_device *dev = (struct net_device *)dev_instance;
1113 struct netdev_private *np = netdev_priv(dev);
1114 void __iomem *ioaddr = np->base;
1115 int hw_frame_id;
1116 int tx_cnt;
1117 int tx_status;
1118 int handled = 0;
1119 int i;
1120
1121
1122 do {
1123 int intr_status = ioread16(ioaddr + IntrStatus);
1124 iowrite16(intr_status, ioaddr + IntrStatus);
1125
1126 if (netif_msg_intr(np))
1127 printk(KERN_DEBUG "%s: Interrupt, status %4.4x.\n",
1128 dev->name, intr_status);
1129
1130 if (!(intr_status & DEFAULT_INTR))
1131 break;
1132
1133 handled = 1;
1134
1135 if (intr_status & (IntrRxDMADone)) {
1136 iowrite16(DEFAULT_INTR & ~(IntrRxDone|IntrRxDMADone),
1137 ioaddr + IntrEnable);
1138 if (np->budget < 0)
1139 np->budget = RX_BUDGET;
1140 tasklet_schedule(&np->rx_tasklet);
1141 }
1142 if (intr_status & (IntrTxDone | IntrDrvRqst)) {
1143 tx_status = ioread16 (ioaddr + TxStatus);
1144 for (tx_cnt=32; tx_status & 0x80; --tx_cnt) {
1145 if (netif_msg_tx_done(np))
1146 printk
1147 ("%s: Transmit status is %2.2x.\n",
1148 dev->name, tx_status);
1149 if (tx_status & 0x1e) {
1150 if (netif_msg_tx_err(np))
1151 printk("%s: Transmit error status %4.4x.\n",
1152 dev->name, tx_status);
1153 np->stats.tx_errors++;
1154 if (tx_status & 0x10)
1155 np->stats.tx_fifo_errors++;
1156 if (tx_status & 0x08)
1157 np->stats.collisions++;
1158 if (tx_status & 0x04)
1159 np->stats.tx_fifo_errors++;
1160 if (tx_status & 0x02)
1161 np->stats.tx_window_errors++;
1162
1163 /*
1164 ** This reset has been verified on
1165 ** DFE-580TX boards ! phdm@macqel.be.
1166 */
1167 if (tx_status & 0x10) { /* TxUnderrun */
1168 /* Restart Tx FIFO and transmitter */
1169 sundance_reset(dev, (NetworkReset|FIFOReset|TxReset) << 16);
1170 /* No need to reset the Tx pointer here */
1171 }
1172 /* Restart the Tx. Need to make sure tx enabled */
1173 i = 10;
1174 do {
1175 iowrite16(ioread16(ioaddr + MACCtrl1) | TxEnable, ioaddr + MACCtrl1);
1176 if (ioread16(ioaddr + MACCtrl1) & TxEnabled)
1177 break;
1178 mdelay(1);
1179 } while (--i);
1180 }
1181 /* Yup, this is a documentation bug. It cost me *hours*. */
1182 iowrite16 (0, ioaddr + TxStatus);
1183 if (tx_cnt < 0) {
1184 iowrite32(5000, ioaddr + DownCounter);
1185 break;
1186 }
1187 tx_status = ioread16 (ioaddr + TxStatus);
1188 }
1189 hw_frame_id = (tx_status >> 8) & 0xff;
1190 } else {
1191 hw_frame_id = ioread8(ioaddr + TxFrameId);
1192 }
1193
1194 if (np->pci_dev->revision >= 0x14) {
1195 spin_lock(&np->lock);
1196 for (; np->cur_tx - np->dirty_tx > 0; np->dirty_tx++) {
1197 int entry = np->dirty_tx % TX_RING_SIZE;
1198 struct sk_buff *skb;
1199 int sw_frame_id;
1200 sw_frame_id = (le32_to_cpu(
1201 np->tx_ring[entry].status) >> 2) & 0xff;
1202 if (sw_frame_id == hw_frame_id &&
1203 !(le32_to_cpu(np->tx_ring[entry].status)
1204 & 0x00010000))
1205 break;
1206 if (sw_frame_id == (hw_frame_id + 1) %
1207 TX_RING_SIZE)
1208 break;
1209 skb = np->tx_skbuff[entry];
1210 /* Free the original skb. */
1211 pci_unmap_single(np->pci_dev,
1212 np->tx_ring[entry].frag[0].addr,
1213 skb->len, PCI_DMA_TODEVICE);
1214 dev_kfree_skb_irq (np->tx_skbuff[entry]);
1215 np->tx_skbuff[entry] = NULL;
1216 np->tx_ring[entry].frag[0].addr = 0;
1217 np->tx_ring[entry].frag[0].length = 0;
1218 }
1219 spin_unlock(&np->lock);
1220 } else {
1221 spin_lock(&np->lock);
1222 for (; np->cur_tx - np->dirty_tx > 0; np->dirty_tx++) {
1223 int entry = np->dirty_tx % TX_RING_SIZE;
1224 struct sk_buff *skb;
1225 if (!(le32_to_cpu(np->tx_ring[entry].status)
1226 & 0x00010000))
1227 break;
1228 skb = np->tx_skbuff[entry];
1229 /* Free the original skb. */
1230 pci_unmap_single(np->pci_dev,
1231 np->tx_ring[entry].frag[0].addr,
1232 skb->len, PCI_DMA_TODEVICE);
1233 dev_kfree_skb_irq (np->tx_skbuff[entry]);
1234 np->tx_skbuff[entry] = NULL;
1235 np->tx_ring[entry].frag[0].addr = 0;
1236 np->tx_ring[entry].frag[0].length = 0;
1237 }
1238 spin_unlock(&np->lock);
1239 }
1240
1241 if (netif_queue_stopped(dev) &&
1242 np->cur_tx - np->dirty_tx < TX_QUEUE_LEN - 4) {
1243 /* The ring is no longer full, clear busy flag. */
1244 netif_wake_queue (dev);
1245 }
1246 /* Abnormal error summary/uncommon events handlers. */
1247 if (intr_status & (IntrPCIErr | LinkChange | StatsMax))
1248 netdev_error(dev, intr_status);
1249 } while (0);
1250 if (netif_msg_intr(np))
1251 printk(KERN_DEBUG "%s: exiting interrupt, status=%#4.4x.\n",
1252 dev->name, ioread16(ioaddr + IntrStatus));
1253 return IRQ_RETVAL(handled);
1254 }
1255
1256 static void rx_poll(unsigned long data)
1257 {
1258 struct net_device *dev = (struct net_device *)data;
1259 struct netdev_private *np = netdev_priv(dev);
1260 int entry = np->cur_rx % RX_RING_SIZE;
1261 int boguscnt = np->budget;
1262 void __iomem *ioaddr = np->base;
1263 int received = 0;
1264
1265 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1266 while (1) {
1267 struct netdev_desc *desc = &(np->rx_ring[entry]);
1268 u32 frame_status = le32_to_cpu(desc->status);
1269 int pkt_len;
1270
1271 if (--boguscnt < 0) {
1272 goto not_done;
1273 }
1274 if (!(frame_status & DescOwn))
1275 break;
1276 pkt_len = frame_status & 0x1fff; /* Chip omits the CRC. */
1277 if (netif_msg_rx_status(np))
1278 printk(KERN_DEBUG " netdev_rx() status was %8.8x.\n",
1279 frame_status);
1280 if (frame_status & 0x001f4000) {
1281 /* There was a error. */
1282 if (netif_msg_rx_err(np))
1283 printk(KERN_DEBUG " netdev_rx() Rx error was %8.8x.\n",
1284 frame_status);
1285 np->stats.rx_errors++;
1286 if (frame_status & 0x00100000) np->stats.rx_length_errors++;
1287 if (frame_status & 0x00010000) np->stats.rx_fifo_errors++;
1288 if (frame_status & 0x00060000) np->stats.rx_frame_errors++;
1289 if (frame_status & 0x00080000) np->stats.rx_crc_errors++;
1290 if (frame_status & 0x00100000) {
1291 printk(KERN_WARNING "%s: Oversized Ethernet frame,"
1292 " status %8.8x.\n",
1293 dev->name, frame_status);
1294 }
1295 } else {
1296 struct sk_buff *skb;
1297 #ifndef final_version
1298 if (netif_msg_rx_status(np))
1299 printk(KERN_DEBUG " netdev_rx() normal Rx pkt length %d"
1300 ", bogus_cnt %d.\n",
1301 pkt_len, boguscnt);
1302 #endif
1303 /* Check if the packet is long enough to accept without copying
1304 to a minimally-sized skbuff. */
1305 if (pkt_len < rx_copybreak
1306 && (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1307 skb_reserve(skb, 2); /* 16 byte align the IP header */
1308 pci_dma_sync_single_for_cpu(np->pci_dev,
1309 desc->frag[0].addr,
1310 np->rx_buf_sz,
1311 PCI_DMA_FROMDEVICE);
1312
1313 skb_copy_to_linear_data(skb, np->rx_skbuff[entry]->data, pkt_len);
1314 pci_dma_sync_single_for_device(np->pci_dev,
1315 desc->frag[0].addr,
1316 np->rx_buf_sz,
1317 PCI_DMA_FROMDEVICE);
1318 skb_put(skb, pkt_len);
1319 } else {
1320 pci_unmap_single(np->pci_dev,
1321 desc->frag[0].addr,
1322 np->rx_buf_sz,
1323 PCI_DMA_FROMDEVICE);
1324 skb_put(skb = np->rx_skbuff[entry], pkt_len);
1325 np->rx_skbuff[entry] = NULL;
1326 }
1327 skb->protocol = eth_type_trans(skb, dev);
1328 /* Note: checksum -> skb->ip_summed = CHECKSUM_UNNECESSARY; */
1329 netif_rx(skb);
1330 dev->last_rx = jiffies;
1331 }
1332 entry = (entry + 1) % RX_RING_SIZE;
1333 received++;
1334 }
1335 np->cur_rx = entry;
1336 refill_rx (dev);
1337 np->budget -= received;
1338 iowrite16(DEFAULT_INTR, ioaddr + IntrEnable);
1339 return;
1340
1341 not_done:
1342 np->cur_rx = entry;
1343 refill_rx (dev);
1344 if (!received)
1345 received = 1;
1346 np->budget -= received;
1347 if (np->budget <= 0)
1348 np->budget = RX_BUDGET;
1349 tasklet_schedule(&np->rx_tasklet);
1350 return;
1351 }
1352
1353 static void refill_rx (struct net_device *dev)
1354 {
1355 struct netdev_private *np = netdev_priv(dev);
1356 int entry;
1357 int cnt = 0;
1358
1359 /* Refill the Rx ring buffers. */
1360 for (;(np->cur_rx - np->dirty_rx + RX_RING_SIZE) % RX_RING_SIZE > 0;
1361 np->dirty_rx = (np->dirty_rx + 1) % RX_RING_SIZE) {
1362 struct sk_buff *skb;
1363 entry = np->dirty_rx % RX_RING_SIZE;
1364 if (np->rx_skbuff[entry] == NULL) {
1365 skb = dev_alloc_skb(np->rx_buf_sz);
1366 np->rx_skbuff[entry] = skb;
1367 if (skb == NULL)
1368 break; /* Better luck next round. */
1369 skb->dev = dev; /* Mark as being used by this device. */
1370 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
1371 np->rx_ring[entry].frag[0].addr = cpu_to_le32(
1372 pci_map_single(np->pci_dev, skb->data,
1373 np->rx_buf_sz, PCI_DMA_FROMDEVICE));
1374 }
1375 /* Perhaps we need not reset this field. */
1376 np->rx_ring[entry].frag[0].length =
1377 cpu_to_le32(np->rx_buf_sz | LastFrag);
1378 np->rx_ring[entry].status = 0;
1379 cnt++;
1380 }
1381 return;
1382 }
1383 static void netdev_error(struct net_device *dev, int intr_status)
1384 {
1385 struct netdev_private *np = netdev_priv(dev);
1386 void __iomem *ioaddr = np->base;
1387 u16 mii_ctl, mii_advertise, mii_lpa;
1388 int speed;
1389
1390 if (intr_status & LinkChange) {
1391 if (np->an_enable) {
1392 mii_advertise = mdio_read (dev, np->phys[0], MII_ADVERTISE);
1393 mii_lpa= mdio_read (dev, np->phys[0], MII_LPA);
1394 mii_advertise &= mii_lpa;
1395 printk (KERN_INFO "%s: Link changed: ", dev->name);
1396 if (mii_advertise & ADVERTISE_100FULL) {
1397 np->speed = 100;
1398 printk ("100Mbps, full duplex\n");
1399 } else if (mii_advertise & ADVERTISE_100HALF) {
1400 np->speed = 100;
1401 printk ("100Mbps, half duplex\n");
1402 } else if (mii_advertise & ADVERTISE_10FULL) {
1403 np->speed = 10;
1404 printk ("10Mbps, full duplex\n");
1405 } else if (mii_advertise & ADVERTISE_10HALF) {
1406 np->speed = 10;
1407 printk ("10Mbps, half duplex\n");
1408 } else
1409 printk ("\n");
1410
1411 } else {
1412 mii_ctl = mdio_read (dev, np->phys[0], MII_BMCR);
1413 speed = (mii_ctl & BMCR_SPEED100) ? 100 : 10;
1414 np->speed = speed;
1415 printk (KERN_INFO "%s: Link changed: %dMbps ,",
1416 dev->name, speed);
1417 printk ("%s duplex.\n", (mii_ctl & BMCR_FULLDPLX) ?
1418 "full" : "half");
1419 }
1420 check_duplex (dev);
1421 if (np->flowctrl && np->mii_if.full_duplex) {
1422 iowrite16(ioread16(ioaddr + MulticastFilter1+2) | 0x0200,
1423 ioaddr + MulticastFilter1+2);
1424 iowrite16(ioread16(ioaddr + MACCtrl0) | EnbFlowCtrl,
1425 ioaddr + MACCtrl0);
1426 }
1427 }
1428 if (intr_status & StatsMax) {
1429 get_stats(dev);
1430 }
1431 if (intr_status & IntrPCIErr) {
1432 printk(KERN_ERR "%s: Something Wicked happened! %4.4x.\n",
1433 dev->name, intr_status);
1434 /* We must do a global reset of DMA to continue. */
1435 }
1436 }
1437
1438 static struct net_device_stats *get_stats(struct net_device *dev)
1439 {
1440 struct netdev_private *np = netdev_priv(dev);
1441 void __iomem *ioaddr = np->base;
1442 int i;
1443
1444 /* We should lock this segment of code for SMP eventually, although
1445 the vulnerability window is very small and statistics are
1446 non-critical. */
1447 /* The chip only need report frame silently dropped. */
1448 np->stats.rx_missed_errors += ioread8(ioaddr + RxMissed);
1449 np->stats.tx_packets += ioread16(ioaddr + TxFramesOK);
1450 np->stats.rx_packets += ioread16(ioaddr + RxFramesOK);
1451 np->stats.collisions += ioread8(ioaddr + StatsLateColl);
1452 np->stats.collisions += ioread8(ioaddr + StatsMultiColl);
1453 np->stats.collisions += ioread8(ioaddr + StatsOneColl);
1454 np->stats.tx_carrier_errors += ioread8(ioaddr + StatsCarrierError);
1455 ioread8(ioaddr + StatsTxDefer);
1456 for (i = StatsTxDefer; i <= StatsMcastRx; i++)
1457 ioread8(ioaddr + i);
1458 np->stats.tx_bytes += ioread16(ioaddr + TxOctetsLow);
1459 np->stats.tx_bytes += ioread16(ioaddr + TxOctetsHigh) << 16;
1460 np->stats.rx_bytes += ioread16(ioaddr + RxOctetsLow);
1461 np->stats.rx_bytes += ioread16(ioaddr + RxOctetsHigh) << 16;
1462
1463 return &np->stats;
1464 }
1465
1466 static void set_rx_mode(struct net_device *dev)
1467 {
1468 struct netdev_private *np = netdev_priv(dev);
1469 void __iomem *ioaddr = np->base;
1470 u16 mc_filter[4]; /* Multicast hash filter */
1471 u32 rx_mode;
1472 int i;
1473
1474 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1475 memset(mc_filter, 0xff, sizeof(mc_filter));
1476 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptAll | AcceptMyPhys;
1477 } else if ((dev->mc_count > multicast_filter_limit)
1478 || (dev->flags & IFF_ALLMULTI)) {
1479 /* Too many to match, or accept all multicasts. */
1480 memset(mc_filter, 0xff, sizeof(mc_filter));
1481 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1482 } else if (dev->mc_count) {
1483 struct dev_mc_list *mclist;
1484 int bit;
1485 int index;
1486 int crc;
1487 memset (mc_filter, 0, sizeof (mc_filter));
1488 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1489 i++, mclist = mclist->next) {
1490 crc = ether_crc_le (ETH_ALEN, mclist->dmi_addr);
1491 for (index=0, bit=0; bit < 6; bit++, crc <<= 1)
1492 if (crc & 0x80000000) index |= 1 << bit;
1493 mc_filter[index/16] |= (1 << (index % 16));
1494 }
1495 rx_mode = AcceptBroadcast | AcceptMultiHash | AcceptMyPhys;
1496 } else {
1497 iowrite8(AcceptBroadcast | AcceptMyPhys, ioaddr + RxMode);
1498 return;
1499 }
1500 if (np->mii_if.full_duplex && np->flowctrl)
1501 mc_filter[3] |= 0x0200;
1502
1503 for (i = 0; i < 4; i++)
1504 iowrite16(mc_filter[i], ioaddr + MulticastFilter0 + i*2);
1505 iowrite8(rx_mode, ioaddr + RxMode);
1506 }
1507
1508 static int __set_mac_addr(struct net_device *dev)
1509 {
1510 struct netdev_private *np = netdev_priv(dev);
1511 u16 addr16;
1512
1513 addr16 = (dev->dev_addr[0] | (dev->dev_addr[1] << 8));
1514 iowrite16(addr16, np->base + StationAddr);
1515 addr16 = (dev->dev_addr[2] | (dev->dev_addr[3] << 8));
1516 iowrite16(addr16, np->base + StationAddr+2);
1517 addr16 = (dev->dev_addr[4] | (dev->dev_addr[5] << 8));
1518 iowrite16(addr16, np->base + StationAddr+4);
1519 return 0;
1520 }
1521
1522 static int check_if_running(struct net_device *dev)
1523 {
1524 if (!netif_running(dev))
1525 return -EINVAL;
1526 return 0;
1527 }
1528
1529 static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1530 {
1531 struct netdev_private *np = netdev_priv(dev);
1532 strcpy(info->driver, DRV_NAME);
1533 strcpy(info->version, DRV_VERSION);
1534 strcpy(info->bus_info, pci_name(np->pci_dev));
1535 }
1536
1537 static int get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1538 {
1539 struct netdev_private *np = netdev_priv(dev);
1540 spin_lock_irq(&np->lock);
1541 mii_ethtool_gset(&np->mii_if, ecmd);
1542 spin_unlock_irq(&np->lock);
1543 return 0;
1544 }
1545
1546 static int set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1547 {
1548 struct netdev_private *np = netdev_priv(dev);
1549 int res;
1550 spin_lock_irq(&np->lock);
1551 res = mii_ethtool_sset(&np->mii_if, ecmd);
1552 spin_unlock_irq(&np->lock);
1553 return res;
1554 }
1555
1556 static int nway_reset(struct net_device *dev)
1557 {
1558 struct netdev_private *np = netdev_priv(dev);
1559 return mii_nway_restart(&np->mii_if);
1560 }
1561
1562 static u32 get_link(struct net_device *dev)
1563 {
1564 struct netdev_private *np = netdev_priv(dev);
1565 return mii_link_ok(&np->mii_if);
1566 }
1567
1568 static u32 get_msglevel(struct net_device *dev)
1569 {
1570 struct netdev_private *np = netdev_priv(dev);
1571 return np->msg_enable;
1572 }
1573
1574 static void set_msglevel(struct net_device *dev, u32 val)
1575 {
1576 struct netdev_private *np = netdev_priv(dev);
1577 np->msg_enable = val;
1578 }
1579
1580 static const struct ethtool_ops ethtool_ops = {
1581 .begin = check_if_running,
1582 .get_drvinfo = get_drvinfo,
1583 .get_settings = get_settings,
1584 .set_settings = set_settings,
1585 .nway_reset = nway_reset,
1586 .get_link = get_link,
1587 .get_msglevel = get_msglevel,
1588 .set_msglevel = set_msglevel,
1589 .get_perm_addr = ethtool_op_get_perm_addr,
1590 };
1591
1592 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1593 {
1594 struct netdev_private *np = netdev_priv(dev);
1595 void __iomem *ioaddr = np->base;
1596 int rc;
1597 int i;
1598
1599 if (!netif_running(dev))
1600 return -EINVAL;
1601
1602 spin_lock_irq(&np->lock);
1603 rc = generic_mii_ioctl(&np->mii_if, if_mii(rq), cmd, NULL);
1604 spin_unlock_irq(&np->lock);
1605 switch (cmd) {
1606 case SIOCDEVPRIVATE:
1607 for (i=0; i<TX_RING_SIZE; i++) {
1608 printk(KERN_DEBUG "%02x %08llx %08x %08x(%02x) %08x %08x\n", i,
1609 (unsigned long long)(np->tx_ring_dma + i*sizeof(*np->tx_ring)),
1610 le32_to_cpu(np->tx_ring[i].next_desc),
1611 le32_to_cpu(np->tx_ring[i].status),
1612 (le32_to_cpu(np->tx_ring[i].status) >> 2)
1613 & 0xff,
1614 le32_to_cpu(np->tx_ring[i].frag[0].addr),
1615 le32_to_cpu(np->tx_ring[i].frag[0].length));
1616 }
1617 printk(KERN_DEBUG "TxListPtr=%08x netif_queue_stopped=%d\n",
1618 ioread32(np->base + TxListPtr),
1619 netif_queue_stopped(dev));
1620 printk(KERN_DEBUG "cur_tx=%d(%02x) dirty_tx=%d(%02x)\n",
1621 np->cur_tx, np->cur_tx % TX_RING_SIZE,
1622 np->dirty_tx, np->dirty_tx % TX_RING_SIZE);
1623 printk(KERN_DEBUG "cur_rx=%d dirty_rx=%d\n", np->cur_rx, np->dirty_rx);
1624 printk(KERN_DEBUG "cur_task=%d\n", np->cur_task);
1625 printk(KERN_DEBUG "TxStatus=%04x\n", ioread16(ioaddr + TxStatus));
1626 return 0;
1627 }
1628
1629
1630 return rc;
1631 }
1632
1633 static int netdev_close(struct net_device *dev)
1634 {
1635 struct netdev_private *np = netdev_priv(dev);
1636 void __iomem *ioaddr = np->base;
1637 struct sk_buff *skb;
1638 int i;
1639
1640 /* Wait and kill tasklet */
1641 tasklet_kill(&np->rx_tasklet);
1642 tasklet_kill(&np->tx_tasklet);
1643 np->cur_tx = 0;
1644 np->dirty_tx = 0;
1645 np->cur_task = 0;
1646 np->last_tx = NULL;
1647
1648 netif_stop_queue(dev);
1649
1650 if (netif_msg_ifdown(np)) {
1651 printk(KERN_DEBUG "%s: Shutting down ethercard, status was Tx %2.2x "
1652 "Rx %4.4x Int %2.2x.\n",
1653 dev->name, ioread8(ioaddr + TxStatus),
1654 ioread32(ioaddr + RxStatus), ioread16(ioaddr + IntrStatus));
1655 printk(KERN_DEBUG "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
1656 dev->name, np->cur_tx, np->dirty_tx, np->cur_rx, np->dirty_rx);
1657 }
1658
1659 /* Disable interrupts by clearing the interrupt mask. */
1660 iowrite16(0x0000, ioaddr + IntrEnable);
1661
1662 /* Disable Rx and Tx DMA for safely release resource */
1663 iowrite32(0x500, ioaddr + DMACtrl);
1664
1665 /* Stop the chip's Tx and Rx processes. */
1666 iowrite16(TxDisable | RxDisable | StatsDisable, ioaddr + MACCtrl1);
1667
1668 for (i = 2000; i > 0; i--) {
1669 if ((ioread32(ioaddr + DMACtrl) & 0xc000) == 0)
1670 break;
1671 mdelay(1);
1672 }
1673
1674 iowrite16(GlobalReset | DMAReset | FIFOReset | NetworkReset,
1675 ioaddr +ASICCtrl + 2);
1676
1677 for (i = 2000; i > 0; i--) {
1678 if ((ioread16(ioaddr + ASICCtrl +2) & ResetBusy) == 0)
1679 break;
1680 mdelay(1);
1681 }
1682
1683 #ifdef __i386__
1684 if (netif_msg_hw(np)) {
1685 printk("\n"KERN_DEBUG" Tx ring at %8.8x:\n",
1686 (int)(np->tx_ring_dma));
1687 for (i = 0; i < TX_RING_SIZE; i++)
1688 printk(" #%d desc. %4.4x %8.8x %8.8x.\n",
1689 i, np->tx_ring[i].status, np->tx_ring[i].frag[0].addr,
1690 np->tx_ring[i].frag[0].length);
1691 printk("\n"KERN_DEBUG " Rx ring %8.8x:\n",
1692 (int)(np->rx_ring_dma));
1693 for (i = 0; i < /*RX_RING_SIZE*/4 ; i++) {
1694 printk(KERN_DEBUG " #%d desc. %4.4x %4.4x %8.8x\n",
1695 i, np->rx_ring[i].status, np->rx_ring[i].frag[0].addr,
1696 np->rx_ring[i].frag[0].length);
1697 }
1698 }
1699 #endif /* __i386__ debugging only */
1700
1701 free_irq(dev->irq, dev);
1702
1703 del_timer_sync(&np->timer);
1704
1705 /* Free all the skbuffs in the Rx queue. */
1706 for (i = 0; i < RX_RING_SIZE; i++) {
1707 np->rx_ring[i].status = 0;
1708 np->rx_ring[i].frag[0].addr = 0xBADF00D0; /* An invalid address. */
1709 skb = np->rx_skbuff[i];
1710 if (skb) {
1711 pci_unmap_single(np->pci_dev,
1712 np->rx_ring[i].frag[0].addr, np->rx_buf_sz,
1713 PCI_DMA_FROMDEVICE);
1714 dev_kfree_skb(skb);
1715 np->rx_skbuff[i] = NULL;
1716 }
1717 }
1718 for (i = 0; i < TX_RING_SIZE; i++) {
1719 np->tx_ring[i].next_desc = 0;
1720 skb = np->tx_skbuff[i];
1721 if (skb) {
1722 pci_unmap_single(np->pci_dev,
1723 np->tx_ring[i].frag[0].addr, skb->len,
1724 PCI_DMA_TODEVICE);
1725 dev_kfree_skb(skb);
1726 np->tx_skbuff[i] = NULL;
1727 }
1728 }
1729
1730 return 0;
1731 }
1732
1733 static void __devexit sundance_remove1 (struct pci_dev *pdev)
1734 {
1735 struct net_device *dev = pci_get_drvdata(pdev);
1736
1737 if (dev) {
1738 struct netdev_private *np = netdev_priv(dev);
1739
1740 unregister_netdev(dev);
1741 pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring,
1742 np->rx_ring_dma);
1743 pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring,
1744 np->tx_ring_dma);
1745 pci_iounmap(pdev, np->base);
1746 pci_release_regions(pdev);
1747 free_netdev(dev);
1748 pci_set_drvdata(pdev, NULL);
1749 }
1750 }
1751
1752 static struct pci_driver sundance_driver = {
1753 .name = DRV_NAME,
1754 .id_table = sundance_pci_tbl,
1755 .probe = sundance_probe1,
1756 .remove = __devexit_p(sundance_remove1),
1757 };
1758
1759 static int __init sundance_init(void)
1760 {
1761 /* when a module, this is printed whether or not devices are found in probe */
1762 #ifdef MODULE
1763 printk(version);
1764 #endif
1765 return pci_register_driver(&sundance_driver);
1766 }
1767
1768 static void __exit sundance_exit(void)
1769 {
1770 pci_unregister_driver(&sundance_driver);
1771 }
1772
1773 module_init(sundance_init);
1774 module_exit(sundance_exit);
1775
1776
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