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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs-2.6
[pv_ops_mirror.git] / drivers / ieee1394 / pcilynx.c
blob8af01ab30cc92da12ab9f114b1f51dadfd46bea1
1 /*
2 * pcilynx.c - Texas Instruments PCILynx driver
3 * Copyright (C) 1999,2000 Andreas Bombe <andreas.bombe@munich.netsurf.de>,
4 * Stephan Linz <linz@mazet.de>
5 * Manfred Weihs <weihs@ict.tuwien.ac.at>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software Foundation,
19 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22 /*
23 * Contributions:
24 *
25 * Manfred Weihs <weihs@ict.tuwien.ac.at>
26 * reading bus info block (containing GUID) from serial
27 * eeprom via i2c and storing it in config ROM
28 * Reworked code for initiating bus resets
29 * (long, short, with or without hold-off)
30 * Enhancements in async and iso send code
31 */
32
33 #include <linux/kernel.h>
34 #include <linux/slab.h>
35 #include <linux/interrupt.h>
36 #include <linux/wait.h>
37 #include <linux/errno.h>
38 #include <linux/module.h>
39 #include <linux/moduleparam.h>
40 #include <linux/init.h>
41 #include <linux/pci.h>
42 #include <linux/fs.h>
43 #include <linux/poll.h>
44 #include <linux/kdev_t.h>
45 #include <linux/dma-mapping.h>
46 #include <asm/byteorder.h>
47 #include <asm/atomic.h>
48 #include <asm/io.h>
49 #include <asm/uaccess.h>
50 #include <asm/irq.h>
51
52 #include "csr1212.h"
53 #include "ieee1394.h"
54 #include "ieee1394_types.h"
55 #include "hosts.h"
56 #include "ieee1394_core.h"
57 #include "highlevel.h"
58 #include "pcilynx.h"
59
60 #include <linux/i2c.h>
61 #include <linux/i2c-algo-bit.h>
62
63 /* print general (card independent) information */
64 #define PRINT_G(level, fmt, args...) printk(level "pcilynx: " fmt "\n" , ## args)
65 /* print card specific information */
66 #define PRINT(level, card, fmt, args...) printk(level "pcilynx%d: " fmt "\n" , card , ## args)
67
68 #ifdef CONFIG_IEEE1394_VERBOSEDEBUG
69 #define PRINT_GD(level, fmt, args...) printk(level "pcilynx: " fmt "\n" , ## args)
70 #define PRINTD(level, card, fmt, args...) printk(level "pcilynx%d: " fmt "\n" , card , ## args)
71 #else
72 #define PRINT_GD(level, fmt, args...) do {} while (0)
73 #define PRINTD(level, card, fmt, args...) do {} while (0)
74 #endif
75
76
77 /* Module Parameters */
78 static int skip_eeprom;
79 module_param(skip_eeprom, int, 0444);
80 MODULE_PARM_DESC(skip_eeprom, "Use generic bus info block instead of serial eeprom (default = 0).");
81
82
83 static struct hpsb_host_driver lynx_driver;
84 static unsigned int card_id;
85
86
87
88 /*
89 * I2C stuff
90 */
91
92 /* the i2c stuff was inspired by i2c-philips-par.c */
93
94 static void bit_setscl(void *data, int state)
95 {
96 if (state) {
97 ((struct ti_lynx *) data)->i2c_driven_state |= 0x00000040;
98 } else {
99 ((struct ti_lynx *) data)->i2c_driven_state &= ~0x00000040;
100 }
101 reg_write((struct ti_lynx *) data, SERIAL_EEPROM_CONTROL, ((struct ti_lynx *) data)->i2c_driven_state);
102 }
103
104 static void bit_setsda(void *data, int state)
105 {
106 if (state) {
107 ((struct ti_lynx *) data)->i2c_driven_state |= 0x00000010;
108 } else {
109 ((struct ti_lynx *) data)->i2c_driven_state &= ~0x00000010;
110 }
111 reg_write((struct ti_lynx *) data, SERIAL_EEPROM_CONTROL, ((struct ti_lynx *) data)->i2c_driven_state);
112 }
113
114 static int bit_getscl(void *data)
115 {
116 return reg_read((struct ti_lynx *) data, SERIAL_EEPROM_CONTROL) & 0x00000040;
117 }
118
119 static int bit_getsda(void *data)
120 {
121 return reg_read((struct ti_lynx *) data, SERIAL_EEPROM_CONTROL) & 0x00000010;
122 }
123
124 static struct i2c_algo_bit_data bit_data = {
125 .setsda = bit_setsda,
126 .setscl = bit_setscl,
127 .getsda = bit_getsda,
128 .getscl = bit_getscl,
129 .udelay = 5,
130 .timeout = 100,
131 };
132
133
134 /*
135 * PCL handling functions.
136 */
137
138 static pcl_t alloc_pcl(struct ti_lynx *lynx)
139 {
140 u8 m;
141 int i, j;
142
143 spin_lock(&lynx->lock);
144 /* FIXME - use ffz() to make this readable */
145 for (i = 0; i < (LOCALRAM_SIZE / 1024); i++) {
146 m = lynx->pcl_bmap[i];
147 for (j = 0; j < 8; j++) {
148 if (m & 1<<j) {
149 continue;
150 }
151 m |= 1<<j;
152 lynx->pcl_bmap[i] = m;
153 spin_unlock(&lynx->lock);
154 return 8 * i + j;
155 }
156 }
157 spin_unlock(&lynx->lock);
158
159 return -1;
160 }
161
162
163 #if 0
164 static void free_pcl(struct ti_lynx *lynx, pcl_t pclid)
165 {
166 int off, bit;
167
168 off = pclid / 8;
169 bit = pclid % 8;
170
171 if (pclid < 0) {
172 return;
173 }
174
175 spin_lock(&lynx->lock);
176 if (lynx->pcl_bmap[off] & 1<<bit) {
177 lynx->pcl_bmap[off] &= ~(1<<bit);
178 } else {
179 PRINT(KERN_ERR, lynx->id,
180 "attempted to free unallocated PCL %d", pclid);
181 }
182 spin_unlock(&lynx->lock);
183 }
184
185 /* functions useful for debugging */
186 static void pretty_print_pcl(const struct ti_pcl *pcl)
187 {
188 int i;
189
190 printk("PCL next %08x, userdata %08x, status %08x, remtrans %08x, nextbuf %08x\n",
191 pcl->next, pcl->user_data, pcl->pcl_status,
192 pcl->remaining_transfer_count, pcl->next_data_buffer);
193
194 printk("PCL");
195 for (i=0; i<13; i++) {
196 printk(" c%x:%08x d%x:%08x",
197 i, pcl->buffer[i].control, i, pcl->buffer[i].pointer);
198 if (!(i & 0x3) && (i != 12)) printk("\nPCL");
199 }
200 printk("\n");
201 }
202
203 static void print_pcl(const struct ti_lynx *lynx, pcl_t pclid)
204 {
205 struct ti_pcl pcl;
206
207 get_pcl(lynx, pclid, &pcl);
208 pretty_print_pcl(&pcl);
209 }
210 #endif
211
212
213
214 /***********************************
215 * IEEE-1394 functionality section *
216 ***********************************/
217
218
219 static int get_phy_reg(struct ti_lynx *lynx, int addr)
220 {
221 int retval;
222 int i = 0;
223
224 unsigned long flags;
225
226 if (addr > 15) {
227 PRINT(KERN_ERR, lynx->id,
228 "%s: PHY register address %d out of range",
229 __FUNCTION__, addr);
230 return -1;
231 }
232
233 spin_lock_irqsave(&lynx->phy_reg_lock, flags);
234
235 reg_write(lynx, LINK_PHY, LINK_PHY_READ | LINK_PHY_ADDR(addr));
236 do {
237 retval = reg_read(lynx, LINK_PHY);
238
239 if (i > 10000) {
240 PRINT(KERN_ERR, lynx->id, "%s: runaway loop, aborting",
241 __FUNCTION__);
242 retval = -1;
243 break;
244 }
245 i++;
246 } while ((retval & 0xf00) != LINK_PHY_RADDR(addr));
247
248 reg_write(lynx, LINK_INT_STATUS, LINK_INT_PHY_REG_RCVD);
249 spin_unlock_irqrestore(&lynx->phy_reg_lock, flags);
250
251 if (retval != -1) {
252 return retval & 0xff;
253 } else {
254 return -1;
255 }
256 }
257
258 static int set_phy_reg(struct ti_lynx *lynx, int addr, int val)
259 {
260 unsigned long flags;
261
262 if (addr > 15) {
263 PRINT(KERN_ERR, lynx->id,
264 "%s: PHY register address %d out of range", __FUNCTION__, addr);
265 return -1;
266 }
267
268 if (val > 0xff) {
269 PRINT(KERN_ERR, lynx->id,
270 "%s: PHY register value %d out of range", __FUNCTION__, val);
271 return -1;
272 }
273
274 spin_lock_irqsave(&lynx->phy_reg_lock, flags);
275
276 reg_write(lynx, LINK_PHY, LINK_PHY_WRITE | LINK_PHY_ADDR(addr)
277 | LINK_PHY_WDATA(val));
278
279 spin_unlock_irqrestore(&lynx->phy_reg_lock, flags);
280
281 return 0;
282 }
283
284 static int sel_phy_reg_page(struct ti_lynx *lynx, int page)
285 {
286 int reg;
287
288 if (page > 7) {
289 PRINT(KERN_ERR, lynx->id,
290 "%s: PHY page %d out of range", __FUNCTION__, page);
291 return -1;
292 }
293
294 reg = get_phy_reg(lynx, 7);
295 if (reg != -1) {
296 reg &= 0x1f;
297 reg |= (page << 5);
298 set_phy_reg(lynx, 7, reg);
299 return 0;
300 } else {
301 return -1;
302 }
303 }
304
305 #if 0 /* not needed at this time */
306 static int sel_phy_reg_port(struct ti_lynx *lynx, int port)
307 {
308 int reg;
309
310 if (port > 15) {
311 PRINT(KERN_ERR, lynx->id,
312 "%s: PHY port %d out of range", __FUNCTION__, port);
313 return -1;
314 }
315
316 reg = get_phy_reg(lynx, 7);
317 if (reg != -1) {
318 reg &= 0xf0;
319 reg |= port;
320 set_phy_reg(lynx, 7, reg);
321 return 0;
322 } else {
323 return -1;
324 }
325 }
326 #endif
327
328 static u32 get_phy_vendorid(struct ti_lynx *lynx)
329 {
330 u32 pvid = 0;
331 sel_phy_reg_page(lynx, 1);
332 pvid |= (get_phy_reg(lynx, 10) << 16);
333 pvid |= (get_phy_reg(lynx, 11) << 8);
334 pvid |= get_phy_reg(lynx, 12);
335 PRINT(KERN_INFO, lynx->id, "PHY vendor id 0x%06x", pvid);
336 return pvid;
337 }
338
339 static u32 get_phy_productid(struct ti_lynx *lynx)
340 {
341 u32 id = 0;
342 sel_phy_reg_page(lynx, 1);
343 id |= (get_phy_reg(lynx, 13) << 16);
344 id |= (get_phy_reg(lynx, 14) << 8);
345 id |= get_phy_reg(lynx, 15);
346 PRINT(KERN_INFO, lynx->id, "PHY product id 0x%06x", id);
347 return id;
348 }
349
350 static quadlet_t generate_own_selfid(struct ti_lynx *lynx,
351 struct hpsb_host *host)
352 {
353 quadlet_t lsid;
354 char phyreg[7];
355 int i;
356
357 phyreg[0] = lynx->phy_reg0;
358 for (i = 1; i < 7; i++) {
359 phyreg[i] = get_phy_reg(lynx, i);
360 }
361
362 /* FIXME? We assume a TSB21LV03A phy here. This code doesn't support
363 more than 3 ports on the PHY anyway. */
364
365 lsid = 0x80400000 | ((phyreg[0] & 0xfc) << 22);
366 lsid |= (phyreg[1] & 0x3f) << 16; /* gap count */
367 lsid |= (phyreg[2] & 0xc0) << 8; /* max speed */
368 if (!hpsb_disable_irm)
369 lsid |= (phyreg[6] & 0x01) << 11; /* contender (phy dependent) */
370 /* lsid |= 1 << 11; *//* set contender (hack) */
371 lsid |= (phyreg[6] & 0x10) >> 3; /* initiated reset */
372
373 for (i = 0; i < (phyreg[2] & 0xf); i++) { /* ports */
374 if (phyreg[3 + i] & 0x4) {
375 lsid |= (((phyreg[3 + i] & 0x8) | 0x10) >> 3)
376 << (6 - i*2);
377 } else {
378 lsid |= 1 << (6 - i*2);
379 }
380 }
381
382 cpu_to_be32s(&lsid);
383 PRINT(KERN_DEBUG, lynx->id, "generated own selfid 0x%x", lsid);
384 return lsid;
385 }
386
387 static void handle_selfid(struct ti_lynx *lynx, struct hpsb_host *host)
388 {
389 quadlet_t *q = lynx->rcv_page;
390 int phyid, isroot, size;
391 quadlet_t lsid = 0;
392 int i;
393
394 if (lynx->phy_reg0 == -1 || lynx->selfid_size == -1) return;
395
396 size = lynx->selfid_size;
397 phyid = lynx->phy_reg0;
398
399 i = (size > 16 ? 16 : size) / 4 - 1;
400 while (i >= 0) {
401 cpu_to_be32s(&q[i]);
402 i--;
403 }
404
405 if (!lynx->phyic.reg_1394a) {
406 lsid = generate_own_selfid(lynx, host);
407 }
408
409 isroot = (phyid & 2) != 0;
410 phyid >>= 2;
411 PRINT(KERN_INFO, lynx->id, "SelfID process finished (phyid %d, %s)",
412 phyid, (isroot ? "root" : "not root"));
413 reg_write(lynx, LINK_ID, (0xffc0 | phyid) << 16);
414
415 if (!lynx->phyic.reg_1394a && !size) {
416 hpsb_selfid_received(host, lsid);
417 }
418
419 while (size > 0) {
420 struct selfid *sid = (struct selfid *)q;
421
422 if (!lynx->phyic.reg_1394a && !sid->extended
423 && (sid->phy_id == (phyid + 1))) {
424 hpsb_selfid_received(host, lsid);
425 }
426
427 if (q[0] == ~q[1]) {
428 PRINT(KERN_DEBUG, lynx->id, "SelfID packet 0x%x rcvd",
429 q[0]);
430 hpsb_selfid_received(host, q[0]);
431 } else {
432 PRINT(KERN_INFO, lynx->id,
433 "inconsistent selfid 0x%x/0x%x", q[0], q[1]);
434 }
435 q += 2;
436 size -= 8;
437 }
438
439 if (!lynx->phyic.reg_1394a && isroot && phyid != 0) {
440 hpsb_selfid_received(host, lsid);
441 }
442
443 hpsb_selfid_complete(host, phyid, isroot);
444
445 if (host->in_bus_reset) return; /* in bus reset again */
446
447 if (isroot) reg_set_bits(lynx, LINK_CONTROL, LINK_CONTROL_CYCMASTER); //FIXME: I do not think, we need this here
448 reg_set_bits(lynx, LINK_CONTROL,
449 LINK_CONTROL_RCV_CMP_VALID | LINK_CONTROL_TX_ASYNC_EN
450 | LINK_CONTROL_RX_ASYNC_EN | LINK_CONTROL_CYCTIMEREN);
451 }
452
453
454
455 /* This must be called with the respective queue_lock held. */
456 static void send_next(struct ti_lynx *lynx, int what)
457 {
458 struct ti_pcl pcl;
459 struct lynx_send_data *d;
460 struct hpsb_packet *packet;
461
462 #if 0 /* has been removed from ieee1394 core */
463 d = (what == hpsb_iso ? &lynx->iso_send : &lynx->async);
464 #else
465 d = &lynx->async;
466 #endif
467 if (!list_empty(&d->pcl_queue)) {
468 PRINT(KERN_ERR, lynx->id, "trying to queue a new packet in nonempty fifo");
469 BUG();
470 }
471
472 packet = driver_packet(d->queue.next);
473 list_move_tail(&packet->driver_list, &d->pcl_queue);
474
475 d->header_dma = pci_map_single(lynx->dev, packet->header,
476 packet->header_size, PCI_DMA_TODEVICE);
477 if (packet->data_size) {
478 d->data_dma = pci_map_single(lynx->dev, packet->data,
479 packet->data_size,
480 PCI_DMA_TODEVICE);
481 } else {
482 d->data_dma = 0;
483 }
484
485 pcl.next = PCL_NEXT_INVALID;
486 pcl.async_error_next = PCL_NEXT_INVALID;
487 pcl.pcl_status = 0;
488 pcl.buffer[0].control = packet->speed_code << 14 | packet->header_size;
489 #ifndef __BIG_ENDIAN
490 pcl.buffer[0].control |= PCL_BIGENDIAN;
491 #endif
492 pcl.buffer[0].pointer = d->header_dma;
493 pcl.buffer[1].control = PCL_LAST_BUFF | packet->data_size;
494 pcl.buffer[1].pointer = d->data_dma;
495
496 switch (packet->type) {
497 case hpsb_async:
498 pcl.buffer[0].control |= PCL_CMD_XMT;
499 break;
500 #if 0 /* has been removed from ieee1394 core */
501 case hpsb_iso:
502 pcl.buffer[0].control |= PCL_CMD_XMT | PCL_ISOMODE;
503 break;
504 #endif
505 case hpsb_raw:
506 pcl.buffer[0].control |= PCL_CMD_UNFXMT;
507 break;
508 }
509
510 put_pcl(lynx, d->pcl, &pcl);
511 run_pcl(lynx, d->pcl_start, d->channel);
512 }
513
514
515 /* called from subsystem core */
516 static int lynx_transmit(struct hpsb_host *host, struct hpsb_packet *packet)
517 {
518 struct ti_lynx *lynx = host->hostdata;
519 struct lynx_send_data *d;
520 unsigned long flags;
521
522 if (packet->data_size >= 4096) {
523 PRINT(KERN_ERR, lynx->id, "transmit packet data too big (%Zd)",
524 packet->data_size);
525 return -EOVERFLOW;
526 }
527
528 switch (packet->type) {
529 case hpsb_async:
530 case hpsb_raw:
531 d = &lynx->async;
532 break;
533 #if 0 /* has been removed from ieee1394 core */
534 case hpsb_iso:
535 d = &lynx->iso_send;
536 break;
537 #endif
538 default:
539 PRINT(KERN_ERR, lynx->id, "invalid packet type %d",
540 packet->type);
541 return -EINVAL;
542 }
543
544 if (packet->tcode == TCODE_WRITEQ
545 || packet->tcode == TCODE_READQ_RESPONSE) {
546 cpu_to_be32s(&packet->header[3]);
547 }
548
549 spin_lock_irqsave(&d->queue_lock, flags);
550
551 list_add_tail(&packet->driver_list, &d->queue);
552 if (list_empty(&d->pcl_queue))
553 send_next(lynx, packet->type);
554
555 spin_unlock_irqrestore(&d->queue_lock, flags);
556
557 return 0;
558 }
559
560
561 /* called from subsystem core */
562 static int lynx_devctl(struct hpsb_host *host, enum devctl_cmd cmd, int arg)
563 {
564 struct ti_lynx *lynx = host->hostdata;
565 int retval = 0;
566 struct hpsb_packet *packet;
567 LIST_HEAD(packet_list);
568 unsigned long flags;
569 int phy_reg;
570
571 switch (cmd) {
572 case RESET_BUS:
573 if (reg_read(lynx, LINK_INT_STATUS) & LINK_INT_PHY_BUSRESET) {
574 retval = 0;
575 break;
576 }
577
578 switch (arg) {
579 case SHORT_RESET:
580 if (lynx->phyic.reg_1394a) {
581 phy_reg = get_phy_reg(lynx, 5);
582 if (phy_reg == -1) {
583 PRINT(KERN_ERR, lynx->id, "cannot reset bus, because read phy reg failed");
584 retval = -1;
585 break;
586 }
587 phy_reg |= 0x40;
588
589 PRINT(KERN_INFO, lynx->id, "resetting bus (short bus reset) on request");
590
591 lynx->selfid_size = -1;
592 lynx->phy_reg0 = -1;
593 set_phy_reg(lynx, 5, phy_reg); /* set ISBR */
594 break;
595 } else {
596 PRINT(KERN_INFO, lynx->id, "cannot do short bus reset, because of old phy");
597 /* fall through to long bus reset */
598 }
599 case LONG_RESET:
600 phy_reg = get_phy_reg(lynx, 1);
601 if (phy_reg == -1) {
602 PRINT(KERN_ERR, lynx->id, "cannot reset bus, because read phy reg failed");
603 retval = -1;
604 break;
605 }
606 phy_reg |= 0x40;
607
608 PRINT(KERN_INFO, lynx->id, "resetting bus (long bus reset) on request");
609
610 lynx->selfid_size = -1;
611 lynx->phy_reg0 = -1;
612 set_phy_reg(lynx, 1, phy_reg); /* clear RHB, set IBR */
613 break;
614 case SHORT_RESET_NO_FORCE_ROOT:
615 if (lynx->phyic.reg_1394a) {
616 phy_reg = get_phy_reg(lynx, 1);
617 if (phy_reg == -1) {
618 PRINT(KERN_ERR, lynx->id, "cannot reset bus, because read phy reg failed");
619 retval = -1;
620 break;
621 }
622 if (phy_reg & 0x80) {
623 phy_reg &= ~0x80;
624 set_phy_reg(lynx, 1, phy_reg); /* clear RHB */
625 }
626
627 phy_reg = get_phy_reg(lynx, 5);
628 if (phy_reg == -1) {
629 PRINT(KERN_ERR, lynx->id, "cannot reset bus, because read phy reg failed");
630 retval = -1;
631 break;
632 }
633 phy_reg |= 0x40;
634
635 PRINT(KERN_INFO, lynx->id, "resetting bus (short bus reset, no force_root) on request");
636
637 lynx->selfid_size = -1;
638 lynx->phy_reg0 = -1;
639 set_phy_reg(lynx, 5, phy_reg); /* set ISBR */
640 break;
641 } else {
642 PRINT(KERN_INFO, lynx->id, "cannot do short bus reset, because of old phy");
643 /* fall through to long bus reset */
644 }
645 case LONG_RESET_NO_FORCE_ROOT:
646 phy_reg = get_phy_reg(lynx, 1);
647 if (phy_reg == -1) {
648 PRINT(KERN_ERR, lynx->id, "cannot reset bus, because read phy reg failed");
649 retval = -1;
650 break;
651 }
652 phy_reg &= ~0x80;
653 phy_reg |= 0x40;
654
655 PRINT(KERN_INFO, lynx->id, "resetting bus (long bus reset, no force_root) on request");
656
657 lynx->selfid_size = -1;
658 lynx->phy_reg0 = -1;
659 set_phy_reg(lynx, 1, phy_reg); /* clear RHB, set IBR */
660 break;
661 case SHORT_RESET_FORCE_ROOT:
662 if (lynx->phyic.reg_1394a) {
663 phy_reg = get_phy_reg(lynx, 1);
664 if (phy_reg == -1) {
665 PRINT(KERN_ERR, lynx->id, "cannot reset bus, because read phy reg failed");
666 retval = -1;
667 break;
668 }
669 if (!(phy_reg & 0x80)) {
670 phy_reg |= 0x80;
671 set_phy_reg(lynx, 1, phy_reg); /* set RHB */
672 }
673
674 phy_reg = get_phy_reg(lynx, 5);
675 if (phy_reg == -1) {
676 PRINT(KERN_ERR, lynx->id, "cannot reset bus, because read phy reg failed");
677 retval = -1;
678 break;
679 }
680 phy_reg |= 0x40;
681
682 PRINT(KERN_INFO, lynx->id, "resetting bus (short bus reset, force_root set) on request");
683
684 lynx->selfid_size = -1;
685 lynx->phy_reg0 = -1;
686 set_phy_reg(lynx, 5, phy_reg); /* set ISBR */
687 break;
688 } else {
689 PRINT(KERN_INFO, lynx->id, "cannot do short bus reset, because of old phy");
690 /* fall through to long bus reset */
691 }
692 case LONG_RESET_FORCE_ROOT:
693 phy_reg = get_phy_reg(lynx, 1);
694 if (phy_reg == -1) {
695 PRINT(KERN_ERR, lynx->id, "cannot reset bus, because read phy reg failed");
696 retval = -1;
697 break;
698 }
699 phy_reg |= 0xc0;
700
701 PRINT(KERN_INFO, lynx->id, "resetting bus (long bus reset, force_root set) on request");
702
703 lynx->selfid_size = -1;
704 lynx->phy_reg0 = -1;
705 set_phy_reg(lynx, 1, phy_reg); /* set IBR and RHB */
706 break;
707 default:
708 PRINT(KERN_ERR, lynx->id, "unknown argument for reset_bus command %d", arg);
709 retval = -1;
710 }
711
712 break;
713
714 case GET_CYCLE_COUNTER:
715 retval = reg_read(lynx, CYCLE_TIMER);
716 break;
717
718 case SET_CYCLE_COUNTER:
719 reg_write(lynx, CYCLE_TIMER, arg);
720 break;
721
722 case SET_BUS_ID:
723 reg_write(lynx, LINK_ID,
724 (arg << 22) | (reg_read(lynx, LINK_ID) & 0x003f0000));
725 break;
726
727 case ACT_CYCLE_MASTER:
728 if (arg) {
729 reg_set_bits(lynx, LINK_CONTROL,
730 LINK_CONTROL_CYCMASTER);
731 } else {
732 reg_clear_bits(lynx, LINK_CONTROL,
733 LINK_CONTROL_CYCMASTER);
734 }
735 break;
736
737 case CANCEL_REQUESTS:
738 spin_lock_irqsave(&lynx->async.queue_lock, flags);
739
740 reg_write(lynx, DMA_CHAN_CTRL(CHANNEL_ASYNC_SEND), 0);
741 list_splice(&lynx->async.queue, &packet_list);
742 INIT_LIST_HEAD(&lynx->async.queue);
743
744 if (list_empty(&lynx->async.pcl_queue)) {
745 spin_unlock_irqrestore(&lynx->async.queue_lock, flags);
746 PRINTD(KERN_DEBUG, lynx->id, "no async packet in PCL to cancel");
747 } else {
748 struct ti_pcl pcl;
749 u32 ack;
750
751 PRINT(KERN_INFO, lynx->id, "cancelling async packet, that was already in PCL");
752
753 get_pcl(lynx, lynx->async.pcl, &pcl);
754
755 packet = driver_packet(lynx->async.pcl_queue.next);
756 list_del_init(&packet->driver_list);
757
758 pci_unmap_single(lynx->dev, lynx->async.header_dma,
759 packet->header_size, PCI_DMA_TODEVICE);
760 if (packet->data_size) {
761 pci_unmap_single(lynx->dev, lynx->async.data_dma,
762 packet->data_size, PCI_DMA_TODEVICE);
763 }
764
765 spin_unlock_irqrestore(&lynx->async.queue_lock, flags);
766
767 if (pcl.pcl_status & DMA_CHAN_STAT_PKTCMPL) {
768 if (pcl.pcl_status & DMA_CHAN_STAT_SPECIALACK) {
769 ack = (pcl.pcl_status >> 15) & 0xf;
770 PRINTD(KERN_INFO, lynx->id, "special ack %d", ack);
771 ack = (ack == 1 ? ACKX_TIMEOUT : ACKX_SEND_ERROR);
772 } else {
773 ack = (pcl.pcl_status >> 15) & 0xf;
774 }
775 } else {
776 PRINT(KERN_INFO, lynx->id, "async packet was not completed");
777 ack = ACKX_ABORTED;
778 }
779 hpsb_packet_sent(host, packet, ack);
780 }
781
782 while (!list_empty(&packet_list)) {
783 packet = driver_packet(packet_list.next);
784 list_del_init(&packet->driver_list);
785 hpsb_packet_sent(host, packet, ACKX_ABORTED);
786 }
787
788 break;
789 #if 0 /* has been removed from ieee1394 core */
790 case ISO_LISTEN_CHANNEL:
791 spin_lock_irqsave(&lynx->iso_rcv.lock, flags);
792
793 if (lynx->iso_rcv.chan_count++ == 0) {
794 reg_write(lynx, DMA_WORD1_CMP_ENABLE(CHANNEL_ISO_RCV),
795 DMA_WORD1_CMP_ENABLE_MASTER);
796 }
797
798 spin_unlock_irqrestore(&lynx->iso_rcv.lock, flags);
799 break;
800
801 case ISO_UNLISTEN_CHANNEL:
802 spin_lock_irqsave(&lynx->iso_rcv.lock, flags);
803
804 if (--lynx->iso_rcv.chan_count == 0) {
805 reg_write(lynx, DMA_WORD1_CMP_ENABLE(CHANNEL_ISO_RCV),
806 0);
807 }
808
809 spin_unlock_irqrestore(&lynx->iso_rcv.lock, flags);
810 break;
811 #endif
812 default:
813 PRINT(KERN_ERR, lynx->id, "unknown devctl command %d", cmd);
814 retval = -1;
815 }
816
817 return retval;
818 }
819
820
821 /***************************************
822 * IEEE-1394 functionality section END *
823 ***************************************/
824
825
826 /********************************************************
827 * Global stuff (interrupt handler, init/shutdown code) *
828 ********************************************************/
829
830
831 static irqreturn_t lynx_irq_handler(int irq, void *dev_id)
832 {
833 struct ti_lynx *lynx = (struct ti_lynx *)dev_id;
834 struct hpsb_host *host = lynx->host;
835 u32 intmask;
836 u32 linkint;
837
838 linkint = reg_read(lynx, LINK_INT_STATUS);
839 intmask = reg_read(lynx, PCI_INT_STATUS);
840
841 if (!(intmask & PCI_INT_INT_PEND))
842 return IRQ_NONE;
843
844 PRINTD(KERN_DEBUG, lynx->id, "interrupt: 0x%08x / 0x%08x", intmask,
845 linkint);
846
847 reg_write(lynx, LINK_INT_STATUS, linkint);
848 reg_write(lynx, PCI_INT_STATUS, intmask);
849
850 if (intmask & PCI_INT_1394) {
851 if (linkint & LINK_INT_PHY_TIMEOUT) {
852 PRINT(KERN_INFO, lynx->id, "PHY timeout occurred");
853 }
854 if (linkint & LINK_INT_PHY_BUSRESET) {
855 PRINT(KERN_INFO, lynx->id, "bus reset interrupt");
856 lynx->selfid_size = -1;
857 lynx->phy_reg0 = -1;
858 if (!host->in_bus_reset)
859 hpsb_bus_reset(host);
860 }
861 if (linkint & LINK_INT_PHY_REG_RCVD) {
862 u32 reg;
863
864 spin_lock(&lynx->phy_reg_lock);
865 reg = reg_read(lynx, LINK_PHY);
866 spin_unlock(&lynx->phy_reg_lock);
867
868 if (!host->in_bus_reset) {
869 PRINT(KERN_INFO, lynx->id,
870 "phy reg received without reset");
871 } else if (reg & 0xf00) {
872 PRINT(KERN_INFO, lynx->id,
873 "unsolicited phy reg %d received",
874 (reg >> 8) & 0xf);
875 } else {
876 lynx->phy_reg0 = reg & 0xff;
877 handle_selfid(lynx, host);
878 }
879 }
880 if (linkint & LINK_INT_ISO_STUCK) {
881 PRINT(KERN_INFO, lynx->id, "isochronous transmitter stuck");
882 }
883 if (linkint & LINK_INT_ASYNC_STUCK) {
884 PRINT(KERN_INFO, lynx->id, "asynchronous transmitter stuck");
885 }
886 if (linkint & LINK_INT_SENT_REJECT) {
887 PRINT(KERN_INFO, lynx->id, "sent reject");
888 }
889 if (linkint & LINK_INT_TX_INVALID_TC) {
890 PRINT(KERN_INFO, lynx->id, "invalid transaction code");
891 }
892 if (linkint & LINK_INT_GRF_OVERFLOW) {
893 /* flush FIFO if overflow happens during reset */
894 if (host->in_bus_reset)
895 reg_write(lynx, FIFO_CONTROL,
896 FIFO_CONTROL_GRF_FLUSH);
897 PRINT(KERN_INFO, lynx->id, "GRF overflow");
898 }
899 if (linkint & LINK_INT_ITF_UNDERFLOW) {
900 PRINT(KERN_INFO, lynx->id, "ITF underflow");
901 }
902 if (linkint & LINK_INT_ATF_UNDERFLOW) {
903 PRINT(KERN_INFO, lynx->id, "ATF underflow");
904 }
905 }
906
907 if (intmask & PCI_INT_DMA_HLT(CHANNEL_ISO_RCV)) {
908 PRINTD(KERN_DEBUG, lynx->id, "iso receive");
909
910 spin_lock(&lynx->iso_rcv.lock);
911
912 lynx->iso_rcv.stat[lynx->iso_rcv.next] =
913 reg_read(lynx, DMA_CHAN_STAT(CHANNEL_ISO_RCV));
914
915 lynx->iso_rcv.used++;
916 lynx->iso_rcv.next = (lynx->iso_rcv.next + 1) % NUM_ISORCV_PCL;
917
918 if ((lynx->iso_rcv.next == lynx->iso_rcv.last)
919 || !lynx->iso_rcv.chan_count) {
920 PRINTD(KERN_DEBUG, lynx->id, "stopped");
921 reg_write(lynx, DMA_WORD1_CMP_ENABLE(CHANNEL_ISO_RCV), 0);
922 }
923
924 run_sub_pcl(lynx, lynx->iso_rcv.pcl_start, lynx->iso_rcv.next,
925 CHANNEL_ISO_RCV);
926
927 spin_unlock(&lynx->iso_rcv.lock);
928
929 tasklet_schedule(&lynx->iso_rcv.tq);
930 }
931
932 if (intmask & PCI_INT_DMA_HLT(CHANNEL_ASYNC_SEND)) {
933 PRINTD(KERN_DEBUG, lynx->id, "async sent");
934 spin_lock(&lynx->async.queue_lock);
935
936 if (list_empty(&lynx->async.pcl_queue)) {
937 spin_unlock(&lynx->async.queue_lock);
938 PRINT(KERN_WARNING, lynx->id, "async dma halted, but no queued packet (maybe it was cancelled)");
939 } else {
940 struct ti_pcl pcl;
941 u32 ack;
942 struct hpsb_packet *packet;
943
944 get_pcl(lynx, lynx->async.pcl, &pcl);
945
946 packet = driver_packet(lynx->async.pcl_queue.next);
947 list_del_init(&packet->driver_list);
948
949 pci_unmap_single(lynx->dev, lynx->async.header_dma,
950 packet->header_size, PCI_DMA_TODEVICE);
951 if (packet->data_size) {
952 pci_unmap_single(lynx->dev, lynx->async.data_dma,
953 packet->data_size, PCI_DMA_TODEVICE);
954 }
955
956 if (!list_empty(&lynx->async.queue)) {
957 send_next(lynx, hpsb_async);
958 }
959
960 spin_unlock(&lynx->async.queue_lock);
961
962 if (pcl.pcl_status & DMA_CHAN_STAT_PKTCMPL) {
963 if (pcl.pcl_status & DMA_CHAN_STAT_SPECIALACK) {
964 ack = (pcl.pcl_status >> 15) & 0xf;
965 PRINTD(KERN_INFO, lynx->id, "special ack %d", ack);
966 ack = (ack == 1 ? ACKX_TIMEOUT : ACKX_SEND_ERROR);
967 } else {
968 ack = (pcl.pcl_status >> 15) & 0xf;
969 }
970 } else {
971 PRINT(KERN_INFO, lynx->id, "async packet was not completed");
972 ack = ACKX_SEND_ERROR;
973 }
974 hpsb_packet_sent(host, packet, ack);
975 }
976 }
977
978 if (intmask & PCI_INT_DMA_HLT(CHANNEL_ISO_SEND)) {
979 PRINTD(KERN_DEBUG, lynx->id, "iso sent");
980 spin_lock(&lynx->iso_send.queue_lock);
981
982 if (list_empty(&lynx->iso_send.pcl_queue)) {
983 spin_unlock(&lynx->iso_send.queue_lock);
984 PRINT(KERN_ERR, lynx->id, "iso send dma halted, but no queued packet");
985 } else {
986 struct ti_pcl pcl;
987 u32 ack;
988 struct hpsb_packet *packet;
989
990 get_pcl(lynx, lynx->iso_send.pcl, &pcl);
991
992 packet = driver_packet(lynx->iso_send.pcl_queue.next);
993 list_del_init(&packet->driver_list);
994
995 pci_unmap_single(lynx->dev, lynx->iso_send.header_dma,
996 packet->header_size, PCI_DMA_TODEVICE);
997 if (packet->data_size) {
998 pci_unmap_single(lynx->dev, lynx->iso_send.data_dma,
999 packet->data_size, PCI_DMA_TODEVICE);
1000 }
1001 #if 0 /* has been removed from ieee1394 core */
1002 if (!list_empty(&lynx->iso_send.queue)) {
1003 send_next(lynx, hpsb_iso);
1004 }
1005 #endif
1006 spin_unlock(&lynx->iso_send.queue_lock);
1007
1008 if (pcl.pcl_status & DMA_CHAN_STAT_PKTCMPL) {
1009 if (pcl.pcl_status & DMA_CHAN_STAT_SPECIALACK) {
1010 ack = (pcl.pcl_status >> 15) & 0xf;
1011 PRINTD(KERN_INFO, lynx->id, "special ack %d", ack);
1012 ack = (ack == 1 ? ACKX_TIMEOUT : ACKX_SEND_ERROR);
1013 } else {
1014 ack = (pcl.pcl_status >> 15) & 0xf;
1015 }
1016 } else {
1017 PRINT(KERN_INFO, lynx->id, "iso send packet was not completed");
1018 ack = ACKX_SEND_ERROR;
1019 }
1020
1021 hpsb_packet_sent(host, packet, ack); //FIXME: maybe we should just use ACK_COMPLETE and ACKX_SEND_ERROR
1022 }
1023 }
1024
1025 if (intmask & PCI_INT_DMA_HLT(CHANNEL_ASYNC_RCV)) {
1026 /* general receive DMA completed */
1027 int stat = reg_read(lynx, DMA_CHAN_STAT(CHANNEL_ASYNC_RCV));
1028
1029 PRINTD(KERN_DEBUG, lynx->id, "received packet size %d",
1030 stat & 0x1fff);
1031
1032 if (stat & DMA_CHAN_STAT_SELFID) {
1033 lynx->selfid_size = stat & 0x1fff;
1034 handle_selfid(lynx, host);
1035 } else {
1036 quadlet_t *q_data = lynx->rcv_page;
1037 if ((*q_data >> 4 & 0xf) == TCODE_READQ_RESPONSE
1038 || (*q_data >> 4 & 0xf) == TCODE_WRITEQ) {
1039 cpu_to_be32s(q_data + 3);
1040 }
1041 hpsb_packet_received(host, q_data, stat & 0x1fff, 0);
1042 }
1043
1044 run_pcl(lynx, lynx->rcv_pcl_start, CHANNEL_ASYNC_RCV);
1045 }
1046
1047 return IRQ_HANDLED;
1048 }
1049
1050
1051 static void iso_rcv_bh(struct ti_lynx *lynx)
1052 {
1053 unsigned int idx;
1054 quadlet_t *data;
1055 unsigned long flags;
1056
1057 spin_lock_irqsave(&lynx->iso_rcv.lock, flags);
1058
1059 while (lynx->iso_rcv.used) {
1060 idx = lynx->iso_rcv.last;
1061 spin_unlock_irqrestore(&lynx->iso_rcv.lock, flags);
1062
1063 data = lynx->iso_rcv.page[idx / ISORCV_PER_PAGE]
1064 + (idx % ISORCV_PER_PAGE) * MAX_ISORCV_SIZE;
1065
1066 if ((*data >> 16) + 4 != (lynx->iso_rcv.stat[idx] & 0x1fff)) {
1067 PRINT(KERN_ERR, lynx->id,
1068 "iso length mismatch 0x%08x/0x%08x", *data,
1069 lynx->iso_rcv.stat[idx]);
1070 }
1071
1072 if (lynx->iso_rcv.stat[idx]
1073 & (DMA_CHAN_STAT_PCIERR | DMA_CHAN_STAT_PKTERR)) {
1074 PRINT(KERN_INFO, lynx->id,
1075 "iso receive error on %d to 0x%p", idx, data);
1076 } else {
1077 hpsb_packet_received(lynx->host, data,
1078 lynx->iso_rcv.stat[idx] & 0x1fff,
1079 0);
1080 }
1081
1082 spin_lock_irqsave(&lynx->iso_rcv.lock, flags);
1083 lynx->iso_rcv.last = (idx + 1) % NUM_ISORCV_PCL;
1084 lynx->iso_rcv.used--;
1085 }
1086
1087 if (lynx->iso_rcv.chan_count) {
1088 reg_write(lynx, DMA_WORD1_CMP_ENABLE(CHANNEL_ISO_RCV),
1089 DMA_WORD1_CMP_ENABLE_MASTER);
1090 }
1091 spin_unlock_irqrestore(&lynx->iso_rcv.lock, flags);
1092 }
1093
1094
1095 static void remove_card(struct pci_dev *dev)
1096 {
1097 struct ti_lynx *lynx;
1098 struct device *lynx_dev;
1099 int i;
1100
1101 lynx = pci_get_drvdata(dev);
1102 if (!lynx) return;
1103 pci_set_drvdata(dev, NULL);
1104
1105 lynx_dev = get_device(&lynx->host->device);
1106
1107 switch (lynx->state) {
1108 case is_host:
1109 reg_write(lynx, PCI_INT_ENABLE, 0);
1110 hpsb_remove_host(lynx->host);
1111 case have_intr:
1112 reg_write(lynx, PCI_INT_ENABLE, 0);
1113 free_irq(lynx->dev->irq, lynx);
1114
1115 /* Disable IRM Contender and LCtrl */
1116 if (lynx->phyic.reg_1394a)
1117 set_phy_reg(lynx, 4, ~0xc0 & get_phy_reg(lynx, 4));
1118
1119 /* Let all other nodes know to ignore us */
1120 lynx_devctl(lynx->host, RESET_BUS, LONG_RESET_NO_FORCE_ROOT);
1121
1122 case have_iomappings:
1123 reg_set_bits(lynx, MISC_CONTROL, MISC_CONTROL_SWRESET);
1124 /* Fix buggy cards with autoboot pin not tied low: */
1125 reg_write(lynx, DMA0_CHAN_CTRL, 0);
1126 iounmap(lynx->registers);
1127 iounmap(lynx->local_rom);
1128 iounmap(lynx->local_ram);
1129 iounmap(lynx->aux_port);
1130 case have_1394_buffers:
1131 for (i = 0; i < ISORCV_PAGES; i++) {
1132 if (lynx->iso_rcv.page[i]) {
1133 pci_free_consistent(lynx->dev, PAGE_SIZE,
1134 lynx->iso_rcv.page[i],
1135 lynx->iso_rcv.page_dma[i]);
1136 }
1137 }
1138 pci_free_consistent(lynx->dev, PAGE_SIZE, lynx->rcv_page,
1139 lynx->rcv_page_dma);
1140 case have_aux_buf:
1141 case have_pcl_mem:
1142 pci_free_consistent(lynx->dev, LOCALRAM_SIZE, lynx->pcl_mem,
1143 lynx->pcl_mem_dma);
1144 case clear:
1145 /* do nothing - already freed */
1146 ;
1147 }
1148
1149 tasklet_kill(&lynx->iso_rcv.tq);
1150
1151 if (lynx_dev)
1152 put_device(lynx_dev);
1153 }
1154
1155
1156 static int __devinit add_card(struct pci_dev *dev,
1157 const struct pci_device_id *devid_is_unused)
1158 {
1159 #define FAIL(fmt, args...) do { \
1160 PRINT_G(KERN_ERR, fmt , ## args); \
1161 remove_card(dev); \
1162 return error; \
1163 } while (0)
1164
1165 char irq_buf[16];
1166 struct hpsb_host *host;
1167 struct ti_lynx *lynx; /* shortcut to currently handled device */
1168 struct ti_pcl pcl;
1169 u32 *pcli;
1170 int i;
1171 int error;
1172
1173 error = -ENXIO;
1174
1175 if (pci_set_dma_mask(dev, DMA_32BIT_MASK))
1176 FAIL("DMA address limits not supported for PCILynx hardware");
1177 if (pci_enable_device(dev))
1178 FAIL("failed to enable PCILynx hardware");
1179 pci_set_master(dev);
1180
1181 error = -ENOMEM;
1182
1183 host = hpsb_alloc_host(&lynx_driver, sizeof(struct ti_lynx), &dev->dev);
1184 if (!host) FAIL("failed to allocate control structure memory");
1185
1186 lynx = host->hostdata;
1187 lynx->id = card_id++;
1188 lynx->dev = dev;
1189 lynx->state = clear;
1190 lynx->host = host;
1191 host->pdev = dev;
1192 pci_set_drvdata(dev, lynx);
1193
1194 spin_lock_init(&lynx->lock);
1195 spin_lock_init(&lynx->phy_reg_lock);
1196
1197 lynx->pcl_mem = pci_alloc_consistent(dev, LOCALRAM_SIZE,
1198 &lynx->pcl_mem_dma);
1199
1200 if (lynx->pcl_mem != NULL) {
1201 lynx->state = have_pcl_mem;
1202 PRINT(KERN_INFO, lynx->id,
1203 "allocated PCL memory %d Bytes @ 0x%p", LOCALRAM_SIZE,
1204 lynx->pcl_mem);
1205 } else {
1206 FAIL("failed to allocate PCL memory area");
1207 }
1208
1209 lynx->rcv_page = pci_alloc_consistent(dev, PAGE_SIZE,
1210 &lynx->rcv_page_dma);
1211 if (lynx->rcv_page == NULL) {
1212 FAIL("failed to allocate receive buffer");
1213 }
1214 lynx->state = have_1394_buffers;
1215
1216 for (i = 0; i < ISORCV_PAGES; i++) {
1217 lynx->iso_rcv.page[i] =
1218 pci_alloc_consistent(dev, PAGE_SIZE,
1219 &lynx->iso_rcv.page_dma[i]);
1220 if (lynx->iso_rcv.page[i] == NULL) {
1221 FAIL("failed to allocate iso receive buffers");
1222 }
1223 }
1224
1225 lynx->registers = ioremap_nocache(pci_resource_start(dev,0),
1226 PCILYNX_MAX_REGISTER);
1227 lynx->local_ram = ioremap(pci_resource_start(dev,1), PCILYNX_MAX_MEMORY);
1228 lynx->aux_port = ioremap(pci_resource_start(dev,2), PCILYNX_MAX_MEMORY);
1229 lynx->local_rom = ioremap(pci_resource_start(dev,PCI_ROM_RESOURCE),
1230 PCILYNX_MAX_MEMORY);
1231 lynx->state = have_iomappings;
1232
1233 if (lynx->registers == NULL) {
1234 FAIL("failed to remap registers - card not accessible");
1235 }
1236
1237 reg_set_bits(lynx, MISC_CONTROL, MISC_CONTROL_SWRESET);
1238 /* Fix buggy cards with autoboot pin not tied low: */
1239 reg_write(lynx, DMA0_CHAN_CTRL, 0);
1240
1241 sprintf (irq_buf, "%d", dev->irq);
1242
1243 if (!request_irq(dev->irq, lynx_irq_handler, IRQF_SHARED,
1244 PCILYNX_DRIVER_NAME, lynx)) {
1245 PRINT(KERN_INFO, lynx->id, "allocated interrupt %s", irq_buf);
1246 lynx->state = have_intr;
1247 } else {
1248 FAIL("failed to allocate shared interrupt %s", irq_buf);
1249 }
1250
1251 /* alloc_pcl return values are not checked, it is expected that the
1252 * provided PCL space is sufficient for the initial allocations */
1253 lynx->rcv_pcl = alloc_pcl(lynx);
1254 lynx->rcv_pcl_start = alloc_pcl(lynx);
1255 lynx->async.pcl = alloc_pcl(lynx);
1256 lynx->async.pcl_start = alloc_pcl(lynx);
1257 lynx->iso_send.pcl = alloc_pcl(lynx);
1258 lynx->iso_send.pcl_start = alloc_pcl(lynx);
1259
1260 for (i = 0; i < NUM_ISORCV_PCL; i++) {
1261 lynx->iso_rcv.pcl[i] = alloc_pcl(lynx);
1262 }
1263 lynx->iso_rcv.pcl_start = alloc_pcl(lynx);
1264
1265 /* all allocations successful - simple init stuff follows */
1266
1267 reg_write(lynx, PCI_INT_ENABLE, PCI_INT_DMA_ALL);
1268
1269 tasklet_init(&lynx->iso_rcv.tq, (void (*)(unsigned long))iso_rcv_bh,
1270 (unsigned long)lynx);
1271
1272 spin_lock_init(&lynx->iso_rcv.lock);
1273
1274 spin_lock_init(&lynx->async.queue_lock);
1275 lynx->async.channel = CHANNEL_ASYNC_SEND;
1276 spin_lock_init(&lynx->iso_send.queue_lock);
1277 lynx->iso_send.channel = CHANNEL_ISO_SEND;
1278
1279 PRINT(KERN_INFO, lynx->id, "remapped memory spaces reg 0x%p, rom 0x%p, "
1280 "ram 0x%p, aux 0x%p", lynx->registers, lynx->local_rom,
1281 lynx->local_ram, lynx->aux_port);
1282
1283 /* now, looking for PHY register set */
1284 if ((get_phy_reg(lynx, 2) & 0xe0) == 0xe0) {
1285 lynx->phyic.reg_1394a = 1;
1286 PRINT(KERN_INFO, lynx->id,
1287 "found 1394a conform PHY (using extended register set)");
1288 lynx->phyic.vendor = get_phy_vendorid(lynx);
1289 lynx->phyic.product = get_phy_productid(lynx);
1290 } else {
1291 lynx->phyic.reg_1394a = 0;
1292 PRINT(KERN_INFO, lynx->id, "found old 1394 PHY");
1293 }
1294
1295 lynx->selfid_size = -1;
1296 lynx->phy_reg0 = -1;
1297
1298 INIT_LIST_HEAD(&lynx->async.queue);
1299 INIT_LIST_HEAD(&lynx->async.pcl_queue);
1300 INIT_LIST_HEAD(&lynx->iso_send.queue);
1301 INIT_LIST_HEAD(&lynx->iso_send.pcl_queue);
1302
1303 pcl.next = pcl_bus(lynx, lynx->rcv_pcl);
1304 put_pcl(lynx, lynx->rcv_pcl_start, &pcl);
1305
1306 pcl.next = PCL_NEXT_INVALID;
1307 pcl.async_error_next = PCL_NEXT_INVALID;
1308
1309 pcl.buffer[0].control = PCL_CMD_RCV | 16;
1310 #ifndef __BIG_ENDIAN
1311 pcl.buffer[0].control |= PCL_BIGENDIAN;
1312 #endif
1313 pcl.buffer[1].control = PCL_LAST_BUFF | 4080;
1314
1315 pcl.buffer[0].pointer = lynx->rcv_page_dma;
1316 pcl.buffer[1].pointer = lynx->rcv_page_dma + 16;
1317 put_pcl(lynx, lynx->rcv_pcl, &pcl);
1318
1319 pcl.next = pcl_bus(lynx, lynx->async.pcl);
1320 pcl.async_error_next = pcl_bus(lynx, lynx->async.pcl);
1321 put_pcl(lynx, lynx->async.pcl_start, &pcl);
1322
1323 pcl.next = pcl_bus(lynx, lynx->iso_send.pcl);
1324 pcl.async_error_next = PCL_NEXT_INVALID;
1325 put_pcl(lynx, lynx->iso_send.pcl_start, &pcl);
1326
1327 pcl.next = PCL_NEXT_INVALID;
1328 pcl.async_error_next = PCL_NEXT_INVALID;
1329 pcl.buffer[0].control = PCL_CMD_RCV | 4;
1330 #ifndef __BIG_ENDIAN
1331 pcl.buffer[0].control |= PCL_BIGENDIAN;
1332 #endif
1333 pcl.buffer[1].control = PCL_LAST_BUFF | 2044;
1334
1335 for (i = 0; i < NUM_ISORCV_PCL; i++) {
1336 int page = i / ISORCV_PER_PAGE;
1337 int sec = i % ISORCV_PER_PAGE;
1338
1339 pcl.buffer[0].pointer = lynx->iso_rcv.page_dma[page]
1340 + sec * MAX_ISORCV_SIZE;
1341 pcl.buffer[1].pointer = pcl.buffer[0].pointer + 4;
1342 put_pcl(lynx, lynx->iso_rcv.pcl[i], &pcl);
1343 }
1344
1345 pcli = (u32 *)&pcl;
1346 for (i = 0; i < NUM_ISORCV_PCL; i++) {
1347 pcli[i] = pcl_bus(lynx, lynx->iso_rcv.pcl[i]);
1348 }
1349 put_pcl(lynx, lynx->iso_rcv.pcl_start, &pcl);
1350
1351 /* FIFO sizes from left to right: ITF=48 ATF=48 GRF=160 */
1352 reg_write(lynx, FIFO_SIZES, 0x003030a0);
1353 /* 20 byte threshold before triggering PCI transfer */
1354 reg_write(lynx, DMA_GLOBAL_REGISTER, 0x2<<24);
1355 /* threshold on both send FIFOs before transmitting:
1356 FIFO size - cache line size - 1 */
1357 i = reg_read(lynx, PCI_LATENCY_CACHELINE) & 0xff;
1358 i = 0x30 - i - 1;
1359 reg_write(lynx, FIFO_XMIT_THRESHOLD, (i << 8) | i);
1360
1361 reg_set_bits(lynx, PCI_INT_ENABLE, PCI_INT_1394);
1362
1363 reg_write(lynx, LINK_INT_ENABLE, LINK_INT_PHY_TIMEOUT
1364 | LINK_INT_PHY_REG_RCVD | LINK_INT_PHY_BUSRESET
1365 | LINK_INT_ISO_STUCK | LINK_INT_ASYNC_STUCK
1366 | LINK_INT_SENT_REJECT | LINK_INT_TX_INVALID_TC
1367 | LINK_INT_GRF_OVERFLOW | LINK_INT_ITF_UNDERFLOW
1368 | LINK_INT_ATF_UNDERFLOW);
1369
1370 reg_write(lynx, DMA_WORD0_CMP_VALUE(CHANNEL_ASYNC_RCV), 0);
1371 reg_write(lynx, DMA_WORD0_CMP_ENABLE(CHANNEL_ASYNC_RCV), 0xa<<4);
1372 reg_write(lynx, DMA_WORD1_CMP_VALUE(CHANNEL_ASYNC_RCV), 0);
1373 reg_write(lynx, DMA_WORD1_CMP_ENABLE(CHANNEL_ASYNC_RCV),
1374 DMA_WORD1_CMP_MATCH_LOCAL_NODE | DMA_WORD1_CMP_MATCH_BROADCAST
1375 | DMA_WORD1_CMP_MATCH_EXACT | DMA_WORD1_CMP_MATCH_BUS_BCAST
1376 | DMA_WORD1_CMP_ENABLE_SELF_ID | DMA_WORD1_CMP_ENABLE_MASTER);
1377
1378 run_pcl(lynx, lynx->rcv_pcl_start, CHANNEL_ASYNC_RCV);
1379
1380 reg_write(lynx, DMA_WORD0_CMP_VALUE(CHANNEL_ISO_RCV), 0);
1381 reg_write(lynx, DMA_WORD0_CMP_ENABLE(CHANNEL_ISO_RCV), 0x9<<4);
1382 reg_write(lynx, DMA_WORD1_CMP_VALUE(CHANNEL_ISO_RCV), 0);
1383 reg_write(lynx, DMA_WORD1_CMP_ENABLE(CHANNEL_ISO_RCV), 0);
1384
1385 run_sub_pcl(lynx, lynx->iso_rcv.pcl_start, 0, CHANNEL_ISO_RCV);
1386
1387 reg_write(lynx, LINK_CONTROL, LINK_CONTROL_RCV_CMP_VALID
1388 | LINK_CONTROL_TX_ISO_EN | LINK_CONTROL_RX_ISO_EN
1389 | LINK_CONTROL_TX_ASYNC_EN | LINK_CONTROL_RX_ASYNC_EN
1390 | LINK_CONTROL_RESET_TX | LINK_CONTROL_RESET_RX);
1391
1392 if (!lynx->phyic.reg_1394a) {
1393 if (!hpsb_disable_irm) {
1394 /* attempt to enable contender bit -FIXME- would this
1395 * work elsewhere? */
1396 reg_set_bits(lynx, GPIO_CTRL_A, 0x1);
1397 reg_write(lynx, GPIO_DATA_BASE + 0x3c, 0x1);
1398 }
1399 } else {
1400 /* set the contender (if appropriate) and LCtrl bit in the
1401 * extended PHY register set. (Should check that PHY_02_EXTENDED
1402 * is set in register 2?)
1403 */
1404 i = get_phy_reg(lynx, 4);
1405 i |= PHY_04_LCTRL;
1406 if (hpsb_disable_irm)
1407 i &= ~PHY_04_CONTENDER;
1408 else
1409 i |= PHY_04_CONTENDER;
1410 if (i != -1) set_phy_reg(lynx, 4, i);
1411 }
1412
1413 if (!skip_eeprom)
1414 {
1415 /* needed for i2c communication with serial eeprom */
1416 struct i2c_adapter *i2c_ad;
1417 struct i2c_algo_bit_data i2c_adapter_data;
1418
1419 error = -ENOMEM;
1420 i2c_ad = kzalloc(sizeof(*i2c_ad), GFP_KERNEL);
1421 if (!i2c_ad) FAIL("failed to allocate I2C adapter memory");
1422
1423 i2c_ad->id = I2C_HW_B_PCILYNX;
1424 strlcpy(i2c_ad->name, "PCILynx I2C", sizeof(i2c_ad->name));
1425 i2c_adapter_data = bit_data;
1426 i2c_ad->algo_data = &i2c_adapter_data;
1427 i2c_adapter_data.data = lynx;
1428 i2c_ad->dev.parent = &dev->dev;
1429
1430 PRINTD(KERN_DEBUG, lynx->id,"original eeprom control: %d",
1431 reg_read(lynx, SERIAL_EEPROM_CONTROL));
1432
1433 /* reset hardware to sane state */
1434 lynx->i2c_driven_state = 0x00000070;
1435 reg_write(lynx, SERIAL_EEPROM_CONTROL, lynx->i2c_driven_state);
1436
1437 if (i2c_bit_add_bus(i2c_ad) < 0)
1438 {
1439 kfree(i2c_ad);
1440 error = -ENXIO;
1441 FAIL("unable to register i2c");
1442 }
1443 else
1444 {
1445 /* do i2c stuff */
1446 unsigned char i2c_cmd = 0x10;
1447 struct i2c_msg msg[2] = { { 0x50, 0, 1, &i2c_cmd },
1448 { 0x50, I2C_M_RD, 20, (unsigned char*) lynx->bus_info_block }
1449 };
1450
1451 /* we use i2c_transfer because we have no i2c_client
1452 at hand */
1453 if (i2c_transfer(i2c_ad, msg, 2) < 0) {
1454 PRINT(KERN_ERR, lynx->id, "unable to read bus info block from i2c");
1455 } else {
1456 PRINT(KERN_INFO, lynx->id, "got bus info block from serial eeprom");
1457 /* FIXME: probably we shoud rewrite the max_rec, max_ROM(1394a),
1458 * generation(1394a) and link_spd(1394a) field and recalculate
1459 * the CRC */
1460
1461 for (i = 0; i < 5 ; i++)
1462 PRINTD(KERN_DEBUG, lynx->id, "Businfo block quadlet %i: %08x",
1463 i, be32_to_cpu(lynx->bus_info_block[i]));
1464
1465 /* info_length, crc_length and 1394 magic number to check, if it is really a bus info block */
1466 if (((be32_to_cpu(lynx->bus_info_block[0]) & 0xffff0000) == 0x04040000) &&
1467 (lynx->bus_info_block[1] == __constant_cpu_to_be32(0x31333934)))
1468 {
1469 PRINT(KERN_DEBUG, lynx->id, "read a valid bus info block from");
1470 } else {
1471 kfree(i2c_ad);
1472 error = -ENXIO;
1473 FAIL("read something from serial eeprom, but it does not seem to be a valid bus info block");
1474 }
1475
1476 }
1477
1478 i2c_del_adapter(i2c_ad);
1479 kfree(i2c_ad);
1480 }
1481 }
1482
1483 host->csr.guid_hi = be32_to_cpu(lynx->bus_info_block[3]);
1484 host->csr.guid_lo = be32_to_cpu(lynx->bus_info_block[4]);
1485 host->csr.cyc_clk_acc = (be32_to_cpu(lynx->bus_info_block[2]) >> 16) & 0xff;
1486 host->csr.max_rec = (be32_to_cpu(lynx->bus_info_block[2]) >> 12) & 0xf;
1487 if (!lynx->phyic.reg_1394a)
1488 host->csr.lnk_spd = (get_phy_reg(lynx, 2) & 0xc0) >> 6;
1489 else
1490 host->csr.lnk_spd = be32_to_cpu(lynx->bus_info_block[2]) & 0x7;
1491
1492 if (hpsb_add_host(host)) {
1493 error = -ENOMEM;
1494 FAIL("Failed to register host with highlevel");
1495 }
1496
1497 lynx->state = is_host;
1498
1499 return 0;
1500 #undef FAIL
1501 }
1502
1503
1504 static struct pci_device_id pci_table[] = {
1505 {
1506 .vendor = PCI_VENDOR_ID_TI,
1507 .device = PCI_DEVICE_ID_TI_PCILYNX,
1508 .subvendor = PCI_ANY_ID,
1509 .subdevice = PCI_ANY_ID,
1510 },
1511 { } /* Terminating entry */
1512 };
1513
1514 static struct pci_driver lynx_pci_driver = {
1515 .name = PCILYNX_DRIVER_NAME,
1516 .id_table = pci_table,
1517 .probe = add_card,
1518 .remove = remove_card,
1519 };
1520
1521 static struct hpsb_host_driver lynx_driver = {
1522 .owner = THIS_MODULE,
1523 .name = PCILYNX_DRIVER_NAME,
1524 .set_hw_config_rom = NULL,
1525 .transmit_packet = lynx_transmit,
1526 .devctl = lynx_devctl,
1527 .isoctl = NULL,
1528 };
1529
1530 MODULE_AUTHOR("Andreas E. Bombe <andreas.bombe@munich.netsurf.de>");
1531 MODULE_DESCRIPTION("driver for Texas Instruments PCI Lynx IEEE-1394 controller");
1532 MODULE_LICENSE("GPL");
1533 MODULE_SUPPORTED_DEVICE("pcilynx");
1534 MODULE_DEVICE_TABLE(pci, pci_table);
1535
1536 static int __init pcilynx_init(void)
1537 {
1538 int ret;
1539
1540 ret = pci_register_driver(&lynx_pci_driver);
1541 if (ret < 0) {
1542 PRINT_G(KERN_ERR, "PCI module init failed");
1543 return ret;
1544 }
1545
1546 return 0;
1547 }
1548
1549 static void __exit pcilynx_cleanup(void)
1550 {
1551 pci_unregister_driver(&lynx_pci_driver);
1552 }
1553
1554
1555 module_init(pcilynx_init);
1556 module_exit(pcilynx_cleanup);
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