2 * pata_hpt3x3 - HPT3x3 driver
3 * (c) Copyright 2005-2006 Red Hat
5 * Was pata_hpt34x but the naming was confusing as it supported the
6 * 343 and 363 so it has been renamed.
9 * linux/drivers/ide/pci/hpt34x.c Version 0.40 Sept 10, 2002
10 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
12 * May be copied or modified under the terms of the GNU General Public
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/pci.h>
19 #include <linux/init.h>
20 #include <linux/blkdev.h>
21 #include <linux/delay.h>
22 #include <scsi/scsi_host.h>
23 #include <linux/libata.h>
25 #define DRV_NAME "pata_hpt3x3"
26 #define DRV_VERSION "0.5.3"
29 * hpt3x3_set_piomode - PIO setup
31 * @adev: device on the interface
33 * Set our PIO requirements. This is fairly simple on the HPT3x3 as
34 * all we have to do is clear the MWDMA and UDMA bits then load the
38 static void hpt3x3_set_piomode(struct ata_port
*ap
, struct ata_device
*adev
)
40 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
42 int dn
= 2 * ap
->port_no
+ adev
->devno
;
44 pci_read_config_dword(pdev
, 0x44, &r1
);
45 pci_read_config_dword(pdev
, 0x48, &r2
);
46 /* Load the PIO timing number */
47 r1
&= ~(7 << (3 * dn
));
48 r1
|= (adev
->pio_mode
- XFER_PIO_0
) << (3 * dn
);
49 r2
&= ~(0x11 << dn
); /* Clear MWDMA and UDMA bits */
51 pci_write_config_dword(pdev
, 0x44, r1
);
52 pci_write_config_dword(pdev
, 0x48, r2
);
55 #if defined(CONFIG_PATA_HPT3X3_DMA)
57 * hpt3x3_set_dmamode - DMA timing setup
59 * @adev: Device being configured
61 * Set up the channel for MWDMA or UDMA modes. Much the same as with
62 * PIO, load the mode number and then set MWDMA or UDMA flag.
64 * 0x44 : bit 0-2 master mode, 3-5 slave mode, etc
65 * 0x48 : bit 4/0 DMA/UDMA bit 5/1 for slave etc
68 static void hpt3x3_set_dmamode(struct ata_port
*ap
, struct ata_device
*adev
)
70 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
72 int dn
= 2 * ap
->port_no
+ adev
->devno
;
73 int mode_num
= adev
->dma_mode
& 0x0F;
75 pci_read_config_dword(pdev
, 0x44, &r1
);
76 pci_read_config_dword(pdev
, 0x48, &r2
);
77 /* Load the timing number */
78 r1
&= ~(7 << (3 * dn
));
79 r1
|= (mode_num
<< (3 * dn
));
80 r2
&= ~(0x11 << dn
); /* Clear MWDMA and UDMA bits */
82 if (adev
->dma_mode
>= XFER_UDMA_0
)
83 r2
|= (0x10 << dn
); /* Ultra mode */
85 r2
|= (0x01 << dn
); /* MWDMA */
87 pci_write_config_dword(pdev
, 0x44, r1
);
88 pci_write_config_dword(pdev
, 0x48, r2
);
90 #endif /* CONFIG_PATA_HPT3X3_DMA */
93 * hpt3x3_atapi_dma - ATAPI DMA check
96 * Just say no - we don't do ATAPI DMA
99 static int hpt3x3_atapi_dma(struct ata_queued_cmd
*qc
)
104 static struct scsi_host_template hpt3x3_sht
= {
105 .module
= THIS_MODULE
,
107 .ioctl
= ata_scsi_ioctl
,
108 .queuecommand
= ata_scsi_queuecmd
,
109 .can_queue
= ATA_DEF_QUEUE
,
110 .this_id
= ATA_SHT_THIS_ID
,
111 .sg_tablesize
= LIBATA_MAX_PRD
,
112 .cmd_per_lun
= ATA_SHT_CMD_PER_LUN
,
113 .emulated
= ATA_SHT_EMULATED
,
114 .use_clustering
= ATA_SHT_USE_CLUSTERING
,
115 .proc_name
= DRV_NAME
,
116 .dma_boundary
= ATA_DMA_BOUNDARY
,
117 .slave_configure
= ata_scsi_slave_config
,
118 .slave_destroy
= ata_scsi_slave_destroy
,
119 .bios_param
= ata_std_bios_param
,
122 static struct ata_port_operations hpt3x3_port_ops
= {
123 .port_disable
= ata_port_disable
,
124 .set_piomode
= hpt3x3_set_piomode
,
125 #if defined(CONFIG_PATA_HPT3X3_DMA)
126 .set_dmamode
= hpt3x3_set_dmamode
,
128 .mode_filter
= ata_pci_default_filter
,
130 .tf_load
= ata_tf_load
,
131 .tf_read
= ata_tf_read
,
132 .check_status
= ata_check_status
,
133 .exec_command
= ata_exec_command
,
134 .dev_select
= ata_std_dev_select
,
136 .freeze
= ata_bmdma_freeze
,
137 .thaw
= ata_bmdma_thaw
,
138 .error_handler
= ata_bmdma_error_handler
,
139 .post_internal_cmd
= ata_bmdma_post_internal_cmd
,
140 .cable_detect
= ata_cable_40wire
,
142 .bmdma_setup
= ata_bmdma_setup
,
143 .bmdma_start
= ata_bmdma_start
,
144 .bmdma_stop
= ata_bmdma_stop
,
145 .bmdma_status
= ata_bmdma_status
,
146 .check_atapi_dma
= hpt3x3_atapi_dma
,
148 .qc_prep
= ata_qc_prep
,
149 .qc_issue
= ata_qc_issue_prot
,
151 .data_xfer
= ata_data_xfer
,
153 .irq_handler
= ata_interrupt
,
154 .irq_clear
= ata_bmdma_irq_clear
,
155 .irq_on
= ata_irq_on
,
156 .irq_ack
= ata_irq_ack
,
158 .port_start
= ata_port_start
,
162 * hpt3x3_init_chipset - chip setup
165 * Perform the setup required at boot and on resume.
168 static void hpt3x3_init_chipset(struct pci_dev
*dev
)
171 /* Initialize the board */
172 pci_write_config_word(dev
, 0x80, 0x00);
173 /* Check if it is a 343 or a 363. 363 has COMMAND_MEMORY set */
174 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
175 if (cmd
& PCI_COMMAND_MEMORY
)
176 pci_write_config_byte(dev
, PCI_LATENCY_TIMER
, 0xF0);
178 pci_write_config_byte(dev
, PCI_LATENCY_TIMER
, 0x20);
182 * hpt3x3_init_one - Initialise an HPT343/363
184 * @id: Entry in match table
186 * Perform basic initialisation. We set the device up so we access all
187 * ports via BAR4. This is neccessary to work around errata.
190 static int hpt3x3_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
192 static int printed_version
;
193 static const struct ata_port_info info
= {
195 .flags
= ATA_FLAG_SLAVE_POSS
,
197 #if defined(CONFIG_PATA_HPT3X3_DMA)
198 /* Further debug needed */
202 .port_ops
= &hpt3x3_port_ops
204 /* Register offsets of taskfiles in BAR4 area */
205 static const u8 offset_cmd
[2] = { 0x20, 0x28 };
206 static const u8 offset_ctl
[2] = { 0x36, 0x3E };
207 const struct ata_port_info
*ppi
[] = { &info
, NULL
};
208 struct ata_host
*host
;
212 hpt3x3_init_chipset(pdev
);
214 if (!printed_version
++)
215 dev_printk(KERN_DEBUG
, &pdev
->dev
, "version " DRV_VERSION
"\n");
217 host
= ata_host_alloc_pinfo(&pdev
->dev
, ppi
, 2);
220 /* acquire resources and fill host */
221 rc
= pcim_enable_device(pdev
);
225 /* Everything is relative to BAR4 if we set up this way */
226 rc
= pcim_iomap_regions(pdev
, 1 << 4, DRV_NAME
);
228 pcim_pin_device(pdev
);
231 host
->iomap
= pcim_iomap_table(pdev
);
232 rc
= pci_set_dma_mask(pdev
, ATA_DMA_MASK
);
235 rc
= pci_set_consistent_dma_mask(pdev
, ATA_DMA_MASK
);
239 base
= host
->iomap
[4]; /* Bus mastering base */
241 for (i
= 0; i
< host
->n_ports
; i
++) {
242 struct ata_ioports
*ioaddr
= &host
->ports
[i
]->ioaddr
;
244 ioaddr
->cmd_addr
= base
+ offset_cmd
[i
];
245 ioaddr
->altstatus_addr
=
246 ioaddr
->ctl_addr
= base
+ offset_ctl
[i
];
247 ioaddr
->scr_addr
= NULL
;
248 ata_std_ports(ioaddr
);
249 ioaddr
->bmdma_addr
= base
+ 8 * i
;
251 pci_set_master(pdev
);
252 return ata_host_activate(host
, pdev
->irq
, ata_interrupt
, IRQF_SHARED
,
257 static int hpt3x3_reinit_one(struct pci_dev
*dev
)
259 hpt3x3_init_chipset(dev
);
260 return ata_pci_device_resume(dev
);
264 static const struct pci_device_id hpt3x3
[] = {
265 { PCI_VDEVICE(TTI
, PCI_DEVICE_ID_TTI_HPT343
), },
270 static struct pci_driver hpt3x3_pci_driver
= {
273 .probe
= hpt3x3_init_one
,
274 .remove
= ata_pci_remove_one
,
276 .suspend
= ata_pci_device_suspend
,
277 .resume
= hpt3x3_reinit_one
,
281 static int __init
hpt3x3_init(void)
283 return pci_register_driver(&hpt3x3_pci_driver
);
287 static void __exit
hpt3x3_exit(void)
289 pci_unregister_driver(&hpt3x3_pci_driver
);
293 MODULE_AUTHOR("Alan Cox");
294 MODULE_DESCRIPTION("low-level driver for the Highpoint HPT343/363");
295 MODULE_LICENSE("GPL");
296 MODULE_DEVICE_TABLE(pci
, hpt3x3
);
297 MODULE_VERSION(DRV_VERSION
);
299 module_init(hpt3x3_init
);
300 module_exit(hpt3x3_exit
);