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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc-2.6
[pv_ops_mirror.git] / drivers / ata / sata_sil.c
blobf5119bf40c24f0e9e65219208e2fd65a47137e1f
1 /*
2 * sata_sil.c - Silicon Image SATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003-2005 Red Hat, Inc.
9 * Copyright 2003 Benjamin Herrenschmidt
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 *
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
29 *
30 * Documentation for SiI 3112:
31 * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2
32 *
33 * Other errata and documentation available under NDA.
34 *
35 */
36
37 #include <linux/kernel.h>
38 #include <linux/module.h>
39 #include <linux/pci.h>
40 #include <linux/init.h>
41 #include <linux/blkdev.h>
42 #include <linux/delay.h>
43 #include <linux/interrupt.h>
44 #include <linux/device.h>
45 #include <scsi/scsi_host.h>
46 #include <linux/libata.h>
47
48 #define DRV_NAME "sata_sil"
49 #define DRV_VERSION "2.3"
50
51 enum {
52 SIL_MMIO_BAR = 5,
53
54 /*
55 * host flags
56 */
57 SIL_FLAG_NO_SATA_IRQ = (1 << 28),
58 SIL_FLAG_RERR_ON_DMA_ACT = (1 << 29),
59 SIL_FLAG_MOD15WRITE = (1 << 30),
60
61 SIL_DFL_PORT_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
62 ATA_FLAG_MMIO,
63 SIL_DFL_LINK_FLAGS = ATA_LFLAG_HRST_TO_RESUME,
64
65 /*
66 * Controller IDs
67 */
68 sil_3112 = 0,
69 sil_3112_no_sata_irq = 1,
70 sil_3512 = 2,
71 sil_3114 = 3,
72
73 /*
74 * Register offsets
75 */
76 SIL_SYSCFG = 0x48,
77
78 /*
79 * Register bits
80 */
81 /* SYSCFG */
82 SIL_MASK_IDE0_INT = (1 << 22),
83 SIL_MASK_IDE1_INT = (1 << 23),
84 SIL_MASK_IDE2_INT = (1 << 24),
85 SIL_MASK_IDE3_INT = (1 << 25),
86 SIL_MASK_2PORT = SIL_MASK_IDE0_INT | SIL_MASK_IDE1_INT,
87 SIL_MASK_4PORT = SIL_MASK_2PORT |
88 SIL_MASK_IDE2_INT | SIL_MASK_IDE3_INT,
89
90 /* BMDMA/BMDMA2 */
91 SIL_INTR_STEERING = (1 << 1),
92
93 SIL_DMA_ENABLE = (1 << 0), /* DMA run switch */
94 SIL_DMA_RDWR = (1 << 3), /* DMA Rd-Wr */
95 SIL_DMA_SATA_IRQ = (1 << 4), /* OR of all SATA IRQs */
96 SIL_DMA_ACTIVE = (1 << 16), /* DMA running */
97 SIL_DMA_ERROR = (1 << 17), /* PCI bus error */
98 SIL_DMA_COMPLETE = (1 << 18), /* cmd complete / IRQ pending */
99 SIL_DMA_N_SATA_IRQ = (1 << 6), /* SATA_IRQ for the next channel */
100 SIL_DMA_N_ACTIVE = (1 << 24), /* ACTIVE for the next channel */
101 SIL_DMA_N_ERROR = (1 << 25), /* ERROR for the next channel */
102 SIL_DMA_N_COMPLETE = (1 << 26), /* COMPLETE for the next channel */
103
104 /* SIEN */
105 SIL_SIEN_N = (1 << 16), /* triggered by SError.N */
106
107 /*
108 * Others
109 */
110 SIL_QUIRK_MOD15WRITE = (1 << 0),
111 SIL_QUIRK_UDMA5MAX = (1 << 1),
112 };
113
114 static int sil_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
115 #ifdef CONFIG_PM
116 static int sil_pci_device_resume(struct pci_dev *pdev);
117 #endif
118 static void sil_dev_config(struct ata_device *dev);
119 static int sil_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
120 static int sil_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
121 static int sil_set_mode(struct ata_link *link, struct ata_device **r_failed);
122 static void sil_freeze(struct ata_port *ap);
123 static void sil_thaw(struct ata_port *ap);
124
125
126 static const struct pci_device_id sil_pci_tbl[] = {
127 { PCI_VDEVICE(CMD, 0x3112), sil_3112 },
128 { PCI_VDEVICE(CMD, 0x0240), sil_3112 },
129 { PCI_VDEVICE(CMD, 0x3512), sil_3512 },
130 { PCI_VDEVICE(CMD, 0x3114), sil_3114 },
131 { PCI_VDEVICE(ATI, 0x436e), sil_3112 },
132 { PCI_VDEVICE(ATI, 0x4379), sil_3112_no_sata_irq },
133 { PCI_VDEVICE(ATI, 0x437a), sil_3112_no_sata_irq },
134
135 { } /* terminate list */
136 };
137
138
139 /* TODO firmware versions should be added - eric */
140 static const struct sil_drivelist {
141 const char *product;
142 unsigned int quirk;
143 } sil_blacklist [] = {
144 { "ST320012AS", SIL_QUIRK_MOD15WRITE },
145 { "ST330013AS", SIL_QUIRK_MOD15WRITE },
146 { "ST340017AS", SIL_QUIRK_MOD15WRITE },
147 { "ST360015AS", SIL_QUIRK_MOD15WRITE },
148 { "ST380023AS", SIL_QUIRK_MOD15WRITE },
149 { "ST3120023AS", SIL_QUIRK_MOD15WRITE },
150 { "ST340014ASL", SIL_QUIRK_MOD15WRITE },
151 { "ST360014ASL", SIL_QUIRK_MOD15WRITE },
152 { "ST380011ASL", SIL_QUIRK_MOD15WRITE },
153 { "ST3120022ASL", SIL_QUIRK_MOD15WRITE },
154 { "ST3160021ASL", SIL_QUIRK_MOD15WRITE },
155 { "Maxtor 4D060H3", SIL_QUIRK_UDMA5MAX },
156 { }
157 };
158
159 static struct pci_driver sil_pci_driver = {
160 .name = DRV_NAME,
161 .id_table = sil_pci_tbl,
162 .probe = sil_init_one,
163 .remove = ata_pci_remove_one,
164 #ifdef CONFIG_PM
165 .suspend = ata_pci_device_suspend,
166 .resume = sil_pci_device_resume,
167 #endif
168 };
169
170 static struct scsi_host_template sil_sht = {
171 .module = THIS_MODULE,
172 .name = DRV_NAME,
173 .ioctl = ata_scsi_ioctl,
174 .queuecommand = ata_scsi_queuecmd,
175 .can_queue = ATA_DEF_QUEUE,
176 .this_id = ATA_SHT_THIS_ID,
177 .sg_tablesize = LIBATA_MAX_PRD,
178 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
179 .emulated = ATA_SHT_EMULATED,
180 .use_clustering = ATA_SHT_USE_CLUSTERING,
181 .proc_name = DRV_NAME,
182 .dma_boundary = ATA_DMA_BOUNDARY,
183 .slave_configure = ata_scsi_slave_config,
184 .slave_destroy = ata_scsi_slave_destroy,
185 .bios_param = ata_std_bios_param,
186 };
187
188 static const struct ata_port_operations sil_ops = {
189 .dev_config = sil_dev_config,
190 .tf_load = ata_tf_load,
191 .tf_read = ata_tf_read,
192 .check_status = ata_check_status,
193 .exec_command = ata_exec_command,
194 .dev_select = ata_std_dev_select,
195 .set_mode = sil_set_mode,
196 .bmdma_setup = ata_bmdma_setup,
197 .bmdma_start = ata_bmdma_start,
198 .bmdma_stop = ata_bmdma_stop,
199 .bmdma_status = ata_bmdma_status,
200 .qc_prep = ata_qc_prep,
201 .qc_issue = ata_qc_issue_prot,
202 .data_xfer = ata_data_xfer,
203 .freeze = sil_freeze,
204 .thaw = sil_thaw,
205 .error_handler = ata_bmdma_error_handler,
206 .post_internal_cmd = ata_bmdma_post_internal_cmd,
207 .irq_clear = ata_bmdma_irq_clear,
208 .irq_on = ata_irq_on,
209 .scr_read = sil_scr_read,
210 .scr_write = sil_scr_write,
211 .port_start = ata_port_start,
212 };
213
214 static const struct ata_port_info sil_port_info[] = {
215 /* sil_3112 */
216 {
217 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_MOD15WRITE,
218 .link_flags = SIL_DFL_LINK_FLAGS,
219 .pio_mask = 0x1f, /* pio0-4 */
220 .mwdma_mask = 0x07, /* mwdma0-2 */
221 .udma_mask = ATA_UDMA5,
222 .port_ops = &sil_ops,
223 },
224 /* sil_3112_no_sata_irq */
225 {
226 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_MOD15WRITE |
227 SIL_FLAG_NO_SATA_IRQ,
228 .link_flags = SIL_DFL_LINK_FLAGS,
229 .pio_mask = 0x1f, /* pio0-4 */
230 .mwdma_mask = 0x07, /* mwdma0-2 */
231 .udma_mask = ATA_UDMA5,
232 .port_ops = &sil_ops,
233 },
234 /* sil_3512 */
235 {
236 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT,
237 .link_flags = SIL_DFL_LINK_FLAGS,
238 .pio_mask = 0x1f, /* pio0-4 */
239 .mwdma_mask = 0x07, /* mwdma0-2 */
240 .udma_mask = ATA_UDMA5,
241 .port_ops = &sil_ops,
242 },
243 /* sil_3114 */
244 {
245 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT,
246 .link_flags = SIL_DFL_LINK_FLAGS,
247 .pio_mask = 0x1f, /* pio0-4 */
248 .mwdma_mask = 0x07, /* mwdma0-2 */
249 .udma_mask = ATA_UDMA5,
250 .port_ops = &sil_ops,
251 },
252 };
253
254 /* per-port register offsets */
255 /* TODO: we can probably calculate rather than use a table */
256 static const struct {
257 unsigned long tf; /* ATA taskfile register block */
258 unsigned long ctl; /* ATA control/altstatus register block */
259 unsigned long bmdma; /* DMA register block */
260 unsigned long bmdma2; /* DMA register block #2 */
261 unsigned long fifo_cfg; /* FIFO Valid Byte Count and Control */
262 unsigned long scr; /* SATA control register block */
263 unsigned long sien; /* SATA Interrupt Enable register */
264 unsigned long xfer_mode;/* data transfer mode register */
265 unsigned long sfis_cfg; /* SATA FIS reception config register */
266 } sil_port[] = {
267 /* port 0 ... */
268 /* tf ctl bmdma bmdma2 fifo scr sien mode sfis */
269 { 0x80, 0x8A, 0x0, 0x10, 0x40, 0x100, 0x148, 0xb4, 0x14c },
270 { 0xC0, 0xCA, 0x8, 0x18, 0x44, 0x180, 0x1c8, 0xf4, 0x1cc },
271 { 0x280, 0x28A, 0x200, 0x210, 0x240, 0x300, 0x348, 0x2b4, 0x34c },
272 { 0x2C0, 0x2CA, 0x208, 0x218, 0x244, 0x380, 0x3c8, 0x2f4, 0x3cc },
273 /* ... port 3 */
274 };
275
276 MODULE_AUTHOR("Jeff Garzik");
277 MODULE_DESCRIPTION("low-level driver for Silicon Image SATA controller");
278 MODULE_LICENSE("GPL");
279 MODULE_DEVICE_TABLE(pci, sil_pci_tbl);
280 MODULE_VERSION(DRV_VERSION);
281
282 static int slow_down;
283 module_param(slow_down, int, 0444);
284 MODULE_PARM_DESC(slow_down, "Sledgehammer used to work around random problems, by limiting commands to 15 sectors (0=off, 1=on)");
285
286
287 static unsigned char sil_get_device_cache_line(struct pci_dev *pdev)
288 {
289 u8 cache_line = 0;
290 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_line);
291 return cache_line;
292 }
293
294 /**
295 * sil_set_mode - wrap set_mode functions
296 * @link: link to set up
297 * @r_failed: returned device when we fail
298 *
299 * Wrap the libata method for device setup as after the setup we need
300 * to inspect the results and do some configuration work
301 */
302
303 static int sil_set_mode(struct ata_link *link, struct ata_device **r_failed)
304 {
305 struct ata_port *ap = link->ap;
306 void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR];
307 void __iomem *addr = mmio_base + sil_port[ap->port_no].xfer_mode;
308 struct ata_device *dev;
309 u32 tmp, dev_mode[2] = { };
310 int rc;
311
312 rc = ata_do_set_mode(link, r_failed);
313 if (rc)
314 return rc;
315
316 ata_link_for_each_dev(dev, link) {
317 if (!ata_dev_enabled(dev))
318 dev_mode[dev->devno] = 0; /* PIO0/1/2 */
319 else if (dev->flags & ATA_DFLAG_PIO)
320 dev_mode[dev->devno] = 1; /* PIO3/4 */
321 else
322 dev_mode[dev->devno] = 3; /* UDMA */
323 /* value 2 indicates MDMA */
324 }
325
326 tmp = readl(addr);
327 tmp &= ~((1<<5) | (1<<4) | (1<<1) | (1<<0));
328 tmp |= dev_mode[0];
329 tmp |= (dev_mode[1] << 4);
330 writel(tmp, addr);
331 readl(addr); /* flush */
332 return 0;
333 }
334
335 static inline void __iomem *sil_scr_addr(struct ata_port *ap,
336 unsigned int sc_reg)
337 {
338 void __iomem *offset = ap->ioaddr.scr_addr;
339
340 switch (sc_reg) {
341 case SCR_STATUS:
342 return offset + 4;
343 case SCR_ERROR:
344 return offset + 8;
345 case SCR_CONTROL:
346 return offset;
347 default:
348 /* do nothing */
349 break;
350 }
351
352 return NULL;
353 }
354
355 static int sil_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
356 {
357 void __iomem *mmio = sil_scr_addr(ap, sc_reg);
358
359 if (mmio) {
360 *val = readl(mmio);
361 return 0;
362 }
363 return -EINVAL;
364 }
365
366 static int sil_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
367 {
368 void __iomem *mmio = sil_scr_addr(ap, sc_reg);
369
370 if (mmio) {
371 writel(val, mmio);
372 return 0;
373 }
374 return -EINVAL;
375 }
376
377 static void sil_host_intr(struct ata_port *ap, u32 bmdma2)
378 {
379 struct ata_eh_info *ehi = &ap->link.eh_info;
380 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
381 u8 status;
382
383 if (unlikely(bmdma2 & SIL_DMA_SATA_IRQ)) {
384 u32 serror;
385
386 /* SIEN doesn't mask SATA IRQs on some 3112s. Those
387 * controllers continue to assert IRQ as long as
388 * SError bits are pending. Clear SError immediately.
389 */
390 sil_scr_read(ap, SCR_ERROR, &serror);
391 sil_scr_write(ap, SCR_ERROR, serror);
392
393 /* Sometimes spurious interrupts occur, double check
394 * it's PHYRDY CHG.
395 */
396 if (serror & SERR_PHYRDY_CHG) {
397 ap->link.eh_info.serror |= serror;
398 goto freeze;
399 }
400
401 if (!(bmdma2 & SIL_DMA_COMPLETE))
402 return;
403 }
404
405 if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) {
406 /* this sometimes happens, just clear IRQ */
407 ata_chk_status(ap);
408 return;
409 }
410
411 /* Check whether we are expecting interrupt in this state */
412 switch (ap->hsm_task_state) {
413 case HSM_ST_FIRST:
414 /* Some pre-ATAPI-4 devices assert INTRQ
415 * at this state when ready to receive CDB.
416 */
417
418 /* Check the ATA_DFLAG_CDB_INTR flag is enough here.
419 * The flag was turned on only for atapi devices.
420 * No need to check is_atapi_taskfile(&qc->tf) again.
421 */
422 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
423 goto err_hsm;
424 break;
425 case HSM_ST_LAST:
426 if (qc->tf.protocol == ATA_PROT_DMA ||
427 qc->tf.protocol == ATA_PROT_ATAPI_DMA) {
428 /* clear DMA-Start bit */
429 ap->ops->bmdma_stop(qc);
430
431 if (bmdma2 & SIL_DMA_ERROR) {
432 qc->err_mask |= AC_ERR_HOST_BUS;
433 ap->hsm_task_state = HSM_ST_ERR;
434 }
435 }
436 break;
437 case HSM_ST:
438 break;
439 default:
440 goto err_hsm;
441 }
442
443 /* check main status, clearing INTRQ */
444 status = ata_chk_status(ap);
445 if (unlikely(status & ATA_BUSY))
446 goto err_hsm;
447
448 /* ack bmdma irq events */
449 ata_bmdma_irq_clear(ap);
450
451 /* kick HSM in the ass */
452 ata_hsm_move(ap, qc, status, 0);
453
454 if (unlikely(qc->err_mask) && (qc->tf.protocol == ATA_PROT_DMA ||
455 qc->tf.protocol == ATA_PROT_ATAPI_DMA))
456 ata_ehi_push_desc(ehi, "BMDMA2 stat 0x%x", bmdma2);
457
458 return;
459
460 err_hsm:
461 qc->err_mask |= AC_ERR_HSM;
462 freeze:
463 ata_port_freeze(ap);
464 }
465
466 static irqreturn_t sil_interrupt(int irq, void *dev_instance)
467 {
468 struct ata_host *host = dev_instance;
469 void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR];
470 int handled = 0;
471 int i;
472
473 spin_lock(&host->lock);
474
475 for (i = 0; i < host->n_ports; i++) {
476 struct ata_port *ap = host->ports[i];
477 u32 bmdma2 = readl(mmio_base + sil_port[ap->port_no].bmdma2);
478
479 if (unlikely(!ap || ap->flags & ATA_FLAG_DISABLED))
480 continue;
481
482 /* turn off SATA_IRQ if not supported */
483 if (ap->flags & SIL_FLAG_NO_SATA_IRQ)
484 bmdma2 &= ~SIL_DMA_SATA_IRQ;
485
486 if (bmdma2 == 0xffffffff ||
487 !(bmdma2 & (SIL_DMA_COMPLETE | SIL_DMA_SATA_IRQ)))
488 continue;
489
490 sil_host_intr(ap, bmdma2);
491 handled = 1;
492 }
493
494 spin_unlock(&host->lock);
495
496 return IRQ_RETVAL(handled);
497 }
498
499 static void sil_freeze(struct ata_port *ap)
500 {
501 void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR];
502 u32 tmp;
503
504 /* global IRQ mask doesn't block SATA IRQ, turn off explicitly */
505 writel(0, mmio_base + sil_port[ap->port_no].sien);
506
507 /* plug IRQ */
508 tmp = readl(mmio_base + SIL_SYSCFG);
509 tmp |= SIL_MASK_IDE0_INT << ap->port_no;
510 writel(tmp, mmio_base + SIL_SYSCFG);
511 readl(mmio_base + SIL_SYSCFG); /* flush */
512 }
513
514 static void sil_thaw(struct ata_port *ap)
515 {
516 void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR];
517 u32 tmp;
518
519 /* clear IRQ */
520 ata_chk_status(ap);
521 ata_bmdma_irq_clear(ap);
522
523 /* turn on SATA IRQ if supported */
524 if (!(ap->flags & SIL_FLAG_NO_SATA_IRQ))
525 writel(SIL_SIEN_N, mmio_base + sil_port[ap->port_no].sien);
526
527 /* turn on IRQ */
528 tmp = readl(mmio_base + SIL_SYSCFG);
529 tmp &= ~(SIL_MASK_IDE0_INT << ap->port_no);
530 writel(tmp, mmio_base + SIL_SYSCFG);
531 }
532
533 /**
534 * sil_dev_config - Apply device/host-specific errata fixups
535 * @dev: Device to be examined
536 *
537 * After the IDENTIFY [PACKET] DEVICE step is complete, and a
538 * device is known to be present, this function is called.
539 * We apply two errata fixups which are specific to Silicon Image,
540 * a Seagate and a Maxtor fixup.
541 *
542 * For certain Seagate devices, we must limit the maximum sectors
543 * to under 8K.
544 *
545 * For certain Maxtor devices, we must not program the drive
546 * beyond udma5.
547 *
548 * Both fixups are unfairly pessimistic. As soon as I get more
549 * information on these errata, I will create a more exhaustive
550 * list, and apply the fixups to only the specific
551 * devices/hosts/firmwares that need it.
552 *
553 * 20040111 - Seagate drives affected by the Mod15Write bug are blacklisted
554 * The Maxtor quirk is in the blacklist, but I'm keeping the original
555 * pessimistic fix for the following reasons...
556 * - There seems to be less info on it, only one device gleaned off the
557 * Windows driver, maybe only one is affected. More info would be greatly
558 * appreciated.
559 * - But then again UDMA5 is hardly anything to complain about
560 */
561 static void sil_dev_config(struct ata_device *dev)
562 {
563 struct ata_port *ap = dev->link->ap;
564 int print_info = ap->link.eh_context.i.flags & ATA_EHI_PRINTINFO;
565 unsigned int n, quirks = 0;
566 unsigned char model_num[ATA_ID_PROD_LEN + 1];
567
568 ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
569
570 for (n = 0; sil_blacklist[n].product; n++)
571 if (!strcmp(sil_blacklist[n].product, model_num)) {
572 quirks = sil_blacklist[n].quirk;
573 break;
574 }
575
576 /* limit requests to 15 sectors */
577 if (slow_down ||
578 ((ap->flags & SIL_FLAG_MOD15WRITE) &&
579 (quirks & SIL_QUIRK_MOD15WRITE))) {
580 if (print_info)
581 ata_dev_printk(dev, KERN_INFO, "applying Seagate "
582 "errata fix (mod15write workaround)\n");
583 dev->max_sectors = 15;
584 return;
585 }
586
587 /* limit to udma5 */
588 if (quirks & SIL_QUIRK_UDMA5MAX) {
589 if (print_info)
590 ata_dev_printk(dev, KERN_INFO, "applying Maxtor "
591 "errata fix %s\n", model_num);
592 dev->udma_mask &= ATA_UDMA5;
593 return;
594 }
595 }
596
597 static void sil_init_controller(struct ata_host *host)
598 {
599 struct pci_dev *pdev = to_pci_dev(host->dev);
600 void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR];
601 u8 cls;
602 u32 tmp;
603 int i;
604
605 /* Initialize FIFO PCI bus arbitration */
606 cls = sil_get_device_cache_line(pdev);
607 if (cls) {
608 cls >>= 3;
609 cls++; /* cls = (line_size/8)+1 */
610 for (i = 0; i < host->n_ports; i++)
611 writew(cls << 8 | cls,
612 mmio_base + sil_port[i].fifo_cfg);
613 } else
614 dev_printk(KERN_WARNING, &pdev->dev,
615 "cache line size not set. Driver may not function\n");
616
617 /* Apply R_ERR on DMA activate FIS errata workaround */
618 if (host->ports[0]->flags & SIL_FLAG_RERR_ON_DMA_ACT) {
619 int cnt;
620
621 for (i = 0, cnt = 0; i < host->n_ports; i++) {
622 tmp = readl(mmio_base + sil_port[i].sfis_cfg);
623 if ((tmp & 0x3) != 0x01)
624 continue;
625 if (!cnt)
626 dev_printk(KERN_INFO, &pdev->dev,
627 "Applying R_ERR on DMA activate "
628 "FIS errata fix\n");
629 writel(tmp & ~0x3, mmio_base + sil_port[i].sfis_cfg);
630 cnt++;
631 }
632 }
633
634 if (host->n_ports == 4) {
635 /* flip the magic "make 4 ports work" bit */
636 tmp = readl(mmio_base + sil_port[2].bmdma);
637 if ((tmp & SIL_INTR_STEERING) == 0)
638 writel(tmp | SIL_INTR_STEERING,
639 mmio_base + sil_port[2].bmdma);
640 }
641 }
642
643 static int sil_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
644 {
645 static int printed_version;
646 int board_id = ent->driver_data;
647 const struct ata_port_info *ppi[] = { &sil_port_info[board_id], NULL };
648 struct ata_host *host;
649 void __iomem *mmio_base;
650 int n_ports, rc;
651 unsigned int i;
652
653 if (!printed_version++)
654 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
655
656 /* allocate host */
657 n_ports = 2;
658 if (board_id == sil_3114)
659 n_ports = 4;
660
661 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
662 if (!host)
663 return -ENOMEM;
664
665 /* acquire resources and fill host */
666 rc = pcim_enable_device(pdev);
667 if (rc)
668 return rc;
669
670 rc = pcim_iomap_regions(pdev, 1 << SIL_MMIO_BAR, DRV_NAME);
671 if (rc == -EBUSY)
672 pcim_pin_device(pdev);
673 if (rc)
674 return rc;
675 host->iomap = pcim_iomap_table(pdev);
676
677 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
678 if (rc)
679 return rc;
680 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
681 if (rc)
682 return rc;
683
684 mmio_base = host->iomap[SIL_MMIO_BAR];
685
686 for (i = 0; i < host->n_ports; i++) {
687 struct ata_port *ap = host->ports[i];
688 struct ata_ioports *ioaddr = &ap->ioaddr;
689
690 ioaddr->cmd_addr = mmio_base + sil_port[i].tf;
691 ioaddr->altstatus_addr =
692 ioaddr->ctl_addr = mmio_base + sil_port[i].ctl;
693 ioaddr->bmdma_addr = mmio_base + sil_port[i].bmdma;
694 ioaddr->scr_addr = mmio_base + sil_port[i].scr;
695 ata_std_ports(ioaddr);
696
697 ata_port_pbar_desc(ap, SIL_MMIO_BAR, -1, "mmio");
698 ata_port_pbar_desc(ap, SIL_MMIO_BAR, sil_port[i].tf, "tf");
699 }
700
701 /* initialize and activate */
702 sil_init_controller(host);
703
704 pci_set_master(pdev);
705 return ata_host_activate(host, pdev->irq, sil_interrupt, IRQF_SHARED,
706 &sil_sht);
707 }
708
709 #ifdef CONFIG_PM
710 static int sil_pci_device_resume(struct pci_dev *pdev)
711 {
712 struct ata_host *host = dev_get_drvdata(&pdev->dev);
713 int rc;
714
715 rc = ata_pci_device_do_resume(pdev);
716 if (rc)
717 return rc;
718
719 sil_init_controller(host);
720 ata_host_resume(host);
721
722 return 0;
723 }
724 #endif
725
726 static int __init sil_init(void)
727 {
728 return pci_register_driver(&sil_pci_driver);
729 }
730
731 static void __exit sil_exit(void)
732 {
733 pci_unregister_driver(&sil_pci_driver);
734 }
735
736
737 module_init(sil_init);
738 module_exit(sil_exit);
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