| blob | 100052aaea9aa9831a3bc0ed8ff1aa37dd74fbd5 |
1 /*
2 * PowerPC version
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 *
5 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
7 * Adapted for Power Macintosh by Paul Mackerras.
8 * Low-level exception handlers and MMU support
9 * rewritten by Paul Mackerras.
10 * Copyright (C) 1996 Paul Mackerras.
11 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
12 * Amiga/APUS changes by Jesper Skov (jskov@cygnus.co.uk).
13 *
14 * This file contains the low-level support and setup for the
15 * PowerPC platform, including trap and interrupt dispatch.
16 * (The PPC 8xx embedded CPUs use head_8xx.S instead.)
17 *
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License
20 * as published by the Free Software Foundation; either version
21 * 2 of the License, or (at your option) any later version.
22 *
23 */
25 #include <asm/processor.h>
26 #include <asm/page.h>
27 #include <asm/mmu.h>
28 #include <asm/pgtable.h>
29 #include <asm/cputable.h>
30 #include <asm/cache.h>
31 #include <asm/thread_info.h>
32 #include <asm/ppc_asm.h>
33 #include <asm/asm-offsets.h>
35 #ifdef CONFIG_APUS
36 #include <asm/amigappc.h>
37 #endif
39 /* 601 only have IBAT; cr0.eq is set on 601 when using this macro */
40 #define LOAD_BAT(n, reg, RA, RB) \
41 /* see the comment for clear_bats() -- Cort */ \
42 li RA,0; \
43 mtspr SPRN_IBAT##n##U,RA; \
44 mtspr SPRN_DBAT##n##U,RA; \
45 lwz RA,(n*16)+0(reg); \
46 lwz RB,(n*16)+4(reg); \
47 mtspr SPRN_IBAT##n##U,RA; \
48 mtspr SPRN_IBAT##n##L,RB; \
49 beq 1f; \
50 lwz RA,(n*16)+8(reg); \
51 lwz RB,(n*16)+12(reg); \
52 mtspr SPRN_DBAT##n##U,RA; \
53 mtspr SPRN_DBAT##n##L,RB; \
54 1:
56 .text
57 .stabs "arch/ppc/kernel/",N_SO,0,0,0f
58 .stabs "head.S",N_SO,0,0,0f
59 0:
60 .globl _stext
61 _stext:
63 /*
64 * _start is defined this way because the XCOFF loader in the OpenFirmware
65 * on the powermac expects the entry point to be a procedure descriptor.
66 */
67 .text
68 .globl _start
69 _start:
70 /*
71 * These are here for legacy reasons, the kernel used to
72 * need to look like a coff function entry for the pmac
73 * but we're always started by some kind of bootloader now.
74 * -- Cort
75 */
76 nop /* used by __secondary_hold on prep (mtx) and chrp smp */
77 nop /* used by __secondary_hold on prep (mtx) and chrp smp */
78 nop
80 /* PMAC
81 * Enter here with the kernel text, data and bss loaded starting at
82 * 0, running with virtual == physical mapping.
83 * r5 points to the prom entry point (the client interface handler
84 * address). Address translation is turned on, with the prom
85 * managing the hash table. Interrupts are disabled. The stack
86 * pointer (r1) points to just below the end of the half-meg region
87 * from 0x380000 - 0x400000, which is mapped in already.
88 *
89 * If we are booted from MacOS via BootX, we enter with the kernel
90 * image loaded somewhere, and the following values in registers:
91 * r3: 'BooX' (0x426f6f58)
92 * r4: virtual address of boot_infos_t
93 * r5: 0
94 *
95 * APUS
96 * r3: 'APUS'
97 * r4: physical address of memory base
98 * Linux/m68k style BootInfo structure at &_end.
99 *
100 * PREP
101 * This is jumped to on prep systems right after the kernel is relocated
102 * to its proper place in memory by the boot loader. The expected layout
103 * of the regs is:
104 * r3: ptr to residual data
105 * r4: initrd_start or if no initrd then 0
106 * r5: initrd_end - unused if r4 is 0
107 * r6: Start of command line string
108 * r7: End of command line string
109 *
110 * This just gets a minimal mmu environment setup so we can call
111 * start_here() to do the real work.
112 * -- Cort
113 */
115 .globl __start
116 __start:
117 mr r31,r3 /* save parameters */
118 mr r30,r4
119 mr r29,r5
120 mr r28,r6
121 mr r27,r7
122 li r24,0 /* cpu # */
124 /*
125 * early_init() does the early machine identification and does
126 * the necessary low-level setup and clears the BSS
127 * -- Cort <cort@fsmlabs.com>
128 */
129 bl early_init
131 #ifdef CONFIG_APUS
132 /* On APUS the __va/__pa constants need to be set to the correct
133 * values before continuing.
134 */
135 mr r4,r30
136 bl fix_mem_constants
137 #endif /* CONFIG_APUS */
139 /* Switch MMU off, clear BATs and flush TLB. At this point, r3 contains
140 * the physical address we are running at, returned by early_init()
141 */
142 bl mmu_off
143 __after_mmu_off:
144 bl clear_bats
145 bl flush_tlbs
147 bl initial_bats
148 #if !defined(CONFIG_APUS) && defined(CONFIG_BOOTX_TEXT)
149 bl setup_disp_bat
150 #endif
152 /*
153 * Call setup_cpu for CPU 0 and initialize 6xx Idle
154 */
155 bl reloc_offset
156 li r24,0 /* cpu# */
157 bl call_setup_cpu /* Call setup_cpu for this CPU */
158 #ifdef CONFIG_6xx
159 bl reloc_offset
160 bl init_idle_6xx
161 #endif /* CONFIG_6xx */
164 #ifndef CONFIG_APUS
165 /*
166 * We need to run with _start at physical address 0.
167 * If the MMU is already turned on, we copy stuff to KERNELBASE,
168 * otherwise we copy it to 0.
169 */
170 bl reloc_offset
171 mr r26,r3
172 addis r4,r3,KERNELBASE@h /* current address of _start */
173 cmpwi 0,r4,0 /* are we already running at 0? */
174 bne relocate_kernel
175 #endif /* CONFIG_APUS */
176 /*
177 * we now have the 1st 16M of ram mapped with the bats.
178 * prep needs the mmu to be turned on here, but pmac already has it on.
179 * this shouldn't bother the pmac since it just gets turned on again
180 * as we jump to our code at KERNELBASE. -- Cort
181 * Actually no, pmac doesn't have it on any more. BootX enters with MMU
182 * off, and in other cases, we now turn it off before changing BATs above.
183 */
184 turn_on_mmu:
185 mfmsr r0
186 ori r0,r0,MSR_DR|MSR_IR
187 mtspr SPRN_SRR1,r0
188 lis r0,start_here@h
189 ori r0,r0,start_here@l
190 mtspr SPRN_SRR0,r0
191 SYNC
192 RFI /* enables MMU */
194 /*
195 * We need __secondary_hold as a place to hold the other cpus on
196 * an SMP machine, even when we are running a UP kernel.
197 */
198 . = 0xc0 /* for prep bootloader */
199 li r3,1 /* MTX only has 1 cpu */
200 .globl __secondary_hold
201 __secondary_hold:
202 /* tell the master we're here */
203 stw r3,4(0)
204 #ifdef CONFIG_SMP
205 100: lwz r4,0(0)
206 /* wait until we're told to start */
207 cmpw 0,r4,r3
208 bne 100b
209 /* our cpu # was at addr 0 - go */
210 mr r24,r3 /* cpu # */
211 b __secondary_start
212 #else
213 b .
214 #endif /* CONFIG_SMP */
216 /*
217 * Exception entry code. This code runs with address translation
218 * turned off, i.e. using physical addresses.
219 * We assume sprg3 has the physical address of the current
220 * task's thread_struct.
221 */
222 #define EXCEPTION_PROLOG \
223 mtspr SPRN_SPRG0,r10; \
224 mtspr SPRN_SPRG1,r11; \
225 mfcr r10; \
226 EXCEPTION_PROLOG_1; \
227 EXCEPTION_PROLOG_2
229 #define EXCEPTION_PROLOG_1 \
230 mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \
231 andi. r11,r11,MSR_PR; \
232 tophys(r11,r1); /* use tophys(r1) if kernel */ \
233 beq 1f; \
234 mfspr r11,SPRN_SPRG3; \
235 lwz r11,THREAD_INFO-THREAD(r11); \
236 addi r11,r11,THREAD_SIZE; \
237 tophys(r11,r11); \
238 1: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */
241 #define EXCEPTION_PROLOG_2 \
242 CLR_TOP32(r11); \
243 stw r10,_CCR(r11); /* save registers */ \
244 stw r12,GPR12(r11); \
245 stw r9,GPR9(r11); \
246 mfspr r10,SPRN_SPRG0; \
247 stw r10,GPR10(r11); \
248 mfspr r12,SPRN_SPRG1; \
249 stw r12,GPR11(r11); \
250 mflr r10; \
251 stw r10,_LINK(r11); \
252 mfspr r12,SPRN_SRR0; \
253 mfspr r9,SPRN_SRR1; \
254 stw r1,GPR1(r11); \
255 stw r1,0(r11); \
256 tovirt(r1,r11); /* set new kernel sp */ \
257 li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \
258 MTMSRD(r10); /* (except for mach check in rtas) */ \
259 stw r0,GPR0(r11); \
260 SAVE_4GPRS(3, r11); \
261 SAVE_2GPRS(7, r11)
263 /*
264 * Note: code which follows this uses cr0.eq (set if from kernel),
265 * r11, r12 (SRR0), and r9 (SRR1).
266 *
267 * Note2: once we have set r1 we are in a position to take exceptions
268 * again, and we could thus set MSR:RI at that point.
269 */
271 /*
272 * Exception vectors.
273 */
274 #define EXCEPTION(n, label, hdlr, xfer) \
275 . = n; \
276 label: \
277 EXCEPTION_PROLOG; \
278 addi r3,r1,STACK_FRAME_OVERHEAD; \
279 xfer(n, hdlr)
281 #define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \
282 li r10,trap; \
283 stw r10,TRAP(r11); \
284 li r10,MSR_KERNEL; \
285 copyee(r10, r9); \
286 bl tfer; \
287 i##n: \
288 .long hdlr; \
289 .long ret
291 #define COPY_EE(d, s) rlwimi d,s,0,16,16
292 #define NOCOPY(d, s)
294 #define EXC_XFER_STD(n, hdlr) \
295 EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \
296 ret_from_except_full)
298 #define EXC_XFER_LITE(n, hdlr) \
299 EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \
300 ret_from_except)
302 #define EXC_XFER_EE(n, hdlr) \
303 EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \
304 ret_from_except_full)
306 #define EXC_XFER_EE_LITE(n, hdlr) \
307 EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \
308 ret_from_except)
310 /* System reset */
311 /* core99 pmac starts the seconary here by changing the vector, and
312 putting it back to what it was (unknown_exception) when done. */
313 #if defined(CONFIG_GEMINI) && defined(CONFIG_SMP)
314 . = 0x100
315 b __secondary_start_gemini
316 #else
317 EXCEPTION(0x100, Reset, unknown_exception, EXC_XFER_STD)
318 #endif
320 /* Machine check */
321 . = 0x200
322 mtspr SPRN_SPRG0,r10
323 mtspr SPRN_SPRG1,r11
324 mfcr r10
325 EXCEPTION_PROLOG_1
326 7: EXCEPTION_PROLOG_2
327 addi r3,r1,STACK_FRAME_OVERHEAD
328 EXC_XFER_STD(0x200, machine_check_exception)
330 /* Data access exception. */
331 . = 0x300
332 DataAccess:
333 EXCEPTION_PROLOG
334 mfspr r10,SPRN_DSISR
335 andis. r0,r10,0xa470 /* weird error? */
336 bne 1f /* if not, try to put a PTE */
337 mfspr r4,SPRN_DAR /* into the hash table */
338 rlwinm r3,r10,32-15,21,21 /* DSISR_STORE -> _PAGE_RW */
339 bl hash_page
340 1: stw r10,_DSISR(r11)
341 mr r5,r10
342 mfspr r4,SPRN_DAR
343 EXC_XFER_EE_LITE(0x300, handle_page_fault)
345 /* Instruction access exception. */
346 . = 0x400
347 InstructionAccess:
348 EXCEPTION_PROLOG
349 andis. r0,r9,0x4000 /* no pte found? */
350 beq 1f /* if so, try to put a PTE */
351 li r3,0 /* into the hash table */
352 mr r4,r12 /* SRR0 is fault address */
353 bl hash_page
354 1: mr r4,r12
355 mr r5,r9
356 EXC_XFER_EE_LITE(0x400, handle_page_fault)
358 /* External interrupt */
359 EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
361 /* Alignment exception */
362 . = 0x600
363 Alignment:
364 EXCEPTION_PROLOG
365 mfspr r4,SPRN_DAR
366 stw r4,_DAR(r11)
367 mfspr r5,SPRN_DSISR
368 stw r5,_DSISR(r11)
369 addi r3,r1,STACK_FRAME_OVERHEAD
370 EXC_XFER_EE(0x600, alignment_exception)
372 /* Program check exception */
373 EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD)
375 /* Floating-point unavailable */
376 . = 0x800
377 FPUnavailable:
378 EXCEPTION_PROLOG
379 bne load_up_fpu /* if from user, just load it up */
380 addi r3,r1,STACK_FRAME_OVERHEAD
381 EXC_XFER_EE_LITE(0x800, kernel_fp_unavailable_exception)
383 /* Decrementer */
384 EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE)
386 EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_EE)
387 EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_EE)
389 /* System call */
390 . = 0xc00
391 SystemCall:
392 EXCEPTION_PROLOG
393 EXC_XFER_EE_LITE(0xc00, DoSyscall)
395 /* Single step - not used on 601 */
396 EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD)
397 EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_EE)
399 /*
400 * The Altivec unavailable trap is at 0x0f20. Foo.
401 * We effectively remap it to 0x3000.
402 * We include an altivec unavailable exception vector even if
403 * not configured for Altivec, so that you can't panic a
404 * non-altivec kernel running on a machine with altivec just
405 * by executing an altivec instruction.
406 */
407 . = 0xf00
408 b Trap_0f
410 . = 0xf20
411 b AltiVecUnavailable
413 Trap_0f:
414 EXCEPTION_PROLOG
415 addi r3,r1,STACK_FRAME_OVERHEAD
416 EXC_XFER_EE(0xf00, unknown_exception)
418 /*
419 * Handle TLB miss for instruction on 603/603e.
420 * Note: we get an alternate set of r0 - r3 to use automatically.
421 */
422 . = 0x1000
423 InstructionTLBMiss:
424 /*
425 * r0: stored ctr
426 * r1: linux style pte ( later becomes ppc hardware pte )
427 * r2: ptr to linux-style pte
428 * r3: scratch
429 */
430 mfctr r0
431 /* Get PTE (linux-style) and check access */
432 mfspr r3,SPRN_IMISS
433 lis r1,KERNELBASE@h /* check if kernel address */
434 cmplw 0,r3,r1
435 mfspr r2,SPRN_SPRG3
436 li r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */
437 lwz r2,PGDIR(r2)
438 blt+ 112f
439 lis r2,swapper_pg_dir@ha /* if kernel address, use */
440 addi r2,r2,swapper_pg_dir@l /* kernel page table */
441 mfspr r1,SPRN_SRR1 /* and MSR_PR bit from SRR1 */
442 rlwinm r1,r1,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
443 112: tophys(r2,r2)
444 rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
445 lwz r2,0(r2) /* get pmd entry */
446 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
447 beq- InstructionAddressInvalid /* return if no mapping */
448 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
449 lwz r3,0(r2) /* get linux-style pte */
450 andc. r1,r1,r3 /* check access & ~permission */
451 bne- InstructionAddressInvalid /* return if access not permitted */
452 ori r3,r3,_PAGE_ACCESSED /* set _PAGE_ACCESSED in pte */
453 /*
454 * NOTE! We are assuming this is not an SMP system, otherwise
455 * we would need to update the pte atomically with lwarx/stwcx.
456 */
457 stw r3,0(r2) /* update PTE (accessed bit) */
458 /* Convert linux-style PTE to low word of PPC-style PTE */
459 rlwinm r1,r3,32-10,31,31 /* _PAGE_RW -> PP lsb */
460 rlwinm r2,r3,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */
461 and r1,r1,r2 /* writable if _RW and _DIRTY */
462 rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */
463 rlwimi r3,r3,32-1,31,31 /* _PAGE_USER -> PP lsb */
464 ori r1,r1,0xe14 /* clear out reserved bits and M */
465 andc r1,r3,r1 /* PP = user? (rw&dirty? 2: 3): 0 */
466 mtspr SPRN_RPA,r1
467 mfspr r3,SPRN_IMISS
468 tlbli r3
469 mfspr r3,SPRN_SRR1 /* Need to restore CR0 */
470 mtcrf 0x80,r3
471 rfi
472 InstructionAddressInvalid:
473 mfspr r3,SPRN_SRR1
474 rlwinm r1,r3,9,6,6 /* Get load/store bit */
476 addis r1,r1,0x2000
477 mtspr SPRN_DSISR,r1 /* (shouldn't be needed) */
478 mtctr r0 /* Restore CTR */
479 andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */
480 or r2,r2,r1
481 mtspr SPRN_SRR1,r2
482 mfspr r1,SPRN_IMISS /* Get failing address */
483 rlwinm. r2,r2,0,31,31 /* Check for little endian access */
484 rlwimi r2,r2,1,30,30 /* change 1 -> 3 */
485 xor r1,r1,r2
486 mtspr SPRN_DAR,r1 /* Set fault address */
487 mfmsr r0 /* Restore "normal" registers */
488 xoris r0,r0,MSR_TGPR>>16
489 mtcrf 0x80,r3 /* Restore CR0 */
490 mtmsr r0
491 b InstructionAccess
493 /*
494 * Handle TLB miss for DATA Load operation on 603/603e
495 */
496 . = 0x1100
497 DataLoadTLBMiss:
498 /*
499 * r0: stored ctr
500 * r1: linux style pte ( later becomes ppc hardware pte )
501 * r2: ptr to linux-style pte
502 * r3: scratch
503 */
504 mfctr r0
505 /* Get PTE (linux-style) and check access */
506 mfspr r3,SPRN_DMISS
507 lis r1,KERNELBASE@h /* check if kernel address */
508 cmplw 0,r3,r1
509 mfspr r2,SPRN_SPRG3
510 li r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */
511 lwz r2,PGDIR(r2)
512 blt+ 112f
513 lis r2,swapper_pg_dir@ha /* if kernel address, use */
514 addi r2,r2,swapper_pg_dir@l /* kernel page table */
515 mfspr r1,SPRN_SRR1 /* and MSR_PR bit from SRR1 */
516 rlwinm r1,r1,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
517 112: tophys(r2,r2)
518 rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
519 lwz r2,0(r2) /* get pmd entry */
520 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
521 beq- DataAddressInvalid /* return if no mapping */
522 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
523 lwz r3,0(r2) /* get linux-style pte */
524 andc. r1,r1,r3 /* check access & ~permission */
525 bne- DataAddressInvalid /* return if access not permitted */
526 ori r3,r3,_PAGE_ACCESSED /* set _PAGE_ACCESSED in pte */
527 /*
528 * NOTE! We are assuming this is not an SMP system, otherwise
529 * we would need to update the pte atomically with lwarx/stwcx.
530 */
531 stw r3,0(r2) /* update PTE (accessed bit) */
532 /* Convert linux-style PTE to low word of PPC-style PTE */
533 rlwinm r1,r3,32-10,31,31 /* _PAGE_RW -> PP lsb */
534 rlwinm r2,r3,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */
535 and r1,r1,r2 /* writable if _RW and _DIRTY */
536 rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */
537 rlwimi r3,r3,32-1,31,31 /* _PAGE_USER -> PP lsb */
538 ori r1,r1,0xe14 /* clear out reserved bits and M */
539 andc r1,r3,r1 /* PP = user? (rw&dirty? 2: 3): 0 */
540 mtspr SPRN_RPA,r1
541 mfspr r3,SPRN_DMISS
542 tlbld r3
543 mfspr r3,SPRN_SRR1 /* Need to restore CR0 */
544 mtcrf 0x80,r3
545 rfi
546 DataAddressInvalid:
547 mfspr r3,SPRN_SRR1
548 rlwinm r1,r3,9,6,6 /* Get load/store bit */
549 addis r1,r1,0x2000
550 mtspr SPRN_DSISR,r1
551 mtctr r0 /* Restore CTR */
552 andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */
553 mtspr SPRN_SRR1,r2
554 mfspr r1,SPRN_DMISS /* Get failing address */
555 rlwinm. r2,r2,0,31,31 /* Check for little endian access */
556 beq 20f /* Jump if big endian */
557 xori r1,r1,3
558 20: mtspr SPRN_DAR,r1 /* Set fault address */
559 mfmsr r0 /* Restore "normal" registers */
560 xoris r0,r0,MSR_TGPR>>16
561 mtcrf 0x80,r3 /* Restore CR0 */
562 mtmsr r0
563 b DataAccess
565 /*
566 * Handle TLB miss for DATA Store on 603/603e
567 */
568 . = 0x1200
569 DataStoreTLBMiss:
570 /*
571 * r0: stored ctr
572 * r1: linux style pte ( later becomes ppc hardware pte )
573 * r2: ptr to linux-style pte
574 * r3: scratch
575 */
576 mfctr r0
577 /* Get PTE (linux-style) and check access */
578 mfspr r3,SPRN_DMISS
579 lis r1,KERNELBASE@h /* check if kernel address */
580 cmplw 0,r3,r1
581 mfspr r2,SPRN_SPRG3
582 li r1,_PAGE_RW|_PAGE_USER|_PAGE_PRESENT /* access flags */
583 lwz r2,PGDIR(r2)
584 blt+ 112f
585 lis r2,swapper_pg_dir@ha /* if kernel address, use */
586 addi r2,r2,swapper_pg_dir@l /* kernel page table */
587 mfspr r1,SPRN_SRR1 /* and MSR_PR bit from SRR1 */
588 rlwinm r1,r1,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
589 112: tophys(r2,r2)
590 rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
591 lwz r2,0(r2) /* get pmd entry */
592 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
593 beq- DataAddressInvalid /* return if no mapping */
594 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
595 lwz r3,0(r2) /* get linux-style pte */
596 andc. r1,r1,r3 /* check access & ~permission */
597 bne- DataAddressInvalid /* return if access not permitted */
598 ori r3,r3,_PAGE_ACCESSED|_PAGE_DIRTY
599 /*
600 * NOTE! We are assuming this is not an SMP system, otherwise
601 * we would need to update the pte atomically with lwarx/stwcx.
602 */
603 stw r3,0(r2) /* update PTE (accessed/dirty bits) */
604 /* Convert linux-style PTE to low word of PPC-style PTE */
605 rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */
606 li r1,0xe15 /* clear out reserved bits and M */
607 andc r1,r3,r1 /* PP = user? 2: 0 */
608 mtspr SPRN_RPA,r1
609 mfspr r3,SPRN_DMISS
610 tlbld r3
611 mfspr r3,SPRN_SRR1 /* Need to restore CR0 */
612 mtcrf 0x80,r3
613 rfi
615 #ifndef CONFIG_ALTIVEC
616 #define altivec_assist_exception unknown_exception
617 #endif
619 EXCEPTION(0x1300, Trap_13, instruction_breakpoint_exception, EXC_XFER_EE)
620 EXCEPTION(0x1400, SMI, SMIException, EXC_XFER_EE)
621 EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE)
622 EXCEPTION(0x1600, Trap_16, altivec_assist_exception, EXC_XFER_EE)
623 EXCEPTION(0x1700, Trap_17, TAUException, EXC_XFER_STD)
624 EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE)
625 EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE)
626 EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_EE)
627 EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_EE)
628 EXCEPTION(0x1c00, Trap_1c, unknown_exception, EXC_XFER_EE)
629 EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE)
630 EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE)
631 EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE)
632 EXCEPTION(0x2000, RunMode, RunModeException, EXC_XFER_EE)
633 EXCEPTION(0x2100, Trap_21, unknown_exception, EXC_XFER_EE)
634 EXCEPTION(0x2200, Trap_22, unknown_exception, EXC_XFER_EE)
635 EXCEPTION(0x2300, Trap_23, unknown_exception, EXC_XFER_EE)
636 EXCEPTION(0x2400, Trap_24, unknown_exception, EXC_XFER_EE)
637 EXCEPTION(0x2500, Trap_25, unknown_exception, EXC_XFER_EE)
638 EXCEPTION(0x2600, Trap_26, unknown_exception, EXC_XFER_EE)
639 EXCEPTION(0x2700, Trap_27, unknown_exception, EXC_XFER_EE)
640 EXCEPTION(0x2800, Trap_28, unknown_exception, EXC_XFER_EE)
641 EXCEPTION(0x2900, Trap_29, unknown_exception, EXC_XFER_EE)
642 EXCEPTION(0x2a00, Trap_2a, unknown_exception, EXC_XFER_EE)
643 EXCEPTION(0x2b00, Trap_2b, unknown_exception, EXC_XFER_EE)
644 EXCEPTION(0x2c00, Trap_2c, unknown_exception, EXC_XFER_EE)
645 EXCEPTION(0x2d00, Trap_2d, unknown_exception, EXC_XFER_EE)
646 EXCEPTION(0x2e00, Trap_2e, unknown_exception, EXC_XFER_EE)
647 EXCEPTION(0x2f00, MOLTrampoline, unknown_exception, EXC_XFER_EE_LITE)
649 .globl mol_trampoline
650 .set mol_trampoline, i0x2f00
652 . = 0x3000
654 AltiVecUnavailable:
655 EXCEPTION_PROLOG
656 #ifdef CONFIG_ALTIVEC
657 bne load_up_altivec /* if from user, just load it up */
658 #endif /* CONFIG_ALTIVEC */
659 addi r3,r1,STACK_FRAME_OVERHEAD
660 EXC_XFER_EE_LITE(0xf20, altivec_unavailable_exception)
662 #ifdef CONFIG_ALTIVEC
663 /* Note that the AltiVec support is closely modeled after the FP
664 * support. Changes to one are likely to be applicable to the
665 * other! */
666 load_up_altivec:
667 /*
668 * Disable AltiVec for the task which had AltiVec previously,
669 * and save its AltiVec registers in its thread_struct.
670 * Enables AltiVec for use in the kernel on return.
671 * On SMP we know the AltiVec units are free, since we give it up every
672 * switch. -- Kumar
673 */
674 mfmsr r5
675 oris r5,r5,MSR_VEC@h
676 MTMSRD(r5) /* enable use of AltiVec now */
677 isync
678 /*
679 * For SMP, we don't do lazy AltiVec switching because it just gets too
680 * horrendously complex, especially when a task switches from one CPU
681 * to another. Instead we call giveup_altivec in switch_to.
682 */
683 #ifndef CONFIG_SMP
684 tophys(r6,0)
685 addis r3,r6,last_task_used_altivec@ha
686 lwz r4,last_task_used_altivec@l(r3)
687 cmpwi 0,r4,0
688 beq 1f
689 add r4,r4,r6
690 addi r4,r4,THREAD /* want THREAD of last_task_used_altivec */
691 SAVE_32VRS(0,r10,r4)
692 mfvscr vr0
693 li r10,THREAD_VSCR
694 stvx vr0,r10,r4
695 lwz r5,PT_REGS(r4)
696 add r5,r5,r6
697 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
698 lis r10,MSR_VEC@h
699 andc r4,r4,r10 /* disable altivec for previous task */
700 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
701 1:
702 #endif /* CONFIG_SMP */
703 /* enable use of AltiVec after return */
704 oris r9,r9,MSR_VEC@h
705 mfspr r5,SPRN_SPRG3 /* current task's THREAD (phys) */
706 li r4,1
707 li r10,THREAD_VSCR
708 stw r4,THREAD_USED_VR(r5)
709 lvx vr0,r10,r5
710 mtvscr vr0
711 REST_32VRS(0,r10,r5)
712 #ifndef CONFIG_SMP
713 subi r4,r5,THREAD
714 sub r4,r4,r6
715 stw r4,last_task_used_altivec@l(r3)
716 #endif /* CONFIG_SMP */
717 /* restore registers and return */
718 /* we haven't used ctr or xer or lr */
719 b fast_exception_return
721 /*
722 * AltiVec unavailable trap from kernel - print a message, but let
723 * the task use AltiVec in the kernel until it returns to user mode.
724 */
725 KernelAltiVec:
726 lwz r3,_MSR(r1)
727 oris r3,r3,MSR_VEC@h
728 stw r3,_MSR(r1) /* enable use of AltiVec after return */
729 lis r3,87f@h
730 ori r3,r3,87f@l
731 mr r4,r2 /* current */
732 lwz r5,_NIP(r1)
733 bl printk
734 b ret_from_except
735 87: .string "AltiVec used in kernel (task=%p, pc=%x) \n"
736 .align 4,0
738 /*
739 * giveup_altivec(tsk)
740 * Disable AltiVec for the task given as the argument,
741 * and save the AltiVec registers in its thread_struct.
742 * Enables AltiVec for use in the kernel on return.
743 */
745 .globl giveup_altivec
746 giveup_altivec:
747 mfmsr r5
748 oris r5,r5,MSR_VEC@h
749 SYNC
750 MTMSRD(r5) /* enable use of AltiVec now */
751 isync
752 cmpwi 0,r3,0
753 beqlr- /* if no previous owner, done */
754 addi r3,r3,THREAD /* want THREAD of task */
755 lwz r5,PT_REGS(r3)
756 cmpwi 0,r5,0
757 SAVE_32VRS(0, r4, r3)
758 mfvscr vr0
759 li r4,THREAD_VSCR
760 stvx vr0,r4,r3
761 beq 1f
762 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
763 lis r3,MSR_VEC@h
764 andc r4,r4,r3 /* disable AltiVec for previous task */
765 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
766 1:
767 #ifndef CONFIG_SMP
768 li r5,0
769 lis r4,last_task_used_altivec@ha
770 stw r5,last_task_used_altivec@l(r4)
771 #endif /* CONFIG_SMP */
772 blr
773 #endif /* CONFIG_ALTIVEC */
775 /*
776 * This code is jumped to from the startup code to copy
777 * the kernel image to physical address 0.
778 */
779 relocate_kernel:
780 addis r9,r26,klimit@ha /* fetch klimit */
781 lwz r25,klimit@l(r9)
782 addis r25,r25,-KERNELBASE@h
783 li r3,0 /* Destination base address */
784 li r6,0 /* Destination offset */
785 li r5,0x4000 /* # bytes of memory to copy */
786 bl copy_and_flush /* copy the first 0x4000 bytes */
787 addi r0,r3,4f@l /* jump to the address of 4f */
788 mtctr r0 /* in copy and do the rest. */
789 bctr /* jump to the copy */
790 4: mr r5,r25
791 bl copy_and_flush /* copy the rest */
792 b turn_on_mmu
794 /*
795 * Copy routine used to copy the kernel to start at physical address 0
796 * and flush and invalidate the caches as needed.
797 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
798 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
799 */
800 copy_and_flush:
801 addi r5,r5,-4
802 addi r6,r6,-4
803 4: li r0,L1_CACHE_BYTES/4
804 mtctr r0
805 3: addi r6,r6,4 /* copy a cache line */
806 lwzx r0,r6,r4
807 stwx r0,r6,r3
808 bdnz 3b
809 dcbst r6,r3 /* write it to memory */
810 sync
811 icbi r6,r3 /* flush the icache line */
812 cmplw 0,r6,r5
813 blt 4b
814 sync /* additional sync needed on g4 */
815 isync
816 addi r5,r5,4
817 addi r6,r6,4
818 blr
820 #ifdef CONFIG_APUS
821 /*
822 * On APUS the physical base address of the kernel is not known at compile
823 * time, which means the __pa/__va constants used are incorrect. In the
824 * __init section is recorded the virtual addresses of instructions using
825 * these constants, so all that has to be done is fix these before
826 * continuing the kernel boot.
827 *
828 * r4 = The physical address of the kernel base.
829 */
830 fix_mem_constants:
831 mr r10,r4
832 addis r10,r10,-KERNELBASE@h /* virt_to_phys constant */
833 neg r11,r10 /* phys_to_virt constant */
835 lis r12,__vtop_table_begin@h
836 ori r12,r12,__vtop_table_begin@l
837 add r12,r12,r10 /* table begin phys address */
838 lis r13,__vtop_table_end@h
839 ori r13,r13,__vtop_table_end@l
840 add r13,r13,r10 /* table end phys address */
841 subi r12,r12,4
842 subi r13,r13,4
843 1: lwzu r14,4(r12) /* virt address of instruction */
844 add r14,r14,r10 /* phys address of instruction */
845 lwz r15,0(r14) /* instruction, now insert top */
846 rlwimi r15,r10,16,16,31 /* half of vp const in low half */
847 stw r15,0(r14) /* of instruction and restore. */
848 dcbst r0,r14 /* write it to memory */
849 sync
850 icbi r0,r14 /* flush the icache line */
851 cmpw r12,r13
852 bne 1b
853 sync /* additional sync needed on g4 */
854 isync
856 /*
857 * Map the memory where the exception handlers will
858 * be copied to when hash constants have been patched.
859 */
860 #ifdef CONFIG_APUS_FAST_EXCEPT
861 lis r8,0xfff0
862 #else
863 lis r8,0
864 #endif
865 ori r8,r8,0x2 /* 128KB, supervisor */
866 mtspr SPRN_DBAT3U,r8
867 mtspr SPRN_DBAT3L,r8
869 lis r12,__ptov_table_begin@h
870 ori r12,r12,__ptov_table_begin@l
871 add r12,r12,r10 /* table begin phys address */
872 lis r13,__ptov_table_end@h
873 ori r13,r13,__ptov_table_end@l
874 add r13,r13,r10 /* table end phys address */
875 subi r12,r12,4
876 subi r13,r13,4
877 1: lwzu r14,4(r12) /* virt address of instruction */
878 add r14,r14,r10 /* phys address of instruction */
879 lwz r15,0(r14) /* instruction, now insert top */
880 rlwimi r15,r11,16,16,31 /* half of pv const in low half*/
881 stw r15,0(r14) /* of instruction and restore. */
882 dcbst r0,r14 /* write it to memory */
883 sync
884 icbi r0,r14 /* flush the icache line */
885 cmpw r12,r13
886 bne 1b
888 sync /* additional sync needed on g4 */
889 isync /* No speculative loading until now */
890 blr
892 /***********************************************************************
893 * Please note that on APUS the exception handlers are located at the
894 * physical address 0xfff0000. For this reason, the exception handlers
895 * cannot use relative branches to access the code below.
896 ***********************************************************************/
897 #endif /* CONFIG_APUS */
899 #ifdef CONFIG_SMP
900 #ifdef CONFIG_GEMINI
901 .globl __secondary_start_gemini
902 __secondary_start_gemini:
903 mfspr r4,SPRN_HID0
904 ori r4,r4,HID0_ICFI
905 li r3,0
906 ori r3,r3,HID0_ICE
907 andc r4,r4,r3
908 mtspr SPRN_HID0,r4
909 sync
910 b __secondary_start
911 #endif /* CONFIG_GEMINI */
913 .globl __secondary_start_pmac_0
914 __secondary_start_pmac_0:
915 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
916 li r24,0
917 b 1f
918 li r24,1
919 b 1f
920 li r24,2
921 b 1f
922 li r24,3
923 1:
924 /* on powersurge, we come in here with IR=0 and DR=1, and DBAT 0
925 set to map the 0xf0000000 - 0xffffffff region */
926 mfmsr r0
927 rlwinm r0,r0,0,28,26 /* clear DR (0x10) */
928 SYNC
929 mtmsr r0
930 isync
932 .globl __secondary_start
933 __secondary_start:
934 /* Copy some CPU settings from CPU 0 */
935 bl __restore_cpu_setup
937 lis r3,-KERNELBASE@h
938 mr r4,r24
939 bl call_setup_cpu /* Call setup_cpu for this CPU */
940 #ifdef CONFIG_6xx
941 lis r3,-KERNELBASE@h
942 bl init_idle_6xx
943 #endif /* CONFIG_6xx */
945 /* get current_thread_info and current */
946 lis r1,secondary_ti@ha
947 tophys(r1,r1)
948 lwz r1,secondary_ti@l(r1)
949 tophys(r2,r1)
950 lwz r2,TI_TASK(r2)
952 /* stack */
953 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
954 li r0,0
955 tophys(r3,r1)
956 stw r0,0(r3)
958 /* load up the MMU */
959 bl load_up_mmu
961 /* ptr to phys current thread */
962 tophys(r4,r2)
963 addi r4,r4,THREAD /* phys address of our thread_struct */
964 CLR_TOP32(r4)
965 mtspr SPRN_SPRG3,r4
966 li r3,0
967 mtspr SPRN_SPRG2,r3 /* 0 => not in RTAS */
969 /* enable MMU and jump to start_secondary */
970 li r4,MSR_KERNEL
971 FIX_SRR1(r4,r5)
972 lis r3,start_secondary@h
973 ori r3,r3,start_secondary@l
974 mtspr SPRN_SRR0,r3
975 mtspr SPRN_SRR1,r4
976 SYNC
977 RFI
978 #endif /* CONFIG_SMP */
980 /*
981 * Those generic dummy functions are kept for CPUs not
982 * included in CONFIG_6xx
983 */
984 #if !defined(CONFIG_6xx)
985 _GLOBAL(__save_cpu_setup)
986 blr
987 _GLOBAL(__restore_cpu_setup)
988 blr
989 #endif /* !defined(CONFIG_6xx) */
992 /*
993 * Load stuff into the MMU. Intended to be called with
994 * IR=0 and DR=0.
995 */
996 load_up_mmu:
997 sync /* Force all PTE updates to finish */
998 isync
999 tlbia /* Clear all TLB entries */
1000 sync /* wait for tlbia/tlbie to finish */
1001 TLBSYNC /* ... on all CPUs */
1002 /* Load the SDR1 register (hash table base & size) */
1003 lis r6,_SDR1@ha
1004 tophys(r6,r6)
1005 lwz r6,_SDR1@l(r6)
1006 mtspr SPRN_SDR1,r6
1007 li r0,16 /* load up segment register values */
1008 mtctr r0 /* for context 0 */
1009 lis r3,0x2000 /* Ku = 1, VSID = 0 */
1010 li r4,0
1011 3: mtsrin r3,r4
1012 addi r3,r3,0x111 /* increment VSID */
1013 addis r4,r4,0x1000 /* address of next segment */
1014 bdnz 3b
1016 /* Load the BAT registers with the values set up by MMU_init.
1017 MMU_init takes care of whether we're on a 601 or not. */
1018 mfpvr r3
1019 srwi r3,r3,16
1020 cmpwi r3,1
1021 lis r3,BATS@ha
1022 addi r3,r3,BATS@l
1023 tophys(r3,r3)
1024 LOAD_BAT(0,r3,r4,r5)
1025 LOAD_BAT(1,r3,r4,r5)
1026 LOAD_BAT(2,r3,r4,r5)
1027 LOAD_BAT(3,r3,r4,r5)
1029 blr
1031 /*
1032 * This is where the main kernel code starts.
1033 */
1034 start_here:
1035 /* ptr to current */
1036 lis r2,init_task@h
1037 ori r2,r2,init_task@l
1038 /* Set up for using our exception vectors */
1039 /* ptr to phys current thread */
1040 tophys(r4,r2)
1041 addi r4,r4,THREAD /* init task's THREAD */
1042 CLR_TOP32(r4)
1043 mtspr SPRN_SPRG3,r4
1044 li r3,0
1045 mtspr SPRN_SPRG2,r3 /* 0 => not in RTAS */
1047 /* stack */
1048 lis r1,init_thread_union@ha
1049 addi r1,r1,init_thread_union@l
1050 li r0,0
1051 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
1052 /*
1053 * Do early bootinfo parsing, platform-specific initialization,
1054 * and set up the MMU.
1055 */
1056 mr r3,r31
1057 mr r4,r30
1058 mr r5,r29
1059 mr r6,r28
1060 mr r7,r27
1061 bl machine_init
1062 bl MMU_init
1064 #ifdef CONFIG_APUS
1065 /* Copy exception code to exception vector base on APUS. */
1066 lis r4,KERNELBASE@h
1067 #ifdef CONFIG_APUS_FAST_EXCEPT
1068 lis r3,0xfff0 /* Copy to 0xfff00000 */
1069 #else
1070 lis r3,0 /* Copy to 0x00000000 */
1071 #endif
1072 li r5,0x4000 /* # bytes of memory to copy */
1073 li r6,0
1074 bl copy_and_flush /* copy the first 0x4000 bytes */
1075 #endif /* CONFIG_APUS */
1077 /*
1078 * Go back to running unmapped so we can load up new values
1079 * for SDR1 (hash table pointer) and the segment registers
1080 * and change to using our exception vectors.
1081 */
1082 lis r4,2f@h
1083 ori r4,r4,2f@l
1084 tophys(r4,r4)
1085 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR)
1086 FIX_SRR1(r3,r5)
1087 mtspr SPRN_SRR0,r4
1088 mtspr SPRN_SRR1,r3
1089 SYNC
1090 RFI
1091 /* Load up the kernel context */
1092 2: bl load_up_mmu
1094 #ifdef CONFIG_BDI_SWITCH
1095 /* Add helper information for the Abatron bdiGDB debugger.
1096 * We do this here because we know the mmu is disabled, and
1097 * will be enabled for real in just a few instructions.
1098 */
1099 lis r5, abatron_pteptrs@h
1100 ori r5, r5, abatron_pteptrs@l
1101 stw r5, 0xf0(r0) /* This much match your Abatron config */
1102 lis r6, swapper_pg_dir@h
1103 ori r6, r6, swapper_pg_dir@l
1104 tophys(r5, r5)
1105 stw r6, 0(r5)
1106 #endif /* CONFIG_BDI_SWITCH */
1108 /* Now turn on the MMU for real! */
1109 li r4,MSR_KERNEL
1110 FIX_SRR1(r4,r5)
1111 lis r3,start_kernel@h
1112 ori r3,r3,start_kernel@l
1113 mtspr SPRN_SRR0,r3
1114 mtspr SPRN_SRR1,r4
1115 SYNC
1116 RFI
1118 /*
1119 * Set up the segment registers for a new context.
1120 */
1121 _GLOBAL(set_context)
1122 mulli r3,r3,897 /* multiply context by skew factor */
1123 rlwinm r3,r3,4,8,27 /* VSID = (context & 0xfffff) << 4 */
1124 addis r3,r3,0x6000 /* Set Ks, Ku bits */
1125 li r0,NUM_USER_SEGMENTS
1126 mtctr r0
1128 #ifdef CONFIG_BDI_SWITCH
1129 /* Context switch the PTE pointer for the Abatron BDI2000.
1130 * The PGDIR is passed as second argument.
1131 */
1132 lis r5, KERNELBASE@h
1133 lwz r5, 0xf0(r5)
1134 stw r4, 0x4(r5)
1135 #endif
1136 li r4,0
1137 isync
1138 3:
1139 mtsrin r3,r4
1140 addi r3,r3,0x111 /* next VSID */
1141 rlwinm r3,r3,0,8,3 /* clear out any overflow from VSID field */
1142 addis r4,r4,0x1000 /* address of next segment */
1143 bdnz 3b
1144 sync
1145 isync
1146 blr
1148 /*
1149 * An undocumented "feature" of 604e requires that the v bit
1150 * be cleared before changing BAT values.
1151 *
1152 * Also, newer IBM firmware does not clear bat3 and 4 so
1153 * this makes sure it's done.
1154 * -- Cort
1155 */
1156 clear_bats:
1157 li r10,0
1158 mfspr r9,SPRN_PVR
1159 rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */
1160 cmpwi r9, 1
1161 beq 1f
1163 mtspr SPRN_DBAT0U,r10
1164 mtspr SPRN_DBAT0L,r10
1165 mtspr SPRN_DBAT1U,r10
1166 mtspr SPRN_DBAT1L,r10
1167 mtspr SPRN_DBAT2U,r10
1168 mtspr SPRN_DBAT2L,r10
1169 mtspr SPRN_DBAT3U,r10
1170 mtspr SPRN_DBAT3L,r10
1171 1:
1172 mtspr SPRN_IBAT0U,r10
1173 mtspr SPRN_IBAT0L,r10
1174 mtspr SPRN_IBAT1U,r10
1175 mtspr SPRN_IBAT1L,r10
1176 mtspr SPRN_IBAT2U,r10
1177 mtspr SPRN_IBAT2L,r10
1178 mtspr SPRN_IBAT3U,r10
1179 mtspr SPRN_IBAT3L,r10
1180 BEGIN_FTR_SECTION
1181 /* Here's a tweak: at this point, CPU setup have
1182 * not been called yet, so HIGH_BAT_EN may not be
1183 * set in HID0 for the 745x processors. However, it
1184 * seems that doesn't affect our ability to actually
1185 * write to these SPRs.
1186 */
1187 mtspr SPRN_DBAT4U,r10
1188 mtspr SPRN_DBAT4L,r10
1189 mtspr SPRN_DBAT5U,r10
1190 mtspr SPRN_DBAT5L,r10
1191 mtspr SPRN_DBAT6U,r10
1192 mtspr SPRN_DBAT6L,r10
1193 mtspr SPRN_DBAT7U,r10
1194 mtspr SPRN_DBAT7L,r10
1195 mtspr SPRN_IBAT4U,r10
1196 mtspr SPRN_IBAT4L,r10
1197 mtspr SPRN_IBAT5U,r10
1198 mtspr SPRN_IBAT5L,r10
1199 mtspr SPRN_IBAT6U,r10
1200 mtspr SPRN_IBAT6L,r10
1201 mtspr SPRN_IBAT7U,r10
1202 mtspr SPRN_IBAT7L,r10
1203 END_FTR_SECTION_IFSET(CPU_FTR_HAS_HIGH_BATS)
1204 blr
1206 flush_tlbs:
1207 lis r10, 0x40
1208 1: addic. r10, r10, -0x1000
1209 tlbie r10
1210 blt 1b
1211 sync
1212 blr
1214 mmu_off:
1215 addi r4, r3, __after_mmu_off - _start
1216 mfmsr r3
1217 andi. r0,r3,MSR_DR|MSR_IR /* MMU enabled? */
1218 beqlr
1219 andc r3,r3,r0
1220 mtspr SPRN_SRR0,r4
1221 mtspr SPRN_SRR1,r3
1222 sync
1223 RFI
1225 /*
1226 * Use the first pair of BAT registers to map the 1st 16MB
1227 * of RAM to KERNELBASE. From this point on we can't safely
1228 * call OF any more.
1229 */
1230 initial_bats:
1231 lis r11,KERNELBASE@h
1232 mfspr r9,SPRN_PVR
1233 rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */
1234 cmpwi 0,r9,1
1235 bne 4f
1236 ori r11,r11,4 /* set up BAT registers for 601 */
1237 li r8,0x7f /* valid, block length = 8MB */
1238 oris r9,r11,0x800000@h /* set up BAT reg for 2nd 8M */
1239 oris r10,r8,0x800000@h /* set up BAT reg for 2nd 8M */
1240 mtspr SPRN_IBAT0U,r11 /* N.B. 601 has valid bit in */
1241 mtspr SPRN_IBAT0L,r8 /* lower BAT register */
1242 mtspr SPRN_IBAT1U,r9
1243 mtspr SPRN_IBAT1L,r10
1244 isync
1245 blr
1247 4: tophys(r8,r11)
1248 #ifdef CONFIG_SMP
1249 ori r8,r8,0x12 /* R/W access, M=1 */
1250 #else
1251 ori r8,r8,2 /* R/W access */
1252 #endif /* CONFIG_SMP */
1253 #ifdef CONFIG_APUS
1254 ori r11,r11,BL_8M<<2|0x2 /* set up 8MB BAT registers for 604 */
1255 #else
1256 ori r11,r11,BL_256M<<2|0x2 /* set up BAT registers for 604 */
1257 #endif /* CONFIG_APUS */
1259 mtspr SPRN_DBAT0L,r8 /* N.B. 6xx (not 601) have valid */
1260 mtspr SPRN_DBAT0U,r11 /* bit in upper BAT register */
1261 mtspr SPRN_IBAT0L,r8
1262 mtspr SPRN_IBAT0U,r11
1263 isync
1264 blr
1266 #if !defined(CONFIG_APUS) && defined(CONFIG_BOOTX_TEXT)
1267 setup_disp_bat:
1268 /*
1269 * setup the display bat prepared for us in prom.c
1270 */
1271 mflr r8
1272 bl reloc_offset
1273 mtlr r8
1274 addis r8,r3,disp_BAT@ha
1275 addi r8,r8,disp_BAT@l
1276 lwz r11,0(r8)
1277 lwz r8,4(r8)
1278 mfspr r9,SPRN_PVR
1279 rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */
1280 cmpwi 0,r9,1
1281 beq 1f
1282 mtspr SPRN_DBAT3L,r8
1283 mtspr SPRN_DBAT3U,r11
1284 blr
1285 1: mtspr SPRN_IBAT3L,r8
1286 mtspr SPRN_IBAT3U,r11
1287 blr
1289 #endif /* !defined(CONFIG_APUS) && defined(CONFIG_BOOTX_TEXT) */
1291 #ifdef CONFIG_8260
1292 /* Jump into the system reset for the rom.
1293 * We first disable the MMU, and then jump to the ROM reset address.
1294 *
1295 * r3 is the board info structure, r4 is the location for starting.
1296 * I use this for building a small kernel that can load other kernels,
1297 * rather than trying to write or rely on a rom monitor that can tftp load.
1298 */
1299 .globl m8260_gorom
1300 m8260_gorom:
1301 mfmsr r0
1302 rlwinm r0,r0,0,17,15 /* clear MSR_EE in r0 */
1303 sync
1304 mtmsr r0
1305 sync
1306 mfspr r11, SPRN_HID0
1307 lis r10, 0
1308 ori r10,r10,HID0_ICE|HID0_DCE
1309 andc r11, r11, r10
1310 mtspr SPRN_HID0, r11
1311 isync
1312 li r5, MSR_ME|MSR_RI
1313 lis r6,2f@h
1314 addis r6,r6,-KERNELBASE@h
1315 ori r6,r6,2f@l
1316 mtspr SPRN_SRR0,r6
1317 mtspr SPRN_SRR1,r5
1318 isync
1319 sync
1320 rfi
1321 2:
1322 mtlr r4
1323 blr
1324 #endif
1327 /*
1328 * We put a few things here that have to be page-aligned.
1329 * This stuff goes at the beginning of the data segment,
1330 * which is page-aligned.
1331 */
1332 .data
1333 .globl sdata
1334 sdata:
1335 .globl empty_zero_page
1336 empty_zero_page:
1337 .space 4096
1339 .globl swapper_pg_dir
1340 swapper_pg_dir:
1341 .space 4096
1343 /*
1344 * This space gets a copy of optional info passed to us by the bootstrap
1345 * Used to pass parameters into the kernel like root=/dev/sda1, etc.
1346 */
1347 .globl cmd_line
1348 cmd_line:
1349 .space 512
1351 .globl intercept_table
1352 intercept_table:
1353 .long 0, 0, i0x200, i0x300, i0x400, 0, i0x600, i0x700
1354 .long i0x800, 0, 0, 0, 0, i0xd00, 0, 0
1355 .long 0, 0, 0, i0x1300, 0, 0, 0, 0
1356 .long 0, 0, 0, 0, 0, 0, 0, 0
1357 .long 0, 0, 0, 0, 0, 0, 0, 0
1358 .long 0, 0, 0, 0, 0, 0, 0, 0
1360 /* Room for two PTE pointers, usually the kernel and current user pointers
1361 * to their respective root page table.
1362 */
1363 abatron_pteptrs:
1364 .space 8