drivers/ide/pci/aec62xx.c

   1 /*
   2  * linux/drivers/ide/pci/aec62xx.c              Version 0.27    Sep 16, 2007
   3  *
   4  * Copyright (C) 1999-2002      Andre Hedrick <andre@linux-ide.org>
   5  * Copyright (C) 2007           MontaVista Software, Inc. <source@mvista.com>
   6  *
   7  */
   8
   9 #include <linux/module.h>
  10 #include <linux/types.h>
  11 #include <linux/pci.h>
  12 #include <linux/delay.h>
  13 #include <linux/hdreg.h>
  14 #include <linux/ide.h>
  15 #include <linux/init.h>
  16
  17 #include <asm/io.h>
  18
  19 struct chipset_bus_clock_list_entry {
  20         u8 xfer_speed;
  21         u8 chipset_settings;
  22         u8 ultra_settings;
  23 };
  24
  25 static const struct chipset_bus_clock_list_entry aec6xxx_33_base [] = {
  26         {       XFER_UDMA_6,    0x31,   0x07    },
  27         {       XFER_UDMA_5,    0x31,   0x06    },
  28         {       XFER_UDMA_4,    0x31,   0x05    },
  29         {       XFER_UDMA_3,    0x31,   0x04    },
  30         {       XFER_UDMA_2,    0x31,   0x03    },
  31         {       XFER_UDMA_1,    0x31,   0x02    },
  32         {       XFER_UDMA_0,    0x31,   0x01    },
  33
  34         {       XFER_MW_DMA_2,  0x31,   0x00    },
  35         {       XFER_MW_DMA_1,  0x31,   0x00    },
  36         {       XFER_MW_DMA_0,  0x0a,   0x00    },
  37         {       XFER_PIO_4,     0x31,   0x00    },
  38         {       XFER_PIO_3,     0x33,   0x00    },
  39         {       XFER_PIO_2,     0x08,   0x00    },
  40         {       XFER_PIO_1,     0x0a,   0x00    },
  41         {       XFER_PIO_0,     0x00,   0x00    },
  42         {       0,              0x00,   0x00    }
  43 };
  44
  45 static const struct chipset_bus_clock_list_entry aec6xxx_34_base [] = {
  46         {       XFER_UDMA_6,    0x41,   0x06    },
  47         {       XFER_UDMA_5,    0x41,   0x05    },
  48         {       XFER_UDMA_4,    0x41,   0x04    },
  49         {       XFER_UDMA_3,    0x41,   0x03    },
  50         {       XFER_UDMA_2,    0x41,   0x02    },
  51         {       XFER_UDMA_1,    0x41,   0x01    },
  52         {       XFER_UDMA_0,    0x41,   0x01    },
  53
  54         {       XFER_MW_DMA_2,  0x41,   0x00    },
  55         {       XFER_MW_DMA_1,  0x42,   0x00    },
  56         {       XFER_MW_DMA_0,  0x7a,   0x00    },
  57         {       XFER_PIO_4,     0x41,   0x00    },
  58         {       XFER_PIO_3,     0x43,   0x00    },
  59         {       XFER_PIO_2,     0x78,   0x00    },
  60         {       XFER_PIO_1,     0x7a,   0x00    },
  61         {       XFER_PIO_0,     0x70,   0x00    },
  62         {       0,              0x00,   0x00    }
  63 };
  64
  65 #define BUSCLOCK(D)     \
  66         ((struct chipset_bus_clock_list_entry *) pci_get_drvdata((D)))
  67
  68
  69 /*
  70  * TO DO: active tuning and correction of cards without a bios.
  71  */
  72 static u8 pci_bus_clock_list (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
  73 {
  74         for ( ; chipset_table->xfer_speed ; chipset_table++)
  75                 if (chipset_table->xfer_speed == speed) {
  76                         return chipset_table->chipset_settings;
  77                 }
  78         return chipset_table->chipset_settings;
  79 }
  80
  81 static u8 pci_bus_clock_list_ultra (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
  82 {
  83         for ( ; chipset_table->xfer_speed ; chipset_table++)
  84                 if (chipset_table->xfer_speed == speed) {
  85                         return chipset_table->ultra_settings;
  86                 }
  87         return chipset_table->ultra_settings;
  88 }
  89
  90 static void aec6210_set_mode(ide_drive_t *drive, const u8 speed)
  91 {
  92         ide_hwif_t *hwif        = HWIF(drive);
  93         struct pci_dev *dev     = hwif->pci_dev;
  94         u16 d_conf              = 0;
  95         u8 ultra = 0, ultra_conf = 0;
  96         u8 tmp0 = 0, tmp1 = 0, tmp2 = 0;
  97         unsigned long flags;
  98
  99         local_irq_save(flags);
 100         /* 0x40|(2*drive->dn): Active, 0x41|(2*drive->dn): Recovery */
 101         pci_read_config_word(dev, 0x40|(2*drive->dn), &d_conf);
 102         tmp0 = pci_bus_clock_list(speed, BUSCLOCK(dev));
 103         d_conf = ((tmp0 & 0xf0) << 4) | (tmp0 & 0xf);
 104         pci_write_config_word(dev, 0x40|(2*drive->dn), d_conf);
 105
 106         tmp1 = 0x00;
 107         tmp2 = 0x00;
 108         pci_read_config_byte(dev, 0x54, &ultra);
 109         tmp1 = ((0x00 << (2*drive->dn)) | (ultra & ~(3 << (2*drive->dn))));
 110         ultra_conf = pci_bus_clock_list_ultra(speed, BUSCLOCK(dev));
 111         tmp2 = ((ultra_conf << (2*drive->dn)) | (tmp1 & ~(3 << (2*drive->dn))));
 112         pci_write_config_byte(dev, 0x54, tmp2);
 113         local_irq_restore(flags);
 114 }
 115
 116 static void aec6260_set_mode(ide_drive_t *drive, const u8 speed)
 117 {
 118         ide_hwif_t *hwif        = HWIF(drive);
 119         struct pci_dev *dev     = hwif->pci_dev;
 120         u8 unit         = (drive->select.b.unit & 0x01);
 121         u8 tmp1 = 0, tmp2 = 0;
 122         u8 ultra = 0, drive_conf = 0, ultra_conf = 0;
 123         unsigned long flags;
 124
 125         local_irq_save(flags);
 126         /* high 4-bits: Active, low 4-bits: Recovery */
 127         pci_read_config_byte(dev, 0x40|drive->dn, &drive_conf);
 128         drive_conf = pci_bus_clock_list(speed, BUSCLOCK(dev));
 129         pci_write_config_byte(dev, 0x40|drive->dn, drive_conf);
 130
 131         pci_read_config_byte(dev, (0x44|hwif->channel), &ultra);
 132         tmp1 = ((0x00 << (4*unit)) | (ultra & ~(7 << (4*unit))));
 133         ultra_conf = pci_bus_clock_list_ultra(speed, BUSCLOCK(dev));
 134         tmp2 = ((ultra_conf << (4*unit)) | (tmp1 & ~(7 << (4*unit))));
 135         pci_write_config_byte(dev, (0x44|hwif->channel), tmp2);
 136         local_irq_restore(flags);
 137 }
 138
 139 static void aec_set_pio_mode(ide_drive_t *drive, const u8 pio)
 140 {
 141         drive->hwif->set_dma_mode(drive, pio + XFER_PIO_0);
 142 }
 143
 144 static unsigned int __devinit init_chipset_aec62xx(struct pci_dev *dev, const char *name)
 145 {
 146         int bus_speed = system_bus_clock();
 147
 148         if (bus_speed <= 33)
 149                 pci_set_drvdata(dev, (void *) aec6xxx_33_base);
 150         else
 151                 pci_set_drvdata(dev, (void *) aec6xxx_34_base);
 152
 153         /* These are necessary to get AEC6280 Macintosh cards to work */
 154         if ((dev->device == PCI_DEVICE_ID_ARTOP_ATP865) ||
 155             (dev->device == PCI_DEVICE_ID_ARTOP_ATP865R)) {
 156                 u8 reg49h = 0, reg4ah = 0;
 157                 /* Clear reset and test bits.  */
 158                 pci_read_config_byte(dev, 0x49, &reg49h);
 159                 pci_write_config_byte(dev, 0x49, reg49h & ~0x30);
 160                 /* Enable chip interrupt output.  */
 161                 pci_read_config_byte(dev, 0x4a, &reg4ah);
 162                 pci_write_config_byte(dev, 0x4a, reg4ah & ~0x01);
 163                 /* Enable burst mode. */
 164                 pci_read_config_byte(dev, 0x4a, &reg4ah);
 165                 pci_write_config_byte(dev, 0x4a, reg4ah | 0x80);
 166         }
 167
 168         return dev->irq;
 169 }
 170
 171 static void __devinit init_hwif_aec62xx(ide_hwif_t *hwif)
 172 {
 173         struct pci_dev *dev     = hwif->pci_dev;
 174
 175         hwif->set_pio_mode = &aec_set_pio_mode;
 176
 177         if (dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF)
 178                 hwif->set_dma_mode = &aec6210_set_mode;
 179         else
 180                 hwif->set_dma_mode = &aec6260_set_mode;
 181
 182         if (hwif->dma_base == 0)
 183                 return;
 184
 185         if (dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF)
 186                 return;
 187
 188         if (hwif->cbl != ATA_CBL_PATA40_SHORT) {
 189                 u8 ata66 = 0, mask = hwif->channel ? 0x02 : 0x01;
 190
 191                 pci_read_config_byte(hwif->pci_dev, 0x49, &ata66);
 192
 193                 hwif->cbl = (ata66 & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
 194         }
 195 }
 196
 197 static const struct ide_port_info aec62xx_chipsets[] __devinitdata = {
 198         {       /* 0 */
 199                 .name           = "AEC6210",
 200                 .init_chipset   = init_chipset_aec62xx,
 201                 .init_hwif      = init_hwif_aec62xx,
 202                 .enablebits     = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
 203                 .host_flags     = IDE_HFLAG_SERIALIZE |
 204                                   IDE_HFLAG_NO_ATAPI_DMA |
 205                                   IDE_HFLAG_OFF_BOARD,
 206                 .pio_mask       = ATA_PIO4,
 207                 .mwdma_mask     = ATA_MWDMA2,
 208                 .udma_mask      = ATA_UDMA2,
 209         },{     /* 1 */
 210                 .name           = "AEC6260",
 211                 .init_chipset   = init_chipset_aec62xx,
 212                 .init_hwif      = init_hwif_aec62xx,
 213                 .host_flags     = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_NO_AUTODMA |
 214                                   IDE_HFLAG_OFF_BOARD,
 215                 .pio_mask       = ATA_PIO4,
 216                 .mwdma_mask     = ATA_MWDMA2,
 217                 .udma_mask      = ATA_UDMA4,
 218         },{     /* 2 */
 219                 .name           = "AEC6260R",
 220                 .init_chipset   = init_chipset_aec62xx,
 221                 .init_hwif      = init_hwif_aec62xx,
 222                 .enablebits     = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
 223                 .host_flags     = IDE_HFLAG_NO_ATAPI_DMA,
 224                 .pio_mask       = ATA_PIO4,
 225                 .mwdma_mask     = ATA_MWDMA2,
 226                 .udma_mask      = ATA_UDMA4,
 227         },{     /* 3 */
 228                 .name           = "AEC6280",
 229                 .init_chipset   = init_chipset_aec62xx,
 230                 .init_hwif      = init_hwif_aec62xx,
 231                 .host_flags     = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_OFF_BOARD,
 232                 .pio_mask       = ATA_PIO4,
 233                 .mwdma_mask     = ATA_MWDMA2,
 234                 .udma_mask      = ATA_UDMA5,
 235         },{     /* 4 */
 236                 .name           = "AEC6280R",
 237                 .init_chipset   = init_chipset_aec62xx,
 238                 .init_hwif      = init_hwif_aec62xx,
 239                 .enablebits     = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
 240                 .host_flags     = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_OFF_BOARD,
 241                 .pio_mask       = ATA_PIO4,
 242                 .mwdma_mask     = ATA_MWDMA2,
 243                 .udma_mask      = ATA_UDMA5,
 244         }
 245 };
 246
 247 /**
 248  *      aec62xx_init_one        -       called when a AEC is found
 249  *      @dev: the aec62xx device
 250  *      @id: the matching pci id
 251  *
 252  *      Called when the PCI registration layer (or the IDE initialization)
 253  *      finds a device matching our IDE device tables.
 254  *
 255  *      NOTE: since we're going to modify the 'name' field for AEC-6[26]80[R]
 256  *      chips, pass a local copy of 'struct ide_port_info' down the call chain.
 257  */
 258
 259 static int __devinit aec62xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 260 {
 261         struct ide_port_info d;
 262         u8 idx = id->driver_data;
 263         int err;
 264
 265         err = pci_enable_device(dev);
 266         if (err)
 267                 return err;
 268
 269         d = aec62xx_chipsets[idx];
 270
 271         if (idx == 3 || idx == 4) {
 272                 unsigned long dma_base = pci_resource_start(dev, 4);
 273
 274                 if (inb(dma_base + 2) & 0x10) {
 275                         d.name = (idx == 4) ? "AEC6880R" : "AEC6880";
 276                         d.udma_mask = ATA_UDMA6;
 277                 }
 278         }
 279
 280         err = ide_setup_pci_device(dev, &d);
 281         if (err)
 282                 pci_disable_device(dev);
 283
 284         return err;
 285 }
 286
 287 static const struct pci_device_id aec62xx_pci_tbl[] = {
 288         { PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP850UF), 0 },
 289         { PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP860),   1 },
 290         { PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP860R),  2 },
 291         { PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP865),   3 },
 292         { PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP865R),  4 },
 293         { 0, },
 294 };
 295 MODULE_DEVICE_TABLE(pci, aec62xx_pci_tbl);
 296
 297 static struct pci_driver driver = {
 298         .name           = "AEC62xx_IDE",
 299         .id_table       = aec62xx_pci_tbl,
 300         .probe          = aec62xx_init_one,
 301 };
 302
 303 static int __init aec62xx_ide_init(void)
 304 {
 305         return ide_pci_register_driver(&driver);
 306 }
 307
 308 module_init(aec62xx_ide_init);
 309
 310 MODULE_AUTHOR("Andre Hedrick");
 311 MODULE_DESCRIPTION("PCI driver module for ARTOP AEC62xx IDE");
 312 MODULE_LICENSE("GPL");