drivers/edac/edac_mc.h

   1 /*
   2  * MC kernel module
   3  * (C) 2003 Linux Networx (http://lnxi.com)
   4  * This file may be distributed under the terms of the
   5  * GNU General Public License.
   6  *
   7  * Written by Thayne Harbaugh
   8  * Based on work by Dan Hollis <goemon at anime dot net> and others.
   9  *      http://www.anime.net/~goemon/linux-ecc/
  10  *
  11  * NMI handling support added by
  12  *     Dave Peterson <dsp@llnl.gov> <dave_peterson@pobox.com>
  13  *
  14  * $Id: edac_mc.h,v 1.4.2.10 2005/10/05 00:43:44 dsp_llnl Exp $
  15  *
  16  */
  17
  18 #ifndef _EDAC_MC_H_
  19 #define _EDAC_MC_H_
  20
  21 #include <linux/kernel.h>
  22 #include <linux/types.h>
  23 #include <linux/module.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/smp.h>
  26 #include <linux/pci.h>
  27 #include <linux/time.h>
  28 #include <linux/nmi.h>
  29 #include <linux/rcupdate.h>
  30 #include <linux/completion.h>
  31 #include <linux/kobject.h>
  32 #include <linux/platform_device.h>
  33
  34 #define EDAC_MC_LABEL_LEN       31
  35 #define MC_PROC_NAME_MAX_LEN 7
  36
  37 #if PAGE_SHIFT < 20
  38 #define PAGES_TO_MiB( pages )   ( ( pages ) >> ( 20 - PAGE_SHIFT ) )
  39 #else                           /* PAGE_SHIFT > 20 */
  40 #define PAGES_TO_MiB( pages )   ( ( pages ) << ( PAGE_SHIFT - 20 ) )
  41 #endif
  42
  43 #define edac_printk(level, prefix, fmt, arg...) \
  44         printk(level "EDAC " prefix ": " fmt, ##arg)
  45
  46 #define edac_mc_printk(mci, level, fmt, arg...) \
  47         printk(level "EDAC MC%d: " fmt, mci->mc_idx, ##arg)
  48
  49 #define edac_mc_chipset_printk(mci, level, prefix, fmt, arg...) \
  50         printk(level "EDAC " prefix " MC%d: " fmt, mci->mc_idx, ##arg)
  51
  52 /* prefixes for edac_printk() and edac_mc_printk() */
  53 #define EDAC_MC "MC"
  54 #define EDAC_PCI "PCI"
  55 #define EDAC_DEBUG "DEBUG"
  56
  57 #ifdef CONFIG_EDAC_DEBUG
  58 extern int edac_debug_level;
  59
  60 #define edac_debug_printk(level, fmt, arg...)                            \
  61         do {                                                             \
  62                 if (level <= edac_debug_level)                           \
  63                         edac_printk(KERN_DEBUG, EDAC_DEBUG, fmt, ##arg); \
  64         } while(0)
  65
  66 #define debugf0( ... ) edac_debug_printk(0, __VA_ARGS__ )
  67 #define debugf1( ... ) edac_debug_printk(1, __VA_ARGS__ )
  68 #define debugf2( ... ) edac_debug_printk(2, __VA_ARGS__ )
  69 #define debugf3( ... ) edac_debug_printk(3, __VA_ARGS__ )
  70 #define debugf4( ... ) edac_debug_printk(4, __VA_ARGS__ )
  71
  72 #else  /* !CONFIG_EDAC_DEBUG */
  73
  74 #define debugf0( ... )
  75 #define debugf1( ... )
  76 #define debugf2( ... )
  77 #define debugf3( ... )
  78 #define debugf4( ... )
  79
  80 #endif  /* !CONFIG_EDAC_DEBUG */
  81
  82 #define BIT(x) (1 << (x))
  83
  84 #define PCI_VEND_DEV(vend, dev) PCI_VENDOR_ID_ ## vend, \
  85         PCI_DEVICE_ID_ ## vend ## _ ## dev
  86
  87 #if defined(CONFIG_X86) && defined(CONFIG_PCI)
  88 #define dev_name(dev) pci_name(to_pci_dev(dev))
  89 #else
  90 #define dev_name(dev) to_platform_device(dev)->name
  91 #endif
  92
  93 /* memory devices */
  94 enum dev_type {
  95         DEV_UNKNOWN = 0,
  96         DEV_X1,
  97         DEV_X2,
  98         DEV_X4,
  99         DEV_X8,
 100         DEV_X16,
 101         DEV_X32,                /* Do these parts exist? */
 102         DEV_X64                 /* Do these parts exist? */
 103 };
 104
 105 #define DEV_FLAG_UNKNOWN        BIT(DEV_UNKNOWN)
 106 #define DEV_FLAG_X1             BIT(DEV_X1)
 107 #define DEV_FLAG_X2             BIT(DEV_X2)
 108 #define DEV_FLAG_X4             BIT(DEV_X4)
 109 #define DEV_FLAG_X8             BIT(DEV_X8)
 110 #define DEV_FLAG_X16            BIT(DEV_X16)
 111 #define DEV_FLAG_X32            BIT(DEV_X32)
 112 #define DEV_FLAG_X64            BIT(DEV_X64)
 113
 114 /* memory types */
 115 enum mem_type {
 116         MEM_EMPTY = 0,          /* Empty csrow */
 117         MEM_RESERVED,           /* Reserved csrow type */
 118         MEM_UNKNOWN,            /* Unknown csrow type */
 119         MEM_FPM,                /* Fast page mode */
 120         MEM_EDO,                /* Extended data out */
 121         MEM_BEDO,               /* Burst Extended data out */
 122         MEM_SDR,                /* Single data rate SDRAM */
 123         MEM_RDR,                /* Registered single data rate SDRAM */
 124         MEM_DDR,                /* Double data rate SDRAM */
 125         MEM_RDDR,               /* Registered Double data rate SDRAM */
 126         MEM_RMBS,               /* Rambus DRAM */
 127         MEM_DDR2,               /* DDR2 RAM */
 128         MEM_FB_DDR2,            /* fully buffered DDR2 */
 129 };
 130
 131 #define MEM_FLAG_EMPTY          BIT(MEM_EMPTY)
 132 #define MEM_FLAG_RESERVED       BIT(MEM_RESERVED)
 133 #define MEM_FLAG_UNKNOWN        BIT(MEM_UNKNOWN)
 134 #define MEM_FLAG_FPM            BIT(MEM_FPM)
 135 #define MEM_FLAG_EDO            BIT(MEM_EDO)
 136 #define MEM_FLAG_BEDO           BIT(MEM_BEDO)
 137 #define MEM_FLAG_SDR            BIT(MEM_SDR)
 138 #define MEM_FLAG_RDR            BIT(MEM_RDR)
 139 #define MEM_FLAG_DDR            BIT(MEM_DDR)
 140 #define MEM_FLAG_RDDR           BIT(MEM_RDDR)
 141 #define MEM_FLAG_RMBS           BIT(MEM_RMBS)
 142 #define MEM_FLAG_DDR2           BIT(MEM_DDR2)
 143 #define MEM_FLAG_FB_DDR2        BIT(MEM_FB_DDR2)
 144
 145 /* chipset Error Detection and Correction capabilities and mode */
 146 enum edac_type {
 147         EDAC_UNKNOWN = 0,       /* Unknown if ECC is available */
 148         EDAC_NONE,              /* Doesnt support ECC */
 149         EDAC_RESERVED,          /* Reserved ECC type */
 150         EDAC_PARITY,            /* Detects parity errors */
 151         EDAC_EC,                /* Error Checking - no correction */
 152         EDAC_SECDED,            /* Single bit error correction, Double detection */
 153         EDAC_S2ECD2ED,          /* Chipkill x2 devices - do these exist? */
 154         EDAC_S4ECD4ED,          /* Chipkill x4 devices */
 155         EDAC_S8ECD8ED,          /* Chipkill x8 devices */
 156         EDAC_S16ECD16ED,        /* Chipkill x16 devices */
 157 };
 158
 159 #define EDAC_FLAG_UNKNOWN       BIT(EDAC_UNKNOWN)
 160 #define EDAC_FLAG_NONE          BIT(EDAC_NONE)
 161 #define EDAC_FLAG_PARITY        BIT(EDAC_PARITY)
 162 #define EDAC_FLAG_EC            BIT(EDAC_EC)
 163 #define EDAC_FLAG_SECDED        BIT(EDAC_SECDED)
 164 #define EDAC_FLAG_S2ECD2ED      BIT(EDAC_S2ECD2ED)
 165 #define EDAC_FLAG_S4ECD4ED      BIT(EDAC_S4ECD4ED)
 166 #define EDAC_FLAG_S8ECD8ED      BIT(EDAC_S8ECD8ED)
 167 #define EDAC_FLAG_S16ECD16ED    BIT(EDAC_S16ECD16ED)
 168
 169 /* scrubbing capabilities */
 170 enum scrub_type {
 171         SCRUB_UNKNOWN = 0,      /* Unknown if scrubber is available */
 172         SCRUB_NONE,             /* No scrubber */
 173         SCRUB_SW_PROG,          /* SW progressive (sequential) scrubbing */
 174         SCRUB_SW_SRC,           /* Software scrub only errors */
 175         SCRUB_SW_PROG_SRC,      /* Progressive software scrub from an error */
 176         SCRUB_SW_TUNABLE,       /* Software scrub frequency is tunable */
 177         SCRUB_HW_PROG,          /* HW progressive (sequential) scrubbing */
 178         SCRUB_HW_SRC,           /* Hardware scrub only errors */
 179         SCRUB_HW_PROG_SRC,      /* Progressive hardware scrub from an error */
 180         SCRUB_HW_TUNABLE        /* Hardware scrub frequency is tunable */
 181 };
 182
 183 #define SCRUB_FLAG_SW_PROG      BIT(SCRUB_SW_PROG)
 184 #define SCRUB_FLAG_SW_SRC       BIT(SCRUB_SW_SRC_CORR)
 185 #define SCRUB_FLAG_SW_PROG_SRC  BIT(SCRUB_SW_PROG_SRC_CORR)
 186 #define SCRUB_FLAG_SW_TUN       BIT(SCRUB_SW_SCRUB_TUNABLE)
 187 #define SCRUB_FLAG_HW_PROG      BIT(SCRUB_HW_PROG)
 188 #define SCRUB_FLAG_HW_SRC       BIT(SCRUB_HW_SRC_CORR)
 189 #define SCRUB_FLAG_HW_PROG_SRC  BIT(SCRUB_HW_PROG_SRC_CORR)
 190 #define SCRUB_FLAG_HW_TUN       BIT(SCRUB_HW_TUNABLE)
 191
 192 /* FIXME - should have notify capabilities: NMI, LOG, PROC, etc */
 193
 194 /*
 195  * There are several things to be aware of that aren't at all obvious:
 196  *
 197  *
 198  * SOCKETS, SOCKET SETS, BANKS, ROWS, CHIP-SELECT ROWS, CHANNELS, etc..
 199  *
 200  * These are some of the many terms that are thrown about that don't always
 201  * mean what people think they mean (Inconceivable!).  In the interest of
 202  * creating a common ground for discussion, terms and their definitions
 203  * will be established.
 204  *
 205  * Memory devices:      The individual chip on a memory stick.  These devices
 206  *                      commonly output 4 and 8 bits each.  Grouping several
 207  *                      of these in parallel provides 64 bits which is common
 208  *                      for a memory stick.
 209  *
 210  * Memory Stick:        A printed circuit board that agregates multiple
 211  *                      memory devices in parallel.  This is the atomic
 212  *                      memory component that is purchaseable by Joe consumer
 213  *                      and loaded into a memory socket.
 214  *
 215  * Socket:              A physical connector on the motherboard that accepts
 216  *                      a single memory stick.
 217  *
 218  * Channel:             Set of memory devices on a memory stick that must be
 219  *                      grouped in parallel with one or more additional
 220  *                      channels from other memory sticks.  This parallel
 221  *                      grouping of the output from multiple channels are
 222  *                      necessary for the smallest granularity of memory access.
 223  *                      Some memory controllers are capable of single channel -
 224  *                      which means that memory sticks can be loaded
 225  *                      individually.  Other memory controllers are only
 226  *                      capable of dual channel - which means that memory
 227  *                      sticks must be loaded as pairs (see "socket set").
 228  *
 229  * Chip-select row:     All of the memory devices that are selected together.
 230  *                      for a single, minimum grain of memory access.
 231  *                      This selects all of the parallel memory devices across
 232  *                      all of the parallel channels.  Common chip-select rows
 233  *                      for single channel are 64 bits, for dual channel 128
 234  *                      bits.
 235  *
 236  * Single-Ranked stick: A Single-ranked stick has 1 chip-select row of memmory.
 237  *                      Motherboards commonly drive two chip-select pins to
 238  *                      a memory stick. A single-ranked stick, will occupy
 239  *                      only one of those rows. The other will be unused.
 240  *
 241  * Double-Ranked stick: A double-ranked stick has two chip-select rows which
 242  *                      access different sets of memory devices.  The two
 243  *                      rows cannot be accessed concurrently.
 244  *
 245  * Double-sided stick:  DEPRECATED TERM, see Double-Ranked stick.
 246  *                      A double-sided stick has two chip-select rows which
 247  *                      access different sets of memory devices.  The two
 248  *                      rows cannot be accessed concurrently.  "Double-sided"
 249  *                      is irrespective of the memory devices being mounted
 250  *                      on both sides of the memory stick.
 251  *
 252  * Socket set:          All of the memory sticks that are required for for
 253  *                      a single memory access or all of the memory sticks
 254  *                      spanned by a chip-select row.  A single socket set
 255  *                      has two chip-select rows and if double-sided sticks
 256  *                      are used these will occupy those chip-select rows.
 257  *
 258  * Bank:                This term is avoided because it is unclear when
 259  *                      needing to distinguish between chip-select rows and
 260  *                      socket sets.
 261  *
 262  * Controller pages:
 263  *
 264  * Physical pages:
 265  *
 266  * Virtual pages:
 267  *
 268  *
 269  * STRUCTURE ORGANIZATION AND CHOICES
 270  *
 271  *
 272  *
 273  * PS - I enjoyed writing all that about as much as you enjoyed reading it.
 274  */
 275
 276 struct channel_info {
 277         int chan_idx;           /* channel index */
 278         u32 ce_count;           /* Correctable Errors for this CHANNEL */
 279         char label[EDAC_MC_LABEL_LEN + 1];  /* DIMM label on motherboard */
 280         struct csrow_info *csrow;       /* the parent */
 281 };
 282
 283 struct csrow_info {
 284         unsigned long first_page;       /* first page number in dimm */
 285         unsigned long last_page;        /* last page number in dimm */
 286         unsigned long page_mask;        /* used for interleaving -
 287                                          * 0UL for non intlv
 288                                          */
 289         u32 nr_pages;           /* number of pages in csrow */
 290         u32 grain;              /* granularity of reported error in bytes */
 291         int csrow_idx;          /* the chip-select row */
 292         enum dev_type dtype;    /* memory device type */
 293         u32 ue_count;           /* Uncorrectable Errors for this csrow */
 294         u32 ce_count;           /* Correctable Errors for this csrow */
 295         enum mem_type mtype;    /* memory csrow type */
 296         enum edac_type edac_mode;       /* EDAC mode for this csrow */
 297         struct mem_ctl_info *mci;       /* the parent */
 298
 299         struct kobject kobj;    /* sysfs kobject for this csrow */
 300         struct completion kobj_complete;
 301
 302         /* FIXME the number of CHANNELs might need to become dynamic */
 303         u32 nr_channels;
 304         struct channel_info *channels;
 305 };
 306
 307 struct mem_ctl_info {
 308         struct list_head link;  /* for global list of mem_ctl_info structs */
 309         unsigned long mtype_cap;        /* memory types supported by mc */
 310         unsigned long edac_ctl_cap;     /* Mem controller EDAC capabilities */
 311         unsigned long edac_cap; /* configuration capabilities - this is
 312                                  * closely related to edac_ctl_cap.  The
 313                                  * difference is that the controller may be
 314                                  * capable of s4ecd4ed which would be listed
 315                                  * in edac_ctl_cap, but if channels aren't
 316                                  * capable of s4ecd4ed then the edac_cap would
 317                                  * not have that capability.
 318                                  */
 319         unsigned long scrub_cap;        /* chipset scrub capabilities */
 320         enum scrub_type scrub_mode;     /* current scrub mode */
 321
 322         /* Translates sdram memory scrub rate given in bytes/sec to the
 323            internal representation and configures whatever else needs
 324            to be configured.
 325         */
 326         int (*set_sdram_scrub_rate) (struct mem_ctl_info *mci, u32 *bw);
 327
 328         /* Get the current sdram memory scrub rate from the internal
 329            representation and converts it to the closest matching
 330            bandwith in bytes/sec.
 331         */
 332         int (*get_sdram_scrub_rate) (struct mem_ctl_info *mci, u32 *bw);
 333
 334         /* pointer to edac checking routine */
 335         void (*edac_check) (struct mem_ctl_info * mci);
 336
 337         /*
 338          * Remaps memory pages: controller pages to physical pages.
 339          * For most MC's, this will be NULL.
 340          */
 341         /* FIXME - why not send the phys page to begin with? */
 342         unsigned long (*ctl_page_to_phys) (struct mem_ctl_info * mci,
 343                                         unsigned long page);
 344         int mc_idx;
 345         int nr_csrows;
 346         struct csrow_info *csrows;
 347         /*
 348          * FIXME - what about controllers on other busses? - IDs must be
 349          * unique.  dev pointer should be sufficiently unique, but
 350          * BUS:SLOT.FUNC numbers may not be unique.
 351          */
 352         struct device *dev;
 353         const char *mod_name;
 354         const char *mod_ver;
 355         const char *ctl_name;
 356         char proc_name[MC_PROC_NAME_MAX_LEN + 1];
 357         void *pvt_info;
 358         u32 ue_noinfo_count;    /* Uncorrectable Errors w/o info */
 359         u32 ce_noinfo_count;    /* Correctable Errors w/o info */
 360         u32 ue_count;           /* Total Uncorrectable Errors for this MC */
 361         u32 ce_count;           /* Total Correctable Errors for this MC */
 362         unsigned long start_time;       /* mci load start time (in jiffies) */
 363
 364         /* this stuff is for safe removal of mc devices from global list while
 365          * NMI handlers may be traversing list
 366          */
 367         struct rcu_head rcu;
 368         struct completion complete;
 369
 370         /* edac sysfs device control */
 371         struct kobject edac_mci_kobj;
 372         struct completion kobj_complete;
 373 };
 374
 375 #ifdef CONFIG_PCI
 376
 377 /* write all or some bits in a byte-register*/
 378 static inline void pci_write_bits8(struct pci_dev *pdev, int offset, u8 value,
 379                 u8 mask)
 380 {
 381         if (mask != 0xff) {
 382                 u8 buf;
 383
 384                 pci_read_config_byte(pdev, offset, &buf);
 385                 value &= mask;
 386                 buf &= ~mask;
 387                 value |= buf;
 388         }
 389
 390         pci_write_config_byte(pdev, offset, value);
 391 }
 392
 393 /* write all or some bits in a word-register*/
 394 static inline void pci_write_bits16(struct pci_dev *pdev, int offset,
 395                 u16 value, u16 mask)
 396 {
 397         if (mask != 0xffff) {
 398                 u16 buf;
 399
 400                 pci_read_config_word(pdev, offset, &buf);
 401                 value &= mask;
 402                 buf &= ~mask;
 403                 value |= buf;
 404         }
 405
 406         pci_write_config_word(pdev, offset, value);
 407 }
 408
 409 /* write all or some bits in a dword-register*/
 410 static inline void pci_write_bits32(struct pci_dev *pdev, int offset,
 411                 u32 value, u32 mask)
 412 {
 413         if (mask != 0xffff) {
 414                 u32 buf;
 415
 416                 pci_read_config_dword(pdev, offset, &buf);
 417                 value &= mask;
 418                 buf &= ~mask;
 419                 value |= buf;
 420         }
 421
 422         pci_write_config_dword(pdev, offset, value);
 423 }
 424
 425 #endif /* CONFIG_PCI */
 426
 427 #ifdef CONFIG_EDAC_DEBUG
 428 void edac_mc_dump_channel(struct channel_info *chan);
 429 void edac_mc_dump_mci(struct mem_ctl_info *mci);
 430 void edac_mc_dump_csrow(struct csrow_info *csrow);
 431 #endif  /* CONFIG_EDAC_DEBUG */
 432
 433 extern int edac_mc_add_mc(struct mem_ctl_info *mci,int mc_idx);
 434 extern struct mem_ctl_info * edac_mc_del_mc(struct device *dev);
 435 extern int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci,
 436                                         unsigned long page);
 437 extern void edac_mc_scrub_block(unsigned long page, unsigned long offset,
 438                 u32 size);
 439
 440 /*
 441  * The no info errors are used when error overflows are reported.
 442  * There are a limited number of error logging registers that can
 443  * be exausted.  When all registers are exhausted and an additional
 444  * error occurs then an error overflow register records that an
 445  * error occured and the type of error, but doesn't have any
 446  * further information.  The ce/ue versions make for cleaner
 447  * reporting logic and function interface - reduces conditional
 448  * statement clutter and extra function arguments.
 449  */
 450 extern void edac_mc_handle_ce(struct mem_ctl_info *mci,
 451                 unsigned long page_frame_number, unsigned long offset_in_page,
 452                 unsigned long syndrome, int row, int channel,
 453                 const char *msg);
 454 extern void edac_mc_handle_ce_no_info(struct mem_ctl_info *mci,
 455                 const char *msg);
 456 extern void edac_mc_handle_ue(struct mem_ctl_info *mci,
 457                 unsigned long page_frame_number, unsigned long offset_in_page,
 458                 int row, const char *msg);
 459 extern void edac_mc_handle_ue_no_info(struct mem_ctl_info *mci,
 460                 const char *msg);
 461 extern void edac_mc_handle_fbd_ue(struct mem_ctl_info *mci,
 462                 unsigned int csrow,
 463                 unsigned int channel0,
 464                 unsigned int channel1,
 465                 char *msg);
 466 extern void edac_mc_handle_fbd_ce(struct mem_ctl_info *mci,
 467                 unsigned int csrow,
 468                 unsigned int channel,
 469                 char *msg);
 470
 471 /*
 472  * This kmalloc's and initializes all the structures.
 473  * Can't be used if all structures don't have the same lifetime.
 474  */
 475 extern struct mem_ctl_info *edac_mc_alloc(unsigned sz_pvt, unsigned nr_csrows,
 476                 unsigned nr_chans);
 477
 478 /* Free an mc previously allocated by edac_mc_alloc() */
 479 extern void edac_mc_free(struct mem_ctl_info *mci);
 480
 481 #endif                          /* _EDAC_MC_H_ */