| blob | 8c9c26aa6ae092e130f93a4076025d17a297ab92 |
1 //
2 // assembly portion of the IA64 MCA handling
3 //
4 // Mods by cfleck to integrate into kernel build
5 // 00/03/15 davidm Added various stop bits to get a clean compile
6 //
7 // 00/03/29 cfleck Added code to save INIT handoff state in pt_regs format, switch to temp
8 // kstack, switch modes, jump to C INIT handler
9 //
10 // 02/01/04 J.Hall <jenna.s.hall@intel.com>
11 // Before entering virtual mode code:
12 // 1. Check for TLB CPU error
13 // 2. Restore current thread pointer to kr6
14 // 3. Move stack ptr 16 bytes to conform to C calling convention
15 //
16 // 04/11/12 Russ Anderson <rja@sgi.com>
17 // Added per cpu MCA/INIT stack save areas.
18 //
19 // 12/08/05 Keith Owens <kaos@sgi.com>
20 // Use per cpu MCA/INIT stacks for all data.
21 //
22 #include <linux/threads.h>
24 #include <asm/asmmacro.h>
25 #include <asm/pgtable.h>
26 #include <asm/processor.h>
27 #include <asm/mca_asm.h>
28 #include <asm/mca.h>
30 #include "entry.h"
32 #define GET_IA64_MCA_DATA(reg) \
33 GET_THIS_PADDR(reg, ia64_mca_data) \
34 ;; \
35 ld8 reg=[reg]
37 .global ia64_do_tlb_purge
38 .global ia64_os_mca_dispatch
39 .global ia64_os_init_dispatch_monarch
40 .global ia64_os_init_dispatch_slave
42 .text
43 .align 16
45 //StartMain////////////////////////////////////////////////////////////////////
47 /*
48 * Just the TLB purge part is moved to a separate function
49 * so we can re-use the code for cpu hotplug code as well
50 * Caller should now setup b1, so we can branch once the
51 * tlb flush is complete.
52 */
54 ia64_do_tlb_purge:
55 #define O(member) IA64_CPUINFO_##member##_OFFSET
57 GET_THIS_PADDR(r2, cpu_info) // load phys addr of cpu_info into r2
58 ;;
59 addl r17=O(PTCE_STRIDE),r2
60 addl r2=O(PTCE_BASE),r2
61 ;;
62 ld8 r18=[r2],(O(PTCE_COUNT)-O(PTCE_BASE));; // r18=ptce_base
63 ld4 r19=[r2],4 // r19=ptce_count[0]
64 ld4 r21=[r17],4 // r21=ptce_stride[0]
65 ;;
66 ld4 r20=[r2] // r20=ptce_count[1]
67 ld4 r22=[r17] // r22=ptce_stride[1]
68 mov r24=0
69 ;;
70 adds r20=-1,r20
71 ;;
72 #undef O
74 2:
75 cmp.ltu p6,p7=r24,r19
76 (p7) br.cond.dpnt.few 4f
77 mov ar.lc=r20
78 3:
79 ptc.e r18
80 ;;
81 add r18=r22,r18
82 br.cloop.sptk.few 3b
83 ;;
84 add r18=r21,r18
85 add r24=1,r24
86 ;;
87 br.sptk.few 2b
88 4:
89 srlz.i // srlz.i implies srlz.d
90 ;;
92 // Now purge addresses formerly mapped by TR registers
93 // 1. Purge ITR&DTR for kernel.
94 movl r16=KERNEL_START
95 mov r18=KERNEL_TR_PAGE_SHIFT<<2
96 ;;
97 ptr.i r16, r18
98 ptr.d r16, r18
99 ;;
100 srlz.i
101 ;;
102 srlz.d
103 ;;
104 // 3. Purge ITR for PAL code.
105 GET_THIS_PADDR(r2, ia64_mca_pal_base)
106 ;;
107 ld8 r16=[r2]
108 mov r18=IA64_GRANULE_SHIFT<<2
109 ;;
110 ptr.i r16,r18
111 ;;
112 srlz.i
113 ;;
114 // 4. Purge DTR for stack.
115 mov r16=IA64_KR(CURRENT_STACK)
116 ;;
117 shl r16=r16,IA64_GRANULE_SHIFT
118 movl r19=PAGE_OFFSET
119 ;;
120 add r16=r19,r16
121 mov r18=IA64_GRANULE_SHIFT<<2
122 ;;
123 ptr.d r16,r18
124 ;;
125 srlz.i
126 ;;
127 // Now branch away to caller.
128 br.sptk.many b1
129 ;;
131 //EndMain//////////////////////////////////////////////////////////////////////
133 //StartMain////////////////////////////////////////////////////////////////////
135 ia64_os_mca_dispatch:
136 // Serialize all MCA processing
137 mov r3=1;;
138 LOAD_PHYSICAL(p0,r2,ia64_mca_serialize);;
139 ia64_os_mca_spin:
140 xchg4 r4=[r2],r3;;
141 cmp.ne p6,p0=r4,r0
142 (p6) br ia64_os_mca_spin
144 mov r3=IA64_MCA_CPU_MCA_STACK_OFFSET // use the MCA stack
145 LOAD_PHYSICAL(p0,r2,1f) // return address
146 mov r19=1 // All MCA events are treated as monarch (for now)
147 br.sptk ia64_state_save // save the state that is not in minstate
148 1:
150 GET_IA64_MCA_DATA(r2)
151 // Using MCA stack, struct ia64_sal_os_state, variable proc_state_param
152 ;;
153 add r3=IA64_MCA_CPU_MCA_STACK_OFFSET+MCA_SOS_OFFSET+SOS(PROC_STATE_PARAM), r2
154 ;;
155 ld8 r18=[r3] // Get processor state parameter on existing PALE_CHECK.
156 ;;
157 tbit.nz p6,p7=r18,60
158 (p7) br.spnt done_tlb_purge_and_reload
160 // The following code purges TC and TR entries. Then reload all TC entries.
161 // Purge percpu data TC entries.
162 begin_tlb_purge_and_reload:
163 movl r18=ia64_reload_tr;;
164 LOAD_PHYSICAL(p0,r18,ia64_reload_tr);;
165 mov b1=r18;;
166 br.sptk.many ia64_do_tlb_purge;;
168 ia64_reload_tr:
169 // Finally reload the TR registers.
170 // 1. Reload DTR/ITR registers for kernel.
171 mov r18=KERNEL_TR_PAGE_SHIFT<<2
172 movl r17=KERNEL_START
173 ;;
174 mov cr.itir=r18
175 mov cr.ifa=r17
176 mov r16=IA64_TR_KERNEL
177 mov r19=ip
178 movl r18=PAGE_KERNEL
179 ;;
180 dep r17=0,r19,0, KERNEL_TR_PAGE_SHIFT
181 ;;
182 or r18=r17,r18
183 ;;
184 itr.i itr[r16]=r18
185 ;;
186 itr.d dtr[r16]=r18
187 ;;
188 srlz.i
189 srlz.d
190 ;;
191 // 3. Reload ITR for PAL code.
192 GET_THIS_PADDR(r2, ia64_mca_pal_pte)
193 ;;
194 ld8 r18=[r2] // load PAL PTE
195 ;;
196 GET_THIS_PADDR(r2, ia64_mca_pal_base)
197 ;;
198 ld8 r16=[r2] // load PAL vaddr
199 mov r19=IA64_GRANULE_SHIFT<<2
200 ;;
201 mov cr.itir=r19
202 mov cr.ifa=r16
203 mov r20=IA64_TR_PALCODE
204 ;;
205 itr.i itr[r20]=r18
206 ;;
207 srlz.i
208 ;;
209 // 4. Reload DTR for stack.
210 mov r16=IA64_KR(CURRENT_STACK)
211 ;;
212 shl r16=r16,IA64_GRANULE_SHIFT
213 movl r19=PAGE_OFFSET
214 ;;
215 add r18=r19,r16
216 movl r20=PAGE_KERNEL
217 ;;
218 add r16=r20,r16
219 mov r19=IA64_GRANULE_SHIFT<<2
220 ;;
221 mov cr.itir=r19
222 mov cr.ifa=r18
223 mov r20=IA64_TR_CURRENT_STACK
224 ;;
225 itr.d dtr[r20]=r16
226 ;;
227 srlz.d
229 done_tlb_purge_and_reload:
231 // switch to per cpu MCA stack
232 mov r3=IA64_MCA_CPU_MCA_STACK_OFFSET // use the MCA stack
233 LOAD_PHYSICAL(p0,r2,1f) // return address
234 br.sptk ia64_new_stack
235 1:
237 // everything saved, now we can set the kernel registers
238 mov r3=IA64_MCA_CPU_MCA_STACK_OFFSET // use the MCA stack
239 LOAD_PHYSICAL(p0,r2,1f) // return address
240 br.sptk ia64_set_kernel_registers
241 1:
243 // This must be done in physical mode
244 GET_IA64_MCA_DATA(r2)
245 ;;
246 mov r7=r2
248 // Enter virtual mode from physical mode
249 VIRTUAL_MODE_ENTER(r2, r3, ia64_os_mca_virtual_begin, r4)
251 // This code returns to SAL via SOS r2, in general SAL has no unwind
252 // data. To get a clean termination when backtracing the C MCA/INIT
253 // handler, set a dummy return address of 0 in this routine. That
254 // requires that ia64_os_mca_virtual_begin be a global function.
255 ENTRY(ia64_os_mca_virtual_begin)
256 .prologue
257 .save rp,r0
258 .body
260 mov ar.rsc=3 // set eager mode for C handler
261 mov r2=r7 // see GET_IA64_MCA_DATA above
262 ;;
264 // Call virtual mode handler
265 alloc r14=ar.pfs,0,0,3,0
266 ;;
267 DATA_PA_TO_VA(r2,r7)
268 ;;
269 add out0=IA64_MCA_CPU_MCA_STACK_OFFSET+MCA_PT_REGS_OFFSET, r2
270 add out1=IA64_MCA_CPU_MCA_STACK_OFFSET+MCA_SWITCH_STACK_OFFSET, r2
271 add out2=IA64_MCA_CPU_MCA_STACK_OFFSET+MCA_SOS_OFFSET, r2
272 br.call.sptk.many b0=ia64_mca_handler
274 // Revert back to physical mode before going back to SAL
275 PHYSICAL_MODE_ENTER(r2, r3, ia64_os_mca_virtual_end, r4)
276 ia64_os_mca_virtual_end:
278 END(ia64_os_mca_virtual_begin)
280 // switch back to previous stack
281 alloc r14=ar.pfs,0,0,0,0 // remove the MCA handler frame
282 mov r3=IA64_MCA_CPU_MCA_STACK_OFFSET // use the MCA stack
283 LOAD_PHYSICAL(p0,r2,1f) // return address
284 br.sptk ia64_old_stack
285 1:
287 mov r3=IA64_MCA_CPU_MCA_STACK_OFFSET // use the MCA stack
288 LOAD_PHYSICAL(p0,r2,1f) // return address
289 br.sptk ia64_state_restore // restore the SAL state
290 1:
292 mov b0=r12 // SAL_CHECK return address
294 // release lock
295 LOAD_PHYSICAL(p0,r3,ia64_mca_serialize);;
296 st4.rel [r3]=r0
298 br b0
300 //EndMain//////////////////////////////////////////////////////////////////////
302 //StartMain////////////////////////////////////////////////////////////////////
304 //
305 // SAL to OS entry point for INIT on all processors. This has been defined for
306 // registration purposes with SAL as a part of ia64_mca_init. Monarch and
307 // slave INIT have identical processing, except for the value of the
308 // sos->monarch flag in r19.
309 //
311 ia64_os_init_dispatch_monarch:
312 mov r19=1 // Bow, bow, ye lower middle classes!
313 br.sptk ia64_os_init_dispatch
315 ia64_os_init_dispatch_slave:
316 mov r19=0 // <igor>yeth, mathter</igor>
318 ia64_os_init_dispatch:
320 mov r3=IA64_MCA_CPU_INIT_STACK_OFFSET // use the INIT stack
321 LOAD_PHYSICAL(p0,r2,1f) // return address
322 br.sptk ia64_state_save // save the state that is not in minstate
323 1:
325 // switch to per cpu INIT stack
326 mov r3=IA64_MCA_CPU_INIT_STACK_OFFSET // use the INIT stack
327 LOAD_PHYSICAL(p0,r2,1f) // return address
328 br.sptk ia64_new_stack
329 1:
331 // everything saved, now we can set the kernel registers
332 mov r3=IA64_MCA_CPU_INIT_STACK_OFFSET // use the INIT stack
333 LOAD_PHYSICAL(p0,r2,1f) // return address
334 br.sptk ia64_set_kernel_registers
335 1:
337 // This must be done in physical mode
338 GET_IA64_MCA_DATA(r2)
339 ;;
340 mov r7=r2
342 // Enter virtual mode from physical mode
343 VIRTUAL_MODE_ENTER(r2, r3, ia64_os_init_virtual_begin, r4)
345 // This code returns to SAL via SOS r2, in general SAL has no unwind
346 // data. To get a clean termination when backtracing the C MCA/INIT
347 // handler, set a dummy return address of 0 in this routine. That
348 // requires that ia64_os_init_virtual_begin be a global function.
349 ENTRY(ia64_os_init_virtual_begin)
350 .prologue
351 .save rp,r0
352 .body
354 mov ar.rsc=3 // set eager mode for C handler
355 mov r2=r7 // see GET_IA64_MCA_DATA above
356 ;;
358 // Call virtual mode handler
359 alloc r14=ar.pfs,0,0,3,0
360 ;;
361 DATA_PA_TO_VA(r2,r7)
362 ;;
363 add out0=IA64_MCA_CPU_INIT_STACK_OFFSET+MCA_PT_REGS_OFFSET, r2
364 add out1=IA64_MCA_CPU_INIT_STACK_OFFSET+MCA_SWITCH_STACK_OFFSET, r2
365 add out2=IA64_MCA_CPU_INIT_STACK_OFFSET+MCA_SOS_OFFSET, r2
366 br.call.sptk.many b0=ia64_init_handler
368 // Revert back to physical mode before going back to SAL
369 PHYSICAL_MODE_ENTER(r2, r3, ia64_os_init_virtual_end, r4)
370 ia64_os_init_virtual_end:
372 END(ia64_os_init_virtual_begin)
374 mov r3=IA64_MCA_CPU_INIT_STACK_OFFSET // use the INIT stack
375 LOAD_PHYSICAL(p0,r2,1f) // return address
376 br.sptk ia64_state_restore // restore the SAL state
377 1:
379 // switch back to previous stack
380 alloc r14=ar.pfs,0,0,0,0 // remove the INIT handler frame
381 mov r3=IA64_MCA_CPU_INIT_STACK_OFFSET // use the INIT stack
382 LOAD_PHYSICAL(p0,r2,1f) // return address
383 br.sptk ia64_old_stack
384 1:
386 mov b0=r12 // SAL_CHECK return address
387 br b0
389 //EndMain//////////////////////////////////////////////////////////////////////
391 // common defines for the stubs
392 #define ms r4
393 #define regs r5
394 #define temp1 r2 /* careful, it overlaps with input registers */
395 #define temp2 r3 /* careful, it overlaps with input registers */
396 #define temp3 r7
397 #define temp4 r14
400 //++
401 // Name:
402 // ia64_state_save()
403 //
404 // Stub Description:
405 //
406 // Save the state that is not in minstate. This is sensitive to the layout of
407 // struct ia64_sal_os_state in mca.h.
408 //
409 // r2 contains the return address, r3 contains either
410 // IA64_MCA_CPU_MCA_STACK_OFFSET or IA64_MCA_CPU_INIT_STACK_OFFSET.
411 //
412 // The OS to SAL section of struct ia64_sal_os_state is set to a default
413 // value of cold boot (MCA) or warm boot (INIT) and return to the same
414 // context. ia64_sal_os_state is also used to hold some registers that
415 // need to be saved and restored across the stack switches.
416 //
417 // Most input registers to this stub come from PAL/SAL
418 // r1 os gp, physical
419 // r8 pal_proc entry point
420 // r9 sal_proc entry point
421 // r10 sal gp
422 // r11 MCA - rendevzous state, INIT - reason code
423 // r12 sal return address
424 // r17 pal min_state
425 // r18 processor state parameter
426 // r19 monarch flag, set by the caller of this routine
427 //
428 // In addition to the SAL to OS state, this routine saves all the
429 // registers that appear in struct pt_regs and struct switch_stack,
430 // excluding those that are already in the PAL minstate area. This
431 // results in a partial pt_regs and switch_stack, the C code copies the
432 // remaining registers from PAL minstate to pt_regs and switch_stack. The
433 // resulting structures contain all the state of the original process when
434 // MCA/INIT occurred.
435 //
436 //--
438 ia64_state_save:
439 add regs=MCA_SOS_OFFSET, r3
440 add ms=MCA_SOS_OFFSET+8, r3
441 mov b0=r2 // save return address
442 cmp.eq p1,p2=IA64_MCA_CPU_MCA_STACK_OFFSET, r3
443 ;;
444 GET_IA64_MCA_DATA(temp2)
445 ;;
446 add temp1=temp2, regs // struct ia64_sal_os_state on MCA or INIT stack
447 add temp2=temp2, ms // struct ia64_sal_os_state+8 on MCA or INIT stack
448 ;;
449 mov regs=temp1 // save the start of sos
450 st8 [temp1]=r1,16 // os_gp
451 st8 [temp2]=r8,16 // pal_proc
452 ;;
453 st8 [temp1]=r9,16 // sal_proc
454 st8 [temp2]=r11,16 // rv_rc
455 mov r11=cr.iipa
456 ;;
457 st8 [temp1]=r18 // proc_state_param
458 st8 [temp2]=r19 // monarch
459 mov r6=IA64_KR(CURRENT)
460 add temp1=SOS(SAL_RA), regs
461 add temp2=SOS(SAL_GP), regs
462 ;;
463 st8 [temp1]=r12,16 // sal_ra
464 st8 [temp2]=r10,16 // sal_gp
465 mov r12=cr.isr
466 ;;
467 st8 [temp1]=r17,16 // pal_min_state
468 st8 [temp2]=r6,16 // prev_IA64_KR_CURRENT
469 mov r6=IA64_KR(CURRENT_STACK)
470 ;;
471 st8 [temp1]=r6,16 // prev_IA64_KR_CURRENT_STACK
472 st8 [temp2]=r0,16 // prev_task, starts off as NULL
473 mov r6=cr.ifa
474 ;;
475 st8 [temp1]=r12,16 // cr.isr
476 st8 [temp2]=r6,16 // cr.ifa
477 mov r12=cr.itir
478 ;;
479 st8 [temp1]=r12,16 // cr.itir
480 st8 [temp2]=r11,16 // cr.iipa
481 mov r12=cr.iim
482 ;;
483 st8 [temp1]=r12 // cr.iim
484 (p1) mov r12=IA64_MCA_COLD_BOOT
485 (p2) mov r12=IA64_INIT_WARM_BOOT
486 mov r6=cr.iha
487 add temp1=SOS(OS_STATUS), regs
488 ;;
489 st8 [temp2]=r6 // cr.iha
490 add temp2=SOS(CONTEXT), regs
491 st8 [temp1]=r12 // os_status, default is cold boot
492 mov r6=IA64_MCA_SAME_CONTEXT
493 ;;
494 st8 [temp2]=r6 // context, default is same context
496 // Save the pt_regs data that is not in minstate. The previous code
497 // left regs at sos.
498 add regs=MCA_PT_REGS_OFFSET-MCA_SOS_OFFSET, regs
499 ;;
500 add temp1=PT(B6), regs
501 mov temp3=b6
502 mov temp4=b7
503 add temp2=PT(B7), regs
504 ;;
505 st8 [temp1]=temp3,PT(AR_CSD)-PT(B6) // save b6
506 st8 [temp2]=temp4,PT(AR_SSD)-PT(B7) // save b7
507 mov temp3=ar.csd
508 mov temp4=ar.ssd
509 cover // must be last in group
510 ;;
511 st8 [temp1]=temp3,PT(AR_UNAT)-PT(AR_CSD) // save ar.csd
512 st8 [temp2]=temp4,PT(AR_PFS)-PT(AR_SSD) // save ar.ssd
513 mov temp3=ar.unat
514 mov temp4=ar.pfs
515 ;;
516 st8 [temp1]=temp3,PT(AR_RNAT)-PT(AR_UNAT) // save ar.unat
517 st8 [temp2]=temp4,PT(AR_BSPSTORE)-PT(AR_PFS) // save ar.pfs
518 mov temp3=ar.rnat
519 mov temp4=ar.bspstore
520 ;;
521 st8 [temp1]=temp3,PT(LOADRS)-PT(AR_RNAT) // save ar.rnat
522 st8 [temp2]=temp4,PT(AR_FPSR)-PT(AR_BSPSTORE) // save ar.bspstore
523 mov temp3=ar.bsp
524 ;;
525 sub temp3=temp3, temp4 // ar.bsp - ar.bspstore
526 mov temp4=ar.fpsr
527 ;;
528 shl temp3=temp3,16 // compute ar.rsc to be used for "loadrs"
529 ;;
530 st8 [temp1]=temp3,PT(AR_CCV)-PT(LOADRS) // save loadrs
531 st8 [temp2]=temp4,PT(F6)-PT(AR_FPSR) // save ar.fpsr
532 mov temp3=ar.ccv
533 ;;
534 st8 [temp1]=temp3,PT(F7)-PT(AR_CCV) // save ar.ccv
535 stf.spill [temp2]=f6,PT(F8)-PT(F6)
536 ;;
537 stf.spill [temp1]=f7,PT(F9)-PT(F7)
538 stf.spill [temp2]=f8,PT(F10)-PT(F8)
539 ;;
540 stf.spill [temp1]=f9,PT(F11)-PT(F9)
541 stf.spill [temp2]=f10
542 ;;
543 stf.spill [temp1]=f11
545 // Save the switch_stack data that is not in minstate nor pt_regs. The
546 // previous code left regs at pt_regs.
547 add regs=MCA_SWITCH_STACK_OFFSET-MCA_PT_REGS_OFFSET, regs
548 ;;
549 add temp1=SW(F2), regs
550 add temp2=SW(F3), regs
551 ;;
552 stf.spill [temp1]=f2,32
553 stf.spill [temp2]=f3,32
554 ;;
555 stf.spill [temp1]=f4,32
556 stf.spill [temp2]=f5,32
557 ;;
558 stf.spill [temp1]=f12,32
559 stf.spill [temp2]=f13,32
560 ;;
561 stf.spill [temp1]=f14,32
562 stf.spill [temp2]=f15,32
563 ;;
564 stf.spill [temp1]=f16,32
565 stf.spill [temp2]=f17,32
566 ;;
567 stf.spill [temp1]=f18,32
568 stf.spill [temp2]=f19,32
569 ;;
570 stf.spill [temp1]=f20,32
571 stf.spill [temp2]=f21,32
572 ;;
573 stf.spill [temp1]=f22,32
574 stf.spill [temp2]=f23,32
575 ;;
576 stf.spill [temp1]=f24,32
577 stf.spill [temp2]=f25,32
578 ;;
579 stf.spill [temp1]=f26,32
580 stf.spill [temp2]=f27,32
581 ;;
582 stf.spill [temp1]=f28,32
583 stf.spill [temp2]=f29,32
584 ;;
585 stf.spill [temp1]=f30,SW(B2)-SW(F30)
586 stf.spill [temp2]=f31,SW(B3)-SW(F31)
587 mov temp3=b2
588 mov temp4=b3
589 ;;
590 st8 [temp1]=temp3,16 // save b2
591 st8 [temp2]=temp4,16 // save b3
592 mov temp3=b4
593 mov temp4=b5
594 ;;
595 st8 [temp1]=temp3,SW(AR_LC)-SW(B4) // save b4
596 st8 [temp2]=temp4 // save b5
597 mov temp3=ar.lc
598 ;;
599 st8 [temp1]=temp3 // save ar.lc
601 // FIXME: Some proms are incorrectly accessing the minstate area as
602 // cached data. The C code uses region 6, uncached virtual. Ensure
603 // that there is no cache data lying around for the first 1K of the
604 // minstate area.
605 // Remove this code in September 2006, that gives platforms a year to
606 // fix their proms and get their customers updated.
608 add r1=32*1,r17
609 add r2=32*2,r17
610 add r3=32*3,r17
611 add r4=32*4,r17
612 add r5=32*5,r17
613 add r6=32*6,r17
614 add r7=32*7,r17
615 ;;
616 fc r17
617 fc r1
618 fc r2
619 fc r3
620 fc r4
621 fc r5
622 fc r6
623 fc r7
624 add r17=32*8,r17
625 add r1=32*8,r1
626 add r2=32*8,r2
627 add r3=32*8,r3
628 add r4=32*8,r4
629 add r5=32*8,r5
630 add r6=32*8,r6
631 add r7=32*8,r7
632 ;;
633 fc r17
634 fc r1
635 fc r2
636 fc r3
637 fc r4
638 fc r5
639 fc r6
640 fc r7
641 add r17=32*8,r17
642 add r1=32*8,r1
643 add r2=32*8,r2
644 add r3=32*8,r3
645 add r4=32*8,r4
646 add r5=32*8,r5
647 add r6=32*8,r6
648 add r7=32*8,r7
649 ;;
650 fc r17
651 fc r1
652 fc r2
653 fc r3
654 fc r4
655 fc r5
656 fc r6
657 fc r7
658 add r17=32*8,r17
659 add r1=32*8,r1
660 add r2=32*8,r2
661 add r3=32*8,r3
662 add r4=32*8,r4
663 add r5=32*8,r5
664 add r6=32*8,r6
665 add r7=32*8,r7
666 ;;
667 fc r17
668 fc r1
669 fc r2
670 fc r3
671 fc r4
672 fc r5
673 fc r6
674 fc r7
676 br.sptk b0
678 //EndStub//////////////////////////////////////////////////////////////////////
681 //++
682 // Name:
683 // ia64_state_restore()
684 //
685 // Stub Description:
686 //
687 // Restore the SAL/OS state. This is sensitive to the layout of struct
688 // ia64_sal_os_state in mca.h.
689 //
690 // r2 contains the return address, r3 contains either
691 // IA64_MCA_CPU_MCA_STACK_OFFSET or IA64_MCA_CPU_INIT_STACK_OFFSET.
692 //
693 // In addition to the SAL to OS state, this routine restores all the
694 // registers that appear in struct pt_regs and struct switch_stack,
695 // excluding those in the PAL minstate area.
696 //
697 //--
699 ia64_state_restore:
700 // Restore the switch_stack data that is not in minstate nor pt_regs.
701 add regs=MCA_SWITCH_STACK_OFFSET, r3
702 mov b0=r2 // save return address
703 ;;
704 GET_IA64_MCA_DATA(temp2)
705 ;;
706 add regs=temp2, regs
707 ;;
708 add temp1=SW(F2), regs
709 add temp2=SW(F3), regs
710 ;;
711 ldf.fill f2=[temp1],32
712 ldf.fill f3=[temp2],32
713 ;;
714 ldf.fill f4=[temp1],32
715 ldf.fill f5=[temp2],32
716 ;;
717 ldf.fill f12=[temp1],32
718 ldf.fill f13=[temp2],32
719 ;;
720 ldf.fill f14=[temp1],32
721 ldf.fill f15=[temp2],32
722 ;;
723 ldf.fill f16=[temp1],32
724 ldf.fill f17=[temp2],32
725 ;;
726 ldf.fill f18=[temp1],32
727 ldf.fill f19=[temp2],32
728 ;;
729 ldf.fill f20=[temp1],32
730 ldf.fill f21=[temp2],32
731 ;;
732 ldf.fill f22=[temp1],32
733 ldf.fill f23=[temp2],32
734 ;;
735 ldf.fill f24=[temp1],32
736 ldf.fill f25=[temp2],32
737 ;;
738 ldf.fill f26=[temp1],32
739 ldf.fill f27=[temp2],32
740 ;;
741 ldf.fill f28=[temp1],32
742 ldf.fill f29=[temp2],32
743 ;;
744 ldf.fill f30=[temp1],SW(B2)-SW(F30)
745 ldf.fill f31=[temp2],SW(B3)-SW(F31)
746 ;;
747 ld8 temp3=[temp1],16 // restore b2
748 ld8 temp4=[temp2],16 // restore b3
749 ;;
750 mov b2=temp3
751 mov b3=temp4
752 ld8 temp3=[temp1],SW(AR_LC)-SW(B4) // restore b4
753 ld8 temp4=[temp2] // restore b5
754 ;;
755 mov b4=temp3
756 mov b5=temp4
757 ld8 temp3=[temp1] // restore ar.lc
758 ;;
759 mov ar.lc=temp3
761 // Restore the pt_regs data that is not in minstate. The previous code
762 // left regs at switch_stack.
763 add regs=MCA_PT_REGS_OFFSET-MCA_SWITCH_STACK_OFFSET, regs
764 ;;
765 add temp1=PT(B6), regs
766 add temp2=PT(B7), regs
767 ;;
768 ld8 temp3=[temp1],PT(AR_CSD)-PT(B6) // restore b6
769 ld8 temp4=[temp2],PT(AR_SSD)-PT(B7) // restore b7
770 ;;
771 mov b6=temp3
772 mov b7=temp4
773 ld8 temp3=[temp1],PT(AR_UNAT)-PT(AR_CSD) // restore ar.csd
774 ld8 temp4=[temp2],PT(AR_PFS)-PT(AR_SSD) // restore ar.ssd
775 ;;
776 mov ar.csd=temp3
777 mov ar.ssd=temp4
778 ld8 temp3=[temp1] // restore ar.unat
779 add temp1=PT(AR_CCV)-PT(AR_UNAT), temp1
780 ld8 temp4=[temp2],PT(AR_FPSR)-PT(AR_PFS) // restore ar.pfs
781 ;;
782 mov ar.unat=temp3
783 mov ar.pfs=temp4
784 // ar.rnat, ar.bspstore, loadrs are restore in ia64_old_stack.
785 ld8 temp3=[temp1],PT(F6)-PT(AR_CCV) // restore ar.ccv
786 ld8 temp4=[temp2],PT(F7)-PT(AR_FPSR) // restore ar.fpsr
787 ;;
788 mov ar.ccv=temp3
789 mov ar.fpsr=temp4
790 ldf.fill f6=[temp1],PT(F8)-PT(F6)
791 ldf.fill f7=[temp2],PT(F9)-PT(F7)
792 ;;
793 ldf.fill f8=[temp1],PT(F10)-PT(F8)
794 ldf.fill f9=[temp2],PT(F11)-PT(F9)
795 ;;
796 ldf.fill f10=[temp1]
797 ldf.fill f11=[temp2]
799 // Restore the SAL to OS state. The previous code left regs at pt_regs.
800 add regs=MCA_SOS_OFFSET-MCA_PT_REGS_OFFSET, regs
801 ;;
802 add temp1=SOS(SAL_RA), regs
803 add temp2=SOS(SAL_GP), regs
804 ;;
805 ld8 r12=[temp1],16 // sal_ra
806 ld8 r9=[temp2],16 // sal_gp
807 ;;
808 ld8 r22=[temp1],16 // pal_min_state, virtual
809 ld8 r13=[temp2],16 // prev_IA64_KR_CURRENT
810 ;;
811 ld8 r16=[temp1],16 // prev_IA64_KR_CURRENT_STACK
812 ld8 r20=[temp2],16 // prev_task
813 ;;
814 ld8 temp3=[temp1],16 // cr.isr
815 ld8 temp4=[temp2],16 // cr.ifa
816 ;;
817 mov cr.isr=temp3
818 mov cr.ifa=temp4
819 ld8 temp3=[temp1],16 // cr.itir
820 ld8 temp4=[temp2],16 // cr.iipa
821 ;;
822 mov cr.itir=temp3
823 mov cr.iipa=temp4
824 ld8 temp3=[temp1] // cr.iim
825 ld8 temp4=[temp2] // cr.iha
826 add temp1=SOS(OS_STATUS), regs
827 add temp2=SOS(CONTEXT), regs
828 ;;
829 mov cr.iim=temp3
830 mov cr.iha=temp4
831 dep r22=0,r22,62,1 // pal_min_state, physical, uncached
832 mov IA64_KR(CURRENT)=r13
833 ld8 r8=[temp1] // os_status
834 ld8 r10=[temp2] // context
836 /* Wire IA64_TR_CURRENT_STACK to the stack that we are resuming to. To
837 * avoid any dependencies on the algorithm in ia64_switch_to(), just
838 * purge any existing CURRENT_STACK mapping and insert the new one.
839 *
840 * r16 contains prev_IA64_KR_CURRENT_STACK, r13 contains
841 * prev_IA64_KR_CURRENT, these values may have been changed by the C
842 * code. Do not use r8, r9, r10, r22, they contain values ready for
843 * the return to SAL.
844 */
846 mov r15=IA64_KR(CURRENT_STACK) // physical granule mapped by IA64_TR_CURRENT_STACK
847 ;;
848 shl r15=r15,IA64_GRANULE_SHIFT
849 ;;
850 dep r15=-1,r15,61,3 // virtual granule
851 mov r18=IA64_GRANULE_SHIFT<<2 // for cr.itir.ps
852 ;;
853 ptr.d r15,r18
854 ;;
855 srlz.d
857 extr.u r19=r13,61,3 // r13 = prev_IA64_KR_CURRENT
858 shl r20=r16,IA64_GRANULE_SHIFT // r16 = prev_IA64_KR_CURRENT_STACK
859 movl r21=PAGE_KERNEL // page properties
860 ;;
861 mov IA64_KR(CURRENT_STACK)=r16
862 cmp.ne p6,p0=RGN_KERNEL,r19 // new stack is in the kernel region?
863 or r21=r20,r21 // construct PA | page properties
864 (p6) br.spnt 1f // the dreaded cpu 0 idle task in region 5:(
865 ;;
866 mov cr.itir=r18
867 mov cr.ifa=r13
868 mov r20=IA64_TR_CURRENT_STACK
869 ;;
870 itr.d dtr[r20]=r21
871 ;;
872 srlz.d
873 1:
875 br.sptk b0
877 //EndStub//////////////////////////////////////////////////////////////////////
880 //++
881 // Name:
882 // ia64_new_stack()
883 //
884 // Stub Description:
885 //
886 // Switch to the MCA/INIT stack.
887 //
888 // r2 contains the return address, r3 contains either
889 // IA64_MCA_CPU_MCA_STACK_OFFSET or IA64_MCA_CPU_INIT_STACK_OFFSET.
890 //
891 // On entry RBS is still on the original stack, this routine switches RBS
892 // to use the MCA/INIT stack.
893 //
894 // On entry, sos->pal_min_state is physical, on exit it is virtual.
895 //
896 //--
898 ia64_new_stack:
899 add regs=MCA_PT_REGS_OFFSET, r3
900 add temp2=MCA_SOS_OFFSET+SOS(PAL_MIN_STATE), r3
901 mov b0=r2 // save return address
902 GET_IA64_MCA_DATA(temp1)
903 invala
904 ;;
905 add temp2=temp2, temp1 // struct ia64_sal_os_state.pal_min_state on MCA or INIT stack
906 add regs=regs, temp1 // struct pt_regs on MCA or INIT stack
907 ;;
908 // Address of minstate area provided by PAL is physical, uncacheable.
909 // Convert to Linux virtual address in region 6 for C code.
910 ld8 ms=[temp2] // pal_min_state, physical
911 ;;
912 dep temp1=-1,ms,62,2 // set region 6
913 mov temp3=IA64_RBS_OFFSET-MCA_PT_REGS_OFFSET
914 ;;
915 st8 [temp2]=temp1 // pal_min_state, virtual
917 add temp4=temp3, regs // start of bspstore on new stack
918 ;;
919 mov ar.bspstore=temp4 // switch RBS to MCA/INIT stack
920 ;;
921 flushrs // must be first in group
922 br.sptk b0
924 //EndStub//////////////////////////////////////////////////////////////////////
927 //++
928 // Name:
929 // ia64_old_stack()
930 //
931 // Stub Description:
932 //
933 // Switch to the old stack.
934 //
935 // r2 contains the return address, r3 contains either
936 // IA64_MCA_CPU_MCA_STACK_OFFSET or IA64_MCA_CPU_INIT_STACK_OFFSET.
937 //
938 // On entry, pal_min_state is virtual, on exit it is physical.
939 //
940 // On entry RBS is on the MCA/INIT stack, this routine switches RBS
941 // back to the previous stack.
942 //
943 // The psr is set to all zeroes. SAL return requires either all zeroes or
944 // just psr.mc set. Leaving psr.mc off allows INIT to be issued if this
945 // code does not perform correctly.
946 //
947 // The dirty registers at the time of the event were flushed to the
948 // MCA/INIT stack in ia64_pt_regs_save(). Restore the dirty registers
949 // before reverting to the previous bspstore.
950 //--
952 ia64_old_stack:
953 add regs=MCA_PT_REGS_OFFSET, r3
954 mov b0=r2 // save return address
955 GET_IA64_MCA_DATA(temp2)
956 LOAD_PHYSICAL(p0,temp1,1f)
957 ;;
958 mov cr.ipsr=r0
959 mov cr.ifs=r0
960 mov cr.iip=temp1
961 ;;
962 invala
963 rfi
964 1:
966 add regs=regs, temp2 // struct pt_regs on MCA or INIT stack
967 ;;
968 add temp1=PT(LOADRS), regs
969 ;;
970 ld8 temp2=[temp1],PT(AR_BSPSTORE)-PT(LOADRS) // restore loadrs
971 ;;
972 ld8 temp3=[temp1],PT(AR_RNAT)-PT(AR_BSPSTORE) // restore ar.bspstore
973 mov ar.rsc=temp2
974 ;;
975 loadrs
976 ld8 temp4=[temp1] // restore ar.rnat
977 ;;
978 mov ar.bspstore=temp3 // back to old stack
979 ;;
980 mov ar.rnat=temp4
981 ;;
983 br.sptk b0
985 //EndStub//////////////////////////////////////////////////////////////////////
988 //++
989 // Name:
990 // ia64_set_kernel_registers()
991 //
992 // Stub Description:
993 //
994 // Set the registers that are required by the C code in order to run on an
995 // MCA/INIT stack.
996 //
997 // r2 contains the return address, r3 contains either
998 // IA64_MCA_CPU_MCA_STACK_OFFSET or IA64_MCA_CPU_INIT_STACK_OFFSET.
999 //
1000 //--
1002 ia64_set_kernel_registers:
1003 add temp3=MCA_SP_OFFSET, r3
1004 mov b0=r2 // save return address
1005 GET_IA64_MCA_DATA(temp1)
1006 ;;
1007 add r12=temp1, temp3 // kernel stack pointer on MCA/INIT stack
1008 add r13=temp1, r3 // set current to start of MCA/INIT stack
1009 add r20=temp1, r3 // physical start of MCA/INIT stack
1010 ;;
1011 DATA_PA_TO_VA(r12,temp2)
1012 DATA_PA_TO_VA(r13,temp3)
1013 ;;
1014 mov IA64_KR(CURRENT)=r13
1016 /* Wire IA64_TR_CURRENT_STACK to the MCA/INIT handler stack. To avoid
1017 * any dependencies on the algorithm in ia64_switch_to(), just purge
1018 * any existing CURRENT_STACK mapping and insert the new one.
1019 */
1021 mov r16=IA64_KR(CURRENT_STACK) // physical granule mapped by IA64_TR_CURRENT_STACK
1022 ;;
1023 shl r16=r16,IA64_GRANULE_SHIFT
1024 ;;
1025 dep r16=-1,r16,61,3 // virtual granule
1026 mov r18=IA64_GRANULE_SHIFT<<2 // for cr.itir.ps
1027 ;;
1028 ptr.d r16,r18
1029 ;;
1030 srlz.d
1032 shr.u r16=r20,IA64_GRANULE_SHIFT // r20 = physical start of MCA/INIT stack
1033 movl r21=PAGE_KERNEL // page properties
1034 ;;
1035 mov IA64_KR(CURRENT_STACK)=r16
1036 or r21=r20,r21 // construct PA | page properties
1037 ;;
1038 mov cr.itir=r18
1039 mov cr.ifa=r13
1040 mov r20=IA64_TR_CURRENT_STACK
1042 movl r17=FPSR_DEFAULT
1043 ;;
1044 mov.m ar.fpsr=r17 // set ar.fpsr to kernel default value
1045 ;;
1046 itr.d dtr[r20]=r21
1047 ;;
1048 srlz.d
1050 br.sptk b0
1052 //EndStub//////////////////////////////////////////////////////////////////////
1054 #undef ms
1055 #undef regs
1056 #undef temp1
1057 #undef temp2
1058 #undef temp3
1059 #undef temp4
1062 // Support function for mca.c, it is here to avoid using inline asm. Given the
1063 // address of an rnat slot, if that address is below the current ar.bspstore
1064 // then return the contents of that slot, otherwise return the contents of
1065 // ar.rnat.
1066 GLOBAL_ENTRY(ia64_get_rnat)
1067 alloc r14=ar.pfs,1,0,0,0
1068 mov ar.rsc=0
1069 ;;
1070 mov r14=ar.bspstore
1071 ;;
1072 cmp.lt p6,p7=in0,r14
1073 ;;
1074 (p6) ld8 r8=[in0]
1075 (p7) mov r8=ar.rnat
1076 mov ar.rsc=3
1077 br.ret.sptk.many rp
1078 END(ia64_get_rnat)