[ARM] 3340/1: Fix the PCI setup for direct master access to SDRAM
[pv_ops_mirror.git] / arch / sh / boards / overdrive / fpga.c
blob3a1ec9403441eb41b871d8ba8a0c8d322b913016
1 /*
2 * Copyright (C) 2000 David J. Mckay (david.mckay@st.com)
4 * May be copied or modified under the terms of the GNU General Public
5 * License. See linux/COPYING for more information.
7 * This file handles programming up the Altera Flex10K that interfaces to
8 * the Galileo, and does the PS/2 keyboard and mouse
13 #include <linux/config.h>
14 #include <linux/kernel.h>
15 #include <linux/smp.h>
16 #include <linux/smp_lock.h>
17 #include <linux/init.h>
18 #include <linux/errno.h>
19 #include <linux/pci.h>
20 #include <linux/delay.h>
23 #include <asm/overdriver/gt64111.h>
24 #include <asm/overdrive/overdrive.h>
25 #include <asm/overdrive/fpga.h>
27 #define FPGA_NotConfigHigh() (*FPGA_ControlReg) = (*FPGA_ControlReg) | ENABLE_FPGA_BIT
28 #define FPGA_NotConfigLow() (*FPGA_ControlReg) = (*FPGA_ControlReg) & RESET_FPGA_MASK
30 /* I need to find out what (if any) the real delay factor here is */
31 /* The delay is definately not critical */
32 #define long_delay() {int i;for(i=0;i<10000;i++);}
33 #define short_delay() {int i;for(i=0;i<100;i++);}
35 static void __init program_overdrive_fpga(const unsigned char *fpgacode,
36 int size)
38 int timeout = 0;
39 int i, j;
40 unsigned char b;
41 static volatile unsigned char *FPGA_ControlReg =
42 (volatile unsigned char *) (OVERDRIVE_CTRL);
43 static volatile unsigned char *FPGA_ProgramReg =
44 (volatile unsigned char *) (FPGA_DCLK_ADDRESS);
46 printk("FPGA: Commencing FPGA Programming\n");
48 /* The PCI reset but MUST be low when programming the FPGA !!! */
49 b = (*FPGA_ControlReg) & RESET_PCI_MASK;
51 (*FPGA_ControlReg) = b;
53 /* Prepare FPGA to program */
55 FPGA_NotConfigHigh();
56 long_delay();
58 FPGA_NotConfigLow();
59 short_delay();
61 while ((*FPGA_ProgramReg & FPGA_NOT_STATUS) != 0) {
62 printk("FPGA: Waiting for NotStatus to go Low ... \n");
65 FPGA_NotConfigHigh();
67 /* Wait for FPGA "ready to be programmed" signal */
68 printk("FPGA: Waiting for NotStatus to go high (FPGA ready)... \n");
70 for (timeout = 0;
71 (((*FPGA_ProgramReg & FPGA_NOT_STATUS) == 0)
72 && (timeout < FPGA_TIMEOUT)); timeout++);
74 /* Check if timeout condition occured - i.e. an error */
76 if (timeout == FPGA_TIMEOUT) {
77 printk
78 ("FPGA: Failed to program - Timeout waiting for notSTATUS to go high\n");
79 return;
82 printk("FPGA: Copying data to FPGA ... %d bytes\n", size);
84 /* Copy array to FPGA - bit at a time */
86 for (i = 0; i < size; i++) {
87 volatile unsigned w = 0;
89 for (j = 0; j < 8; j++) {
90 *FPGA_ProgramReg = (fpgacode[i] >> j) & 0x01;
91 short_delay();
93 if ((i & 0x3ff) == 0) {
94 printk(".");
98 /* Waiting for CONFDONE to go high - means the program is complete */
100 for (timeout = 0;
101 (((*FPGA_ProgramReg & FPGA_CONFDONE) == 0)
102 && (timeout < FPGA_TIMEOUT)); timeout++) {
104 *FPGA_ProgramReg = 0x0;
105 long_delay();
108 if (timeout == FPGA_TIMEOUT) {
109 printk
110 ("FPGA: Failed to program - Timeout waiting for CONFDONE to go high\n");
111 return;
112 } else { /* Clock another 10 times - gets the device into a working state */
113 for (i = 0; i < 10; i++) {
114 *FPGA_ProgramReg = 0x0;
115 short_delay();
119 printk("FPGA: Programming complete\n");
123 static const unsigned char __init fpgacode[] = {
124 #include "./overdrive.ttf" /* Code from maxplus2 compiler */
125 , 0, 0
129 int __init init_overdrive_fpga(void)
131 program_overdrive_fpga(fpgacode, sizeof(fpgacode));
133 return 0;