arch/sh/boards/overdrive/galileo.c

   1 /*
   2  * Copyright (C) 2000 David J. Mckay (david.mckay@st.com)
   3  *
   4  * May be copied or modified under the terms of the GNU General Public
   5  * License.  See linux/COPYING for more information.
   6  *
   7  * This file contains the PCI routines required for the Galileo GT6411
   8  * PCI bridge as used on the Orion and Overdrive boards.
   9  *
  10  */
  11
  12 #include <linux/config.h>
  13 #include <linux/kernel.h>
  14 #include <linux/smp.h>
  15 #include <linux/smp_lock.h>
  16 #include <linux/init.h>
  17 #include <linux/errno.h>
  18 #include <linux/pci.h>
  19 #include <linux/delay.h>
  20 #include <linux/types.h>
  21 #include <linux/ioport.h>
  22
  23 #include <asm/overdrive/overdrive.h>
  24 #include <asm/overdrive/gt64111.h>
  25
  26
  27 /* After boot, we shift the Galileo registers so that they appear
  28  * in BANK6, along with IO space. This means we can have one contingous
  29  * lump of PCI address space without these registers appearing in the
  30  * middle of them
  31  */
  32
  33 #define GT64111_BASE_ADDRESS  0xbb000000
  34 #define GT64111_IO_BASE_ADDRESS  0x1000
  35 /* The GT64111 registers appear at this address to the SH4 after reset */
  36 #define RESET_GT64111_BASE_ADDRESS           0xb4000000
  37
  38 /* Macros used to access the Galileo registers */
  39 #define RESET_GT64111_REG(x) (RESET_GT64111_BASE_ADDRESS+x)
  40 #define GT64111_REG(x) (GT64111_BASE_ADDRESS+x)
  41
  42 #define RESET_GT_WRITE(x,v) writel((v),RESET_GT64111_REG(x))
  43
  44 #define RESET_GT_READ(x) readl(RESET_GT64111_REG(x))
  45
  46 #define GT_WRITE(x,v) writel((v),GT64111_REG(x))
  47 #define GT_WRITE_BYTE(x,v) writeb((v),GT64111_REG(x))
  48 #define GT_WRITE_SHORT(x,v) writew((v),GT64111_REG(x))
  49
  50 #define GT_READ(x)    readl(GT64111_REG(x))
  51 #define GT_READ_BYTE(x)  readb(GT64111_REG(x))
  52 #define GT_READ_SHORT(x) readw(GT64111_REG(x))
  53
  54
  55 /* Where the various SH banks start at */
  56 #define SH_BANK4_ADR 0xb0000000
  57 #define SH_BANK5_ADR 0xb4000000
  58 #define SH_BANK6_ADR 0xb8000000
  59
  60 /* Masks out everything but lines 28,27,26 */
  61 #define BANK_SELECT_MASK 0x1c000000
  62
  63 #define SH4_TO_BANK(x) ( (x) & BANK_SELECT_MASK)
  64
  65 /*
  66  * Masks used for address conversaion. Bank 6 is used for IO and
  67  * has all the address bits zeroed by the FPGA. Special case this
  68  */
  69 #define MEMORY_BANK_MASK 0x1fffffff
  70 #define IO_BANK_MASK  0x03ffffff
  71
  72 /* Mark bank 6 as the bank used for IO. You can change this in the FPGA code
  73  * if you want
  74  */
  75 #define IO_BANK_ADR PCI_GTIO_BASE
  76
  77 /* Will select the correct mask to apply depending on the SH$ address */
  78 #define SELECT_BANK_MASK(x) \
  79    ( (SH4_TO_BANK(x)==SH4_TO_BANK(IO_BANK_ADR)) ? IO_BANK_MASK : MEMORY_BANK_MASK)
  80
  81 /* Converts between PCI space and P2 region */
  82 #define SH4_TO_PCI(x) ((x)&SELECT_BANK_MASK(x))
  83
  84 /* Various macros for figuring out what to stick in the Galileo registers.
  85  * You *really* don't want to figure this stuff out by hand, you always get
  86  * it wrong
  87  */
  88 #define GT_MEM_LO_ADR(x) ((((unsigned)((x)&SELECT_BANK_MASK(x)))>>21)&0x7ff)
  89 #define GT_MEM_HI_ADR(x) ((((unsigned)((x)&SELECT_BANK_MASK(x)))>>21)&0x7f)
  90 #define GT_MEM_SUB_ADR(x) ((((unsigned)((x)&SELECT_BANK_MASK(x)))>>20)&0xff)
  91
  92 #define PROGRAM_HI_LO(block,a,s) \
  93     GT_WRITE(block##_LO_DEC_ADR,GT_MEM_LO_ADR(a));\
  94     GT_WRITE(block##_HI_DEC_ADR,GT_MEM_HI_ADR(a+s-1))
  95
  96 #define PROGRAM_SUB_HI_LO(block,a,s) \
  97     GT_WRITE(block##_LO_DEC_ADR,GT_MEM_SUB_ADR(a));\
  98     GT_WRITE(block##_HI_DEC_ADR,GT_MEM_SUB_ADR(a+s-1))
  99
 100 /* We need to set the size, and the offset register */
 101
 102 #define GT_BAR_MASK(x) ((x)&~0xfff)
 103
 104 /* Macro to set up the BAR in the Galileo. Essentially used for the DRAM */
 105 #define PROGRAM_GT_BAR(block,a,s) \
 106   GT_WRITE(PCI_##block##_BANK_SIZE,GT_BAR_MASK((s-1)));\
 107   write_config_to_galileo(PCI_CONFIG_##block##_BASE_ADR,\
 108                              GT_BAR_MASK(a))
 109
 110 #define DISABLE_GT_BAR(block) \
 111   GT_WRITE(PCI_##block##_BANK_SIZE,0),\
 112   GT_CONFIG_WRITE(PCI_CONFIG_##block##_BASE_ADR,\
 113     0x80000000)
 114
 115 /* Macros to disable things we are not going to use */
 116 #define DISABLE_DECODE(x) GT_WRITE(x##_LO_DEC_ADR,0x7ff);\
 117                           GT_WRITE(x##_HI_DEC_ADR,0x00)
 118
 119 #define DISABLE_SUB_DECODE(x) GT_WRITE(x##_LO_DEC_ADR,0xff);\
 120                               GT_WRITE(x##_HI_DEC_ADR,0x00)
 121
 122 static void __init reset_pci(void)
 123 {
 124         /* Set RESET_PCI bit high */
 125         writeb(readb(OVERDRIVE_CTRL) | ENABLE_PCI_BIT, OVERDRIVE_CTRL);
 126         udelay(250);
 127
 128         /* Set RESET_PCI bit low */
 129         writeb(readb(OVERDRIVE_CTRL) & RESET_PCI_MASK, OVERDRIVE_CTRL);
 130         udelay(250);
 131
 132         writeb(readb(OVERDRIVE_CTRL) | ENABLE_PCI_BIT, OVERDRIVE_CTRL);
 133         udelay(250);
 134 }
 135
 136 static int write_config_to_galileo(int where, u32 val);
 137 #define GT_CONFIG_WRITE(where,val) write_config_to_galileo(where,val)
 138
 139 #define ENABLE_PCI_DRAM
 140
 141
 142 #ifdef TEST_DRAM
 143 /* Test function to check out if the PCI DRAM is working OK */
 144 static int  /* __init */ test_dram(unsigned *base, unsigned size)
 145 {
 146         unsigned *p = base;
 147         unsigned *end = (unsigned *) (((unsigned) base) + size);
 148         unsigned w;
 149
 150         for (p = base; p < end; p++) {
 151                 *p = 0xffffffff;
 152                 if (*p != 0xffffffff) {
 153                         printk("AAARGH -write failed!!! at %p is %x\n", p,
 154                                *p);
 155                         return 0;
 156                 }
 157                 *p = 0x0;
 158                 if (*p != 0x0) {
 159                         printk("AAARGH -write failed!!!\n");
 160                         return 0;
 161                 }
 162         }
 163
 164         for (p = base; p < end; p++) {
 165                 *p = (unsigned) p;
 166                 if (*p != (unsigned) p) {
 167                         printk("Failed at 0x%p, actually is 0x%x\n", p,
 168                                *p);
 169                         return 0;
 170                 }
 171         }
 172
 173         for (p = base; p < end; p++) {
 174                 w = ((unsigned) p & 0xffff0000);
 175                 *p = w | (w >> 16);
 176         }
 177
 178         for (p = base; p < end; p++) {
 179                 w = ((unsigned) p & 0xffff0000);
 180                 w |= (w >> 16);
 181                 if (*p != w) {
 182                         printk
 183                             ("Failed at 0x%p, should be 0x%x actually is 0x%x\n",
 184                              p, w, *p);
 185                         return 0;
 186                 }
 187         }
 188
 189         return 1;
 190 }
 191 #endif
 192
 193
 194 /* Function to set up and initialise the galileo. This sets up the BARS,
 195  * maps the DRAM into the address space etc,etc
 196  */
 197 int __init galileo_init(void)
 198 {
 199         reset_pci();
 200
 201         /* Now shift the galileo regs into this block */
 202         RESET_GT_WRITE(INTERNAL_SPACE_DEC,
 203                        GT_MEM_LO_ADR(GT64111_BASE_ADDRESS));
 204
 205         /* Should have a sanity check here, that you can read back  at the new
 206          * address what you just wrote
 207          */
 208
 209         /* Disable decode for all regions */
 210         DISABLE_DECODE(RAS10);
 211         DISABLE_DECODE(RAS32);
 212         DISABLE_DECODE(CS20);
 213         DISABLE_DECODE(CS3);
 214         DISABLE_DECODE(PCI_IO);
 215         DISABLE_DECODE(PCI_MEM0);
 216         DISABLE_DECODE(PCI_MEM1);
 217
 218         /* Disable all BARS */
 219         GT_WRITE(BAR_ENABLE_ADR, 0x1ff);
 220         DISABLE_GT_BAR(RAS10);
 221         DISABLE_GT_BAR(RAS32);
 222         DISABLE_GT_BAR(CS20);
 223         DISABLE_GT_BAR(CS3);
 224
 225         /* Tell the BAR where the IO registers now are */
 226         GT_CONFIG_WRITE(PCI_CONFIG_INT_REG_IO_ADR,GT_BAR_MASK(
 227                                             (GT64111_IO_BASE_ADDRESS &
 228                                              IO_BANK_MASK)));
 229         /* set up a 112 Mb decode */
 230         PROGRAM_HI_LO(PCI_MEM0, SH_BANK4_ADR, 112 * 1024 * 1024);
 231
 232         /* Set up a 32 MB io space decode */
 233         PROGRAM_HI_LO(PCI_IO, IO_BANK_ADR, 32 * 1024 * 1024);
 234
 235 #ifdef ENABLE_PCI_DRAM
 236         /* Program up the DRAM configuration - there is DRAM only in bank 0 */
 237         /* Now set up the DRAM decode */
 238         PROGRAM_HI_LO(RAS10, PCI_DRAM_BASE, PCI_DRAM_SIZE);
 239         /* And the sub decode */
 240         PROGRAM_SUB_HI_LO(RAS0, PCI_DRAM_BASE, PCI_DRAM_SIZE);
 241
 242         DISABLE_SUB_DECODE(RAS1);
 243
 244         /* Set refresh rate */
 245         GT_WRITE(DRAM_BANK0_PARMS, 0x3f);
 246         GT_WRITE(DRAM_CFG, 0x100);
 247
 248         /* we have to lob off the top bits rememeber!! */
 249         PROGRAM_GT_BAR(RAS10, SH4_TO_PCI(PCI_DRAM_BASE), PCI_DRAM_SIZE);
 250
 251 #endif
 252
 253         /* We are only interested in decoding RAS10 and the Galileo's internal
 254          * registers (as IO) on the PCI bus
 255          */
 256 #ifdef ENABLE_PCI_DRAM
 257         GT_WRITE(BAR_ENABLE_ADR, (~((1 << 8) | (1 << 3))) & 0x1ff);
 258 #else
 259         GT_WRITE(BAR_ENABLE_ADR, (~(1 << 3)) & 0x1ff);
 260 #endif
 261
 262         /* Change the class code to host bridge, it actually powers up
 263          * as a memory controller
 264          */
 265         GT_CONFIG_WRITE(8, 0x06000011);
 266
 267         /* Allow the galileo to master the PCI bus */
 268         GT_CONFIG_WRITE(PCI_COMMAND,
 269                         PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
 270                         PCI_COMMAND_IO);
 271
 272
 273 #if 0
 274         printk("Testing PCI DRAM - ");
 275         if(test_dram(PCI_DRAM_BASE,PCI_DRAM_SIZE)) {
 276                 printk("Passed\n");
 277         }else {
 278                 printk("FAILED\n");
 279         }
 280 #endif
 281         return 0;
 282
 283 }
 284
 285
 286 #define SET_CONFIG_BITS(bus,devfn,where)\
 287   ((1<<31) | ((bus) << 16) | ((devfn) << 8) | ((where) & ~3))
 288
 289 #define CONFIG_CMD(dev, where) SET_CONFIG_BITS((dev)->bus->number,(dev)->devfn,where)
 290
 291 /* This write to the galileo config registers, unlike the functions below, can
 292  * be used before the PCI subsystem has started up
 293  */
 294 static int __init write_config_to_galileo(int where, u32 val)
 295 {
 296         GT_WRITE(PCI_CFG_ADR, SET_CONFIG_BITS(0, 0, where));
 297
 298         GT_WRITE(PCI_CFG_DATA, val);
 299         return 0;
 300 }
 301
 302 /* We exclude the galileo and slot 31, the galileo because I don't know how to stop
 303  * the setup code shagging up the setup I have done on it, and 31 because the whole
 304  * thing locks up if you try to access that slot (which doesn't exist of course anyway
 305  */
 306
 307 #define EXCLUDED_DEV(dev) ((dev->bus->number==0) && ((PCI_SLOT(dev->devfn)==0) || (PCI_SLOT(dev->devfn) == 31)))
 308
 309 static int galileo_read_config_byte(struct pci_dev *dev, int where,
 310                                     u8 * val)
 311 {
 312
 313
 314         /* I suspect this doesn't work because this drives a special cycle ? */
 315         if (EXCLUDED_DEV(dev)) {
 316                 *val = 0xff;
 317                 return PCIBIOS_SUCCESSFUL;
 318         }
 319         /* Start the config cycle */
 320         GT_WRITE(PCI_CFG_ADR, CONFIG_CMD(dev, where));
 321         /* Read back the result */
 322         *val = GT_READ_BYTE(PCI_CFG_DATA + (where & 3));
 323
 324         return PCIBIOS_SUCCESSFUL;
 325 }
 326
 327
 328 static int galileo_read_config_word(struct pci_dev *dev, int where,
 329                                     u16 * val)
 330 {
 331
 332         if (EXCLUDED_DEV(dev)) {
 333                 *val = 0xffff;
 334                 return PCIBIOS_SUCCESSFUL;
 335         }
 336
 337         GT_WRITE(PCI_CFG_ADR, CONFIG_CMD(dev, where));
 338         *val = GT_READ_SHORT(PCI_CFG_DATA + (where & 2));
 339
 340         return PCIBIOS_SUCCESSFUL;
 341 }
 342
 343
 344 static int galileo_read_config_dword(struct pci_dev *dev, int where,
 345                                      u32 * val)
 346 {
 347         if (EXCLUDED_DEV(dev)) {
 348                 *val = 0xffffffff;
 349                 return PCIBIOS_SUCCESSFUL;
 350         }
 351
 352         GT_WRITE(PCI_CFG_ADR, CONFIG_CMD(dev, where));
 353         *val = GT_READ(PCI_CFG_DATA);
 354
 355         return PCIBIOS_SUCCESSFUL;
 356 }
 357
 358 static int galileo_write_config_byte(struct pci_dev *dev, int where,
 359                                      u8 val)
 360 {
 361         GT_WRITE(PCI_CFG_ADR, CONFIG_CMD(dev, where));
 362
 363         GT_WRITE_BYTE(PCI_CFG_DATA + (where & 3), val);
 364
 365         return PCIBIOS_SUCCESSFUL;
 366 }
 367
 368
 369 static int galileo_write_config_word(struct pci_dev *dev, int where,
 370                                      u16 val)
 371 {
 372         GT_WRITE(PCI_CFG_ADR, CONFIG_CMD(dev, where));
 373
 374         GT_WRITE_SHORT(PCI_CFG_DATA + (where & 2), val);
 375
 376         return PCIBIOS_SUCCESSFUL;
 377 }
 378
 379 static int galileo_write_config_dword(struct pci_dev *dev, int where,
 380                                       u32 val)
 381 {
 382         GT_WRITE(PCI_CFG_ADR, CONFIG_CMD(dev, where));
 383
 384         GT_WRITE(PCI_CFG_DATA, val);
 385
 386         return PCIBIOS_SUCCESSFUL;
 387 }
 388
 389 static struct pci_ops pci_config_ops = {
 390         galileo_read_config_byte,
 391         galileo_read_config_word,
 392         galileo_read_config_dword,
 393         galileo_write_config_byte,
 394         galileo_write_config_word,
 395         galileo_write_config_dword
 396 };
 397
 398
 399 /* Everything hangs off this */
 400 static struct pci_bus *pci_root_bus;
 401
 402
 403 static u8 __init no_swizzle(struct pci_dev *dev, u8 * pin)
 404 {
 405         return PCI_SLOT(dev->devfn);
 406 }
 407
 408 static int __init map_od_irq(struct pci_dev *dev, u8 slot, u8 pin)
 409 {
 410         /* Slot 1: Galileo
 411          * Slot 2: PCI Slot 1
 412          * Slot 3: PCI Slot 2
 413          * Slot 4: ESS
 414          */
 415         switch (slot) {
 416         case 2:
 417                 return OVERDRIVE_PCI_IRQ1;
 418         case 3:
 419                 /* Note this assumes you have a hacked card in slot 2 */
 420                 return OVERDRIVE_PCI_IRQ2;
 421         case 4:
 422                 return OVERDRIVE_ESS_IRQ;
 423         default:
 424                 /* printk("PCI: Unexpected IRQ mapping request for slot %d\n", slot); */
 425                 return -1;
 426         }
 427 }
 428
 429
 430
 431 void __init
 432 pcibios_fixup_pbus_ranges(struct pci_bus *bus, struct pbus_set_ranges_data *ranges)
 433 {
 434         ranges->io_start -= bus->resource[0]->start;
 435         ranges->io_end -= bus->resource[0]->start;
 436         ranges->mem_start -= bus->resource[1]->start;
 437         ranges->mem_end -= bus->resource[1]->start;
 438 }
 439
 440 static void __init pci_fixup_ide_bases(struct pci_dev *d)
 441 {
 442         int i;
 443
 444         /*
 445          * PCI IDE controllers use non-standard I/O port decoding, respect it.
 446          */
 447         if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE)
 448                 return;
 449         printk("PCI: IDE base address fixup for %s\n", pci_name(d));
 450         for(i=0; i<4; i++) {
 451                 struct resource *r = &d->resource[i];
 452                 if ((r->start & ~0x80) == 0x374) {
 453                         r->start |= 2;
 454                         r->end = r->start;
 455                 }
 456         }
 457 }
 458 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);
 459
 460 void __init pcibios_init(void)
 461 {
 462         static struct resource galio,galmem;
 463
 464         /* Allocate the registers used by the Galileo */
 465         galio.flags = IORESOURCE_IO;
 466         galio.name  = "Galileo GT64011";
 467         galmem.flags = IORESOURCE_MEM|IORESOURCE_PREFETCH;
 468         galmem.name  = "Galileo GT64011 DRAM";
 469
 470         allocate_resource(&ioport_resource, &galio, 256,
 471                     GT64111_IO_BASE_ADDRESS,GT64111_IO_BASE_ADDRESS+256, 256, NULL, NULL);
 472         allocate_resource(&iomem_resource, &galmem,PCI_DRAM_SIZE,
 473                     PHYSADDR(PCI_DRAM_BASE), PHYSADDR(PCI_DRAM_BASE)+PCI_DRAM_SIZE,
 474                              PCI_DRAM_SIZE, NULL, NULL);
 475
 476         /* ok, do the scan man */
 477         pci_root_bus = pci_scan_bus(0, &pci_config_ops, NULL);
 478
 479         pci_assign_unassigned_resources();
 480         pci_fixup_irqs(no_swizzle, map_od_irq);
 481
 482 #ifdef TEST_DRAM
 483         printk("Testing PCI DRAM - ");
 484         if(test_dram(PCI_DRAM_BASE,PCI_DRAM_SIZE)) {
 485                 printk("Passed\n");
 486         }else {
 487                 printk("FAILED\n");
 488         }
 489 #endif
 490
 491 }
 492
 493 char * __init pcibios_setup(char *str)
 494 {
 495         return str;
 496 }
 497
 498
 499
 500 int pcibios_enable_device(struct pci_dev *dev)
 501 {
 502
 503         u16 cmd, old_cmd;
 504         int idx;
 505         struct resource *r;
 506
 507         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 508         old_cmd = cmd;
 509         for (idx = 0; idx < 6; idx++) {
 510                 r = dev->resource + idx;
 511                 if (!r->start && r->end) {
 512                         printk(KERN_ERR
 513                                "PCI: Device %s not available because"
 514                                " of resource collisions\n",
 515                                pci_name(dev));
 516                         return -EINVAL;
 517                 }
 518                 if (r->flags & IORESOURCE_IO)
 519                         cmd |= PCI_COMMAND_IO;
 520                 if (r->flags & IORESOURCE_MEM)
 521                         cmd |= PCI_COMMAND_MEMORY;
 522         }
 523         if (cmd != old_cmd) {
 524                 printk("PCI: enabling device %s (%04x -> %04x)\n",
 525                        pci_name(dev), old_cmd, cmd);
 526                 pci_write_config_word(dev, PCI_COMMAND, cmd);
 527         }
 528         return 0;
 529
 530 }
 531
 532 /* We should do some optimisation work here I think. Ok for now though */
 533 void __init pcibios_fixup_bus(struct pci_bus *bus)
 534 {
 535
 536 }
 537
 538 void pcibios_align_resource(void *data, struct resource *res,
 539                             unsigned long size)
 540 {
 541 }
 542
 543 void __init pcibios_update_resource(struct pci_dev *dev, struct resource *root,
 544                              struct resource *res, int resource)
 545 {
 546
 547         unsigned long where, size;
 548         u32 reg;
 549
 550
 551         printk("PCI: Assigning %3s %08lx to %s\n",
 552                res->flags & IORESOURCE_IO ? "IO" : "MEM",
 553                res->start, dev->name);
 554
 555         where = PCI_BASE_ADDRESS_0 + resource * 4;
 556         size = res->end - res->start;
 557
 558         pci_read_config_dword(dev, where, &reg);
 559         reg = (reg & size) | (((u32) (res->start - root->start)) & ~size);
 560         pci_write_config_dword(dev, where, reg);
 561 }
 562
 563
 564 void __init pcibios_update_irq(struct pci_dev *dev, int irq)
 565 {
 566         printk("PCI: Assigning IRQ %02d to %s\n", irq, dev->name);
 567         pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
 568 }
 569
 570 /*
 571  *  If we set up a device for bus mastering, we need to check the latency
 572  *  timer as certain crappy BIOSes forget to set it properly.
 573  */
 574 unsigned int pcibios_max_latency = 255;
 575
 576 void pcibios_set_master(struct pci_dev *dev)
 577 {
 578         u8 lat;
 579         pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
 580         if (lat < 16)
 581                 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
 582         else if (lat > pcibios_max_latency)
 583                 lat = pcibios_max_latency;
 584         else
 585                 return;
 586         printk("PCI: Setting latency timer of device %s to %d\n", pci_name(dev), lat);
 587         pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
 588 }