?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
[MIPS] update cobalt_defconfig
[pv_ops_mirror.git] / drivers / scsi / gdth.c
blob60446b88f7213c5f494dff47ae87296c4c23903a
1 /************************************************************************
2 * Linux driver for *
3 * ICP vortex GmbH: GDT ISA/EISA/PCI Disk Array Controllers *
4 * Intel Corporation: Storage RAID Controllers *
5 * *
6 * gdth.c *
7 * Copyright (C) 1995-06 ICP vortex GmbH, Achim Leubner *
8 * Copyright (C) 2002-04 Intel Corporation *
9 * Copyright (C) 2003-06 Adaptec Inc. *
10 * <achim_leubner@adaptec.com> *
11 * *
12 * Additions/Fixes: *
13 * Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com> *
14 * Johannes Dinner <johannes_dinner@adaptec.com> *
15 * *
16 * This program is free software; you can redistribute it and/or modify *
17 * it under the terms of the GNU General Public License as published *
18 * by the Free Software Foundation; either version 2 of the License, *
19 * or (at your option) any later version. *
20 * *
21 * This program is distributed in the hope that it will be useful, *
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
24 * GNU General Public License for more details. *
25 * *
26 * You should have received a copy of the GNU General Public License *
27 * along with this kernel; if not, write to the Free Software *
28 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. *
29 * *
30 * Linux kernel 2.4.x, 2.6.x supported *
31 * *
32 * $Log: gdth.c,v $
33 * Revision 1.74 2006/04/10 13:44:47 achim
34 * Community changes for 2.6.x
35 * Kernel 2.2.x no longer supported
36 * scsi_request interface removed, thanks to Christoph Hellwig
37 *
38 * Revision 1.73 2004/03/31 13:33:03 achim
39 * Special command 0xfd implemented to detect 64-bit DMA support
40 *
41 * Revision 1.72 2004/03/17 08:56:04 achim
42 * 64-bit DMA only enabled if FW >= x.43
43 *
44 * Revision 1.71 2004/03/05 15:51:29 achim
45 * Screen service: separate message buffer, bugfixes
46 *
47 * Revision 1.70 2004/02/27 12:19:07 achim
48 * Bugfix: Reset bit in config (0xfe) call removed
49 *
50 * Revision 1.69 2004/02/20 09:50:24 achim
51 * Compatibility changes for kernels < 2.4.20
52 * Bugfix screen service command size
53 * pci_set_dma_mask() error handling added
54 *
55 * Revision 1.68 2004/02/19 15:46:54 achim
56 * 64-bit DMA bugfixes
57 * Drive size bugfix for drives > 1TB
58 *
59 * Revision 1.67 2004/01/14 13:11:57 achim
60 * Tool access over /proc no longer supported
61 * Bugfixes IOCTLs
62 *
63 * Revision 1.66 2003/12/19 15:04:06 achim
64 * Bugfixes support for drives > 2TB
65 *
66 * Revision 1.65 2003/12/15 11:21:56 achim
67 * 64-bit DMA support added
68 * Support for drives > 2 TB implemented
69 * Kernels 2.2.x, 2.4.x, 2.6.x supported
70 *
71 * Revision 1.64 2003/09/17 08:30:26 achim
72 * EISA/ISA controller scan disabled
73 * Command line switch probe_eisa_isa added
74 *
75 * Revision 1.63 2003/07/12 14:01:00 Daniele Bellucci <bellucda@tiscali.it>
76 * Minor cleanups in gdth_ioctl.
77 *
78 * Revision 1.62 2003/02/27 15:01:59 achim
79 * Dynamic DMA mapping implemented
80 * New (character device) IOCTL interface added
81 * Other controller related changes made
82 *
83 * Revision 1.61 2002/11/08 13:09:52 boji
84 * Added support for XSCALE based RAID Controllers
85 * Fixed SCREENSERVICE initialization in SMP cases
86 * Added checks for gdth_polling before GDTH_HA_LOCK
87 *
88 * Revision 1.60 2002/02/05 09:35:22 achim
89 * MODULE_LICENSE only if kernel >= 2.4.11
90 *
91 * Revision 1.59 2002/01/30 09:46:33 achim
92 * Small changes
93 *
94 * Revision 1.58 2002/01/29 15:30:02 achim
95 * Set default value of shared_access to Y
96 * New status S_CACHE_RESERV for clustering added
97 *
98 * Revision 1.57 2001/08/21 11:16:35 achim
99 * Bugfix free_irq()
100 *
101 * Revision 1.56 2001/08/09 11:19:39 achim
102 * Scsi_Host_Template changes
103 *
104 * Revision 1.55 2001/08/09 10:11:28 achim
105 * Command HOST_UNFREEZE_IO before cache service init.
106 *
107 * Revision 1.54 2001/07/20 13:48:12 achim
108 * Expand: gdth_analyse_hdrive() removed
109 *
110 * Revision 1.53 2001/07/17 09:52:49 achim
111 * Small OEM related change
112 *
113 * Revision 1.52 2001/06/19 15:06:20 achim
114 * New host command GDT_UNFREEZE_IO added
115 *
116 * Revision 1.51 2001/05/22 06:42:37 achim
117 * PCI: Subdevice ID added
118 *
119 * Revision 1.50 2001/05/17 13:42:16 achim
120 * Support for Intel Storage RAID Controllers added
121 *
122 * Revision 1.50 2001/05/17 12:12:34 achim
123 * Support for Intel Storage RAID Controllers added
124 *
125 * Revision 1.49 2001/03/15 15:07:17 achim
126 * New __setup interface for boot command line options added
127 *
128 * Revision 1.48 2001/02/06 12:36:28 achim
129 * Bugfix Cluster protocol
130 *
131 * Revision 1.47 2001/01/10 14:42:06 achim
132 * New switch shared_access added
133 *
134 * Revision 1.46 2001/01/09 08:11:35 achim
135 * gdth_command() removed
136 * meaning of Scsi_Pointer members changed
137 *
138 * Revision 1.45 2000/11/16 12:02:24 achim
139 * Changes for kernel 2.4
140 *
141 * Revision 1.44 2000/10/11 08:44:10 achim
142 * Clustering changes: New flag media_changed added
143 *
144 * Revision 1.43 2000/09/20 12:59:01 achim
145 * DPMEM remap functions for all PCI controller types implemented
146 * Small changes for ia64 platform
147 *
148 * Revision 1.42 2000/07/20 09:04:50 achim
149 * Small changes for kernel 2.4
150 *
151 * Revision 1.41 2000/07/04 14:11:11 achim
152 * gdth_analyse_hdrive() added to rescan drives after online expansion
153 *
154 * Revision 1.40 2000/06/27 11:24:16 achim
155 * Changes Clustering, Screenservice
156 *
157 * Revision 1.39 2000/06/15 13:09:04 achim
158 * Changes for gdth_do_cmd()
159 *
160 * Revision 1.38 2000/06/15 12:08:43 achim
161 * Bugfix gdth_sync_event(), service SCREENSERVICE
162 * Data direction for command 0xc2 changed to DOU
163 *
164 * Revision 1.37 2000/05/25 13:50:10 achim
165 * New driver parameter virt_ctr added
166 *
167 * Revision 1.36 2000/05/04 08:50:46 achim
168 * Event buffer now in gdth_ha_str
169 *
170 * Revision 1.35 2000/03/03 10:44:08 achim
171 * New event_string only valid for the RP controller family
172 *
173 * Revision 1.34 2000/03/02 14:55:29 achim
174 * New mechanism for async. event handling implemented
175 *
176 * Revision 1.33 2000/02/21 15:37:37 achim
177 * Bugfix Alpha platform + DPMEM above 4GB
178 *
179 * Revision 1.32 2000/02/14 16:17:37 achim
180 * Bugfix sense_buffer[] + raw devices
181 *
182 * Revision 1.31 2000/02/10 10:29:00 achim
183 * Delete sense_buffer[0], if command OK
184 *
185 * Revision 1.30 1999/11/02 13:42:39 achim
186 * ARRAY_DRV_LIST2 implemented
187 * Now 255 log. and 100 host drives supported
188 *
189 * Revision 1.29 1999/10/05 13:28:47 achim
190 * GDT_CLUST_RESET added
191 *
192 * Revision 1.28 1999/08/12 13:44:54 achim
193 * MOUNTALL removed
194 * Cluster drives -> removeable drives
195 *
196 * Revision 1.27 1999/06/22 07:22:38 achim
197 * Small changes
198 *
199 * Revision 1.26 1999/06/10 16:09:12 achim
200 * Cluster Host Drive support: Bugfixes
201 *
202 * Revision 1.25 1999/06/01 16:03:56 achim
203 * gdth_init_pci(): Manipulate config. space to start RP controller
204 *
205 * Revision 1.24 1999/05/26 11:53:06 achim
206 * Cluster Host Drive support added
207 *
208 * Revision 1.23 1999/03/26 09:12:31 achim
209 * Default value for hdr_channel set to 0
210 *
211 * Revision 1.22 1999/03/22 16:27:16 achim
212 * Bugfix: gdth_store_event() must not be locked with GDTH_LOCK_HA()
213 *
214 * Revision 1.21 1999/03/16 13:40:34 achim
215 * Problems with reserved drives solved
216 * gdth_eh_bus_reset() implemented
217 *
218 * Revision 1.20 1999/03/10 09:08:13 achim
219 * Bugfix: Corrections in gdth_direction_tab[] made
220 * Bugfix: Increase command timeout (gdth_update_timeout()) NOT in gdth_putq()
221 *
222 * Revision 1.19 1999/03/05 14:38:16 achim
223 * Bugfix: Heads/Sectors mapping for reserved devices possibly wrong
224 * -> gdth_eval_mapping() implemented, changes in gdth_bios_param()
225 * INIT_RETRIES set to 100s to avoid DEINIT-Timeout for controllers
226 * with BIOS disabled and memory test set to Intensive
227 * Enhanced /proc support
228 *
229 * Revision 1.18 1999/02/24 09:54:33 achim
230 * Command line parameter hdr_channel implemented
231 * Bugfix for EISA controllers + Linux 2.2.x
232 *
233 * Revision 1.17 1998/12/17 15:58:11 achim
234 * Command line parameters implemented
235 * Changes for Alpha platforms
236 * PCI controller scan changed
237 * SMP support improved (spin_lock_irqsave(),...)
238 * New async. events, new scan/reserve commands included
239 *
240 * Revision 1.16 1998/09/28 16:08:46 achim
241 * GDT_PCIMPR: DPMEM remapping, if required
242 * mdelay() added
243 *
244 * Revision 1.15 1998/06/03 14:54:06 achim
245 * gdth_delay(), gdth_flush() implemented
246 * Bugfix: gdth_release() changed
247 *
248 * Revision 1.14 1998/05/22 10:01:17 achim
249 * mj: pcibios_strerror() removed
250 * Improved SMP support (if version >= 2.1.95)
251 * gdth_halt(): halt_called flag added (if version < 2.1)
252 *
253 * Revision 1.13 1998/04/16 09:14:57 achim
254 * Reserve drives (for raw service) implemented
255 * New error handling code enabled
256 * Get controller name from board_info() IOCTL
257 * Final round of PCI device driver patches by Martin Mares
258 *
259 * Revision 1.12 1998/03/03 09:32:37 achim
260 * Fibre channel controller support added
261 *
262 * Revision 1.11 1998/01/27 16:19:14 achim
263 * SA_SHIRQ added
264 * add_timer()/del_timer() instead of GDTH_TIMER
265 * scsi_add_timer()/scsi_del_timer() instead of SCSI_TIMER
266 * New error handling included
267 *
268 * Revision 1.10 1997/10/31 12:29:57 achim
269 * Read heads/sectors from host drive
270 *
271 * Revision 1.9 1997/09/04 10:07:25 achim
272 * IO-mapping with virt_to_bus(), gdth_readb(), gdth_writeb(), ...
273 * register_reboot_notifier() to get a notify on shutown used
274 *
275 * Revision 1.8 1997/04/02 12:14:30 achim
276 * Version 1.00 (see gdth.h), tested with kernel 2.0.29
277 *
278 * Revision 1.7 1997/03/12 13:33:37 achim
279 * gdth_reset() changed, new async. events
280 *
281 * Revision 1.6 1997/03/04 14:01:11 achim
282 * Shutdown routine gdth_halt() implemented
283 *
284 * Revision 1.5 1997/02/21 09:08:36 achim
285 * New controller included (RP, RP1, RP2 series)
286 * IOCTL interface implemented
287 *
288 * Revision 1.4 1996/07/05 12:48:55 achim
289 * Function gdth_bios_param() implemented
290 * New constant GDTH_MAXC_P_L inserted
291 * GDT_WRITE_THR, GDT_EXT_INFO implemented
292 * Function gdth_reset() changed
293 *
294 * Revision 1.3 1996/05/10 09:04:41 achim
295 * Small changes for Linux 1.2.13
296 *
297 * Revision 1.2 1996/05/09 12:45:27 achim
298 * Loadable module support implemented
299 * /proc support corrections made
300 *
301 * Revision 1.1 1996/04/11 07:35:57 achim
302 * Initial revision
303 *
304 ************************************************************************/
305
306 /* All GDT Disk Array Controllers are fully supported by this driver.
307 * This includes the PCI/EISA/ISA SCSI Disk Array Controllers and the
308 * PCI Fibre Channel Disk Array Controllers. See gdth.h for a complete
309 * list of all controller types.
310 *
311 * If you have one or more GDT3000/3020 EISA controllers with
312 * controller BIOS disabled, you have to set the IRQ values with the
313 * command line option "gdth=irq1,irq2,...", where the irq1,irq2,... are
314 * the IRQ values for the EISA controllers.
315 *
316 * After the optional list of IRQ values, other possible
317 * command line options are:
318 * disable:Y disable driver
319 * disable:N enable driver
320 * reserve_mode:0 reserve no drives for the raw service
321 * reserve_mode:1 reserve all not init., removable drives
322 * reserve_mode:2 reserve all not init. drives
323 * reserve_list:h,b,t,l,h,b,t,l,... reserve particular drive(s) with
324 * h- controller no., b- channel no.,
325 * t- target ID, l- LUN
326 * reverse_scan:Y reverse scan order for PCI controllers
327 * reverse_scan:N scan PCI controllers like BIOS
328 * max_ids:x x - target ID count per channel (1..MAXID)
329 * rescan:Y rescan all channels/IDs
330 * rescan:N use all devices found until now
331 * virt_ctr:Y map every channel to a virtual controller
332 * virt_ctr:N use multi channel support
333 * hdr_channel:x x - number of virtual bus for host drives
334 * shared_access:Y disable driver reserve/release protocol to
335 * access a shared resource from several nodes,
336 * appropriate controller firmware required
337 * shared_access:N enable driver reserve/release protocol
338 * probe_eisa_isa:Y scan for EISA/ISA controllers
339 * probe_eisa_isa:N do not scan for EISA/ISA controllers
340 * force_dma32:Y use only 32 bit DMA mode
341 * force_dma32:N use 64 bit DMA mode, if supported
342 *
343 * The default values are: "gdth=disable:N,reserve_mode:1,reverse_scan:N,
344 * max_ids:127,rescan:N,virt_ctr:N,hdr_channel:0,
345 * shared_access:Y,probe_eisa_isa:N,force_dma32:N".
346 * Here is another example: "gdth=reserve_list:0,1,2,0,0,1,3,0,rescan:Y".
347 *
348 * When loading the gdth driver as a module, the same options are available.
349 * You can set the IRQs with "IRQ=...". However, the syntax to specify the
350 * options changes slightly. You must replace all ',' between options
351 * with ' ' and all ':' with '=' and you must use
352 * '1' in place of 'Y' and '0' in place of 'N'.
353 *
354 * Default: "modprobe gdth disable=0 reserve_mode=1 reverse_scan=0
355 * max_ids=127 rescan=0 virt_ctr=0 hdr_channel=0 shared_access=0
356 * probe_eisa_isa=0 force_dma32=0"
357 * The other example: "modprobe gdth reserve_list=0,1,2,0,0,1,3,0 rescan=1".
358 */
359
360 /* The meaning of the Scsi_Pointer members in this driver is as follows:
361 * ptr: Chaining
362 * this_residual: Command priority
363 * buffer: phys. DMA sense buffer
364 * dma_handle: phys. DMA buffer (kernel >= 2.4.0)
365 * buffers_residual: Timeout value
366 * Status: Command status (gdth_do_cmd()), DMA mem. mappings
367 * Message: Additional info (gdth_do_cmd()), DMA direction
368 * have_data_in: Flag for gdth_wait_completion()
369 * sent_command: Opcode special command
370 * phase: Service/parameter/return code special command
371 */
372
373
374 /* interrupt coalescing */
375 /* #define INT_COAL */
376
377 /* statistics */
378 #define GDTH_STATISTICS
379
380 #include <linux/module.h>
381
382 #include <linux/version.h>
383 #include <linux/kernel.h>
384 #include <linux/types.h>
385 #include <linux/pci.h>
386 #include <linux/string.h>
387 #include <linux/ctype.h>
388 #include <linux/ioport.h>
389 #include <linux/delay.h>
390 #include <linux/interrupt.h>
391 #include <linux/in.h>
392 #include <linux/proc_fs.h>
393 #include <linux/time.h>
394 #include <linux/timer.h>
395 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,6)
396 #include <linux/dma-mapping.h>
397 #else
398 #define DMA_32BIT_MASK 0x00000000ffffffffULL
399 #define DMA_64BIT_MASK 0xffffffffffffffffULL
400 #endif
401
402 #ifdef GDTH_RTC
403 #include <linux/mc146818rtc.h>
404 #endif
405 #include <linux/reboot.h>
406
407 #include <asm/dma.h>
408 #include <asm/system.h>
409 #include <asm/io.h>
410 #include <asm/uaccess.h>
411 #include <linux/spinlock.h>
412 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
413 #include <linux/blkdev.h>
414 #else
415 #include <linux/blk.h>
416 #include "sd.h"
417 #endif
418
419 #include "scsi.h"
420 #include <scsi/scsi_host.h>
421 #include "gdth_kcompat.h"
422 #include "gdth.h"
423
424 static void gdth_delay(int milliseconds);
425 static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs);
426 static irqreturn_t gdth_interrupt(int irq, void *dev_id);
427 static int gdth_sync_event(int hanum,int service,unchar index,Scsi_Cmnd *scp);
428 static int gdth_async_event(int hanum);
429 static void gdth_log_event(gdth_evt_data *dvr, char *buffer);
430
431 static void gdth_putq(int hanum,Scsi_Cmnd *scp,unchar priority);
432 static void gdth_next(int hanum);
433 static int gdth_fill_raw_cmd(int hanum,Scsi_Cmnd *scp,unchar b);
434 static int gdth_special_cmd(int hanum,Scsi_Cmnd *scp);
435 static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source,
436 ushort idx, gdth_evt_data *evt);
437 static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr);
438 static void gdth_readapp_event(gdth_ha_str *ha, unchar application,
439 gdth_evt_str *estr);
440 static void gdth_clear_events(void);
441
442 static void gdth_copy_internal_data(int hanum,Scsi_Cmnd *scp,
443 char *buffer,ushort count);
444 static int gdth_internal_cache_cmd(int hanum,Scsi_Cmnd *scp);
445 static int gdth_fill_cache_cmd(int hanum,Scsi_Cmnd *scp,ushort hdrive);
446
447 static int gdth_search_eisa(ushort eisa_adr);
448 static int gdth_search_isa(ulong32 bios_adr);
449 static int gdth_search_pci(gdth_pci_str *pcistr);
450 static void gdth_search_dev(gdth_pci_str *pcistr, ushort *cnt,
451 ushort vendor, ushort dev);
452 static void gdth_sort_pci(gdth_pci_str *pcistr, int cnt);
453 static int gdth_init_eisa(ushort eisa_adr,gdth_ha_str *ha);
454 static int gdth_init_isa(ulong32 bios_adr,gdth_ha_str *ha);
455 static int gdth_init_pci(gdth_pci_str *pcistr,gdth_ha_str *ha);
456
457 static void gdth_enable_int(int hanum);
458 static int gdth_get_status(unchar *pIStatus,int irq);
459 static int gdth_test_busy(int hanum);
460 static int gdth_get_cmd_index(int hanum);
461 static void gdth_release_event(int hanum);
462 static int gdth_wait(int hanum,int index,ulong32 time);
463 static int gdth_internal_cmd(int hanum,unchar service,ushort opcode,ulong32 p1,
464 ulong64 p2,ulong64 p3);
465 static int gdth_search_drives(int hanum);
466 static int gdth_analyse_hdrive(int hanum, ushort hdrive);
467
468 static const char *gdth_ctr_name(int hanum);
469
470 static int gdth_open(struct inode *inode, struct file *filep);
471 static int gdth_close(struct inode *inode, struct file *filep);
472 static int gdth_ioctl(struct inode *inode, struct file *filep,
473 unsigned int cmd, unsigned long arg);
474
475 static void gdth_flush(int hanum);
476 static int gdth_halt(struct notifier_block *nb, ulong event, void *buf);
477 static int gdth_queuecommand(Scsi_Cmnd *scp,void (*done)(Scsi_Cmnd *));
478 static void gdth_scsi_done(struct scsi_cmnd *scp);
479
480 #ifdef DEBUG_GDTH
481 static unchar DebugState = DEBUG_GDTH;
482
483 #ifdef __SERIAL__
484 #define MAX_SERBUF 160
485 static void ser_init(void);
486 static void ser_puts(char *str);
487 static void ser_putc(char c);
488 static int ser_printk(const char *fmt, ...);
489 static char strbuf[MAX_SERBUF+1];
490 #ifdef __COM2__
491 #define COM_BASE 0x2f8
492 #else
493 #define COM_BASE 0x3f8
494 #endif
495 static void ser_init()
496 {
497 unsigned port=COM_BASE;
498
499 outb(0x80,port+3);
500 outb(0,port+1);
501 /* 19200 Baud, if 9600: outb(12,port) */
502 outb(6, port);
503 outb(3,port+3);
504 outb(0,port+1);
505 /*
506 ser_putc('I');
507 ser_putc(' ');
508 */
509 }
510
511 static void ser_puts(char *str)
512 {
513 char *ptr;
514
515 ser_init();
516 for (ptr=str;*ptr;++ptr)
517 ser_putc(*ptr);
518 }
519
520 static void ser_putc(char c)
521 {
522 unsigned port=COM_BASE;
523
524 while ((inb(port+5) & 0x20)==0);
525 outb(c,port);
526 if (c==0x0a)
527 {
528 while ((inb(port+5) & 0x20)==0);
529 outb(0x0d,port);
530 }
531 }
532
533 static int ser_printk(const char *fmt, ...)
534 {
535 va_list args;
536 int i;
537
538 va_start(args,fmt);
539 i = vsprintf(strbuf,fmt,args);
540 ser_puts(strbuf);
541 va_end(args);
542 return i;
543 }
544
545 #define TRACE(a) {if (DebugState==1) {ser_printk a;}}
546 #define TRACE2(a) {if (DebugState==1 || DebugState==2) {ser_printk a;}}
547 #define TRACE3(a) {if (DebugState!=0) {ser_printk a;}}
548
549 #else /* !__SERIAL__ */
550 #define TRACE(a) {if (DebugState==1) {printk a;}}
551 #define TRACE2(a) {if (DebugState==1 || DebugState==2) {printk a;}}
552 #define TRACE3(a) {if (DebugState!=0) {printk a;}}
553 #endif
554
555 #else /* !DEBUG */
556 #define TRACE(a)
557 #define TRACE2(a)
558 #define TRACE3(a)
559 #endif
560
561 #ifdef GDTH_STATISTICS
562 static ulong32 max_rq=0, max_index=0, max_sg=0;
563 #ifdef INT_COAL
564 static ulong32 max_int_coal=0;
565 #endif
566 static ulong32 act_ints=0, act_ios=0, act_stats=0, act_rq=0;
567 static struct timer_list gdth_timer;
568 #endif
569
570 #define PTR2USHORT(a) (ushort)(ulong)(a)
571 #define GDTOFFSOF(a,b) (size_t)&(((a*)0)->b)
572 #define INDEX_OK(i,t) ((i)<ARRAY_SIZE(t))
573
574 #define NUMDATA(a) ( (gdth_num_str *)((a)->hostdata))
575 #define HADATA(a) (&((gdth_ext_str *)((a)->hostdata))->haext)
576 #define CMDDATA(a) (&((gdth_ext_str *)((a)->hostdata))->cmdext)
577
578 #define BUS_L2P(a,b) ((b)>(a)->virt_bus ? (b-1):(b))
579
580 #define gdth_readb(addr) readb(addr)
581 #define gdth_readw(addr) readw(addr)
582 #define gdth_readl(addr) readl(addr)
583 #define gdth_writeb(b,addr) writeb((b),(addr))
584 #define gdth_writew(b,addr) writew((b),(addr))
585 #define gdth_writel(b,addr) writel((b),(addr))
586
587 static unchar gdth_drq_tab[4] = {5,6,7,7}; /* DRQ table */
588 static unchar gdth_irq_tab[6] = {0,10,11,12,14,0}; /* IRQ table */
589 static unchar gdth_polling; /* polling if TRUE */
590 static unchar gdth_from_wait = FALSE; /* gdth_wait() */
591 static int wait_index,wait_hanum; /* gdth_wait() */
592 static int gdth_ctr_count = 0; /* controller count */
593 static int gdth_ctr_vcount = 0; /* virt. ctr. count */
594 static int gdth_ctr_released = 0; /* gdth_release() */
595 static struct Scsi_Host *gdth_ctr_tab[MAXHA]; /* controller table */
596 static struct Scsi_Host *gdth_ctr_vtab[MAXHA*MAXBUS]; /* virt. ctr. table */
597 static unchar gdth_write_through = FALSE; /* write through */
598 static gdth_evt_str ebuffer[MAX_EVENTS]; /* event buffer */
599 static int elastidx;
600 static int eoldidx;
601 static int major;
602
603 #define DIN 1 /* IN data direction */
604 #define DOU 2 /* OUT data direction */
605 #define DNO DIN /* no data transfer */
606 #define DUN DIN /* unknown data direction */
607 static unchar gdth_direction_tab[0x100] = {
608 DNO,DNO,DIN,DIN,DOU,DIN,DIN,DOU,DIN,DUN,DOU,DOU,DUN,DUN,DUN,DIN,
609 DNO,DIN,DIN,DOU,DIN,DOU,DNO,DNO,DOU,DNO,DIN,DNO,DIN,DOU,DNO,DUN,
610 DIN,DUN,DIN,DUN,DOU,DIN,DUN,DUN,DIN,DIN,DOU,DNO,DUN,DIN,DOU,DOU,
611 DOU,DOU,DOU,DNO,DIN,DNO,DNO,DIN,DOU,DOU,DOU,DOU,DIN,DOU,DIN,DOU,
612 DOU,DOU,DIN,DIN,DIN,DNO,DUN,DNO,DNO,DNO,DUN,DNO,DOU,DIN,DUN,DUN,
613 DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DIN,DUN,DUN,DUN,DUN,DUN,
614 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
615 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
616 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
617 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,
618 DUN,DUN,DUN,DUN,DUN,DNO,DNO,DUN,DIN,DNO,DOU,DUN,DNO,DUN,DOU,DOU,
619 DOU,DOU,DOU,DNO,DUN,DIN,DOU,DIN,DIN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
620 DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
621 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
622 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
623 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN
624 };
625
626 /* LILO and modprobe/insmod parameters */
627 /* IRQ list for GDT3000/3020 EISA controllers */
628 static int irq[MAXHA] __initdata =
629 {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
630 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
631 /* disable driver flag */
632 static int disable __initdata = 0;
633 /* reserve flag */
634 static int reserve_mode = 1;
635 /* reserve list */
636 static int reserve_list[MAX_RES_ARGS] =
637 {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
638 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
639 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
640 /* scan order for PCI controllers */
641 static int reverse_scan = 0;
642 /* virtual channel for the host drives */
643 static int hdr_channel = 0;
644 /* max. IDs per channel */
645 static int max_ids = MAXID;
646 /* rescan all IDs */
647 static int rescan = 0;
648 /* map channels to virtual controllers */
649 static int virt_ctr = 0;
650 /* shared access */
651 static int shared_access = 1;
652 /* enable support for EISA and ISA controllers */
653 static int probe_eisa_isa = 0;
654 /* 64 bit DMA mode, support for drives > 2 TB, if force_dma32 = 0 */
655 static int force_dma32 = 0;
656
657 /* parameters for modprobe/insmod */
658 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,11)
659 module_param_array(irq, int, NULL, 0);
660 module_param(disable, int, 0);
661 module_param(reserve_mode, int, 0);
662 module_param_array(reserve_list, int, NULL, 0);
663 module_param(reverse_scan, int, 0);
664 module_param(hdr_channel, int, 0);
665 module_param(max_ids, int, 0);
666 module_param(rescan, int, 0);
667 module_param(virt_ctr, int, 0);
668 module_param(shared_access, int, 0);
669 module_param(probe_eisa_isa, int, 0);
670 module_param(force_dma32, int, 0);
671 #else
672 MODULE_PARM(irq, "i");
673 MODULE_PARM(disable, "i");
674 MODULE_PARM(reserve_mode, "i");
675 MODULE_PARM(reserve_list, "4-" __MODULE_STRING(MAX_RES_ARGS) "i");
676 MODULE_PARM(reverse_scan, "i");
677 MODULE_PARM(hdr_channel, "i");
678 MODULE_PARM(max_ids, "i");
679 MODULE_PARM(rescan, "i");
680 MODULE_PARM(virt_ctr, "i");
681 MODULE_PARM(shared_access, "i");
682 MODULE_PARM(probe_eisa_isa, "i");
683 MODULE_PARM(force_dma32, "i");
684 #endif
685 MODULE_AUTHOR("Achim Leubner");
686 MODULE_LICENSE("GPL");
687
688 /* ioctl interface */
689 static const struct file_operations gdth_fops = {
690 .ioctl = gdth_ioctl,
691 .open = gdth_open,
692 .release = gdth_close,
693 };
694
695 #include "gdth_proc.h"
696 #include "gdth_proc.c"
697
698 /* notifier block to get a notify on system shutdown/halt/reboot */
699 static struct notifier_block gdth_notifier = {
700 gdth_halt, NULL, 0
701 };
702 static int notifier_disabled = 0;
703
704 static void gdth_delay(int milliseconds)
705 {
706 if (milliseconds == 0) {
707 udelay(1);
708 } else {
709 mdelay(milliseconds);
710 }
711 }
712
713 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
714 static void gdth_scsi_done(struct scsi_cmnd *scp)
715 {
716 TRACE2(("gdth_scsi_done()\n"));
717
718 if (scp->request)
719 complete((struct completion *)scp->request);
720 }
721
722 int __gdth_execute(struct scsi_device *sdev, gdth_cmd_str *gdtcmd, char *cmnd,
723 int timeout, u32 *info)
724 {
725 Scsi_Cmnd *scp;
726 DECLARE_COMPLETION_ONSTACK(wait);
727 int rval;
728
729 scp = kmalloc(sizeof(*scp), GFP_KERNEL);
730 if (!scp)
731 return -ENOMEM;
732 memset(scp, 0, sizeof(*scp));
733 scp->device = sdev;
734 /* use request field to save the ptr. to completion struct. */
735 scp->request = (struct request *)&wait;
736 scp->timeout_per_command = timeout*HZ;
737 scp->request_buffer = gdtcmd;
738 scp->cmd_len = 12;
739 memcpy(scp->cmnd, cmnd, 12);
740 scp->SCp.this_residual = IOCTL_PRI; /* priority */
741 scp->done = gdth_scsi_done; /* some fn. test this */
742 gdth_queuecommand(scp, gdth_scsi_done);
743 wait_for_completion(&wait);
744
745 rval = scp->SCp.Status;
746 if (info)
747 *info = scp->SCp.Message;
748 kfree(scp);
749 return rval;
750 }
751 #else
752 static void gdth_scsi_done(Scsi_Cmnd *scp)
753 {
754 TRACE2(("gdth_scsi_done()\n"));
755
756 scp->request.rq_status = RQ_SCSI_DONE;
757 if (scp->request.waiting)
758 complete(scp->request.waiting);
759 }
760
761 int __gdth_execute(struct scsi_device *sdev, gdth_cmd_str *gdtcmd, char *cmnd,
762 int timeout, u32 *info)
763 {
764 Scsi_Cmnd *scp = scsi_allocate_device(sdev, 1, FALSE);
765 unsigned bufflen = gdtcmd ? sizeof(gdth_cmd_str) : 0;
766 DECLARE_COMPLETION_ONSTACK(wait);
767 int rval;
768
769 if (!scp)
770 return -ENOMEM;
771 scp->cmd_len = 12;
772 scp->use_sg = 0;
773 scp->SCp.this_residual = IOCTL_PRI; /* priority */
774 scp->request.rq_status = RQ_SCSI_BUSY;
775 scp->request.waiting = &wait;
776 scsi_do_cmd(scp, cmnd, gdtcmd, bufflen, gdth_scsi_done, timeout*HZ, 1);
777 wait_for_completion(&wait);
778
779 rval = scp->SCp.Status;
780 if (info)
781 *info = scp->SCp.Message;
782
783 scsi_release_command(scp);
784 return rval;
785 }
786 #endif
787
788 int gdth_execute(struct Scsi_Host *shost, gdth_cmd_str *gdtcmd, char *cmnd,
789 int timeout, u32 *info)
790 {
791 struct scsi_device *sdev = scsi_get_host_dev(shost);
792 int rval = __gdth_execute(sdev, gdtcmd, cmnd, timeout, info);
793
794 scsi_free_host_dev(sdev);
795 return rval;
796 }
797
798 static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs)
799 {
800 *cyls = size /HEADS/SECS;
801 if (*cyls <= MAXCYLS) {
802 *heads = HEADS;
803 *secs = SECS;
804 } else { /* too high for 64*32 */
805 *cyls = size /MEDHEADS/MEDSECS;
806 if (*cyls <= MAXCYLS) {
807 *heads = MEDHEADS;
808 *secs = MEDSECS;
809 } else { /* too high for 127*63 */
810 *cyls = size /BIGHEADS/BIGSECS;
811 *heads = BIGHEADS;
812 *secs = BIGSECS;
813 }
814 }
815 }
816
817 /* controller search and initialization functions */
818
819 static int __init gdth_search_eisa(ushort eisa_adr)
820 {
821 ulong32 id;
822
823 TRACE(("gdth_search_eisa() adr. %x\n",eisa_adr));
824 id = inl(eisa_adr+ID0REG);
825 if (id == GDT3A_ID || id == GDT3B_ID) { /* GDT3000A or GDT3000B */
826 if ((inb(eisa_adr+EISAREG) & 8) == 0)
827 return 0; /* not EISA configured */
828 return 1;
829 }
830 if (id == GDT3_ID) /* GDT3000 */
831 return 1;
832
833 return 0;
834 }
835
836
837 static int __init gdth_search_isa(ulong32 bios_adr)
838 {
839 void __iomem *addr;
840 ulong32 id;
841
842 TRACE(("gdth_search_isa() bios adr. %x\n",bios_adr));
843 if ((addr = ioremap(bios_adr+BIOS_ID_OFFS, sizeof(ulong32))) != NULL) {
844 id = gdth_readl(addr);
845 iounmap(addr);
846 if (id == GDT2_ID) /* GDT2000 */
847 return 1;
848 }
849 return 0;
850 }
851
852
853 static int __init gdth_search_pci(gdth_pci_str *pcistr)
854 {
855 ushort device, cnt;
856
857 TRACE(("gdth_search_pci()\n"));
858
859 cnt = 0;
860 for (device = 0; device <= PCI_DEVICE_ID_VORTEX_GDT6555; ++device)
861 gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX, device);
862 for (device = PCI_DEVICE_ID_VORTEX_GDT6x17RP;
863 device <= PCI_DEVICE_ID_VORTEX_GDTMAXRP; ++device)
864 gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX, device);
865 gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX,
866 PCI_DEVICE_ID_VORTEX_GDTNEWRX);
867 gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX,
868 PCI_DEVICE_ID_VORTEX_GDTNEWRX2);
869 gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_INTEL,
870 PCI_DEVICE_ID_INTEL_SRC);
871 gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_INTEL,
872 PCI_DEVICE_ID_INTEL_SRC_XSCALE);
873 return cnt;
874 }
875
876 /* Vortex only makes RAID controllers.
877 * We do not really want to specify all 550 ids here, so wildcard match.
878 */
879 static struct pci_device_id gdthtable[] __attribute_used__ = {
880 {PCI_VENDOR_ID_VORTEX,PCI_ANY_ID,PCI_ANY_ID, PCI_ANY_ID},
881 {PCI_VENDOR_ID_INTEL,PCI_DEVICE_ID_INTEL_SRC,PCI_ANY_ID,PCI_ANY_ID},
882 {PCI_VENDOR_ID_INTEL,PCI_DEVICE_ID_INTEL_SRC_XSCALE,PCI_ANY_ID,PCI_ANY_ID},
883 {0}
884 };
885 MODULE_DEVICE_TABLE(pci,gdthtable);
886
887 static void __init gdth_search_dev(gdth_pci_str *pcistr, ushort *cnt,
888 ushort vendor, ushort device)
889 {
890 ulong base0, base1, base2;
891 struct pci_dev *pdev;
892
893 TRACE(("gdth_search_dev() cnt %d vendor %x device %x\n",
894 *cnt, vendor, device));
895
896 pdev = NULL;
897 while ((pdev = pci_find_device(vendor, device, pdev))
898 != NULL) {
899 if (pci_enable_device(pdev))
900 continue;
901 if (*cnt >= MAXHA)
902 return;
903 /* GDT PCI controller found, resources are already in pdev */
904 pcistr[*cnt].pdev = pdev;
905 pcistr[*cnt].vendor_id = vendor;
906 pcistr[*cnt].device_id = device;
907 pcistr[*cnt].subdevice_id = pdev->subsystem_device;
908 pcistr[*cnt].bus = pdev->bus->number;
909 pcistr[*cnt].device_fn = pdev->devfn;
910 pcistr[*cnt].irq = pdev->irq;
911 base0 = pci_resource_flags(pdev, 0);
912 base1 = pci_resource_flags(pdev, 1);
913 base2 = pci_resource_flags(pdev, 2);
914 if (device <= PCI_DEVICE_ID_VORTEX_GDT6000B || /* GDT6000/B */
915 device >= PCI_DEVICE_ID_VORTEX_GDT6x17RP) { /* MPR */
916 if (!(base0 & IORESOURCE_MEM))
917 continue;
918 pcistr[*cnt].dpmem = pci_resource_start(pdev, 0);
919 } else { /* GDT6110, GDT6120, .. */
920 if (!(base0 & IORESOURCE_MEM) ||
921 !(base2 & IORESOURCE_MEM) ||
922 !(base1 & IORESOURCE_IO))
923 continue;
924 pcistr[*cnt].dpmem = pci_resource_start(pdev, 2);
925 pcistr[*cnt].io_mm = pci_resource_start(pdev, 0);
926 pcistr[*cnt].io = pci_resource_start(pdev, 1);
927 }
928 TRACE2(("Controller found at %d/%d, irq %d, dpmem 0x%lx\n",
929 pcistr[*cnt].bus, PCI_SLOT(pcistr[*cnt].device_fn),
930 pcistr[*cnt].irq, pcistr[*cnt].dpmem));
931 (*cnt)++;
932 }
933 }
934
935
936 static void __init gdth_sort_pci(gdth_pci_str *pcistr, int cnt)
937 {
938 gdth_pci_str temp;
939 int i, changed;
940
941 TRACE(("gdth_sort_pci() cnt %d\n",cnt));
942 if (cnt == 0)
943 return;
944
945 do {
946 changed = FALSE;
947 for (i = 0; i < cnt-1; ++i) {
948 if (!reverse_scan) {
949 if ((pcistr[i].bus > pcistr[i+1].bus) ||
950 (pcistr[i].bus == pcistr[i+1].bus &&
951 PCI_SLOT(pcistr[i].device_fn) >
952 PCI_SLOT(pcistr[i+1].device_fn))) {
953 temp = pcistr[i];
954 pcistr[i] = pcistr[i+1];
955 pcistr[i+1] = temp;
956 changed = TRUE;
957 }
958 } else {
959 if ((pcistr[i].bus < pcistr[i+1].bus) ||
960 (pcistr[i].bus == pcistr[i+1].bus &&
961 PCI_SLOT(pcistr[i].device_fn) <
962 PCI_SLOT(pcistr[i+1].device_fn))) {
963 temp = pcistr[i];
964 pcistr[i] = pcistr[i+1];
965 pcistr[i+1] = temp;
966 changed = TRUE;
967 }
968 }
969 }
970 } while (changed);
971 }
972
973
974 static int __init gdth_init_eisa(ushort eisa_adr,gdth_ha_str *ha)
975 {
976 ulong32 retries,id;
977 unchar prot_ver,eisacf,i,irq_found;
978
979 TRACE(("gdth_init_eisa() adr. %x\n",eisa_adr));
980
981 /* disable board interrupts, deinitialize services */
982 outb(0xff,eisa_adr+EDOORREG);
983 outb(0x00,eisa_adr+EDENABREG);
984 outb(0x00,eisa_adr+EINTENABREG);
985
986 outb(0xff,eisa_adr+LDOORREG);
987 retries = INIT_RETRIES;
988 gdth_delay(20);
989 while (inb(eisa_adr+EDOORREG) != 0xff) {
990 if (--retries == 0) {
991 printk("GDT-EISA: Initialization error (DEINIT failed)\n");
992 return 0;
993 }
994 gdth_delay(1);
995 TRACE2(("wait for DEINIT: retries=%d\n",retries));
996 }
997 prot_ver = inb(eisa_adr+MAILBOXREG);
998 outb(0xff,eisa_adr+EDOORREG);
999 if (prot_ver != PROTOCOL_VERSION) {
1000 printk("GDT-EISA: Illegal protocol version\n");
1001 return 0;
1002 }
1003 ha->bmic = eisa_adr;
1004 ha->brd_phys = (ulong32)eisa_adr >> 12;
1005
1006 outl(0,eisa_adr+MAILBOXREG);
1007 outl(0,eisa_adr+MAILBOXREG+4);
1008 outl(0,eisa_adr+MAILBOXREG+8);
1009 outl(0,eisa_adr+MAILBOXREG+12);
1010
1011 /* detect IRQ */
1012 if ((id = inl(eisa_adr+ID0REG)) == GDT3_ID) {
1013 ha->oem_id = OEM_ID_ICP;
1014 ha->type = GDT_EISA;
1015 ha->stype = id;
1016 outl(1,eisa_adr+MAILBOXREG+8);
1017 outb(0xfe,eisa_adr+LDOORREG);
1018 retries = INIT_RETRIES;
1019 gdth_delay(20);
1020 while (inb(eisa_adr+EDOORREG) != 0xfe) {
1021 if (--retries == 0) {
1022 printk("GDT-EISA: Initialization error (get IRQ failed)\n");
1023 return 0;
1024 }
1025 gdth_delay(1);
1026 }
1027 ha->irq = inb(eisa_adr+MAILBOXREG);
1028 outb(0xff,eisa_adr+EDOORREG);
1029 TRACE2(("GDT3000/3020: IRQ=%d\n",ha->irq));
1030 /* check the result */
1031 if (ha->irq == 0) {
1032 TRACE2(("Unknown IRQ, use IRQ table from cmd line !\n"));
1033 for (i = 0, irq_found = FALSE;
1034 i < MAXHA && irq[i] != 0xff; ++i) {
1035 if (irq[i]==10 || irq[i]==11 || irq[i]==12 || irq[i]==14) {
1036 irq_found = TRUE;
1037 break;
1038 }
1039 }
1040 if (irq_found) {
1041 ha->irq = irq[i];
1042 irq[i] = 0;
1043 printk("GDT-EISA: Can not detect controller IRQ,\n");
1044 printk("Use IRQ setting from command line (IRQ = %d)\n",
1045 ha->irq);
1046 } else {
1047 printk("GDT-EISA: Initialization error (unknown IRQ), Enable\n");
1048 printk("the controller BIOS or use command line parameters\n");
1049 return 0;
1050 }
1051 }
1052 } else {
1053 eisacf = inb(eisa_adr+EISAREG) & 7;
1054 if (eisacf > 4) /* level triggered */
1055 eisacf -= 4;
1056 ha->irq = gdth_irq_tab[eisacf];
1057 ha->oem_id = OEM_ID_ICP;
1058 ha->type = GDT_EISA;
1059 ha->stype = id;
1060 }
1061
1062 ha->dma64_support = 0;
1063 return 1;
1064 }
1065
1066
1067 static int __init gdth_init_isa(ulong32 bios_adr,gdth_ha_str *ha)
1068 {
1069 register gdt2_dpram_str __iomem *dp2_ptr;
1070 int i;
1071 unchar irq_drq,prot_ver;
1072 ulong32 retries;
1073
1074 TRACE(("gdth_init_isa() bios adr. %x\n",bios_adr));
1075
1076 ha->brd = ioremap(bios_adr, sizeof(gdt2_dpram_str));
1077 if (ha->brd == NULL) {
1078 printk("GDT-ISA: Initialization error (DPMEM remap error)\n");
1079 return 0;
1080 }
1081 dp2_ptr = ha->brd;
1082 gdth_writeb(1, &dp2_ptr->io.memlock); /* switch off write protection */
1083 /* reset interface area */
1084 memset_io(&dp2_ptr->u, 0, sizeof(dp2_ptr->u));
1085 if (gdth_readl(&dp2_ptr->u) != 0) {
1086 printk("GDT-ISA: Initialization error (DPMEM write error)\n");
1087 iounmap(ha->brd);
1088 return 0;
1089 }
1090
1091 /* disable board interrupts, read DRQ and IRQ */
1092 gdth_writeb(0xff, &dp2_ptr->io.irqdel);
1093 gdth_writeb(0x00, &dp2_ptr->io.irqen);
1094 gdth_writeb(0x00, &dp2_ptr->u.ic.S_Status);
1095 gdth_writeb(0x00, &dp2_ptr->u.ic.Cmd_Index);
1096
1097 irq_drq = gdth_readb(&dp2_ptr->io.rq);
1098 for (i=0; i<3; ++i) {
1099 if ((irq_drq & 1)==0)
1100 break;
1101 irq_drq >>= 1;
1102 }
1103 ha->drq = gdth_drq_tab[i];
1104
1105 irq_drq = gdth_readb(&dp2_ptr->io.rq) >> 3;
1106 for (i=1; i<5; ++i) {
1107 if ((irq_drq & 1)==0)
1108 break;
1109 irq_drq >>= 1;
1110 }
1111 ha->irq = gdth_irq_tab[i];
1112
1113 /* deinitialize services */
1114 gdth_writel(bios_adr, &dp2_ptr->u.ic.S_Info[0]);
1115 gdth_writeb(0xff, &dp2_ptr->u.ic.S_Cmd_Indx);
1116 gdth_writeb(0, &dp2_ptr->io.event);
1117 retries = INIT_RETRIES;
1118 gdth_delay(20);
1119 while (gdth_readb(&dp2_ptr->u.ic.S_Status) != 0xff) {
1120 if (--retries == 0) {
1121 printk("GDT-ISA: Initialization error (DEINIT failed)\n");
1122 iounmap(ha->brd);
1123 return 0;
1124 }
1125 gdth_delay(1);
1126 }
1127 prot_ver = (unchar)gdth_readl(&dp2_ptr->u.ic.S_Info[0]);
1128 gdth_writeb(0, &dp2_ptr->u.ic.Status);
1129 gdth_writeb(0xff, &dp2_ptr->io.irqdel);
1130 if (prot_ver != PROTOCOL_VERSION) {
1131 printk("GDT-ISA: Illegal protocol version\n");
1132 iounmap(ha->brd);
1133 return 0;
1134 }
1135
1136 ha->oem_id = OEM_ID_ICP;
1137 ha->type = GDT_ISA;
1138 ha->ic_all_size = sizeof(dp2_ptr->u);
1139 ha->stype= GDT2_ID;
1140 ha->brd_phys = bios_adr >> 4;
1141
1142 /* special request to controller BIOS */
1143 gdth_writel(0x00, &dp2_ptr->u.ic.S_Info[0]);
1144 gdth_writel(0x00, &dp2_ptr->u.ic.S_Info[1]);
1145 gdth_writel(0x01, &dp2_ptr->u.ic.S_Info[2]);
1146 gdth_writel(0x00, &dp2_ptr->u.ic.S_Info[3]);
1147 gdth_writeb(0xfe, &dp2_ptr->u.ic.S_Cmd_Indx);
1148 gdth_writeb(0, &dp2_ptr->io.event);
1149 retries = INIT_RETRIES;
1150 gdth_delay(20);
1151 while (gdth_readb(&dp2_ptr->u.ic.S_Status) != 0xfe) {
1152 if (--retries == 0) {
1153 printk("GDT-ISA: Initialization error\n");
1154 iounmap(ha->brd);
1155 return 0;
1156 }
1157 gdth_delay(1);
1158 }
1159 gdth_writeb(0, &dp2_ptr->u.ic.Status);
1160 gdth_writeb(0xff, &dp2_ptr->io.irqdel);
1161
1162 ha->dma64_support = 0;
1163 return 1;
1164 }
1165
1166
1167 static int __init gdth_init_pci(gdth_pci_str *pcistr,gdth_ha_str *ha)
1168 {
1169 register gdt6_dpram_str __iomem *dp6_ptr;
1170 register gdt6c_dpram_str __iomem *dp6c_ptr;
1171 register gdt6m_dpram_str __iomem *dp6m_ptr;
1172 ulong32 retries;
1173 unchar prot_ver;
1174 ushort command;
1175 int i, found = FALSE;
1176
1177 TRACE(("gdth_init_pci()\n"));
1178
1179 if (pcistr->vendor_id == PCI_VENDOR_ID_INTEL)
1180 ha->oem_id = OEM_ID_INTEL;
1181 else
1182 ha->oem_id = OEM_ID_ICP;
1183 ha->brd_phys = (pcistr->bus << 8) | (pcistr->device_fn & 0xf8);
1184 ha->stype = (ulong32)pcistr->device_id;
1185 ha->subdevice_id = pcistr->subdevice_id;
1186 ha->irq = pcistr->irq;
1187 ha->pdev = pcistr->pdev;
1188
1189 if (ha->stype <= PCI_DEVICE_ID_VORTEX_GDT6000B) { /* GDT6000/B */
1190 TRACE2(("init_pci() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
1191 ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6_dpram_str));
1192 if (ha->brd == NULL) {
1193 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1194 return 0;
1195 }
1196 /* check and reset interface area */
1197 dp6_ptr = ha->brd;
1198 gdth_writel(DPMEM_MAGIC, &dp6_ptr->u);
1199 if (gdth_readl(&dp6_ptr->u) != DPMEM_MAGIC) {
1200 printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
1201 pcistr->dpmem);
1202 found = FALSE;
1203 for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
1204 iounmap(ha->brd);
1205 ha->brd = ioremap(i, sizeof(ushort));
1206 if (ha->brd == NULL) {
1207 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1208 return 0;
1209 }
1210 if (gdth_readw(ha->brd) != 0xffff) {
1211 TRACE2(("init_pci_old() address 0x%x busy\n", i));
1212 continue;
1213 }
1214 iounmap(ha->brd);
1215 pci_write_config_dword(pcistr->pdev,
1216 PCI_BASE_ADDRESS_0, i);
1217 ha->brd = ioremap(i, sizeof(gdt6_dpram_str));
1218 if (ha->brd == NULL) {
1219 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1220 return 0;
1221 }
1222 dp6_ptr = ha->brd;
1223 gdth_writel(DPMEM_MAGIC, &dp6_ptr->u);
1224 if (gdth_readl(&dp6_ptr->u) == DPMEM_MAGIC) {
1225 printk("GDT-PCI: Use free address at 0x%x\n", i);
1226 found = TRUE;
1227 break;
1228 }
1229 }
1230 if (!found) {
1231 printk("GDT-PCI: No free address found!\n");
1232 iounmap(ha->brd);
1233 return 0;
1234 }
1235 }
1236 memset_io(&dp6_ptr->u, 0, sizeof(dp6_ptr->u));
1237 if (gdth_readl(&dp6_ptr->u) != 0) {
1238 printk("GDT-PCI: Initialization error (DPMEM write error)\n");
1239 iounmap(ha->brd);
1240 return 0;
1241 }
1242
1243 /* disable board interrupts, deinit services */
1244 gdth_writeb(0xff, &dp6_ptr->io.irqdel);
1245 gdth_writeb(0x00, &dp6_ptr->io.irqen);
1246 gdth_writeb(0x00, &dp6_ptr->u.ic.S_Status);
1247 gdth_writeb(0x00, &dp6_ptr->u.ic.Cmd_Index);
1248
1249 gdth_writel(pcistr->dpmem, &dp6_ptr->u.ic.S_Info[0]);
1250 gdth_writeb(0xff, &dp6_ptr->u.ic.S_Cmd_Indx);
1251 gdth_writeb(0, &dp6_ptr->io.event);
1252 retries = INIT_RETRIES;
1253 gdth_delay(20);
1254 while (gdth_readb(&dp6_ptr->u.ic.S_Status) != 0xff) {
1255 if (--retries == 0) {
1256 printk("GDT-PCI: Initialization error (DEINIT failed)\n");
1257 iounmap(ha->brd);
1258 return 0;
1259 }
1260 gdth_delay(1);
1261 }
1262 prot_ver = (unchar)gdth_readl(&dp6_ptr->u.ic.S_Info[0]);
1263 gdth_writeb(0, &dp6_ptr->u.ic.S_Status);
1264 gdth_writeb(0xff, &dp6_ptr->io.irqdel);
1265 if (prot_ver != PROTOCOL_VERSION) {
1266 printk("GDT-PCI: Illegal protocol version\n");
1267 iounmap(ha->brd);
1268 return 0;
1269 }
1270
1271 ha->type = GDT_PCI;
1272 ha->ic_all_size = sizeof(dp6_ptr->u);
1273
1274 /* special command to controller BIOS */
1275 gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[0]);
1276 gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[1]);
1277 gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[2]);
1278 gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[3]);
1279 gdth_writeb(0xfe, &dp6_ptr->u.ic.S_Cmd_Indx);
1280 gdth_writeb(0, &dp6_ptr->io.event);
1281 retries = INIT_RETRIES;
1282 gdth_delay(20);
1283 while (gdth_readb(&dp6_ptr->u.ic.S_Status) != 0xfe) {
1284 if (--retries == 0) {
1285 printk("GDT-PCI: Initialization error\n");
1286 iounmap(ha->brd);
1287 return 0;
1288 }
1289 gdth_delay(1);
1290 }
1291 gdth_writeb(0, &dp6_ptr->u.ic.S_Status);
1292 gdth_writeb(0xff, &dp6_ptr->io.irqdel);
1293
1294 ha->dma64_support = 0;
1295
1296 } else if (ha->stype <= PCI_DEVICE_ID_VORTEX_GDT6555) { /* GDT6110, ... */
1297 ha->plx = (gdt6c_plx_regs *)pcistr->io;
1298 TRACE2(("init_pci_new() dpmem %lx irq %d\n",
1299 pcistr->dpmem,ha->irq));
1300 ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6c_dpram_str));
1301 if (ha->brd == NULL) {
1302 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1303 iounmap(ha->brd);
1304 return 0;
1305 }
1306 /* check and reset interface area */
1307 dp6c_ptr = ha->brd;
1308 gdth_writel(DPMEM_MAGIC, &dp6c_ptr->u);
1309 if (gdth_readl(&dp6c_ptr->u) != DPMEM_MAGIC) {
1310 printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
1311 pcistr->dpmem);
1312 found = FALSE;
1313 for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
1314 iounmap(ha->brd);
1315 ha->brd = ioremap(i, sizeof(ushort));
1316 if (ha->brd == NULL) {
1317 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1318 return 0;
1319 }
1320 if (gdth_readw(ha->brd) != 0xffff) {
1321 TRACE2(("init_pci_plx() address 0x%x busy\n", i));
1322 continue;
1323 }
1324 iounmap(ha->brd);
1325 pci_write_config_dword(pcistr->pdev,
1326 PCI_BASE_ADDRESS_2, i);
1327 ha->brd = ioremap(i, sizeof(gdt6c_dpram_str));
1328 if (ha->brd == NULL) {
1329 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1330 return 0;
1331 }
1332 dp6c_ptr = ha->brd;
1333 gdth_writel(DPMEM_MAGIC, &dp6c_ptr->u);
1334 if (gdth_readl(&dp6c_ptr->u) == DPMEM_MAGIC) {
1335 printk("GDT-PCI: Use free address at 0x%x\n", i);
1336 found = TRUE;
1337 break;
1338 }
1339 }
1340 if (!found) {
1341 printk("GDT-PCI: No free address found!\n");
1342 iounmap(ha->brd);
1343 return 0;
1344 }
1345 }
1346 memset_io(&dp6c_ptr->u, 0, sizeof(dp6c_ptr->u));
1347 if (gdth_readl(&dp6c_ptr->u) != 0) {
1348 printk("GDT-PCI: Initialization error (DPMEM write error)\n");
1349 iounmap(ha->brd);
1350 return 0;
1351 }
1352
1353 /* disable board interrupts, deinit services */
1354 outb(0x00,PTR2USHORT(&ha->plx->control1));
1355 outb(0xff,PTR2USHORT(&ha->plx->edoor_reg));
1356
1357 gdth_writeb(0x00, &dp6c_ptr->u.ic.S_Status);
1358 gdth_writeb(0x00, &dp6c_ptr->u.ic.Cmd_Index);
1359
1360 gdth_writel(pcistr->dpmem, &dp6c_ptr->u.ic.S_Info[0]);
1361 gdth_writeb(0xff, &dp6c_ptr->u.ic.S_Cmd_Indx);
1362
1363 outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
1364
1365 retries = INIT_RETRIES;
1366 gdth_delay(20);
1367 while (gdth_readb(&dp6c_ptr->u.ic.S_Status) != 0xff) {
1368 if (--retries == 0) {
1369 printk("GDT-PCI: Initialization error (DEINIT failed)\n");
1370 iounmap(ha->brd);
1371 return 0;
1372 }
1373 gdth_delay(1);
1374 }
1375 prot_ver = (unchar)gdth_readl(&dp6c_ptr->u.ic.S_Info[0]);
1376 gdth_writeb(0, &dp6c_ptr->u.ic.Status);
1377 if (prot_ver != PROTOCOL_VERSION) {
1378 printk("GDT-PCI: Illegal protocol version\n");
1379 iounmap(ha->brd);
1380 return 0;
1381 }
1382
1383 ha->type = GDT_PCINEW;
1384 ha->ic_all_size = sizeof(dp6c_ptr->u);
1385
1386 /* special command to controller BIOS */
1387 gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[0]);
1388 gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[1]);
1389 gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[2]);
1390 gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[3]);
1391 gdth_writeb(0xfe, &dp6c_ptr->u.ic.S_Cmd_Indx);
1392
1393 outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
1394
1395 retries = INIT_RETRIES;
1396 gdth_delay(20);
1397 while (gdth_readb(&dp6c_ptr->u.ic.S_Status) != 0xfe) {
1398 if (--retries == 0) {
1399 printk("GDT-PCI: Initialization error\n");
1400 iounmap(ha->brd);
1401 return 0;
1402 }
1403 gdth_delay(1);
1404 }
1405 gdth_writeb(0, &dp6c_ptr->u.ic.S_Status);
1406
1407 ha->dma64_support = 0;
1408
1409 } else { /* MPR */
1410 TRACE2(("init_pci_mpr() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
1411 ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6m_dpram_str));
1412 if (ha->brd == NULL) {
1413 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1414 return 0;
1415 }
1416
1417 /* manipulate config. space to enable DPMEM, start RP controller */
1418 pci_read_config_word(pcistr->pdev, PCI_COMMAND, &command);
1419 command |= 6;
1420 pci_write_config_word(pcistr->pdev, PCI_COMMAND, command);
1421 if (pci_resource_start(pcistr->pdev, 8) == 1UL)
1422 pci_resource_start(pcistr->pdev, 8) = 0UL;
1423 i = 0xFEFF0001UL;
1424 pci_write_config_dword(pcistr->pdev, PCI_ROM_ADDRESS, i);
1425 gdth_delay(1);
1426 pci_write_config_dword(pcistr->pdev, PCI_ROM_ADDRESS,
1427 pci_resource_start(pcistr->pdev, 8));
1428
1429 dp6m_ptr = ha->brd;
1430
1431 /* Ensure that it is safe to access the non HW portions of DPMEM.
1432 * Aditional check needed for Xscale based RAID controllers */
1433 while( ((int)gdth_readb(&dp6m_ptr->i960r.sema0_reg) ) & 3 )
1434 gdth_delay(1);
1435
1436 /* check and reset interface area */
1437 gdth_writel(DPMEM_MAGIC, &dp6m_ptr->u);
1438 if (gdth_readl(&dp6m_ptr->u) != DPMEM_MAGIC) {
1439 printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
1440 pcistr->dpmem);
1441 found = FALSE;
1442 for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
1443 iounmap(ha->brd);
1444 ha->brd = ioremap(i, sizeof(ushort));
1445 if (ha->brd == NULL) {
1446 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1447 return 0;
1448 }
1449 if (gdth_readw(ha->brd) != 0xffff) {
1450 TRACE2(("init_pci_mpr() address 0x%x busy\n", i));
1451 continue;
1452 }
1453 iounmap(ha->brd);
1454 pci_write_config_dword(pcistr->pdev,
1455 PCI_BASE_ADDRESS_0, i);
1456 ha->brd = ioremap(i, sizeof(gdt6m_dpram_str));
1457 if (ha->brd == NULL) {
1458 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1459 return 0;
1460 }
1461 dp6m_ptr = ha->brd;
1462 gdth_writel(DPMEM_MAGIC, &dp6m_ptr->u);
1463 if (gdth_readl(&dp6m_ptr->u) == DPMEM_MAGIC) {
1464 printk("GDT-PCI: Use free address at 0x%x\n", i);
1465 found = TRUE;
1466 break;
1467 }
1468 }
1469 if (!found) {
1470 printk("GDT-PCI: No free address found!\n");
1471 iounmap(ha->brd);
1472 return 0;
1473 }
1474 }
1475 memset_io(&dp6m_ptr->u, 0, sizeof(dp6m_ptr->u));
1476
1477 /* disable board interrupts, deinit services */
1478 gdth_writeb(gdth_readb(&dp6m_ptr->i960r.edoor_en_reg) | 4,
1479 &dp6m_ptr->i960r.edoor_en_reg);
1480 gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
1481 gdth_writeb(0x00, &dp6m_ptr->u.ic.S_Status);
1482 gdth_writeb(0x00, &dp6m_ptr->u.ic.Cmd_Index);
1483
1484 gdth_writel(pcistr->dpmem, &dp6m_ptr->u.ic.S_Info[0]);
1485 gdth_writeb(0xff, &dp6m_ptr->u.ic.S_Cmd_Indx);
1486 gdth_writeb(1, &dp6m_ptr->i960r.ldoor_reg);
1487 retries = INIT_RETRIES;
1488 gdth_delay(20);
1489 while (gdth_readb(&dp6m_ptr->u.ic.S_Status) != 0xff) {
1490 if (--retries == 0) {
1491 printk("GDT-PCI: Initialization error (DEINIT failed)\n");
1492 iounmap(ha->brd);
1493 return 0;
1494 }
1495 gdth_delay(1);
1496 }
1497 prot_ver = (unchar)gdth_readl(&dp6m_ptr->u.ic.S_Info[0]);
1498 gdth_writeb(0, &dp6m_ptr->u.ic.S_Status);
1499 if (prot_ver != PROTOCOL_VERSION) {
1500 printk("GDT-PCI: Illegal protocol version\n");
1501 iounmap(ha->brd);
1502 return 0;
1503 }
1504
1505 ha->type = GDT_PCIMPR;
1506 ha->ic_all_size = sizeof(dp6m_ptr->u);
1507
1508 /* special command to controller BIOS */
1509 gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[0]);
1510 gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[1]);
1511 gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[2]);
1512 gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[3]);
1513 gdth_writeb(0xfe, &dp6m_ptr->u.ic.S_Cmd_Indx);
1514 gdth_writeb(1, &dp6m_ptr->i960r.ldoor_reg);
1515 retries = INIT_RETRIES;
1516 gdth_delay(20);
1517 while (gdth_readb(&dp6m_ptr->u.ic.S_Status) != 0xfe) {
1518 if (--retries == 0) {
1519 printk("GDT-PCI: Initialization error\n");
1520 iounmap(ha->brd);
1521 return 0;
1522 }
1523 gdth_delay(1);
1524 }
1525 gdth_writeb(0, &dp6m_ptr->u.ic.S_Status);
1526
1527 /* read FW version to detect 64-bit DMA support */
1528 gdth_writeb(0xfd, &dp6m_ptr->u.ic.S_Cmd_Indx);
1529 gdth_writeb(1, &dp6m_ptr->i960r.ldoor_reg);
1530 retries = INIT_RETRIES;
1531 gdth_delay(20);
1532 while (gdth_readb(&dp6m_ptr->u.ic.S_Status) != 0xfd) {
1533 if (--retries == 0) {
1534 printk("GDT-PCI: Initialization error (DEINIT failed)\n");
1535 iounmap(ha->brd);
1536 return 0;
1537 }
1538 gdth_delay(1);
1539 }
1540 prot_ver = (unchar)(gdth_readl(&dp6m_ptr->u.ic.S_Info[0]) >> 16);
1541 gdth_writeb(0, &dp6m_ptr->u.ic.S_Status);
1542 if (prot_ver < 0x2b) /* FW < x.43: no 64-bit DMA support */
1543 ha->dma64_support = 0;
1544 else
1545 ha->dma64_support = 1;
1546 }
1547
1548 return 1;
1549 }
1550
1551
1552 /* controller protocol functions */
1553
1554 static void __init gdth_enable_int(int hanum)
1555 {
1556 gdth_ha_str *ha;
1557 ulong flags;
1558 gdt2_dpram_str __iomem *dp2_ptr;
1559 gdt6_dpram_str __iomem *dp6_ptr;
1560 gdt6m_dpram_str __iomem *dp6m_ptr;
1561
1562 TRACE(("gdth_enable_int() hanum %d\n",hanum));
1563 ha = HADATA(gdth_ctr_tab[hanum]);
1564 spin_lock_irqsave(&ha->smp_lock, flags);
1565
1566 if (ha->type == GDT_EISA) {
1567 outb(0xff, ha->bmic + EDOORREG);
1568 outb(0xff, ha->bmic + EDENABREG);
1569 outb(0x01, ha->bmic + EINTENABREG);
1570 } else if (ha->type == GDT_ISA) {
1571 dp2_ptr = ha->brd;
1572 gdth_writeb(1, &dp2_ptr->io.irqdel);
1573 gdth_writeb(0, &dp2_ptr->u.ic.Cmd_Index);
1574 gdth_writeb(1, &dp2_ptr->io.irqen);
1575 } else if (ha->type == GDT_PCI) {
1576 dp6_ptr = ha->brd;
1577 gdth_writeb(1, &dp6_ptr->io.irqdel);
1578 gdth_writeb(0, &dp6_ptr->u.ic.Cmd_Index);
1579 gdth_writeb(1, &dp6_ptr->io.irqen);
1580 } else if (ha->type == GDT_PCINEW) {
1581 outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
1582 outb(0x03, PTR2USHORT(&ha->plx->control1));
1583 } else if (ha->type == GDT_PCIMPR) {
1584 dp6m_ptr = ha->brd;
1585 gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
1586 gdth_writeb(gdth_readb(&dp6m_ptr->i960r.edoor_en_reg) & ~4,
1587 &dp6m_ptr->i960r.edoor_en_reg);
1588 }
1589 spin_unlock_irqrestore(&ha->smp_lock, flags);
1590 }
1591
1592
1593 static int gdth_get_status(unchar *pIStatus,int irq)
1594 {
1595 register gdth_ha_str *ha;
1596 int i;
1597
1598 TRACE(("gdth_get_status() irq %d ctr_count %d\n",
1599 irq,gdth_ctr_count));
1600
1601 *pIStatus = 0;
1602 for (i=0; i<gdth_ctr_count; ++i) {
1603 ha = HADATA(gdth_ctr_tab[i]);
1604 if (ha->irq != (unchar)irq) /* check IRQ */
1605 continue;
1606 if (ha->type == GDT_EISA)
1607 *pIStatus = inb((ushort)ha->bmic + EDOORREG);
1608 else if (ha->type == GDT_ISA)
1609 *pIStatus =
1610 gdth_readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
1611 else if (ha->type == GDT_PCI)
1612 *pIStatus =
1613 gdth_readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
1614 else if (ha->type == GDT_PCINEW)
1615 *pIStatus = inb(PTR2USHORT(&ha->plx->edoor_reg));
1616 else if (ha->type == GDT_PCIMPR)
1617 *pIStatus =
1618 gdth_readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.edoor_reg);
1619
1620 if (*pIStatus)
1621 return i; /* board found */
1622 }
1623 return -1;
1624 }
1625
1626
1627 static int gdth_test_busy(int hanum)
1628 {
1629 register gdth_ha_str *ha;
1630 register int gdtsema0 = 0;
1631
1632 TRACE(("gdth_test_busy() hanum %d\n",hanum));
1633
1634 ha = HADATA(gdth_ctr_tab[hanum]);
1635 if (ha->type == GDT_EISA)
1636 gdtsema0 = (int)inb(ha->bmic + SEMA0REG);
1637 else if (ha->type == GDT_ISA)
1638 gdtsema0 = (int)gdth_readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
1639 else if (ha->type == GDT_PCI)
1640 gdtsema0 = (int)gdth_readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
1641 else if (ha->type == GDT_PCINEW)
1642 gdtsema0 = (int)inb(PTR2USHORT(&ha->plx->sema0_reg));
1643 else if (ha->type == GDT_PCIMPR)
1644 gdtsema0 =
1645 (int)gdth_readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
1646
1647 return (gdtsema0 & 1);
1648 }
1649
1650
1651 static int gdth_get_cmd_index(int hanum)
1652 {
1653 register gdth_ha_str *ha;
1654 int i;
1655
1656 TRACE(("gdth_get_cmd_index() hanum %d\n",hanum));
1657
1658 ha = HADATA(gdth_ctr_tab[hanum]);
1659 for (i=0; i<GDTH_MAXCMDS; ++i) {
1660 if (ha->cmd_tab[i].cmnd == UNUSED_CMND) {
1661 ha->cmd_tab[i].cmnd = ha->pccb->RequestBuffer;
1662 ha->cmd_tab[i].service = ha->pccb->Service;
1663 ha->pccb->CommandIndex = (ulong32)i+2;
1664 return (i+2);
1665 }
1666 }
1667 return 0;
1668 }
1669
1670
1671 static void gdth_set_sema0(int hanum)
1672 {
1673 register gdth_ha_str *ha;
1674
1675 TRACE(("gdth_set_sema0() hanum %d\n",hanum));
1676
1677 ha = HADATA(gdth_ctr_tab[hanum]);
1678 if (ha->type == GDT_EISA) {
1679 outb(1, ha->bmic + SEMA0REG);
1680 } else if (ha->type == GDT_ISA) {
1681 gdth_writeb(1, &((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
1682 } else if (ha->type == GDT_PCI) {
1683 gdth_writeb(1, &((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
1684 } else if (ha->type == GDT_PCINEW) {
1685 outb(1, PTR2USHORT(&ha->plx->sema0_reg));
1686 } else if (ha->type == GDT_PCIMPR) {
1687 gdth_writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
1688 }
1689 }
1690
1691
1692 static void gdth_copy_command(int hanum)
1693 {
1694 register gdth_ha_str *ha;
1695 register gdth_cmd_str *cmd_ptr;
1696 register gdt6m_dpram_str __iomem *dp6m_ptr;
1697 register gdt6c_dpram_str __iomem *dp6c_ptr;
1698 gdt6_dpram_str __iomem *dp6_ptr;
1699 gdt2_dpram_str __iomem *dp2_ptr;
1700 ushort cp_count,dp_offset,cmd_no;
1701
1702 TRACE(("gdth_copy_command() hanum %d\n",hanum));
1703
1704 ha = HADATA(gdth_ctr_tab[hanum]);
1705 cp_count = ha->cmd_len;
1706 dp_offset= ha->cmd_offs_dpmem;
1707 cmd_no = ha->cmd_cnt;
1708 cmd_ptr = ha->pccb;
1709
1710 ++ha->cmd_cnt;
1711 if (ha->type == GDT_EISA)
1712 return; /* no DPMEM, no copy */
1713
1714 /* set cpcount dword aligned */
1715 if (cp_count & 3)
1716 cp_count += (4 - (cp_count & 3));
1717
1718 ha->cmd_offs_dpmem += cp_count;
1719
1720 /* set offset and service, copy command to DPMEM */
1721 if (ha->type == GDT_ISA) {
1722 dp2_ptr = ha->brd;
1723 gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
1724 &dp2_ptr->u.ic.comm_queue[cmd_no].offset);
1725 gdth_writew((ushort)cmd_ptr->Service,
1726 &dp2_ptr->u.ic.comm_queue[cmd_no].serv_id);
1727 memcpy_toio(&dp2_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
1728 } else if (ha->type == GDT_PCI) {
1729 dp6_ptr = ha->brd;
1730 gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
1731 &dp6_ptr->u.ic.comm_queue[cmd_no].offset);
1732 gdth_writew((ushort)cmd_ptr->Service,
1733 &dp6_ptr->u.ic.comm_queue[cmd_no].serv_id);
1734 memcpy_toio(&dp6_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
1735 } else if (ha->type == GDT_PCINEW) {
1736 dp6c_ptr = ha->brd;
1737 gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
1738 &dp6c_ptr->u.ic.comm_queue[cmd_no].offset);
1739 gdth_writew((ushort)cmd_ptr->Service,
1740 &dp6c_ptr->u.ic.comm_queue[cmd_no].serv_id);
1741 memcpy_toio(&dp6c_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
1742 } else if (ha->type == GDT_PCIMPR) {
1743 dp6m_ptr = ha->brd;
1744 gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
1745 &dp6m_ptr->u.ic.comm_queue[cmd_no].offset);
1746 gdth_writew((ushort)cmd_ptr->Service,
1747 &dp6m_ptr->u.ic.comm_queue[cmd_no].serv_id);
1748 memcpy_toio(&dp6m_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
1749 }
1750 }
1751
1752
1753 static void gdth_release_event(int hanum)
1754 {
1755 register gdth_ha_str *ha;
1756
1757 TRACE(("gdth_release_event() hanum %d\n",hanum));
1758 ha = HADATA(gdth_ctr_tab[hanum]);
1759
1760 #ifdef GDTH_STATISTICS
1761 {
1762 ulong32 i,j;
1763 for (i=0,j=0; j<GDTH_MAXCMDS; ++j) {
1764 if (ha->cmd_tab[j].cmnd != UNUSED_CMND)
1765 ++i;
1766 }
1767 if (max_index < i) {
1768 max_index = i;
1769 TRACE3(("GDT: max_index = %d\n",(ushort)i));
1770 }
1771 }
1772 #endif
1773
1774 if (ha->pccb->OpCode == GDT_INIT)
1775 ha->pccb->Service |= 0x80;
1776
1777 if (ha->type == GDT_EISA) {
1778 if (ha->pccb->OpCode == GDT_INIT) /* store DMA buffer */
1779 outl(ha->ccb_phys, ha->bmic + MAILBOXREG);
1780 outb(ha->pccb->Service, ha->bmic + LDOORREG);
1781 } else if (ha->type == GDT_ISA) {
1782 gdth_writeb(0, &((gdt2_dpram_str __iomem *)ha->brd)->io.event);
1783 } else if (ha->type == GDT_PCI) {
1784 gdth_writeb(0, &((gdt6_dpram_str __iomem *)ha->brd)->io.event);
1785 } else if (ha->type == GDT_PCINEW) {
1786 outb(1, PTR2USHORT(&ha->plx->ldoor_reg));
1787 } else if (ha->type == GDT_PCIMPR) {
1788 gdth_writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.ldoor_reg);
1789 }
1790 }
1791
1792
1793 static int gdth_wait(int hanum,int index,ulong32 time)
1794 {
1795 gdth_ha_str *ha;
1796 int answer_found = FALSE;
1797
1798 TRACE(("gdth_wait() hanum %d index %d time %d\n",hanum,index,time));
1799
1800 ha = HADATA(gdth_ctr_tab[hanum]);
1801 if (index == 0)
1802 return 1; /* no wait required */
1803
1804 gdth_from_wait = TRUE;
1805 do {
1806 gdth_interrupt((int)ha->irq,ha);
1807 if (wait_hanum==hanum && wait_index==index) {
1808 answer_found = TRUE;
1809 break;
1810 }
1811 gdth_delay(1);
1812 } while (--time);
1813 gdth_from_wait = FALSE;
1814
1815 while (gdth_test_busy(hanum))
1816 gdth_delay(0);
1817
1818 return (answer_found);
1819 }
1820
1821
1822 static int gdth_internal_cmd(int hanum,unchar service,ushort opcode,ulong32 p1,
1823 ulong64 p2,ulong64 p3)
1824 {
1825 register gdth_ha_str *ha;
1826 register gdth_cmd_str *cmd_ptr;
1827 int retries,index;
1828
1829 TRACE2(("gdth_internal_cmd() service %d opcode %d\n",service,opcode));
1830
1831 ha = HADATA(gdth_ctr_tab[hanum]);
1832 cmd_ptr = ha->pccb;
1833 memset((char*)cmd_ptr,0,sizeof(gdth_cmd_str));
1834
1835 /* make command */
1836 for (retries = INIT_RETRIES;;) {
1837 cmd_ptr->Service = service;
1838 cmd_ptr->RequestBuffer = INTERNAL_CMND;
1839 if (!(index=gdth_get_cmd_index(hanum))) {
1840 TRACE(("GDT: No free command index found\n"));
1841 return 0;
1842 }
1843 gdth_set_sema0(hanum);
1844 cmd_ptr->OpCode = opcode;
1845 cmd_ptr->BoardNode = LOCALBOARD;
1846 if (service == CACHESERVICE) {
1847 if (opcode == GDT_IOCTL) {
1848 cmd_ptr->u.ioctl.subfunc = p1;
1849 cmd_ptr->u.ioctl.channel = (ulong32)p2;
1850 cmd_ptr->u.ioctl.param_size = (ushort)p3;
1851 cmd_ptr->u.ioctl.p_param = ha->scratch_phys;
1852 } else {
1853 if (ha->cache_feat & GDT_64BIT) {
1854 cmd_ptr->u.cache64.DeviceNo = (ushort)p1;
1855 cmd_ptr->u.cache64.BlockNo = p2;
1856 } else {
1857 cmd_ptr->u.cache.DeviceNo = (ushort)p1;
1858 cmd_ptr->u.cache.BlockNo = (ulong32)p2;
1859 }
1860 }
1861 } else if (service == SCSIRAWSERVICE) {
1862 if (ha->raw_feat & GDT_64BIT) {
1863 cmd_ptr->u.raw64.direction = p1;
1864 cmd_ptr->u.raw64.bus = (unchar)p2;
1865 cmd_ptr->u.raw64.target = (unchar)p3;
1866 cmd_ptr->u.raw64.lun = (unchar)(p3 >> 8);
1867 } else {
1868 cmd_ptr->u.raw.direction = p1;
1869 cmd_ptr->u.raw.bus = (unchar)p2;
1870 cmd_ptr->u.raw.target = (unchar)p3;
1871 cmd_ptr->u.raw.lun = (unchar)(p3 >> 8);
1872 }
1873 } else if (service == SCREENSERVICE) {
1874 if (opcode == GDT_REALTIME) {
1875 *(ulong32 *)&cmd_ptr->u.screen.su.data[0] = p1;
1876 *(ulong32 *)&cmd_ptr->u.screen.su.data[4] = (ulong32)p2;
1877 *(ulong32 *)&cmd_ptr->u.screen.su.data[8] = (ulong32)p3;
1878 }
1879 }
1880 ha->cmd_len = sizeof(gdth_cmd_str);
1881 ha->cmd_offs_dpmem = 0;
1882 ha->cmd_cnt = 0;
1883 gdth_copy_command(hanum);
1884 gdth_release_event(hanum);
1885 gdth_delay(20);
1886 if (!gdth_wait(hanum,index,INIT_TIMEOUT)) {
1887 printk("GDT: Initialization error (timeout service %d)\n",service);
1888 return 0;
1889 }
1890 if (ha->status != S_BSY || --retries == 0)
1891 break;
1892 gdth_delay(1);
1893 }
1894
1895 return (ha->status != S_OK ? 0:1);
1896 }
1897
1898
1899 /* search for devices */
1900
1901 static int __init gdth_search_drives(int hanum)
1902 {
1903 register gdth_ha_str *ha;
1904 ushort cdev_cnt, i;
1905 int ok;
1906 ulong32 bus_no, drv_cnt, drv_no, j;
1907 gdth_getch_str *chn;
1908 gdth_drlist_str *drl;
1909 gdth_iochan_str *ioc;
1910 gdth_raw_iochan_str *iocr;
1911 gdth_arcdl_str *alst;
1912 gdth_alist_str *alst2;
1913 gdth_oem_str_ioctl *oemstr;
1914 #ifdef INT_COAL
1915 gdth_perf_modes *pmod;
1916 #endif
1917
1918 #ifdef GDTH_RTC
1919 unchar rtc[12];
1920 ulong flags;
1921 #endif
1922
1923 TRACE(("gdth_search_drives() hanum %d\n",hanum));
1924 ha = HADATA(gdth_ctr_tab[hanum]);
1925 ok = 0;
1926
1927 /* initialize controller services, at first: screen service */
1928 ha->screen_feat = 0;
1929 if (!force_dma32) {
1930 ok = gdth_internal_cmd(hanum,SCREENSERVICE,GDT_X_INIT_SCR,0,0,0);
1931 if (ok)
1932 ha->screen_feat = GDT_64BIT;
1933 }
1934 if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
1935 ok = gdth_internal_cmd(hanum,SCREENSERVICE,GDT_INIT,0,0,0);
1936 if (!ok) {
1937 printk("GDT-HA %d: Initialization error screen service (code %d)\n",
1938 hanum, ha->status);
1939 return 0;
1940 }
1941 TRACE2(("gdth_search_drives(): SCREENSERVICE initialized\n"));
1942
1943 #ifdef GDTH_RTC
1944 /* read realtime clock info, send to controller */
1945 /* 1. wait for the falling edge of update flag */
1946 spin_lock_irqsave(&rtc_lock, flags);
1947 for (j = 0; j < 1000000; ++j)
1948 if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP)
1949 break;
1950 for (j = 0; j < 1000000; ++j)
1951 if (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP))
1952 break;
1953 /* 2. read info */
1954 do {
1955 for (j = 0; j < 12; ++j)
1956 rtc[j] = CMOS_READ(j);
1957 } while (rtc[0] != CMOS_READ(0));
1958 spin_lock_irqrestore(&rtc_lock, flags);
1959 TRACE2(("gdth_search_drives(): RTC: %x/%x/%x\n",*(ulong32 *)&rtc[0],
1960 *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]));
1961 /* 3. send to controller firmware */
1962 gdth_internal_cmd(hanum,SCREENSERVICE,GDT_REALTIME, *(ulong32 *)&rtc[0],
1963 *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]);
1964 #endif
1965
1966 /* unfreeze all IOs */
1967 gdth_internal_cmd(hanum,CACHESERVICE,GDT_UNFREEZE_IO,0,0,0);
1968
1969 /* initialize cache service */
1970 ha->cache_feat = 0;
1971 if (!force_dma32) {
1972 ok = gdth_internal_cmd(hanum,CACHESERVICE,GDT_X_INIT_HOST,LINUX_OS,0,0);
1973 if (ok)
1974 ha->cache_feat = GDT_64BIT;
1975 }
1976 if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
1977 ok = gdth_internal_cmd(hanum,CACHESERVICE,GDT_INIT,LINUX_OS,0,0);
1978 if (!ok) {
1979 printk("GDT-HA %d: Initialization error cache service (code %d)\n",
1980 hanum, ha->status);
1981 return 0;
1982 }
1983 TRACE2(("gdth_search_drives(): CACHESERVICE initialized\n"));
1984 cdev_cnt = (ushort)ha->info;
1985 ha->fw_vers = ha->service;
1986
1987 #ifdef INT_COAL
1988 if (ha->type == GDT_PCIMPR) {
1989 /* set perf. modes */
1990 pmod = (gdth_perf_modes *)ha->pscratch;
1991 pmod->version = 1;
1992 pmod->st_mode = 1; /* enable one status buffer */
1993 *((ulong64 *)&pmod->st_buff_addr1) = ha->coal_stat_phys;
1994 pmod->st_buff_indx1 = COALINDEX;
1995 pmod->st_buff_addr2 = 0;
1996 pmod->st_buff_u_addr2 = 0;
1997 pmod->st_buff_indx2 = 0;
1998 pmod->st_buff_size = sizeof(gdth_coal_status) * MAXOFFSETS;
1999 pmod->cmd_mode = 0; // disable all cmd buffers
2000 pmod->cmd_buff_addr1 = 0;
2001 pmod->cmd_buff_u_addr1 = 0;
2002 pmod->cmd_buff_indx1 = 0;
2003 pmod->cmd_buff_addr2 = 0;
2004 pmod->cmd_buff_u_addr2 = 0;
2005 pmod->cmd_buff_indx2 = 0;
2006 pmod->cmd_buff_size = 0;
2007 pmod->reserved1 = 0;
2008 pmod->reserved2 = 0;
2009 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,SET_PERF_MODES,
2010 INVALID_CHANNEL,sizeof(gdth_perf_modes))) {
2011 printk("GDT-HA %d: Interrupt coalescing activated\n", hanum);
2012 }
2013 }
2014 #endif
2015
2016 /* detect number of buses - try new IOCTL */
2017 iocr = (gdth_raw_iochan_str *)ha->pscratch;
2018 iocr->hdr.version = 0xffffffff;
2019 iocr->hdr.list_entries = MAXBUS;
2020 iocr->hdr.first_chan = 0;
2021 iocr->hdr.last_chan = MAXBUS-1;
2022 iocr->hdr.list_offset = GDTOFFSOF(gdth_raw_iochan_str, list[0]);
2023 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,IOCHAN_RAW_DESC,
2024 INVALID_CHANNEL,sizeof(gdth_raw_iochan_str))) {
2025 TRACE2(("IOCHAN_RAW_DESC supported!\n"));
2026 ha->bus_cnt = iocr->hdr.chan_count;
2027 for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
2028 if (iocr->list[bus_no].proc_id < MAXID)
2029 ha->bus_id[bus_no] = iocr->list[bus_no].proc_id;
2030 else
2031 ha->bus_id[bus_no] = 0xff;
2032 }
2033 } else {
2034 /* old method */
2035 chn = (gdth_getch_str *)ha->pscratch;
2036 for (bus_no = 0; bus_no < MAXBUS; ++bus_no) {
2037 chn->channel_no = bus_no;
2038 if (!gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
2039 SCSI_CHAN_CNT | L_CTRL_PATTERN,
2040 IO_CHANNEL | INVALID_CHANNEL,
2041 sizeof(gdth_getch_str))) {
2042 if (bus_no == 0) {
2043 printk("GDT-HA %d: Error detecting channel count (0x%x)\n",
2044 hanum, ha->status);
2045 return 0;
2046 }
2047 break;
2048 }
2049 if (chn->siop_id < MAXID)
2050 ha->bus_id[bus_no] = chn->siop_id;
2051 else
2052 ha->bus_id[bus_no] = 0xff;
2053 }
2054 ha->bus_cnt = (unchar)bus_no;
2055 }
2056 TRACE2(("gdth_search_drives() %d channels\n",ha->bus_cnt));
2057
2058 /* read cache configuration */
2059 if (!gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,CACHE_INFO,
2060 INVALID_CHANNEL,sizeof(gdth_cinfo_str))) {
2061 printk("GDT-HA %d: Initialization error cache service (code %d)\n",
2062 hanum, ha->status);
2063 return 0;
2064 }
2065 ha->cpar = ((gdth_cinfo_str *)ha->pscratch)->cpar;
2066 TRACE2(("gdth_search_drives() cinfo: vs %x sta %d str %d dw %d b %d\n",
2067 ha->cpar.version,ha->cpar.state,ha->cpar.strategy,
2068 ha->cpar.write_back,ha->cpar.block_size));
2069
2070 /* read board info and features */
2071 ha->more_proc = FALSE;
2072 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,BOARD_INFO,
2073 INVALID_CHANNEL,sizeof(gdth_binfo_str))) {
2074 memcpy(&ha->binfo, (gdth_binfo_str *)ha->pscratch,
2075 sizeof(gdth_binfo_str));
2076 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,BOARD_FEATURES,
2077 INVALID_CHANNEL,sizeof(gdth_bfeat_str))) {
2078 TRACE2(("BOARD_INFO/BOARD_FEATURES supported\n"));
2079 ha->bfeat = *(gdth_bfeat_str *)ha->pscratch;
2080 ha->more_proc = TRUE;
2081 }
2082 } else {
2083 TRACE2(("BOARD_INFO requires firmware >= 1.10/2.08\n"));
2084 strcpy(ha->binfo.type_string, gdth_ctr_name(hanum));
2085 }
2086 TRACE2(("Controller name: %s\n",ha->binfo.type_string));
2087
2088 /* read more informations */
2089 if (ha->more_proc) {
2090 /* physical drives, channel addresses */
2091 ioc = (gdth_iochan_str *)ha->pscratch;
2092 ioc->hdr.version = 0xffffffff;
2093 ioc->hdr.list_entries = MAXBUS;
2094 ioc->hdr.first_chan = 0;
2095 ioc->hdr.last_chan = MAXBUS-1;
2096 ioc->hdr.list_offset = GDTOFFSOF(gdth_iochan_str, list[0]);
2097 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,IOCHAN_DESC,
2098 INVALID_CHANNEL,sizeof(gdth_iochan_str))) {
2099 for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
2100 ha->raw[bus_no].address = ioc->list[bus_no].address;
2101 ha->raw[bus_no].local_no = ioc->list[bus_no].local_no;
2102 }
2103 } else {
2104 for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
2105 ha->raw[bus_no].address = IO_CHANNEL;
2106 ha->raw[bus_no].local_no = bus_no;
2107 }
2108 }
2109 for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
2110 chn = (gdth_getch_str *)ha->pscratch;
2111 chn->channel_no = ha->raw[bus_no].local_no;
2112 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
2113 SCSI_CHAN_CNT | L_CTRL_PATTERN,
2114 ha->raw[bus_no].address | INVALID_CHANNEL,
2115 sizeof(gdth_getch_str))) {
2116 ha->raw[bus_no].pdev_cnt = chn->drive_cnt;
2117 TRACE2(("Channel %d: %d phys. drives\n",
2118 bus_no,chn->drive_cnt));
2119 }
2120 if (ha->raw[bus_no].pdev_cnt > 0) {
2121 drl = (gdth_drlist_str *)ha->pscratch;
2122 drl->sc_no = ha->raw[bus_no].local_no;
2123 drl->sc_cnt = ha->raw[bus_no].pdev_cnt;
2124 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
2125 SCSI_DR_LIST | L_CTRL_PATTERN,
2126 ha->raw[bus_no].address | INVALID_CHANNEL,
2127 sizeof(gdth_drlist_str))) {
2128 for (j = 0; j < ha->raw[bus_no].pdev_cnt; ++j)
2129 ha->raw[bus_no].id_list[j] = drl->sc_list[j];
2130 } else {
2131 ha->raw[bus_no].pdev_cnt = 0;
2132 }
2133 }
2134 }
2135
2136 /* logical drives */
2137 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,CACHE_DRV_CNT,
2138 INVALID_CHANNEL,sizeof(ulong32))) {
2139 drv_cnt = *(ulong32 *)ha->pscratch;
2140 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,CACHE_DRV_LIST,
2141 INVALID_CHANNEL,drv_cnt * sizeof(ulong32))) {
2142 for (j = 0; j < drv_cnt; ++j) {
2143 drv_no = ((ulong32 *)ha->pscratch)[j];
2144 if (drv_no < MAX_LDRIVES) {
2145 ha->hdr[drv_no].is_logdrv = TRUE;
2146 TRACE2(("Drive %d is log. drive\n",drv_no));
2147 }
2148 }
2149 }
2150 alst = (gdth_arcdl_str *)ha->pscratch;
2151 alst->entries_avail = MAX_LDRIVES;
2152 alst->first_entry = 0;
2153 alst->list_offset = GDTOFFSOF(gdth_arcdl_str, list[0]);
2154 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
2155 ARRAY_DRV_LIST2 | LA_CTRL_PATTERN,
2156 INVALID_CHANNEL, sizeof(gdth_arcdl_str) +
2157 (alst->entries_avail-1) * sizeof(gdth_alist_str))) {
2158 for (j = 0; j < alst->entries_init; ++j) {
2159 ha->hdr[j].is_arraydrv = alst->list[j].is_arrayd;
2160 ha->hdr[j].is_master = alst->list[j].is_master;
2161 ha->hdr[j].is_parity = alst->list[j].is_parity;
2162 ha->hdr[j].is_hotfix = alst->list[j].is_hotfix;
2163 ha->hdr[j].master_no = alst->list[j].cd_handle;
2164 }
2165 } else if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
2166 ARRAY_DRV_LIST | LA_CTRL_PATTERN,
2167 0, 35 * sizeof(gdth_alist_str))) {
2168 for (j = 0; j < 35; ++j) {
2169 alst2 = &((gdth_alist_str *)ha->pscratch)[j];
2170 ha->hdr[j].is_arraydrv = alst2->is_arrayd;
2171 ha->hdr[j].is_master = alst2->is_master;
2172 ha->hdr[j].is_parity = alst2->is_parity;
2173 ha->hdr[j].is_hotfix = alst2->is_hotfix;
2174 ha->hdr[j].master_no = alst2->cd_handle;
2175 }
2176 }
2177 }
2178 }
2179
2180 /* initialize raw service */
2181 ha->raw_feat = 0;
2182 if (!force_dma32) {
2183 ok = gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_X_INIT_RAW,0,0,0);
2184 if (ok)
2185 ha->raw_feat = GDT_64BIT;
2186 }
2187 if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
2188 ok = gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_INIT,0,0,0);
2189 if (!ok) {
2190 printk("GDT-HA %d: Initialization error raw service (code %d)\n",
2191 hanum, ha->status);
2192 return 0;
2193 }
2194 TRACE2(("gdth_search_drives(): RAWSERVICE initialized\n"));
2195
2196 /* set/get features raw service (scatter/gather) */
2197 if (gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_SET_FEAT,SCATTER_GATHER,
2198 0,0)) {
2199 TRACE2(("gdth_search_drives(): set features RAWSERVICE OK\n"));
2200 if (gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_GET_FEAT,0,0,0)) {
2201 TRACE2(("gdth_search_dr(): get feat RAWSERVICE %d\n",
2202 ha->info));
2203 ha->raw_feat |= (ushort)ha->info;
2204 }
2205 }
2206
2207 /* set/get features cache service (equal to raw service) */
2208 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_SET_FEAT,0,
2209 SCATTER_GATHER,0)) {
2210 TRACE2(("gdth_search_drives(): set features CACHESERVICE OK\n"));
2211 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_GET_FEAT,0,0,0)) {
2212 TRACE2(("gdth_search_dr(): get feat CACHESERV. %d\n",
2213 ha->info));
2214 ha->cache_feat |= (ushort)ha->info;
2215 }
2216 }
2217
2218 /* reserve drives for raw service */
2219 if (reserve_mode != 0) {
2220 gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_RESERVE_ALL,
2221 reserve_mode == 1 ? 1 : 3, 0, 0);
2222 TRACE2(("gdth_search_drives(): RESERVE_ALL code %d\n",
2223 ha->status));
2224 }
2225 for (i = 0; i < MAX_RES_ARGS; i += 4) {
2226 if (reserve_list[i] == hanum && reserve_list[i+1] < ha->bus_cnt &&
2227 reserve_list[i+2] < ha->tid_cnt && reserve_list[i+3] < MAXLUN) {
2228 TRACE2(("gdth_search_drives(): reserve ha %d bus %d id %d lun %d\n",
2229 reserve_list[i], reserve_list[i+1],
2230 reserve_list[i+2], reserve_list[i+3]));
2231 if (!gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_RESERVE,0,
2232 reserve_list[i+1], reserve_list[i+2] |
2233 (reserve_list[i+3] << 8))) {
2234 printk("GDT-HA %d: Error raw service (RESERVE, code %d)\n",
2235 hanum, ha->status);
2236 }
2237 }
2238 }
2239
2240 /* Determine OEM string using IOCTL */
2241 oemstr = (gdth_oem_str_ioctl *)ha->pscratch;
2242 oemstr->params.ctl_version = 0x01;
2243 oemstr->params.buffer_size = sizeof(oemstr->text);
2244 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
2245 CACHE_READ_OEM_STRING_RECORD,INVALID_CHANNEL,
2246 sizeof(gdth_oem_str_ioctl))) {
2247 TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD OK\n"));
2248 printk("GDT-HA %d: Vendor: %s Name: %s\n",
2249 hanum,oemstr->text.oem_company_name,ha->binfo.type_string);
2250 /* Save the Host Drive inquiry data */
2251 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
2252 strlcpy(ha->oem_name,oemstr->text.scsi_host_drive_inquiry_vendor_id,
2253 sizeof(ha->oem_name));
2254 #else
2255 strncpy(ha->oem_name,oemstr->text.scsi_host_drive_inquiry_vendor_id,7);
2256 ha->oem_name[7] = '\0';
2257 #endif
2258 } else {
2259 /* Old method, based on PCI ID */
2260 TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD failed\n"));
2261 printk("GDT-HA %d: Name: %s\n",
2262 hanum,ha->binfo.type_string);
2263 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
2264 if (ha->oem_id == OEM_ID_INTEL)
2265 strlcpy(ha->oem_name,"Intel ", sizeof(ha->oem_name));
2266 else
2267 strlcpy(ha->oem_name,"ICP ", sizeof(ha->oem_name));
2268 #else
2269 if (ha->oem_id == OEM_ID_INTEL)
2270 strcpy(ha->oem_name,"Intel ");
2271 else
2272 strcpy(ha->oem_name,"ICP ");
2273 #endif
2274 }
2275
2276 /* scanning for host drives */
2277 for (i = 0; i < cdev_cnt; ++i)
2278 gdth_analyse_hdrive(hanum,i);
2279
2280 TRACE(("gdth_search_drives() OK\n"));
2281 return 1;
2282 }
2283
2284 static int gdth_analyse_hdrive(int hanum,ushort hdrive)
2285 {
2286 register gdth_ha_str *ha;
2287 ulong32 drv_cyls;
2288 int drv_hds, drv_secs;
2289
2290 TRACE(("gdth_analyse_hdrive() hanum %d drive %d\n",hanum,hdrive));
2291 if (hdrive >= MAX_HDRIVES)
2292 return 0;
2293 ha = HADATA(gdth_ctr_tab[hanum]);
2294
2295 if (!gdth_internal_cmd(hanum,CACHESERVICE,GDT_INFO,hdrive,0,0))
2296 return 0;
2297 ha->hdr[hdrive].present = TRUE;
2298 ha->hdr[hdrive].size = ha->info;
2299
2300 /* evaluate mapping (sectors per head, heads per cylinder) */
2301 ha->hdr[hdrive].size &= ~SECS32;
2302 if (ha->info2 == 0) {
2303 gdth_eval_mapping(ha->hdr[hdrive].size,&drv_cyls,&drv_hds,&drv_secs);
2304 } else {
2305 drv_hds = ha->info2 & 0xff;
2306 drv_secs = (ha->info2 >> 8) & 0xff;
2307 drv_cyls = (ulong32)ha->hdr[hdrive].size / drv_hds / drv_secs;
2308 }
2309 ha->hdr[hdrive].heads = (unchar)drv_hds;
2310 ha->hdr[hdrive].secs = (unchar)drv_secs;
2311 /* round size */
2312 ha->hdr[hdrive].size = drv_cyls * drv_hds * drv_secs;
2313
2314 if (ha->cache_feat & GDT_64BIT) {
2315 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_X_INFO,hdrive,0,0)
2316 && ha->info2 != 0) {
2317 ha->hdr[hdrive].size = ((ulong64)ha->info2 << 32) | ha->info;
2318 }
2319 }
2320 TRACE2(("gdth_search_dr() cdr. %d size %d hds %d scs %d\n",
2321 hdrive,ha->hdr[hdrive].size,drv_hds,drv_secs));
2322
2323 /* get informations about device */
2324 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_DEVTYPE,hdrive,0,0)) {
2325 TRACE2(("gdth_search_dr() cache drive %d devtype %d\n",
2326 hdrive,ha->info));
2327 ha->hdr[hdrive].devtype = (ushort)ha->info;
2328 }
2329
2330 /* cluster info */
2331 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_CLUST_INFO,hdrive,0,0)) {
2332 TRACE2(("gdth_search_dr() cache drive %d cluster info %d\n",
2333 hdrive,ha->info));
2334 if (!shared_access)
2335 ha->hdr[hdrive].cluster_type = (unchar)ha->info;
2336 }
2337
2338 /* R/W attributes */
2339 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_RW_ATTRIBS,hdrive,0,0)) {
2340 TRACE2(("gdth_search_dr() cache drive %d r/w attrib. %d\n",
2341 hdrive,ha->info));
2342 ha->hdr[hdrive].rw_attribs = (unchar)ha->info;
2343 }
2344
2345 return 1;
2346 }
2347
2348
2349 /* command queueing/sending functions */
2350
2351 static void gdth_putq(int hanum,Scsi_Cmnd *scp,unchar priority)
2352 {
2353 register gdth_ha_str *ha;
2354 register Scsi_Cmnd *pscp;
2355 register Scsi_Cmnd *nscp;
2356 ulong flags;
2357 unchar b, t;
2358
2359 TRACE(("gdth_putq() priority %d\n",priority));
2360 ha = HADATA(gdth_ctr_tab[hanum]);
2361 spin_lock_irqsave(&ha->smp_lock, flags);
2362
2363 if (scp->done != gdth_scsi_done) {
2364 scp->SCp.this_residual = (int)priority;
2365 b = virt_ctr ? NUMDATA(scp->device->host)->busnum:scp->device->channel;
2366 t = scp->device->id;
2367 if (priority >= DEFAULT_PRI) {
2368 if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
2369 (b==ha->virt_bus && t<MAX_HDRIVES && ha->hdr[t].lock)) {
2370 TRACE2(("gdth_putq(): locked IO ->update_timeout()\n"));
2371 scp->SCp.buffers_residual = gdth_update_timeout(hanum, scp, 0);
2372 }
2373 }
2374 }
2375
2376 if (ha->req_first==NULL) {
2377 ha->req_first = scp; /* queue was empty */
2378 scp->SCp.ptr = NULL;
2379 } else { /* queue not empty */
2380 pscp = ha->req_first;
2381 nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
2382 /* priority: 0-highest,..,0xff-lowest */
2383 while (nscp && (unchar)nscp->SCp.this_residual <= priority) {
2384 pscp = nscp;
2385 nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
2386 }
2387 pscp->SCp.ptr = (char *)scp;
2388 scp->SCp.ptr = (char *)nscp;
2389 }
2390 spin_unlock_irqrestore(&ha->smp_lock, flags);
2391
2392 #ifdef GDTH_STATISTICS
2393 flags = 0;
2394 for (nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
2395 ++flags;
2396 if (max_rq < flags) {
2397 max_rq = flags;
2398 TRACE3(("GDT: max_rq = %d\n",(ushort)max_rq));
2399 }
2400 #endif
2401 }
2402
2403 static void gdth_next(int hanum)
2404 {
2405 register gdth_ha_str *ha;
2406 register Scsi_Cmnd *pscp;
2407 register Scsi_Cmnd *nscp;
2408 unchar b, t, l, firsttime;
2409 unchar this_cmd, next_cmd;
2410 ulong flags = 0;
2411 int cmd_index;
2412
2413 TRACE(("gdth_next() hanum %d\n",hanum));
2414 ha = HADATA(gdth_ctr_tab[hanum]);
2415 if (!gdth_polling)
2416 spin_lock_irqsave(&ha->smp_lock, flags);
2417
2418 ha->cmd_cnt = ha->cmd_offs_dpmem = 0;
2419 this_cmd = firsttime = TRUE;
2420 next_cmd = gdth_polling ? FALSE:TRUE;
2421 cmd_index = 0;
2422
2423 for (nscp = pscp = ha->req_first; nscp; nscp = (Scsi_Cmnd *)nscp->SCp.ptr) {
2424 if (nscp != pscp && nscp != (Scsi_Cmnd *)pscp->SCp.ptr)
2425 pscp = (Scsi_Cmnd *)pscp->SCp.ptr;
2426 if (nscp->done != gdth_scsi_done) {
2427 b = virt_ctr ?
2428 NUMDATA(nscp->device->host)->busnum : nscp->device->channel;
2429 t = nscp->device->id;
2430 l = nscp->device->lun;
2431 if (nscp->SCp.this_residual >= DEFAULT_PRI) {
2432 if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
2433 (b == ha->virt_bus && t < MAX_HDRIVES && ha->hdr[t].lock))
2434 continue;
2435 }
2436 } else
2437 b = t = l = 0;
2438
2439 if (firsttime) {
2440 if (gdth_test_busy(hanum)) { /* controller busy ? */
2441 TRACE(("gdth_next() controller %d busy !\n",hanum));
2442 if (!gdth_polling) {
2443 spin_unlock_irqrestore(&ha->smp_lock, flags);
2444 return;
2445 }
2446 while (gdth_test_busy(hanum))
2447 gdth_delay(1);
2448 }
2449 firsttime = FALSE;
2450 }
2451
2452 if (nscp->done != gdth_scsi_done) {
2453 if (nscp->SCp.phase == -1) {
2454 nscp->SCp.phase = CACHESERVICE; /* default: cache svc. */
2455 if (nscp->cmnd[0] == TEST_UNIT_READY) {
2456 TRACE2(("TEST_UNIT_READY Bus %d Id %d LUN %d\n",
2457 b, t, l));
2458 /* TEST_UNIT_READY -> set scan mode */
2459 if ((ha->scan_mode & 0x0f) == 0) {
2460 if (b == 0 && t == 0 && l == 0) {
2461 ha->scan_mode |= 1;
2462 TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
2463 }
2464 } else if ((ha->scan_mode & 0x0f) == 1) {
2465 if (b == 0 && ((t == 0 && l == 1) ||
2466 (t == 1 && l == 0))) {
2467 nscp->SCp.sent_command = GDT_SCAN_START;
2468 nscp->SCp.phase = ((ha->scan_mode & 0x10 ? 1:0) << 8)
2469 | SCSIRAWSERVICE;
2470 ha->scan_mode = 0x12;
2471 TRACE2(("Scan mode: 0x%x (SCAN_START)\n",
2472 ha->scan_mode));
2473 } else {
2474 ha->scan_mode &= 0x10;
2475 TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
2476 }
2477 } else if (ha->scan_mode == 0x12) {
2478 if (b == ha->bus_cnt && t == ha->tid_cnt-1) {
2479 nscp->SCp.phase = SCSIRAWSERVICE;
2480 nscp->SCp.sent_command = GDT_SCAN_END;
2481 ha->scan_mode &= 0x10;
2482 TRACE2(("Scan mode: 0x%x (SCAN_END)\n",
2483 ha->scan_mode));
2484 }
2485 }
2486 }
2487 if (b == ha->virt_bus && nscp->cmnd[0] != INQUIRY &&
2488 nscp->cmnd[0] != READ_CAPACITY && nscp->cmnd[0] != MODE_SENSE &&
2489 (ha->hdr[t].cluster_type & CLUSTER_DRIVE)) {
2490 /* always GDT_CLUST_INFO! */
2491 nscp->SCp.sent_command = GDT_CLUST_INFO;
2492 }
2493 }
2494 }
2495
2496 if (nscp->SCp.sent_command != -1) {
2497 if ((nscp->SCp.phase & 0xff) == CACHESERVICE) {
2498 if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
2499 this_cmd = FALSE;
2500 next_cmd = FALSE;
2501 } else if ((nscp->SCp.phase & 0xff) == SCSIRAWSERVICE) {
2502 if (!(cmd_index=gdth_fill_raw_cmd(hanum,nscp,BUS_L2P(ha,b))))
2503 this_cmd = FALSE;
2504 next_cmd = FALSE;
2505 } else {
2506 memset((char*)nscp->sense_buffer,0,16);
2507 nscp->sense_buffer[0] = 0x70;
2508 nscp->sense_buffer[2] = NOT_READY;
2509 nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
2510 if (!nscp->SCp.have_data_in)
2511 nscp->SCp.have_data_in++;
2512 else
2513 nscp->scsi_done(nscp);
2514 }
2515 } else if (nscp->done == gdth_scsi_done) {
2516 if (!(cmd_index=gdth_special_cmd(hanum,nscp)))
2517 this_cmd = FALSE;
2518 next_cmd = FALSE;
2519 } else if (b != ha->virt_bus) {
2520 if (ha->raw[BUS_L2P(ha,b)].io_cnt[t] >= GDTH_MAX_RAW ||
2521 !(cmd_index=gdth_fill_raw_cmd(hanum,nscp,BUS_L2P(ha,b))))
2522 this_cmd = FALSE;
2523 else
2524 ha->raw[BUS_L2P(ha,b)].io_cnt[t]++;
2525 } else if (t >= MAX_HDRIVES || !ha->hdr[t].present || l != 0) {
2526 TRACE2(("Command 0x%x to bus %d id %d lun %d -> IGNORE\n",
2527 nscp->cmnd[0], b, t, l));
2528 nscp->result = DID_BAD_TARGET << 16;
2529 if (!nscp->SCp.have_data_in)
2530 nscp->SCp.have_data_in++;
2531 else
2532 nscp->scsi_done(nscp);
2533 } else {
2534 switch (nscp->cmnd[0]) {
2535 case TEST_UNIT_READY:
2536 case INQUIRY:
2537 case REQUEST_SENSE:
2538 case READ_CAPACITY:
2539 case VERIFY:
2540 case START_STOP:
2541 case MODE_SENSE:
2542 case SERVICE_ACTION_IN:
2543 TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
2544 nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
2545 nscp->cmnd[4],nscp->cmnd[5]));
2546 if (ha->hdr[t].media_changed && nscp->cmnd[0] != INQUIRY) {
2547 /* return UNIT_ATTENTION */
2548 TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
2549 nscp->cmnd[0], t));
2550 ha->hdr[t].media_changed = FALSE;
2551 memset((char*)nscp->sense_buffer,0,16);
2552 nscp->sense_buffer[0] = 0x70;
2553 nscp->sense_buffer[2] = UNIT_ATTENTION;
2554 nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
2555 if (!nscp->SCp.have_data_in)
2556 nscp->SCp.have_data_in++;
2557 else
2558 nscp->scsi_done(nscp);
2559 } else if (gdth_internal_cache_cmd(hanum,nscp))
2560 nscp->scsi_done(nscp);
2561 break;
2562
2563 case ALLOW_MEDIUM_REMOVAL:
2564 TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
2565 nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
2566 nscp->cmnd[4],nscp->cmnd[5]));
2567 if ( (nscp->cmnd[4]&1) && !(ha->hdr[t].devtype&1) ) {
2568 TRACE(("Prevent r. nonremov. drive->do nothing\n"));
2569 nscp->result = DID_OK << 16;
2570 nscp->sense_buffer[0] = 0;
2571 if (!nscp->SCp.have_data_in)
2572 nscp->SCp.have_data_in++;
2573 else
2574 nscp->scsi_done(nscp);
2575 } else {
2576 nscp->cmnd[3] = (ha->hdr[t].devtype&1) ? 1:0;
2577 TRACE(("Prevent/allow r. %d rem. drive %d\n",
2578 nscp->cmnd[4],nscp->cmnd[3]));
2579 if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
2580 this_cmd = FALSE;
2581 }
2582 break;
2583
2584 case RESERVE:
2585 case RELEASE:
2586 TRACE2(("cache cmd %s\n",nscp->cmnd[0] == RESERVE ?
2587 "RESERVE" : "RELEASE"));
2588 if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
2589 this_cmd = FALSE;
2590 break;
2591
2592 case READ_6:
2593 case WRITE_6:
2594 case READ_10:
2595 case WRITE_10:
2596 case READ_16:
2597 case WRITE_16:
2598 if (ha->hdr[t].media_changed) {
2599 /* return UNIT_ATTENTION */
2600 TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
2601 nscp->cmnd[0], t));
2602 ha->hdr[t].media_changed = FALSE;
2603 memset((char*)nscp->sense_buffer,0,16);
2604 nscp->sense_buffer[0] = 0x70;
2605 nscp->sense_buffer[2] = UNIT_ATTENTION;
2606 nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
2607 if (!nscp->SCp.have_data_in)
2608 nscp->SCp.have_data_in++;
2609 else
2610 nscp->scsi_done(nscp);
2611 } else if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
2612 this_cmd = FALSE;
2613 break;
2614
2615 default:
2616 TRACE2(("cache cmd %x/%x/%x/%x/%x/%x unknown\n",nscp->cmnd[0],
2617 nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
2618 nscp->cmnd[4],nscp->cmnd[5]));
2619 printk("GDT-HA %d: Unknown SCSI command 0x%x to cache service !\n",
2620 hanum, nscp->cmnd[0]);
2621 nscp->result = DID_ABORT << 16;
2622 if (!nscp->SCp.have_data_in)
2623 nscp->SCp.have_data_in++;
2624 else
2625 nscp->scsi_done(nscp);
2626 break;
2627 }
2628 }
2629
2630 if (!this_cmd)
2631 break;
2632 if (nscp == ha->req_first)
2633 ha->req_first = pscp = (Scsi_Cmnd *)nscp->SCp.ptr;
2634 else
2635 pscp->SCp.ptr = nscp->SCp.ptr;
2636 if (!next_cmd)
2637 break;
2638 }
2639
2640 if (ha->cmd_cnt > 0) {
2641 gdth_release_event(hanum);
2642 }
2643
2644 if (!gdth_polling)
2645 spin_unlock_irqrestore(&ha->smp_lock, flags);
2646
2647 if (gdth_polling && ha->cmd_cnt > 0) {
2648 if (!gdth_wait(hanum,cmd_index,POLL_TIMEOUT))
2649 printk("GDT-HA %d: Command %d timed out !\n",
2650 hanum,cmd_index);
2651 }
2652 }
2653
2654 static void gdth_copy_internal_data(int hanum,Scsi_Cmnd *scp,
2655 char *buffer,ushort count)
2656 {
2657 ushort cpcount,i;
2658 ushort cpsum,cpnow;
2659 struct scatterlist *sl;
2660 gdth_ha_str *ha;
2661 char *address;
2662
2663 cpcount = count<=(ushort)scp->request_bufflen ? count:(ushort)scp->request_bufflen;
2664 ha = HADATA(gdth_ctr_tab[hanum]);
2665
2666 if (scp->use_sg) {
2667 sl = (struct scatterlist *)scp->request_buffer;
2668 for (i=0,cpsum=0; i<scp->use_sg; ++i,++sl) {
2669 unsigned long flags;
2670 cpnow = (ushort)sl->length;
2671 TRACE(("copy_internal() now %d sum %d count %d %d\n",
2672 cpnow,cpsum,cpcount,(ushort)scp->bufflen));
2673 if (cpsum+cpnow > cpcount)
2674 cpnow = cpcount - cpsum;
2675 cpsum += cpnow;
2676 if (!sl->page) {
2677 printk("GDT-HA %d: invalid sc/gt element in gdth_copy_internal_data()\n",
2678 hanum);
2679 return;
2680 }
2681 local_irq_save(flags);
2682 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
2683 address = kmap_atomic(sl->page, KM_BIO_SRC_IRQ) + sl->offset;
2684 memcpy(address,buffer,cpnow);
2685 flush_dcache_page(sl->page);
2686 kunmap_atomic(address, KM_BIO_SRC_IRQ);
2687 #else
2688 address = kmap_atomic(sl->page, KM_BH_IRQ) + sl->offset;
2689 memcpy(address,buffer,cpnow);
2690 flush_dcache_page(sl->page);
2691 kunmap_atomic(address, KM_BH_IRQ);
2692 #endif
2693 local_irq_restore(flags);
2694 if (cpsum == cpcount)
2695 break;
2696 buffer += cpnow;
2697 }
2698 } else {
2699 TRACE(("copy_internal() count %d\n",cpcount));
2700 memcpy((char*)scp->request_buffer,buffer,cpcount);
2701 }
2702 }
2703
2704 static int gdth_internal_cache_cmd(int hanum,Scsi_Cmnd *scp)
2705 {
2706 register gdth_ha_str *ha;
2707 unchar t;
2708 gdth_inq_data inq;
2709 gdth_rdcap_data rdc;
2710 gdth_sense_data sd;
2711 gdth_modep_data mpd;
2712
2713 ha = HADATA(gdth_ctr_tab[hanum]);
2714 t = scp->device->id;
2715 TRACE(("gdth_internal_cache_cmd() cmd 0x%x hdrive %d\n",
2716 scp->cmnd[0],t));
2717
2718 scp->result = DID_OK << 16;
2719 scp->sense_buffer[0] = 0;
2720
2721 switch (scp->cmnd[0]) {
2722 case TEST_UNIT_READY:
2723 case VERIFY:
2724 case START_STOP:
2725 TRACE2(("Test/Verify/Start hdrive %d\n",t));
2726 break;
2727
2728 case INQUIRY:
2729 TRACE2(("Inquiry hdrive %d devtype %d\n",
2730 t,ha->hdr[t].devtype));
2731 inq.type_qual = (ha->hdr[t].devtype&4) ? TYPE_ROM:TYPE_DISK;
2732 /* you can here set all disks to removable, if you want to do
2733 a flush using the ALLOW_MEDIUM_REMOVAL command */
2734 inq.modif_rmb = 0x00;
2735 if ((ha->hdr[t].devtype & 1) ||
2736 (ha->hdr[t].cluster_type & CLUSTER_DRIVE))
2737 inq.modif_rmb = 0x80;
2738 inq.version = 2;
2739 inq.resp_aenc = 2;
2740 inq.add_length= 32;
2741 strcpy(inq.vendor,ha->oem_name);
2742 sprintf(inq.product,"Host Drive #%02d",t);
2743 strcpy(inq.revision," ");
2744 gdth_copy_internal_data(hanum,scp,(char*)&inq,sizeof(gdth_inq_data));
2745 break;
2746
2747 case REQUEST_SENSE:
2748 TRACE2(("Request sense hdrive %d\n",t));
2749 sd.errorcode = 0x70;
2750 sd.segno = 0x00;
2751 sd.key = NO_SENSE;
2752 sd.info = 0;
2753 sd.add_length= 0;
2754 gdth_copy_internal_data(hanum,scp,(char*)&sd,sizeof(gdth_sense_data));
2755 break;
2756
2757 case MODE_SENSE:
2758 TRACE2(("Mode sense hdrive %d\n",t));
2759 memset((char*)&mpd,0,sizeof(gdth_modep_data));
2760 mpd.hd.data_length = sizeof(gdth_modep_data);
2761 mpd.hd.dev_par = (ha->hdr[t].devtype&2) ? 0x80:0;
2762 mpd.hd.bd_length = sizeof(mpd.bd);
2763 mpd.bd.block_length[0] = (SECTOR_SIZE & 0x00ff0000) >> 16;
2764 mpd.bd.block_length[1] = (SECTOR_SIZE & 0x0000ff00) >> 8;
2765 mpd.bd.block_length[2] = (SECTOR_SIZE & 0x000000ff);
2766 gdth_copy_internal_data(hanum,scp,(char*)&mpd,sizeof(gdth_modep_data));
2767 break;
2768
2769 case READ_CAPACITY:
2770 TRACE2(("Read capacity hdrive %d\n",t));
2771 if (ha->hdr[t].size > (ulong64)0xffffffff)
2772 rdc.last_block_no = 0xffffffff;
2773 else
2774 rdc.last_block_no = cpu_to_be32(ha->hdr[t].size-1);
2775 rdc.block_length = cpu_to_be32(SECTOR_SIZE);
2776 gdth_copy_internal_data(hanum,scp,(char*)&rdc,sizeof(gdth_rdcap_data));
2777 break;
2778
2779 case SERVICE_ACTION_IN:
2780 if ((scp->cmnd[1] & 0x1f) == SAI_READ_CAPACITY_16 &&
2781 (ha->cache_feat & GDT_64BIT)) {
2782 gdth_rdcap16_data rdc16;
2783
2784 TRACE2(("Read capacity (16) hdrive %d\n",t));
2785 rdc16.last_block_no = cpu_to_be64(ha->hdr[t].size-1);
2786 rdc16.block_length = cpu_to_be32(SECTOR_SIZE);
2787 gdth_copy_internal_data(hanum,scp,(char*)&rdc16,sizeof(gdth_rdcap16_data));
2788 } else {
2789 scp->result = DID_ABORT << 16;
2790 }
2791 break;
2792
2793 default:
2794 TRACE2(("Internal cache cmd 0x%x unknown\n",scp->cmnd[0]));
2795 break;
2796 }
2797
2798 if (!scp->SCp.have_data_in)
2799 scp->SCp.have_data_in++;
2800 else
2801 return 1;
2802
2803 return 0;
2804 }
2805
2806 static int gdth_fill_cache_cmd(int hanum,Scsi_Cmnd *scp,ushort hdrive)
2807 {
2808 register gdth_ha_str *ha;
2809 register gdth_cmd_str *cmdp;
2810 struct scatterlist *sl;
2811 ulong32 cnt, blockcnt;
2812 ulong64 no, blockno;
2813 dma_addr_t phys_addr;
2814 int i, cmd_index, read_write, sgcnt, mode64;
2815 struct page *page;
2816 ulong offset;
2817
2818 ha = HADATA(gdth_ctr_tab[hanum]);
2819 cmdp = ha->pccb;
2820 TRACE(("gdth_fill_cache_cmd() cmd 0x%x cmdsize %d hdrive %d\n",
2821 scp->cmnd[0],scp->cmd_len,hdrive));
2822
2823 if (ha->type==GDT_EISA && ha->cmd_cnt>0)
2824 return 0;
2825
2826 mode64 = (ha->cache_feat & GDT_64BIT) ? TRUE : FALSE;
2827 /* test for READ_16, WRITE_16 if !mode64 ? ---
2828 not required, should not occur due to error return on
2829 READ_CAPACITY_16 */
2830
2831 cmdp->Service = CACHESERVICE;
2832 cmdp->RequestBuffer = scp;
2833 /* search free command index */
2834 if (!(cmd_index=gdth_get_cmd_index(hanum))) {
2835 TRACE(("GDT: No free command index found\n"));
2836 return 0;
2837 }
2838 /* if it's the first command, set command semaphore */
2839 if (ha->cmd_cnt == 0)
2840 gdth_set_sema0(hanum);
2841
2842 /* fill command */
2843 read_write = 0;
2844 if (scp->SCp.sent_command != -1)
2845 cmdp->OpCode = scp->SCp.sent_command; /* special cache cmd. */
2846 else if (scp->cmnd[0] == RESERVE)
2847 cmdp->OpCode = GDT_RESERVE_DRV;
2848 else if (scp->cmnd[0] == RELEASE)
2849 cmdp->OpCode = GDT_RELEASE_DRV;
2850 else if (scp->cmnd[0] == ALLOW_MEDIUM_REMOVAL) {
2851 if (scp->cmnd[4] & 1) /* prevent ? */
2852 cmdp->OpCode = GDT_MOUNT;
2853 else if (scp->cmnd[3] & 1) /* removable drive ? */
2854 cmdp->OpCode = GDT_UNMOUNT;
2855 else
2856 cmdp->OpCode = GDT_FLUSH;
2857 } else if (scp->cmnd[0] == WRITE_6 || scp->cmnd[0] == WRITE_10 ||
2858 scp->cmnd[0] == WRITE_12 || scp->cmnd[0] == WRITE_16
2859 ) {
2860 read_write = 1;
2861 if (gdth_write_through || ((ha->hdr[hdrive].rw_attribs & 1) &&
2862 (ha->cache_feat & GDT_WR_THROUGH)))
2863 cmdp->OpCode = GDT_WRITE_THR;
2864 else
2865 cmdp->OpCode = GDT_WRITE;
2866 } else {
2867 read_write = 2;
2868 cmdp->OpCode = GDT_READ;
2869 }
2870
2871 cmdp->BoardNode = LOCALBOARD;
2872 if (mode64) {
2873 cmdp->u.cache64.DeviceNo = hdrive;
2874 cmdp->u.cache64.BlockNo = 1;
2875 cmdp->u.cache64.sg_canz = 0;
2876 } else {
2877 cmdp->u.cache.DeviceNo = hdrive;
2878 cmdp->u.cache.BlockNo = 1;
2879 cmdp->u.cache.sg_canz = 0;
2880 }
2881
2882 if (read_write) {
2883 if (scp->cmd_len == 16) {
2884 memcpy(&no, &scp->cmnd[2], sizeof(ulong64));
2885 blockno = be64_to_cpu(no);
2886 memcpy(&cnt, &scp->cmnd[10], sizeof(ulong32));
2887 blockcnt = be32_to_cpu(cnt);
2888 } else if (scp->cmd_len == 10) {
2889 memcpy(&no, &scp->cmnd[2], sizeof(ulong32));
2890 blockno = be32_to_cpu(no);
2891 memcpy(&cnt, &scp->cmnd[7], sizeof(ushort));
2892 blockcnt = be16_to_cpu(cnt);
2893 } else {
2894 memcpy(&no, &scp->cmnd[0], sizeof(ulong32));
2895 blockno = be32_to_cpu(no) & 0x001fffffUL;
2896 blockcnt= scp->cmnd[4]==0 ? 0x100 : scp->cmnd[4];
2897 }
2898 if (mode64) {
2899 cmdp->u.cache64.BlockNo = blockno;
2900 cmdp->u.cache64.BlockCnt = blockcnt;
2901 } else {
2902 cmdp->u.cache.BlockNo = (ulong32)blockno;
2903 cmdp->u.cache.BlockCnt = blockcnt;
2904 }
2905
2906 if (scp->use_sg) {
2907 sl = (struct scatterlist *)scp->request_buffer;
2908 sgcnt = scp->use_sg;
2909 scp->SCp.Status = GDTH_MAP_SG;
2910 scp->SCp.Message = (read_write == 1 ?
2911 PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
2912 sgcnt = pci_map_sg(ha->pdev,sl,scp->use_sg,scp->SCp.Message);
2913 if (mode64) {
2914 cmdp->u.cache64.DestAddr= (ulong64)-1;
2915 cmdp->u.cache64.sg_canz = sgcnt;
2916 for (i=0; i<sgcnt; ++i,++sl) {
2917 cmdp->u.cache64.sg_lst[i].sg_ptr = sg_dma_address(sl);
2918 #ifdef GDTH_DMA_STATISTICS
2919 if (cmdp->u.cache64.sg_lst[i].sg_ptr > (ulong64)0xffffffff)
2920 ha->dma64_cnt++;
2921 else
2922 ha->dma32_cnt++;
2923 #endif
2924 cmdp->u.cache64.sg_lst[i].sg_len = sg_dma_len(sl);
2925 }
2926 } else {
2927 cmdp->u.cache.DestAddr= 0xffffffff;
2928 cmdp->u.cache.sg_canz = sgcnt;
2929 for (i=0; i<sgcnt; ++i,++sl) {
2930 cmdp->u.cache.sg_lst[i].sg_ptr = sg_dma_address(sl);
2931 #ifdef GDTH_DMA_STATISTICS
2932 ha->dma32_cnt++;
2933 #endif
2934 cmdp->u.cache.sg_lst[i].sg_len = sg_dma_len(sl);
2935 }
2936 }
2937
2938 #ifdef GDTH_STATISTICS
2939 if (max_sg < (ulong32)sgcnt) {
2940 max_sg = (ulong32)sgcnt;
2941 TRACE3(("GDT: max_sg = %d\n",max_sg));
2942 }
2943 #endif
2944
2945 } else if (scp->request_bufflen) {
2946 scp->SCp.Status = GDTH_MAP_SINGLE;
2947 scp->SCp.Message = (read_write == 1 ?
2948 PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
2949 page = virt_to_page(scp->request_buffer);
2950 offset = (ulong)scp->request_buffer & ~PAGE_MASK;
2951 phys_addr = pci_map_page(ha->pdev,page,offset,
2952 scp->request_bufflen,scp->SCp.Message);
2953 scp->SCp.dma_handle = phys_addr;
2954 if (mode64) {
2955 if (ha->cache_feat & SCATTER_GATHER) {
2956 cmdp->u.cache64.DestAddr = (ulong64)-1;
2957 cmdp->u.cache64.sg_canz = 1;
2958 cmdp->u.cache64.sg_lst[0].sg_ptr = phys_addr;
2959 cmdp->u.cache64.sg_lst[0].sg_len = scp->request_bufflen;
2960 cmdp->u.cache64.sg_lst[1].sg_len = 0;
2961 } else {
2962 cmdp->u.cache64.DestAddr = phys_addr;
2963 cmdp->u.cache64.sg_canz= 0;
2964 }
2965 } else {
2966 if (ha->cache_feat & SCATTER_GATHER) {
2967 cmdp->u.cache.DestAddr = 0xffffffff;
2968 cmdp->u.cache.sg_canz = 1;
2969 cmdp->u.cache.sg_lst[0].sg_ptr = phys_addr;
2970 cmdp->u.cache.sg_lst[0].sg_len = scp->request_bufflen;
2971 cmdp->u.cache.sg_lst[1].sg_len = 0;
2972 } else {
2973 cmdp->u.cache.DestAddr = phys_addr;
2974 cmdp->u.cache.sg_canz= 0;
2975 }
2976 }
2977 }
2978 }
2979 /* evaluate command size, check space */
2980 if (mode64) {
2981 TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
2982 cmdp->u.cache64.DestAddr,cmdp->u.cache64.sg_canz,
2983 cmdp->u.cache64.sg_lst[0].sg_ptr,
2984 cmdp->u.cache64.sg_lst[0].sg_len));
2985 TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
2986 cmdp->OpCode,cmdp->u.cache64.BlockNo,cmdp->u.cache64.BlockCnt));
2987 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) +
2988 (ushort)cmdp->u.cache64.sg_canz * sizeof(gdth_sg64_str);
2989 } else {
2990 TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
2991 cmdp->u.cache.DestAddr,cmdp->u.cache.sg_canz,
2992 cmdp->u.cache.sg_lst[0].sg_ptr,
2993 cmdp->u.cache.sg_lst[0].sg_len));
2994 TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
2995 cmdp->OpCode,cmdp->u.cache.BlockNo,cmdp->u.cache.BlockCnt));
2996 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) +
2997 (ushort)cmdp->u.cache.sg_canz * sizeof(gdth_sg_str);
2998 }
2999 if (ha->cmd_len & 3)
3000 ha->cmd_len += (4 - (ha->cmd_len & 3));
3001
3002 if (ha->cmd_cnt > 0) {
3003 if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
3004 ha->ic_all_size) {
3005 TRACE2(("gdth_fill_cache() DPMEM overflow\n"));
3006 ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
3007 return 0;
3008 }
3009 }
3010
3011 /* copy command */
3012 gdth_copy_command(hanum);
3013 return cmd_index;
3014 }
3015
3016 static int gdth_fill_raw_cmd(int hanum,Scsi_Cmnd *scp,unchar b)
3017 {
3018 register gdth_ha_str *ha;
3019 register gdth_cmd_str *cmdp;
3020 struct scatterlist *sl;
3021 ushort i;
3022 dma_addr_t phys_addr, sense_paddr;
3023 int cmd_index, sgcnt, mode64;
3024 unchar t,l;
3025 struct page *page;
3026 ulong offset;
3027
3028 ha = HADATA(gdth_ctr_tab[hanum]);
3029 t = scp->device->id;
3030 l = scp->device->lun;
3031 cmdp = ha->pccb;
3032 TRACE(("gdth_fill_raw_cmd() cmd 0x%x bus %d ID %d LUN %d\n",
3033 scp->cmnd[0],b,t,l));
3034
3035 if (ha->type==GDT_EISA && ha->cmd_cnt>0)
3036 return 0;
3037
3038 mode64 = (ha->raw_feat & GDT_64BIT) ? TRUE : FALSE;
3039
3040 cmdp->Service = SCSIRAWSERVICE;
3041 cmdp->RequestBuffer = scp;
3042 /* search free command index */
3043 if (!(cmd_index=gdth_get_cmd_index(hanum))) {
3044 TRACE(("GDT: No free command index found\n"));
3045 return 0;
3046 }
3047 /* if it's the first command, set command semaphore */
3048 if (ha->cmd_cnt == 0)
3049 gdth_set_sema0(hanum);
3050
3051 /* fill command */
3052 if (scp->SCp.sent_command != -1) {
3053 cmdp->OpCode = scp->SCp.sent_command; /* special raw cmd. */
3054 cmdp->BoardNode = LOCALBOARD;
3055 if (mode64) {
3056 cmdp->u.raw64.direction = (scp->SCp.phase >> 8);
3057 TRACE2(("special raw cmd 0x%x param 0x%x\n",
3058 cmdp->OpCode, cmdp->u.raw64.direction));
3059 /* evaluate command size */
3060 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst);
3061 } else {
3062 cmdp->u.raw.direction = (scp->SCp.phase >> 8);
3063 TRACE2(("special raw cmd 0x%x param 0x%x\n",
3064 cmdp->OpCode, cmdp->u.raw.direction));
3065 /* evaluate command size */
3066 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst);
3067 }
3068
3069 } else {
3070 page = virt_to_page(scp->sense_buffer);
3071 offset = (ulong)scp->sense_buffer & ~PAGE_MASK;
3072 sense_paddr = pci_map_page(ha->pdev,page,offset,
3073 16,PCI_DMA_FROMDEVICE);
3074 *(ulong32 *)&scp->SCp.buffer = (ulong32)sense_paddr;
3075 /* high part, if 64bit */
3076 *(ulong32 *)&scp->host_scribble = (ulong32)((ulong64)sense_paddr >> 32);
3077 cmdp->OpCode = GDT_WRITE; /* always */
3078 cmdp->BoardNode = LOCALBOARD;
3079 if (mode64) {
3080 cmdp->u.raw64.reserved = 0;
3081 cmdp->u.raw64.mdisc_time = 0;
3082 cmdp->u.raw64.mcon_time = 0;
3083 cmdp->u.raw64.clen = scp->cmd_len;
3084 cmdp->u.raw64.target = t;
3085 cmdp->u.raw64.lun = l;
3086 cmdp->u.raw64.bus = b;
3087 cmdp->u.raw64.priority = 0;
3088 cmdp->u.raw64.sdlen = scp->request_bufflen;
3089 cmdp->u.raw64.sense_len = 16;
3090 cmdp->u.raw64.sense_data = sense_paddr;
3091 cmdp->u.raw64.direction =
3092 gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
3093 memcpy(cmdp->u.raw64.cmd,scp->cmnd,16);
3094 cmdp->u.raw64.sg_ranz = 0;
3095 } else {
3096 cmdp->u.raw.reserved = 0;
3097 cmdp->u.raw.mdisc_time = 0;
3098 cmdp->u.raw.mcon_time = 0;
3099 cmdp->u.raw.clen = scp->cmd_len;
3100 cmdp->u.raw.target = t;
3101 cmdp->u.raw.lun = l;
3102 cmdp->u.raw.bus = b;
3103 cmdp->u.raw.priority = 0;
3104 cmdp->u.raw.link_p = 0;
3105 cmdp->u.raw.sdlen = scp->request_bufflen;
3106 cmdp->u.raw.sense_len = 16;
3107 cmdp->u.raw.sense_data = sense_paddr;
3108 cmdp->u.raw.direction =
3109 gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
3110 memcpy(cmdp->u.raw.cmd,scp->cmnd,12);
3111 cmdp->u.raw.sg_ranz = 0;
3112 }
3113
3114 if (scp->use_sg) {
3115 sl = (struct scatterlist *)scp->request_buffer;
3116 sgcnt = scp->use_sg;
3117 scp->SCp.Status = GDTH_MAP_SG;
3118 scp->SCp.Message = PCI_DMA_BIDIRECTIONAL;
3119 sgcnt = pci_map_sg(ha->pdev,sl,scp->use_sg,scp->SCp.Message);
3120 if (mode64) {
3121 cmdp->u.raw64.sdata = (ulong64)-1;
3122 cmdp->u.raw64.sg_ranz = sgcnt;
3123 for (i=0; i<sgcnt; ++i,++sl) {
3124 cmdp->u.raw64.sg_lst[i].sg_ptr = sg_dma_address(sl);
3125 #ifdef GDTH_DMA_STATISTICS
3126 if (cmdp->u.raw64.sg_lst[i].sg_ptr > (ulong64)0xffffffff)
3127 ha->dma64_cnt++;
3128 else
3129 ha->dma32_cnt++;
3130 #endif
3131 cmdp->u.raw64.sg_lst[i].sg_len = sg_dma_len(sl);
3132 }
3133 } else {
3134 cmdp->u.raw.sdata = 0xffffffff;
3135 cmdp->u.raw.sg_ranz = sgcnt;
3136 for (i=0; i<sgcnt; ++i,++sl) {
3137 cmdp->u.raw.sg_lst[i].sg_ptr = sg_dma_address(sl);
3138 #ifdef GDTH_DMA_STATISTICS
3139 ha->dma32_cnt++;
3140 #endif
3141 cmdp->u.raw.sg_lst[i].sg_len = sg_dma_len(sl);
3142 }
3143 }
3144
3145 #ifdef GDTH_STATISTICS
3146 if (max_sg < sgcnt) {
3147 max_sg = sgcnt;
3148 TRACE3(("GDT: max_sg = %d\n",sgcnt));
3149 }
3150 #endif
3151
3152 } else if (scp->request_bufflen) {
3153 scp->SCp.Status = GDTH_MAP_SINGLE;
3154 scp->SCp.Message = PCI_DMA_BIDIRECTIONAL;
3155 page = virt_to_page(scp->request_buffer);
3156 offset = (ulong)scp->request_buffer & ~PAGE_MASK;
3157 phys_addr = pci_map_page(ha->pdev,page,offset,
3158 scp->request_bufflen,scp->SCp.Message);
3159 scp->SCp.dma_handle = phys_addr;
3160
3161 if (mode64) {
3162 if (ha->raw_feat & SCATTER_GATHER) {
3163 cmdp->u.raw64.sdata = (ulong64)-1;
3164 cmdp->u.raw64.sg_ranz= 1;
3165 cmdp->u.raw64.sg_lst[0].sg_ptr = phys_addr;
3166 cmdp->u.raw64.sg_lst[0].sg_len = scp->request_bufflen;
3167 cmdp->u.raw64.sg_lst[1].sg_len = 0;
3168 } else {
3169 cmdp->u.raw64.sdata = phys_addr;
3170 cmdp->u.raw64.sg_ranz= 0;
3171 }
3172 } else {
3173 if (ha->raw_feat & SCATTER_GATHER) {
3174 cmdp->u.raw.sdata = 0xffffffff;
3175 cmdp->u.raw.sg_ranz= 1;
3176 cmdp->u.raw.sg_lst[0].sg_ptr = phys_addr;
3177 cmdp->u.raw.sg_lst[0].sg_len = scp->request_bufflen;
3178 cmdp->u.raw.sg_lst[1].sg_len = 0;
3179 } else {
3180 cmdp->u.raw.sdata = phys_addr;
3181 cmdp->u.raw.sg_ranz= 0;
3182 }
3183 }
3184 }
3185 if (mode64) {
3186 TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
3187 cmdp->u.raw64.sdata,cmdp->u.raw64.sg_ranz,
3188 cmdp->u.raw64.sg_lst[0].sg_ptr,
3189 cmdp->u.raw64.sg_lst[0].sg_len));
3190 /* evaluate command size */
3191 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) +
3192 (ushort)cmdp->u.raw64.sg_ranz * sizeof(gdth_sg64_str);
3193 } else {
3194 TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
3195 cmdp->u.raw.sdata,cmdp->u.raw.sg_ranz,
3196 cmdp->u.raw.sg_lst[0].sg_ptr,
3197 cmdp->u.raw.sg_lst[0].sg_len));
3198 /* evaluate command size */
3199 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) +
3200 (ushort)cmdp->u.raw.sg_ranz * sizeof(gdth_sg_str);
3201 }
3202 }
3203 /* check space */
3204 if (ha->cmd_len & 3)
3205 ha->cmd_len += (4 - (ha->cmd_len & 3));
3206
3207 if (ha->cmd_cnt > 0) {
3208 if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
3209 ha->ic_all_size) {
3210 TRACE2(("gdth_fill_raw() DPMEM overflow\n"));
3211 ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
3212 return 0;
3213 }
3214 }
3215
3216 /* copy command */
3217 gdth_copy_command(hanum);
3218 return cmd_index;
3219 }
3220
3221 static int gdth_special_cmd(int hanum,Scsi_Cmnd *scp)
3222 {
3223 register gdth_ha_str *ha;
3224 register gdth_cmd_str *cmdp;
3225 int cmd_index;
3226
3227 ha = HADATA(gdth_ctr_tab[hanum]);
3228 cmdp= ha->pccb;
3229 TRACE2(("gdth_special_cmd(): "));
3230
3231 if (ha->type==GDT_EISA && ha->cmd_cnt>0)
3232 return 0;
3233
3234 memcpy( cmdp, scp->request_buffer, sizeof(gdth_cmd_str));
3235 cmdp->RequestBuffer = scp;
3236
3237 /* search free command index */
3238 if (!(cmd_index=gdth_get_cmd_index(hanum))) {
3239 TRACE(("GDT: No free command index found\n"));
3240 return 0;
3241 }
3242
3243 /* if it's the first command, set command semaphore */
3244 if (ha->cmd_cnt == 0)
3245 gdth_set_sema0(hanum);
3246
3247 /* evaluate command size, check space */
3248 if (cmdp->OpCode == GDT_IOCTL) {
3249 TRACE2(("IOCTL\n"));
3250 ha->cmd_len =
3251 GDTOFFSOF(gdth_cmd_str,u.ioctl.p_param) + sizeof(ulong64);
3252 } else if (cmdp->Service == CACHESERVICE) {
3253 TRACE2(("cache command %d\n",cmdp->OpCode));
3254 if (ha->cache_feat & GDT_64BIT)
3255 ha->cmd_len =
3256 GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) + sizeof(gdth_sg64_str);
3257 else
3258 ha->cmd_len =
3259 GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) + sizeof(gdth_sg_str);
3260 } else if (cmdp->Service == SCSIRAWSERVICE) {
3261 TRACE2(("raw command %d\n",cmdp->OpCode));
3262 if (ha->raw_feat & GDT_64BIT)
3263 ha->cmd_len =
3264 GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) + sizeof(gdth_sg64_str);
3265 else
3266 ha->cmd_len =
3267 GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) + sizeof(gdth_sg_str);
3268 }
3269
3270 if (ha->cmd_len & 3)
3271 ha->cmd_len += (4 - (ha->cmd_len & 3));
3272
3273 if (ha->cmd_cnt > 0) {
3274 if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
3275 ha->ic_all_size) {
3276 TRACE2(("gdth_special_cmd() DPMEM overflow\n"));
3277 ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
3278 return 0;
3279 }
3280 }
3281
3282 /* copy command */
3283 gdth_copy_command(hanum);
3284 return cmd_index;
3285 }
3286
3287
3288 /* Controller event handling functions */
3289 static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source,
3290 ushort idx, gdth_evt_data *evt)
3291 {
3292 gdth_evt_str *e;
3293 struct timeval tv;
3294
3295 /* no GDTH_LOCK_HA() ! */
3296 TRACE2(("gdth_store_event() source %d idx %d\n", source, idx));
3297 if (source == 0) /* no source -> no event */
3298 return NULL;
3299
3300 if (ebuffer[elastidx].event_source == source &&
3301 ebuffer[elastidx].event_idx == idx &&
3302 ((evt->size != 0 && ebuffer[elastidx].event_data.size != 0 &&
3303 !memcmp((char *)&ebuffer[elastidx].event_data.eu,
3304 (char *)&evt->eu, evt->size)) ||
3305 (evt->size == 0 && ebuffer[elastidx].event_data.size == 0 &&
3306 !strcmp((char *)&ebuffer[elastidx].event_data.event_string,
3307 (char *)&evt->event_string)))) {
3308 e = &ebuffer[elastidx];
3309 do_gettimeofday(&tv);
3310 e->last_stamp = tv.tv_sec;
3311 ++e->same_count;
3312 } else {
3313 if (ebuffer[elastidx].event_source != 0) { /* entry not free ? */
3314 ++elastidx;
3315 if (elastidx == MAX_EVENTS)
3316 elastidx = 0;
3317 if (elastidx == eoldidx) { /* reached mark ? */
3318 ++eoldidx;
3319 if (eoldidx == MAX_EVENTS)
3320 eoldidx = 0;
3321 }
3322 }
3323 e = &ebuffer[elastidx];
3324 e->event_source = source;
3325 e->event_idx = idx;
3326 do_gettimeofday(&tv);
3327 e->first_stamp = e->last_stamp = tv.tv_sec;
3328 e->same_count = 1;
3329 e->event_data = *evt;
3330 e->application = 0;
3331 }
3332 return e;
3333 }
3334
3335 static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr)
3336 {
3337 gdth_evt_str *e;
3338 int eindex;
3339 ulong flags;
3340
3341 TRACE2(("gdth_read_event() handle %d\n", handle));
3342 spin_lock_irqsave(&ha->smp_lock, flags);
3343 if (handle == -1)
3344 eindex = eoldidx;
3345 else
3346 eindex = handle;
3347 estr->event_source = 0;
3348
3349 if (eindex >= MAX_EVENTS) {
3350 spin_unlock_irqrestore(&ha->smp_lock, flags);
3351 return eindex;
3352 }
3353 e = &ebuffer[eindex];
3354 if (e->event_source != 0) {
3355 if (eindex != elastidx) {
3356 if (++eindex == MAX_EVENTS)
3357 eindex = 0;
3358 } else {
3359 eindex = -1;
3360 }
3361 memcpy(estr, e, sizeof(gdth_evt_str));
3362 }
3363 spin_unlock_irqrestore(&ha->smp_lock, flags);
3364 return eindex;
3365 }
3366
3367 static void gdth_readapp_event(gdth_ha_str *ha,
3368 unchar application, gdth_evt_str *estr)
3369 {
3370 gdth_evt_str *e;
3371 int eindex;
3372 ulong flags;
3373 unchar found = FALSE;
3374
3375 TRACE2(("gdth_readapp_event() app. %d\n", application));
3376 spin_lock_irqsave(&ha->smp_lock, flags);
3377 eindex = eoldidx;
3378 for (;;) {
3379 e = &ebuffer[eindex];
3380 if (e->event_source == 0)
3381 break;
3382 if ((e->application & application) == 0) {
3383 e->application |= application;
3384 found = TRUE;
3385 break;
3386 }
3387 if (eindex == elastidx)
3388 break;
3389 if (++eindex == MAX_EVENTS)
3390 eindex = 0;
3391 }
3392 if (found)
3393 memcpy(estr, e, sizeof(gdth_evt_str));
3394 else
3395 estr->event_source = 0;
3396 spin_unlock_irqrestore(&ha->smp_lock, flags);
3397 }
3398
3399 static void gdth_clear_events(void)
3400 {
3401 TRACE(("gdth_clear_events()"));
3402
3403 eoldidx = elastidx = 0;
3404 ebuffer[0].event_source = 0;
3405 }
3406
3407
3408 /* SCSI interface functions */
3409
3410 static irqreturn_t gdth_interrupt(int irq,void *dev_id)
3411 {
3412 gdth_ha_str *ha2 = (gdth_ha_str *)dev_id;
3413 register gdth_ha_str *ha;
3414 gdt6m_dpram_str __iomem *dp6m_ptr = NULL;
3415 gdt6_dpram_str __iomem *dp6_ptr;
3416 gdt2_dpram_str __iomem *dp2_ptr;
3417 Scsi_Cmnd *scp;
3418 int hanum, rval, i;
3419 unchar IStatus;
3420 ushort Service;
3421 ulong flags = 0;
3422 #ifdef INT_COAL
3423 int coalesced = FALSE;
3424 int next = FALSE;
3425 gdth_coal_status *pcs = NULL;
3426 int act_int_coal = 0;
3427 #endif
3428
3429 TRACE(("gdth_interrupt() IRQ %d\n",irq));
3430
3431 /* if polling and not from gdth_wait() -> return */
3432 if (gdth_polling) {
3433 if (!gdth_from_wait) {
3434 return IRQ_HANDLED;
3435 }
3436 }
3437
3438 if (!gdth_polling)
3439 spin_lock_irqsave(&ha2->smp_lock, flags);
3440 wait_index = 0;
3441
3442 /* search controller */
3443 if ((hanum = gdth_get_status(&IStatus,irq)) == -1) {
3444 /* spurious interrupt */
3445 if (!gdth_polling)
3446 spin_unlock_irqrestore(&ha2->smp_lock, flags);
3447 return IRQ_HANDLED;
3448 }
3449 ha = HADATA(gdth_ctr_tab[hanum]);
3450
3451 #ifdef GDTH_STATISTICS
3452 ++act_ints;
3453 #endif
3454
3455 #ifdef INT_COAL
3456 /* See if the fw is returning coalesced status */
3457 if (IStatus == COALINDEX) {
3458 /* Coalesced status. Setup the initial status
3459 buffer pointer and flags */
3460 pcs = ha->coal_stat;
3461 coalesced = TRUE;
3462 next = TRUE;
3463 }
3464
3465 do {
3466 if (coalesced) {
3467 /* For coalesced requests all status
3468 information is found in the status buffer */
3469 IStatus = (unchar)(pcs->status & 0xff);
3470 }
3471 #endif
3472
3473 if (ha->type == GDT_EISA) {
3474 if (IStatus & 0x80) { /* error flag */
3475 IStatus &= ~0x80;
3476 ha->status = inw(ha->bmic + MAILBOXREG+8);
3477 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3478 } else /* no error */
3479 ha->status = S_OK;
3480 ha->info = inl(ha->bmic + MAILBOXREG+12);
3481 ha->service = inw(ha->bmic + MAILBOXREG+10);
3482 ha->info2 = inl(ha->bmic + MAILBOXREG+4);
3483
3484 outb(0xff, ha->bmic + EDOORREG); /* acknowledge interrupt */
3485 outb(0x00, ha->bmic + SEMA1REG); /* reset status semaphore */
3486 } else if (ha->type == GDT_ISA) {
3487 dp2_ptr = ha->brd;
3488 if (IStatus & 0x80) { /* error flag */
3489 IStatus &= ~0x80;
3490 ha->status = gdth_readw(&dp2_ptr->u.ic.Status);
3491 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3492 } else /* no error */
3493 ha->status = S_OK;
3494 ha->info = gdth_readl(&dp2_ptr->u.ic.Info[0]);
3495 ha->service = gdth_readw(&dp2_ptr->u.ic.Service);
3496 ha->info2 = gdth_readl(&dp2_ptr->u.ic.Info[1]);
3497
3498 gdth_writeb(0xff, &dp2_ptr->io.irqdel); /* acknowledge interrupt */
3499 gdth_writeb(0, &dp2_ptr->u.ic.Cmd_Index);/* reset command index */
3500 gdth_writeb(0, &dp2_ptr->io.Sema1); /* reset status semaphore */
3501 } else if (ha->type == GDT_PCI) {
3502 dp6_ptr = ha->brd;
3503 if (IStatus & 0x80) { /* error flag */
3504 IStatus &= ~0x80;
3505 ha->status = gdth_readw(&dp6_ptr->u.ic.Status);
3506 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3507 } else /* no error */
3508 ha->status = S_OK;
3509 ha->info = gdth_readl(&dp6_ptr->u.ic.Info[0]);
3510 ha->service = gdth_readw(&dp6_ptr->u.ic.Service);
3511 ha->info2 = gdth_readl(&dp6_ptr->u.ic.Info[1]);
3512
3513 gdth_writeb(0xff, &dp6_ptr->io.irqdel); /* acknowledge interrupt */
3514 gdth_writeb(0, &dp6_ptr->u.ic.Cmd_Index);/* reset command index */
3515 gdth_writeb(0, &dp6_ptr->io.Sema1); /* reset status semaphore */
3516 } else if (ha->type == GDT_PCINEW) {
3517 if (IStatus & 0x80) { /* error flag */
3518 IStatus &= ~0x80;
3519 ha->status = inw(PTR2USHORT(&ha->plx->status));
3520 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3521 } else
3522 ha->status = S_OK;
3523 ha->info = inl(PTR2USHORT(&ha->plx->info[0]));
3524 ha->service = inw(PTR2USHORT(&ha->plx->service));
3525 ha->info2 = inl(PTR2USHORT(&ha->plx->info[1]));
3526
3527 outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
3528 outb(0x00, PTR2USHORT(&ha->plx->sema1_reg));
3529 } else if (ha->type == GDT_PCIMPR) {
3530 dp6m_ptr = ha->brd;
3531 if (IStatus & 0x80) { /* error flag */
3532 IStatus &= ~0x80;
3533 #ifdef INT_COAL
3534 if (coalesced)
3535 ha->status = pcs->ext_status & 0xffff;
3536 else
3537 #endif
3538 ha->status = gdth_readw(&dp6m_ptr->i960r.status);
3539 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3540 } else /* no error */
3541 ha->status = S_OK;
3542 #ifdef INT_COAL
3543 /* get information */
3544 if (coalesced) {
3545 ha->info = pcs->info0;
3546 ha->info2 = pcs->info1;
3547 ha->service = (pcs->ext_status >> 16) & 0xffff;
3548 } else
3549 #endif
3550 {
3551 ha->info = gdth_readl(&dp6m_ptr->i960r.info[0]);
3552 ha->service = gdth_readw(&dp6m_ptr->i960r.service);
3553 ha->info2 = gdth_readl(&dp6m_ptr->i960r.info[1]);
3554 }
3555 /* event string */
3556 if (IStatus == ASYNCINDEX) {
3557 if (ha->service != SCREENSERVICE &&
3558 (ha->fw_vers & 0xff) >= 0x1a) {
3559 ha->dvr.severity = gdth_readb
3560 (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.severity);
3561 for (i = 0; i < 256; ++i) {
3562 ha->dvr.event_string[i] = gdth_readb
3563 (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.evt_str[i]);
3564 if (ha->dvr.event_string[i] == 0)
3565 break;
3566 }
3567 }
3568 }
3569 #ifdef INT_COAL
3570 /* Make sure that non coalesced interrupts get cleared
3571 before being handled by gdth_async_event/gdth_sync_event */
3572 if (!coalesced)
3573 #endif
3574 {
3575 gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
3576 gdth_writeb(0, &dp6m_ptr->i960r.sema1_reg);
3577 }
3578 } else {
3579 TRACE2(("gdth_interrupt() unknown controller type\n"));
3580 if (!gdth_polling)
3581 spin_unlock_irqrestore(&ha2->smp_lock, flags);
3582 return IRQ_HANDLED;
3583 }
3584
3585 TRACE(("gdth_interrupt() index %d stat %d info %d\n",
3586 IStatus,ha->status,ha->info));
3587
3588 if (gdth_from_wait) {
3589 wait_hanum = hanum;
3590 wait_index = (int)IStatus;
3591 }
3592
3593 if (IStatus == ASYNCINDEX) {
3594 TRACE2(("gdth_interrupt() async. event\n"));
3595 gdth_async_event(hanum);
3596 if (!gdth_polling)
3597 spin_unlock_irqrestore(&ha2->smp_lock, flags);
3598 gdth_next(hanum);
3599 return IRQ_HANDLED;
3600 }
3601
3602 if (IStatus == SPEZINDEX) {
3603 TRACE2(("Service unknown or not initialized !\n"));
3604 ha->dvr.size = sizeof(ha->dvr.eu.driver);
3605 ha->dvr.eu.driver.ionode = hanum;
3606 gdth_store_event(ha, ES_DRIVER, 4, &ha->dvr);
3607 if (!gdth_polling)
3608 spin_unlock_irqrestore(&ha2->smp_lock, flags);
3609 return IRQ_HANDLED;
3610 }
3611 scp = ha->cmd_tab[IStatus-2].cmnd;
3612 Service = ha->cmd_tab[IStatus-2].service;
3613 ha->cmd_tab[IStatus-2].cmnd = UNUSED_CMND;
3614 if (scp == UNUSED_CMND) {
3615 TRACE2(("gdth_interrupt() index to unused command (%d)\n",IStatus));
3616 ha->dvr.size = sizeof(ha->dvr.eu.driver);
3617 ha->dvr.eu.driver.ionode = hanum;
3618 ha->dvr.eu.driver.index = IStatus;
3619 gdth_store_event(ha, ES_DRIVER, 1, &ha->dvr);
3620 if (!gdth_polling)
3621 spin_unlock_irqrestore(&ha2->smp_lock, flags);
3622 return IRQ_HANDLED;
3623 }
3624 if (scp == INTERNAL_CMND) {
3625 TRACE(("gdth_interrupt() answer to internal command\n"));
3626 if (!gdth_polling)
3627 spin_unlock_irqrestore(&ha2->smp_lock, flags);
3628 return IRQ_HANDLED;
3629 }
3630
3631 TRACE(("gdth_interrupt() sync. status\n"));
3632 rval = gdth_sync_event(hanum,Service,IStatus,scp);
3633 if (!gdth_polling)
3634 spin_unlock_irqrestore(&ha2->smp_lock, flags);
3635 if (rval == 2) {
3636 gdth_putq(hanum,scp,scp->SCp.this_residual);
3637 } else if (rval == 1) {
3638 scp->scsi_done(scp);
3639 }
3640
3641 #ifdef INT_COAL
3642 if (coalesced) {
3643 /* go to the next status in the status buffer */
3644 ++pcs;
3645 #ifdef GDTH_STATISTICS
3646 ++act_int_coal;
3647 if (act_int_coal > max_int_coal) {
3648 max_int_coal = act_int_coal;
3649 printk("GDT: max_int_coal = %d\n",(ushort)max_int_coal);
3650 }
3651 #endif
3652 /* see if there is another status */
3653 if (pcs->status == 0)
3654 /* Stop the coalesce loop */
3655 next = FALSE;
3656 }
3657 } while (next);
3658
3659 /* coalescing only for new GDT_PCIMPR controllers available */
3660 if (ha->type == GDT_PCIMPR && coalesced) {
3661 gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
3662 gdth_writeb(0, &dp6m_ptr->i960r.sema1_reg);
3663 }
3664 #endif
3665
3666 gdth_next(hanum);
3667 return IRQ_HANDLED;
3668 }
3669
3670 static int gdth_sync_event(int hanum,int service,unchar index,Scsi_Cmnd *scp)
3671 {
3672 register gdth_ha_str *ha;
3673 gdth_msg_str *msg;
3674 gdth_cmd_str *cmdp;
3675 unchar b, t;
3676
3677 ha = HADATA(gdth_ctr_tab[hanum]);
3678 cmdp = ha->pccb;
3679 TRACE(("gdth_sync_event() serv %d status %d\n",
3680 service,ha->status));
3681
3682 if (service == SCREENSERVICE) {
3683 msg = ha->pmsg;
3684 TRACE(("len: %d, answer: %d, ext: %d, alen: %d\n",
3685 msg->msg_len,msg->msg_answer,msg->msg_ext,msg->msg_alen));
3686 if (msg->msg_len > MSGLEN+1)
3687 msg->msg_len = MSGLEN+1;
3688 if (msg->msg_len)
3689 if (!(msg->msg_answer && msg->msg_ext)) {
3690 msg->msg_text[msg->msg_len] = '\0';
3691 printk("%s",msg->msg_text);
3692 }
3693
3694 if (msg->msg_ext && !msg->msg_answer) {
3695 while (gdth_test_busy(hanum))
3696 gdth_delay(0);
3697 cmdp->Service = SCREENSERVICE;
3698 cmdp->RequestBuffer = SCREEN_CMND;
3699 gdth_get_cmd_index(hanum);
3700 gdth_set_sema0(hanum);
3701 cmdp->OpCode = GDT_READ;
3702 cmdp->BoardNode = LOCALBOARD;
3703 cmdp->u.screen.reserved = 0;
3704 cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
3705 cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
3706 ha->cmd_offs_dpmem = 0;
3707 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
3708 + sizeof(ulong64);
3709 ha->cmd_cnt = 0;
3710 gdth_copy_command(hanum);
3711 gdth_release_event(hanum);
3712 return 0;
3713 }
3714
3715 if (msg->msg_answer && msg->msg_alen) {
3716 /* default answers (getchar() not possible) */
3717 if (msg->msg_alen == 1) {
3718 msg->msg_alen = 0;
3719 msg->msg_len = 1;
3720 msg->msg_text[0] = 0;
3721 } else {
3722 msg->msg_alen -= 2;
3723 msg->msg_len = 2;
3724 msg->msg_text[0] = 1;
3725 msg->msg_text[1] = 0;
3726 }
3727 msg->msg_ext = 0;
3728 msg->msg_answer = 0;
3729 while (gdth_test_busy(hanum))
3730 gdth_delay(0);
3731 cmdp->Service = SCREENSERVICE;
3732 cmdp->RequestBuffer = SCREEN_CMND;
3733 gdth_get_cmd_index(hanum);
3734 gdth_set_sema0(hanum);
3735 cmdp->OpCode = GDT_WRITE;
3736 cmdp->BoardNode = LOCALBOARD;
3737 cmdp->u.screen.reserved = 0;
3738 cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
3739 cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
3740 ha->cmd_offs_dpmem = 0;
3741 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
3742 + sizeof(ulong64);
3743 ha->cmd_cnt = 0;
3744 gdth_copy_command(hanum);
3745 gdth_release_event(hanum);
3746 return 0;
3747 }
3748 printk("\n");
3749
3750 } else {
3751 b = virt_ctr ? NUMDATA(scp->device->host)->busnum : scp->device->channel;
3752 t = scp->device->id;
3753 if (scp->SCp.sent_command == -1 && b != ha->virt_bus) {
3754 ha->raw[BUS_L2P(ha,b)].io_cnt[t]--;
3755 }
3756 /* cache or raw service */
3757 if (ha->status == S_BSY) {
3758 TRACE2(("Controller busy -> retry !\n"));
3759 if (scp->SCp.sent_command == GDT_MOUNT)
3760 scp->SCp.sent_command = GDT_CLUST_INFO;
3761 /* retry */
3762 return 2;
3763 }
3764 if (scp->SCp.Status == GDTH_MAP_SG)
3765 pci_unmap_sg(ha->pdev,scp->request_buffer,
3766 scp->use_sg,scp->SCp.Message);
3767 else if (scp->SCp.Status == GDTH_MAP_SINGLE)
3768 pci_unmap_page(ha->pdev,scp->SCp.dma_handle,
3769 scp->request_bufflen,scp->SCp.Message);
3770 if (scp->SCp.buffer) {
3771 dma_addr_t addr;
3772 addr = (dma_addr_t)*(ulong32 *)&scp->SCp.buffer;
3773 if (scp->host_scribble)
3774 addr += (dma_addr_t)
3775 ((ulong64)(*(ulong32 *)&scp->host_scribble) << 32);
3776 pci_unmap_page(ha->pdev,addr,16,PCI_DMA_FROMDEVICE);
3777 }
3778
3779 if (ha->status == S_OK) {
3780 scp->SCp.Status = S_OK;
3781 scp->SCp.Message = ha->info;
3782 if (scp->SCp.sent_command != -1) {
3783 TRACE2(("gdth_sync_event(): special cmd 0x%x OK\n",
3784 scp->SCp.sent_command));
3785 /* special commands GDT_CLUST_INFO/GDT_MOUNT ? */
3786 if (scp->SCp.sent_command == GDT_CLUST_INFO) {
3787 ha->hdr[t].cluster_type = (unchar)ha->info;
3788 if (!(ha->hdr[t].cluster_type &
3789 CLUSTER_MOUNTED)) {
3790 /* NOT MOUNTED -> MOUNT */
3791 scp->SCp.sent_command = GDT_MOUNT;
3792 if (ha->hdr[t].cluster_type &
3793 CLUSTER_RESERVED) {
3794 /* cluster drive RESERVED (on the other node) */
3795 scp->SCp.phase = -2; /* reservation conflict */
3796 }
3797 } else {
3798 scp->SCp.sent_command = -1;
3799 }
3800 } else {
3801 if (scp->SCp.sent_command == GDT_MOUNT) {
3802 ha->hdr[t].cluster_type |= CLUSTER_MOUNTED;
3803 ha->hdr[t].media_changed = TRUE;
3804 } else if (scp->SCp.sent_command == GDT_UNMOUNT) {
3805 ha->hdr[t].cluster_type &= ~CLUSTER_MOUNTED;
3806 ha->hdr[t].media_changed = TRUE;
3807 }
3808 scp->SCp.sent_command = -1;
3809 }
3810 /* retry */
3811 scp->SCp.this_residual = HIGH_PRI;
3812 return 2;
3813 } else {
3814 /* RESERVE/RELEASE ? */
3815 if (scp->cmnd[0] == RESERVE) {
3816 ha->hdr[t].cluster_type |= CLUSTER_RESERVED;
3817 } else if (scp->cmnd[0] == RELEASE) {
3818 ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
3819 }
3820 scp->result = DID_OK << 16;
3821 scp->sense_buffer[0] = 0;
3822 }
3823 } else {
3824 scp->SCp.Status = ha->status;
3825 scp->SCp.Message = ha->info;
3826
3827 if (scp->SCp.sent_command != -1) {
3828 TRACE2(("gdth_sync_event(): special cmd 0x%x error 0x%x\n",
3829 scp->SCp.sent_command, ha->status));
3830 if (scp->SCp.sent_command == GDT_SCAN_START ||
3831 scp->SCp.sent_command == GDT_SCAN_END) {
3832 scp->SCp.sent_command = -1;
3833 /* retry */
3834 scp->SCp.this_residual = HIGH_PRI;
3835 return 2;
3836 }
3837 memset((char*)scp->sense_buffer,0,16);
3838 scp->sense_buffer[0] = 0x70;
3839 scp->sense_buffer[2] = NOT_READY;
3840 scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
3841 } else if (service == CACHESERVICE) {
3842 if (ha->status == S_CACHE_UNKNOWN &&
3843 (ha->hdr[t].cluster_type &
3844 CLUSTER_RESERVE_STATE) == CLUSTER_RESERVE_STATE) {
3845 /* bus reset -> force GDT_CLUST_INFO */
3846 ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
3847 }
3848 memset((char*)scp->sense_buffer,0,16);
3849 if (ha->status == (ushort)S_CACHE_RESERV) {
3850 scp->result = (DID_OK << 16) | (RESERVATION_CONFLICT << 1);
3851 } else {
3852 scp->sense_buffer[0] = 0x70;
3853 scp->sense_buffer[2] = NOT_READY;
3854 scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
3855 }
3856 if (scp->done != gdth_scsi_done) {
3857 ha->dvr.size = sizeof(ha->dvr.eu.sync);
3858 ha->dvr.eu.sync.ionode = hanum;
3859 ha->dvr.eu.sync.service = service;
3860 ha->dvr.eu.sync.status = ha->status;
3861 ha->dvr.eu.sync.info = ha->info;
3862 ha->dvr.eu.sync.hostdrive = t;
3863 if (ha->status >= 0x8000)
3864 gdth_store_event(ha, ES_SYNC, 0, &ha->dvr);
3865 else
3866 gdth_store_event(ha, ES_SYNC, service, &ha->dvr);
3867 }
3868 } else {
3869 /* sense buffer filled from controller firmware (DMA) */
3870 if (ha->status != S_RAW_SCSI || ha->info >= 0x100) {
3871 scp->result = DID_BAD_TARGET << 16;
3872 } else {
3873 scp->result = (DID_OK << 16) | ha->info;
3874 }
3875 }
3876 }
3877 if (!scp->SCp.have_data_in)
3878 scp->SCp.have_data_in++;
3879 else
3880 return 1;
3881 }
3882
3883 return 0;
3884 }
3885
3886 static char *async_cache_tab[] = {
3887 /* 0*/ "\011\000\002\002\002\004\002\006\004"
3888 "GDT HA %u, service %u, async. status %u/%lu unknown",
3889 /* 1*/ "\011\000\002\002\002\004\002\006\004"
3890 "GDT HA %u, service %u, async. status %u/%lu unknown",
3891 /* 2*/ "\005\000\002\006\004"
3892 "GDT HA %u, Host Drive %lu not ready",
3893 /* 3*/ "\005\000\002\006\004"
3894 "GDT HA %u, Host Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
3895 /* 4*/ "\005\000\002\006\004"
3896 "GDT HA %u, mirror update on Host Drive %lu failed",
3897 /* 5*/ "\005\000\002\006\004"
3898 "GDT HA %u, Mirror Drive %lu failed",
3899 /* 6*/ "\005\000\002\006\004"
3900 "GDT HA %u, Mirror Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
3901 /* 7*/ "\005\000\002\006\004"
3902 "GDT HA %u, Host Drive %lu write protected",
3903 /* 8*/ "\005\000\002\006\004"
3904 "GDT HA %u, media changed in Host Drive %lu",
3905 /* 9*/ "\005\000\002\006\004"
3906 "GDT HA %u, Host Drive %lu is offline",
3907 /*10*/ "\005\000\002\006\004"
3908 "GDT HA %u, media change of Mirror Drive %lu",
3909 /*11*/ "\005\000\002\006\004"
3910 "GDT HA %u, Mirror Drive %lu is write protected",
3911 /*12*/ "\005\000\002\006\004"
3912 "GDT HA %u, general error on Host Drive %lu. Please check the devices of this drive!",
3913 /*13*/ "\007\000\002\006\002\010\002"
3914 "GDT HA %u, Array Drive %u: Cache Drive %u failed",
3915 /*14*/ "\005\000\002\006\002"
3916 "GDT HA %u, Array Drive %u: FAIL state entered",
3917 /*15*/ "\005\000\002\006\002"
3918 "GDT HA %u, Array Drive %u: error",
3919 /*16*/ "\007\000\002\006\002\010\002"
3920 "GDT HA %u, Array Drive %u: failed drive replaced by Cache Drive %u",
3921 /*17*/ "\005\000\002\006\002"
3922 "GDT HA %u, Array Drive %u: parity build failed",
3923 /*18*/ "\005\000\002\006\002"
3924 "GDT HA %u, Array Drive %u: drive rebuild failed",
3925 /*19*/ "\005\000\002\010\002"
3926 "GDT HA %u, Test of Hot Fix %u failed",
3927 /*20*/ "\005\000\002\006\002"
3928 "GDT HA %u, Array Drive %u: drive build finished successfully",
3929 /*21*/ "\005\000\002\006\002"
3930 "GDT HA %u, Array Drive %u: drive rebuild finished successfully",
3931 /*22*/ "\007\000\002\006\002\010\002"
3932 "GDT HA %u, Array Drive %u: Hot Fix %u activated",
3933 /*23*/ "\005\000\002\006\002"
3934 "GDT HA %u, Host Drive %u: processing of i/o aborted due to serious drive error",
3935 /*24*/ "\005\000\002\010\002"
3936 "GDT HA %u, mirror update on Cache Drive %u completed",
3937 /*25*/ "\005\000\002\010\002"
3938 "GDT HA %u, mirror update on Cache Drive %lu failed",
3939 /*26*/ "\005\000\002\006\002"
3940 "GDT HA %u, Array Drive %u: drive rebuild started",
3941 /*27*/ "\005\000\002\012\001"
3942 "GDT HA %u, Fault bus %u: SHELF OK detected",
3943 /*28*/ "\005\000\002\012\001"
3944 "GDT HA %u, Fault bus %u: SHELF not OK detected",
3945 /*29*/ "\007\000\002\012\001\013\001"
3946 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug started",
3947 /*30*/ "\007\000\002\012\001\013\001"
3948 "GDT HA %u, Fault bus %u, ID %u: new disk detected",
3949 /*31*/ "\007\000\002\012\001\013\001"
3950 "GDT HA %u, Fault bus %u, ID %u: old disk detected",
3951 /*32*/ "\007\000\002\012\001\013\001"
3952 "GDT HA %u, Fault bus %u, ID %u: plugging an active disk is invalid",
3953 /*33*/ "\007\000\002\012\001\013\001"
3954 "GDT HA %u, Fault bus %u, ID %u: invalid device detected",
3955 /*34*/ "\011\000\002\012\001\013\001\006\004"
3956 "GDT HA %u, Fault bus %u, ID %u: insufficient disk capacity (%lu MB required)",
3957 /*35*/ "\007\000\002\012\001\013\001"
3958 "GDT HA %u, Fault bus %u, ID %u: disk write protected",
3959 /*36*/ "\007\000\002\012\001\013\001"
3960 "GDT HA %u, Fault bus %u, ID %u: disk not available",
3961 /*37*/ "\007\000\002\012\001\006\004"
3962 "GDT HA %u, Fault bus %u: swap detected (%lu)",
3963 /*38*/ "\007\000\002\012\001\013\001"
3964 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug finished successfully",
3965 /*39*/ "\007\000\002\012\001\013\001"
3966 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted due to user Hot Plug",
3967 /*40*/ "\007\000\002\012\001\013\001"
3968 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted",
3969 /*41*/ "\007\000\002\012\001\013\001"
3970 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug for Hot Fix started",
3971 /*42*/ "\005\000\002\006\002"
3972 "GDT HA %u, Array Drive %u: drive build started",
3973 /*43*/ "\003\000\002"
3974 "GDT HA %u, DRAM parity error detected",
3975 /*44*/ "\005\000\002\006\002"
3976 "GDT HA %u, Mirror Drive %u: update started",
3977 /*45*/ "\007\000\002\006\002\010\002"
3978 "GDT HA %u, Mirror Drive %u: Hot Fix %u activated",
3979 /*46*/ "\005\000\002\006\002"
3980 "GDT HA %u, Array Drive %u: no matching Pool Hot Fix Drive available",
3981 /*47*/ "\005\000\002\006\002"
3982 "GDT HA %u, Array Drive %u: Pool Hot Fix Drive available",
3983 /*48*/ "\005\000\002\006\002"
3984 "GDT HA %u, Mirror Drive %u: no matching Pool Hot Fix Drive available",
3985 /*49*/ "\005\000\002\006\002"
3986 "GDT HA %u, Mirror Drive %u: Pool Hot Fix Drive available",
3987 /*50*/ "\007\000\002\012\001\013\001"
3988 "GDT HA %u, SCSI bus %u, ID %u: IGNORE_WIDE_RESIDUE message received",
3989 /*51*/ "\005\000\002\006\002"
3990 "GDT HA %u, Array Drive %u: expand started",
3991 /*52*/ "\005\000\002\006\002"
3992 "GDT HA %u, Array Drive %u: expand finished successfully",
3993 /*53*/ "\005\000\002\006\002"
3994 "GDT HA %u, Array Drive %u: expand failed",
3995 /*54*/ "\003\000\002"
3996 "GDT HA %u, CPU temperature critical",
3997 /*55*/ "\003\000\002"
3998 "GDT HA %u, CPU temperature OK",
3999 /*56*/ "\005\000\002\006\004"
4000 "GDT HA %u, Host drive %lu created",
4001 /*57*/ "\005\000\002\006\002"
4002 "GDT HA %u, Array Drive %u: expand restarted",
4003 /*58*/ "\005\000\002\006\002"
4004 "GDT HA %u, Array Drive %u: expand stopped",
4005 /*59*/ "\005\000\002\010\002"
4006 "GDT HA %u, Mirror Drive %u: drive build quited",
4007 /*60*/ "\005\000\002\006\002"
4008 "GDT HA %u, Array Drive %u: parity build quited",
4009 /*61*/ "\005\000\002\006\002"
4010 "GDT HA %u, Array Drive %u: drive rebuild quited",
4011 /*62*/ "\005\000\002\006\002"
4012 "GDT HA %u, Array Drive %u: parity verify started",
4013 /*63*/ "\005\000\002\006\002"
4014 "GDT HA %u, Array Drive %u: parity verify done",
4015 /*64*/ "\005\000\002\006\002"
4016 "GDT HA %u, Array Drive %u: parity verify failed",
4017 /*65*/ "\005\000\002\006\002"
4018 "GDT HA %u, Array Drive %u: parity error detected",
4019 /*66*/ "\005\000\002\006\002"
4020 "GDT HA %u, Array Drive %u: parity verify quited",
4021 /*67*/ "\005\000\002\006\002"
4022 "GDT HA %u, Host Drive %u reserved",
4023 /*68*/ "\005\000\002\006\002"
4024 "GDT HA %u, Host Drive %u mounted and released",
4025 /*69*/ "\005\000\002\006\002"
4026 "GDT HA %u, Host Drive %u released",
4027 /*70*/ "\003\000\002"
4028 "GDT HA %u, DRAM error detected and corrected with ECC",
4029 /*71*/ "\003\000\002"
4030 "GDT HA %u, Uncorrectable DRAM error detected with ECC",
4031 /*72*/ "\011\000\002\012\001\013\001\014\001"
4032 "GDT HA %u, SCSI bus %u, ID %u, LUN %u: reassigning block",
4033 /*73*/ "\005\000\002\006\002"
4034 "GDT HA %u, Host drive %u resetted locally",
4035 /*74*/ "\005\000\002\006\002"
4036 "GDT HA %u, Host drive %u resetted remotely",
4037 /*75*/ "\003\000\002"
4038 "GDT HA %u, async. status 75 unknown",
4039 };
4040
4041
4042 static int gdth_async_event(int hanum)
4043 {
4044 gdth_ha_str *ha;
4045 gdth_cmd_str *cmdp;
4046 int cmd_index;
4047
4048 ha = HADATA(gdth_ctr_tab[hanum]);
4049 cmdp= ha->pccb;
4050 TRACE2(("gdth_async_event() ha %d serv %d\n",
4051 hanum,ha->service));
4052
4053 if (ha->service == SCREENSERVICE) {
4054 if (ha->status == MSG_REQUEST) {
4055 while (gdth_test_busy(hanum))
4056 gdth_delay(0);
4057 cmdp->Service = SCREENSERVICE;
4058 cmdp->RequestBuffer = SCREEN_CMND;
4059 cmd_index = gdth_get_cmd_index(hanum);
4060 gdth_set_sema0(hanum);
4061 cmdp->OpCode = GDT_READ;
4062 cmdp->BoardNode = LOCALBOARD;
4063 cmdp->u.screen.reserved = 0;
4064 cmdp->u.screen.su.msg.msg_handle= MSG_INV_HANDLE;
4065 cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
4066 ha->cmd_offs_dpmem = 0;
4067 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
4068 + sizeof(ulong64);
4069 ha->cmd_cnt = 0;
4070 gdth_copy_command(hanum);
4071 if (ha->type == GDT_EISA)
4072 printk("[EISA slot %d] ",(ushort)ha->brd_phys);
4073 else if (ha->type == GDT_ISA)
4074 printk("[DPMEM 0x%4X] ",(ushort)ha->brd_phys);
4075 else
4076 printk("[PCI %d/%d] ",(ushort)(ha->brd_phys>>8),
4077 (ushort)((ha->brd_phys>>3)&0x1f));
4078 gdth_release_event(hanum);
4079 }
4080
4081 } else {
4082 if (ha->type == GDT_PCIMPR &&
4083 (ha->fw_vers & 0xff) >= 0x1a) {
4084 ha->dvr.size = 0;
4085 ha->dvr.eu.async.ionode = hanum;
4086 ha->dvr.eu.async.status = ha->status;
4087 /* severity and event_string already set! */
4088 } else {
4089 ha->dvr.size = sizeof(ha->dvr.eu.async);
4090 ha->dvr.eu.async.ionode = hanum;
4091 ha->dvr.eu.async.service = ha->service;
4092 ha->dvr.eu.async.status = ha->status;
4093 ha->dvr.eu.async.info = ha->info;
4094 *(ulong32 *)ha->dvr.eu.async.scsi_coord = ha->info2;
4095 }
4096 gdth_store_event( ha, ES_ASYNC, ha->service, &ha->dvr );
4097 gdth_log_event( &ha->dvr, NULL );
4098
4099 /* new host drive from expand? */
4100 if (ha->service == CACHESERVICE && ha->status == 56) {
4101 TRACE2(("gdth_async_event(): new host drive %d created\n",
4102 (ushort)ha->info));
4103 /* gdth_analyse_hdrive(hanum, (ushort)ha->info); */
4104 }
4105 }
4106 return 1;
4107 }
4108
4109 static void gdth_log_event(gdth_evt_data *dvr, char *buffer)
4110 {
4111 gdth_stackframe stack;
4112 char *f = NULL;
4113 int i,j;
4114
4115 TRACE2(("gdth_log_event()\n"));
4116 if (dvr->size == 0) {
4117 if (buffer == NULL) {
4118 printk("Adapter %d: %s\n",dvr->eu.async.ionode,dvr->event_string);
4119 } else {
4120 sprintf(buffer,"Adapter %d: %s\n",
4121 dvr->eu.async.ionode,dvr->event_string);
4122 }
4123 } else if (dvr->eu.async.service == CACHESERVICE &&
4124 INDEX_OK(dvr->eu.async.status, async_cache_tab)) {
4125 TRACE2(("GDT: Async. event cache service, event no.: %d\n",
4126 dvr->eu.async.status));
4127
4128 f = async_cache_tab[dvr->eu.async.status];
4129
4130 /* i: parameter to push, j: stack element to fill */
4131 for (j=0,i=1; i < f[0]; i+=2) {
4132 switch (f[i+1]) {
4133 case 4:
4134 stack.b[j++] = *(ulong32*)&dvr->eu.stream[(int)f[i]];
4135 break;
4136 case 2:
4137 stack.b[j++] = *(ushort*)&dvr->eu.stream[(int)f[i]];
4138 break;
4139 case 1:
4140 stack.b[j++] = *(unchar*)&dvr->eu.stream[(int)f[i]];
4141 break;
4142 default:
4143 break;
4144 }
4145 }
4146
4147 if (buffer == NULL) {
4148 printk(&f[(int)f[0]],stack);
4149 printk("\n");
4150 } else {
4151 sprintf(buffer,&f[(int)f[0]],stack);
4152 }
4153
4154 } else {
4155 if (buffer == NULL) {
4156 printk("GDT HA %u, Unknown async. event service %d event no. %d\n",
4157 dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
4158 } else {
4159 sprintf(buffer,"GDT HA %u, Unknown async. event service %d event no. %d",
4160 dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
4161 }
4162 }
4163 }
4164
4165 #ifdef GDTH_STATISTICS
4166 static void gdth_timeout(ulong data)
4167 {
4168 ulong32 i;
4169 Scsi_Cmnd *nscp;
4170 gdth_ha_str *ha;
4171 ulong flags;
4172 int hanum = 0;
4173
4174 ha = HADATA(gdth_ctr_tab[hanum]);
4175 spin_lock_irqsave(&ha->smp_lock, flags);
4176
4177 for (act_stats=0,i=0; i<GDTH_MAXCMDS; ++i)
4178 if (ha->cmd_tab[i].cmnd != UNUSED_CMND)
4179 ++act_stats;
4180
4181 for (act_rq=0,nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
4182 ++act_rq;
4183
4184 TRACE2(("gdth_to(): ints %d, ios %d, act_stats %d, act_rq %d\n",
4185 act_ints, act_ios, act_stats, act_rq));
4186 act_ints = act_ios = 0;
4187
4188 gdth_timer.expires = jiffies + 30 * HZ;
4189 add_timer(&gdth_timer);
4190 spin_unlock_irqrestore(&ha->smp_lock, flags);
4191 }
4192 #endif
4193
4194 static void __init internal_setup(char *str,int *ints)
4195 {
4196 int i, argc;
4197 char *cur_str, *argv;
4198
4199 TRACE2(("internal_setup() str %s ints[0] %d\n",
4200 str ? str:"NULL", ints ? ints[0]:0));
4201
4202 /* read irq[] from ints[] */
4203 if (ints) {
4204 argc = ints[0];
4205 if (argc > 0) {
4206 if (argc > MAXHA)
4207 argc = MAXHA;
4208 for (i = 0; i < argc; ++i)
4209 irq[i] = ints[i+1];
4210 }
4211 }
4212
4213 /* analyse string */
4214 argv = str;
4215 while (argv && (cur_str = strchr(argv, ':'))) {
4216 int val = 0, c = *++cur_str;
4217
4218 if (c == 'n' || c == 'N')
4219 val = 0;
4220 else if (c == 'y' || c == 'Y')
4221 val = 1;
4222 else
4223 val = (int)simple_strtoul(cur_str, NULL, 0);
4224
4225 if (!strncmp(argv, "disable:", 8))
4226 disable = val;
4227 else if (!strncmp(argv, "reserve_mode:", 13))
4228 reserve_mode = val;
4229 else if (!strncmp(argv, "reverse_scan:", 13))
4230 reverse_scan = val;
4231 else if (!strncmp(argv, "hdr_channel:", 12))
4232 hdr_channel = val;
4233 else if (!strncmp(argv, "max_ids:", 8))
4234 max_ids = val;
4235 else if (!strncmp(argv, "rescan:", 7))
4236 rescan = val;
4237 else if (!strncmp(argv, "virt_ctr:", 9))
4238 virt_ctr = val;
4239 else if (!strncmp(argv, "shared_access:", 14))
4240 shared_access = val;
4241 else if (!strncmp(argv, "probe_eisa_isa:", 15))
4242 probe_eisa_isa = val;
4243 else if (!strncmp(argv, "reserve_list:", 13)) {
4244 reserve_list[0] = val;
4245 for (i = 1; i < MAX_RES_ARGS; i++) {
4246 cur_str = strchr(cur_str, ',');
4247 if (!cur_str)
4248 break;
4249 if (!isdigit((int)*++cur_str)) {
4250 --cur_str;
4251 break;
4252 }
4253 reserve_list[i] =
4254 (int)simple_strtoul(cur_str, NULL, 0);
4255 }
4256 if (!cur_str)
4257 break;
4258 argv = ++cur_str;
4259 continue;
4260 }
4261
4262 if ((argv = strchr(argv, ',')))
4263 ++argv;
4264 }
4265 }
4266
4267 int __init option_setup(char *str)
4268 {
4269 int ints[MAXHA];
4270 char *cur = str;
4271 int i = 1;
4272
4273 TRACE2(("option_setup() str %s\n", str ? str:"NULL"));
4274
4275 while (cur && isdigit(*cur) && i <= MAXHA) {
4276 ints[i++] = simple_strtoul(cur, NULL, 0);
4277 if ((cur = strchr(cur, ',')) != NULL) cur++;
4278 }
4279
4280 ints[0] = i - 1;
4281 internal_setup(cur, ints);
4282 return 1;
4283 }
4284
4285 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
4286 static int __init gdth_detect(struct scsi_host_template *shtp)
4287 #else
4288 static int __init gdth_detect(Scsi_Host_Template *shtp)
4289 #endif
4290 {
4291 struct Scsi_Host *shp;
4292 gdth_pci_str pcistr[MAXHA];
4293 gdth_ha_str *ha;
4294 ulong32 isa_bios;
4295 ushort eisa_slot;
4296 int i,hanum,cnt,ctr,err;
4297 unchar b;
4298
4299
4300 #ifdef DEBUG_GDTH
4301 printk("GDT: This driver contains debugging information !! Trace level = %d\n",
4302 DebugState);
4303 printk(" Destination of debugging information: ");
4304 #ifdef __SERIAL__
4305 #ifdef __COM2__
4306 printk("Serial port COM2\n");
4307 #else
4308 printk("Serial port COM1\n");
4309 #endif
4310 #else
4311 printk("Console\n");
4312 #endif
4313 gdth_delay(3000);
4314 #endif
4315
4316 TRACE(("gdth_detect()\n"));
4317
4318 if (disable) {
4319 printk("GDT-HA: Controller driver disabled from command line !\n");
4320 return 0;
4321 }
4322
4323 printk("GDT-HA: Storage RAID Controller Driver. Version: %s\n",GDTH_VERSION_STR);
4324 /* initializations */
4325 gdth_polling = TRUE; b = 0;
4326 gdth_clear_events();
4327
4328 /* As default we do not probe for EISA or ISA controllers */
4329 if (probe_eisa_isa) {
4330 /* scanning for controllers, at first: ISA controller */
4331 for (isa_bios=0xc8000UL; isa_bios<=0xd8000UL; isa_bios+=0x8000UL) {
4332 dma_addr_t scratch_dma_handle;
4333 scratch_dma_handle = 0;
4334
4335 if (gdth_ctr_count >= MAXHA)
4336 break;
4337 if (gdth_search_isa(isa_bios)) { /* controller found */
4338 shp = scsi_register(shtp,sizeof(gdth_ext_str));
4339 if (shp == NULL)
4340 continue;
4341
4342 ha = HADATA(shp);
4343 if (!gdth_init_isa(isa_bios,ha)) {
4344 scsi_unregister(shp);
4345 continue;
4346 }
4347 #ifdef __ia64__
4348 break;
4349 #else
4350 /* controller found and initialized */
4351 printk("Configuring GDT-ISA HA at BIOS 0x%05X IRQ %u DRQ %u\n",
4352 isa_bios,ha->irq,ha->drq);
4353
4354 if (request_irq(ha->irq,gdth_interrupt,IRQF_DISABLED,"gdth",ha)) {
4355 printk("GDT-ISA: Unable to allocate IRQ\n");
4356 scsi_unregister(shp);
4357 continue;
4358 }
4359 if (request_dma(ha->drq,"gdth")) {
4360 printk("GDT-ISA: Unable to allocate DMA channel\n");
4361 free_irq(ha->irq,ha);
4362 scsi_unregister(shp);
4363 continue;
4364 }
4365 set_dma_mode(ha->drq,DMA_MODE_CASCADE);
4366 enable_dma(ha->drq);
4367 shp->unchecked_isa_dma = 1;
4368 shp->irq = ha->irq;
4369 shp->dma_channel = ha->drq;
4370 hanum = gdth_ctr_count;
4371 gdth_ctr_tab[gdth_ctr_count++] = shp;
4372 gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
4373
4374 NUMDATA(shp)->hanum = (ushort)hanum;
4375 NUMDATA(shp)->busnum= 0;
4376
4377 ha->pccb = CMDDATA(shp);
4378 ha->ccb_phys = 0L;
4379 ha->pdev = NULL;
4380 ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
4381 &scratch_dma_handle);
4382 ha->scratch_phys = scratch_dma_handle;
4383 ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
4384 &scratch_dma_handle);
4385 ha->msg_phys = scratch_dma_handle;
4386 #ifdef INT_COAL
4387 ha->coal_stat = (gdth_coal_status *)
4388 pci_alloc_consistent(ha->pdev, sizeof(gdth_coal_status) *
4389 MAXOFFSETS, &scratch_dma_handle);
4390 ha->coal_stat_phys = scratch_dma_handle;
4391 #endif
4392
4393 ha->scratch_busy = FALSE;
4394 ha->req_first = NULL;
4395 ha->tid_cnt = MAX_HDRIVES;
4396 if (max_ids > 0 && max_ids < ha->tid_cnt)
4397 ha->tid_cnt = max_ids;
4398 for (i=0; i<GDTH_MAXCMDS; ++i)
4399 ha->cmd_tab[i].cmnd = UNUSED_CMND;
4400 ha->scan_mode = rescan ? 0x10 : 0;
4401
4402 if (ha->pscratch == NULL || ha->pmsg == NULL ||
4403 !gdth_search_drives(hanum)) {
4404 printk("GDT-ISA: Error during device scan\n");
4405 --gdth_ctr_count;
4406 --gdth_ctr_vcount;
4407
4408 #ifdef INT_COAL
4409 if (ha->coal_stat)
4410 pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
4411 MAXOFFSETS, ha->coal_stat,
4412 ha->coal_stat_phys);
4413 #endif
4414 if (ha->pscratch)
4415 pci_free_consistent(ha->pdev, GDTH_SCRATCH,
4416 ha->pscratch, ha->scratch_phys);
4417 if (ha->pmsg)
4418 pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
4419 ha->pmsg, ha->msg_phys);
4420
4421 free_irq(ha->irq,ha);
4422 scsi_unregister(shp);
4423 continue;
4424 }
4425 if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
4426 hdr_channel = ha->bus_cnt;
4427 ha->virt_bus = hdr_channel;
4428
4429 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,20) && \
4430 LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
4431 shp->highmem_io = 0;
4432 #endif
4433 if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
4434 shp->max_cmd_len = 16;
4435
4436 shp->max_id = ha->tid_cnt;
4437 shp->max_lun = MAXLUN;
4438 shp->max_channel = virt_ctr ? 0 : ha->bus_cnt;
4439 if (virt_ctr) {
4440 virt_ctr = 1;
4441 /* register addit. SCSI channels as virtual controllers */
4442 for (b = 1; b < ha->bus_cnt + 1; ++b) {
4443 shp = scsi_register(shtp,sizeof(gdth_num_str));
4444 shp->unchecked_isa_dma = 1;
4445 shp->irq = ha->irq;
4446 shp->dma_channel = ha->drq;
4447 gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
4448 NUMDATA(shp)->hanum = (ushort)hanum;
4449 NUMDATA(shp)->busnum = b;
4450 }
4451 }
4452
4453 spin_lock_init(&ha->smp_lock);
4454 gdth_enable_int(hanum);
4455 #endif /* !__ia64__ */
4456 }
4457 }
4458
4459 /* scanning for EISA controllers */
4460 for (eisa_slot=0x1000; eisa_slot<=0x8000; eisa_slot+=0x1000) {
4461 dma_addr_t scratch_dma_handle;
4462 scratch_dma_handle = 0;
4463
4464 if (gdth_ctr_count >= MAXHA)
4465 break;
4466 if (gdth_search_eisa(eisa_slot)) { /* controller found */
4467 shp = scsi_register(shtp,sizeof(gdth_ext_str));
4468 if (shp == NULL)
4469 continue;
4470
4471 ha = HADATA(shp);
4472 if (!gdth_init_eisa(eisa_slot,ha)) {
4473 scsi_unregister(shp);
4474 continue;
4475 }
4476 /* controller found and initialized */
4477 printk("Configuring GDT-EISA HA at Slot %d IRQ %u\n",
4478 eisa_slot>>12,ha->irq);
4479
4480 if (request_irq(ha->irq,gdth_interrupt,IRQF_DISABLED,"gdth",ha)) {
4481 printk("GDT-EISA: Unable to allocate IRQ\n");
4482 scsi_unregister(shp);
4483 continue;
4484 }
4485 shp->unchecked_isa_dma = 0;
4486 shp->irq = ha->irq;
4487 shp->dma_channel = 0xff;
4488 hanum = gdth_ctr_count;
4489 gdth_ctr_tab[gdth_ctr_count++] = shp;
4490 gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
4491
4492 NUMDATA(shp)->hanum = (ushort)hanum;
4493 NUMDATA(shp)->busnum= 0;
4494 TRACE2(("EISA detect Bus 0: hanum %d\n",
4495 NUMDATA(shp)->hanum));
4496
4497 ha->pccb = CMDDATA(shp);
4498 ha->ccb_phys = 0L;
4499
4500 ha->pdev = NULL;
4501 ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
4502 &scratch_dma_handle);
4503 ha->scratch_phys = scratch_dma_handle;
4504 ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
4505 &scratch_dma_handle);
4506 ha->msg_phys = scratch_dma_handle;
4507 #ifdef INT_COAL
4508 ha->coal_stat = (gdth_coal_status *)
4509 pci_alloc_consistent(ha->pdev, sizeof(gdth_coal_status) *
4510 MAXOFFSETS, &scratch_dma_handle);
4511 ha->coal_stat_phys = scratch_dma_handle;
4512 #endif
4513 ha->ccb_phys =
4514 pci_map_single(ha->pdev,ha->pccb,
4515 sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
4516 ha->scratch_busy = FALSE;
4517 ha->req_first = NULL;
4518 ha->tid_cnt = MAX_HDRIVES;
4519 if (max_ids > 0 && max_ids < ha->tid_cnt)
4520 ha->tid_cnt = max_ids;
4521 for (i=0; i<GDTH_MAXCMDS; ++i)
4522 ha->cmd_tab[i].cmnd = UNUSED_CMND;
4523 ha->scan_mode = rescan ? 0x10 : 0;
4524
4525 if (ha->pscratch == NULL || ha->pmsg == NULL ||
4526 !gdth_search_drives(hanum)) {
4527 printk("GDT-EISA: Error during device scan\n");
4528 --gdth_ctr_count;
4529 --gdth_ctr_vcount;
4530 #ifdef INT_COAL
4531 if (ha->coal_stat)
4532 pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
4533 MAXOFFSETS, ha->coal_stat,
4534 ha->coal_stat_phys);
4535 #endif
4536 if (ha->pscratch)
4537 pci_free_consistent(ha->pdev, GDTH_SCRATCH,
4538 ha->pscratch, ha->scratch_phys);
4539 if (ha->pmsg)
4540 pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
4541 ha->pmsg, ha->msg_phys);
4542 if (ha->ccb_phys)
4543 pci_unmap_single(ha->pdev,ha->ccb_phys,
4544 sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
4545 free_irq(ha->irq,ha);
4546 scsi_unregister(shp);
4547 continue;
4548 }
4549 if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
4550 hdr_channel = ha->bus_cnt;
4551 ha->virt_bus = hdr_channel;
4552
4553 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,20) && \
4554 LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
4555 shp->highmem_io = 0;
4556 #endif
4557 if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
4558 shp->max_cmd_len = 16;
4559
4560 shp->max_id = ha->tid_cnt;
4561 shp->max_lun = MAXLUN;
4562 shp->max_channel = virt_ctr ? 0 : ha->bus_cnt;
4563 if (virt_ctr) {
4564 virt_ctr = 1;
4565 /* register addit. SCSI channels as virtual controllers */
4566 for (b = 1; b < ha->bus_cnt + 1; ++b) {
4567 shp = scsi_register(shtp,sizeof(gdth_num_str));
4568 shp->unchecked_isa_dma = 0;
4569 shp->irq = ha->irq;
4570 shp->dma_channel = 0xff;
4571 gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
4572 NUMDATA(shp)->hanum = (ushort)hanum;
4573 NUMDATA(shp)->busnum = b;
4574 }
4575 }
4576
4577 spin_lock_init(&ha->smp_lock);
4578 gdth_enable_int(hanum);
4579 }
4580 }
4581 }
4582
4583 /* scanning for PCI controllers */
4584 cnt = gdth_search_pci(pcistr);
4585 printk("GDT-HA: Found %d PCI Storage RAID Controllers\n",cnt);
4586 gdth_sort_pci(pcistr,cnt);
4587 for (ctr = 0; ctr < cnt; ++ctr) {
4588 dma_addr_t scratch_dma_handle;
4589 scratch_dma_handle = 0;
4590
4591 if (gdth_ctr_count >= MAXHA)
4592 break;
4593 shp = scsi_register(shtp,sizeof(gdth_ext_str));
4594 if (shp == NULL)
4595 continue;
4596
4597 ha = HADATA(shp);
4598 if (!gdth_init_pci(&pcistr[ctr],ha)) {
4599 scsi_unregister(shp);
4600 continue;
4601 }
4602 /* controller found and initialized */
4603 printk("Configuring GDT-PCI HA at %d/%d IRQ %u\n",
4604 pcistr[ctr].bus,PCI_SLOT(pcistr[ctr].device_fn),ha->irq);
4605
4606 if (request_irq(ha->irq, gdth_interrupt,
4607 IRQF_DISABLED|IRQF_SHARED, "gdth", ha))
4608 {
4609 printk("GDT-PCI: Unable to allocate IRQ\n");
4610 scsi_unregister(shp);
4611 continue;
4612 }
4613 shp->unchecked_isa_dma = 0;
4614 shp->irq = ha->irq;
4615 shp->dma_channel = 0xff;
4616 hanum = gdth_ctr_count;
4617 gdth_ctr_tab[gdth_ctr_count++] = shp;
4618 gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
4619
4620 NUMDATA(shp)->hanum = (ushort)hanum;
4621 NUMDATA(shp)->busnum= 0;
4622
4623 ha->pccb = CMDDATA(shp);
4624 ha->ccb_phys = 0L;
4625
4626 ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
4627 &scratch_dma_handle);
4628 ha->scratch_phys = scratch_dma_handle;
4629 ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
4630 &scratch_dma_handle);
4631 ha->msg_phys = scratch_dma_handle;
4632 #ifdef INT_COAL
4633 ha->coal_stat = (gdth_coal_status *)
4634 pci_alloc_consistent(ha->pdev, sizeof(gdth_coal_status) *
4635 MAXOFFSETS, &scratch_dma_handle);
4636 ha->coal_stat_phys = scratch_dma_handle;
4637 #endif
4638 ha->scratch_busy = FALSE;
4639 ha->req_first = NULL;
4640 ha->tid_cnt = pcistr[ctr].device_id >= 0x200 ? MAXID : MAX_HDRIVES;
4641 if (max_ids > 0 && max_ids < ha->tid_cnt)
4642 ha->tid_cnt = max_ids;
4643 for (i=0; i<GDTH_MAXCMDS; ++i)
4644 ha->cmd_tab[i].cmnd = UNUSED_CMND;
4645 ha->scan_mode = rescan ? 0x10 : 0;
4646
4647 err = FALSE;
4648 if (ha->pscratch == NULL || ha->pmsg == NULL ||
4649 !gdth_search_drives(hanum)) {
4650 err = TRUE;
4651 } else {
4652 if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
4653 hdr_channel = ha->bus_cnt;
4654 ha->virt_bus = hdr_channel;
4655
4656
4657 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
4658 scsi_set_pci_device(shp, pcistr[ctr].pdev);
4659 #endif
4660 if (!(ha->cache_feat & ha->raw_feat & ha->screen_feat &GDT_64BIT)||
4661 /* 64-bit DMA only supported from FW >= x.43 */
4662 (!ha->dma64_support)) {
4663 if (pci_set_dma_mask(pcistr[ctr].pdev, DMA_32BIT_MASK)) {
4664 printk(KERN_WARNING "GDT-PCI %d: Unable to set 32-bit DMA\n", hanum);
4665 err = TRUE;
4666 }
4667 } else {
4668 shp->max_cmd_len = 16;
4669 if (!pci_set_dma_mask(pcistr[ctr].pdev, DMA_64BIT_MASK)) {
4670 printk("GDT-PCI %d: 64-bit DMA enabled\n", hanum);
4671 } else if (pci_set_dma_mask(pcistr[ctr].pdev, DMA_32BIT_MASK)) {
4672 printk(KERN_WARNING "GDT-PCI %d: Unable to set 64/32-bit DMA\n", hanum);
4673 err = TRUE;
4674 }
4675 }
4676 }
4677
4678 if (err) {
4679 printk("GDT-PCI %d: Error during device scan\n", hanum);
4680 --gdth_ctr_count;
4681 --gdth_ctr_vcount;
4682 #ifdef INT_COAL
4683 if (ha->coal_stat)
4684 pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
4685 MAXOFFSETS, ha->coal_stat,
4686 ha->coal_stat_phys);
4687 #endif
4688 if (ha->pscratch)
4689 pci_free_consistent(ha->pdev, GDTH_SCRATCH,
4690 ha->pscratch, ha->scratch_phys);
4691 if (ha->pmsg)
4692 pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
4693 ha->pmsg, ha->msg_phys);
4694 free_irq(ha->irq,ha);
4695 scsi_unregister(shp);
4696 continue;
4697 }
4698
4699 shp->max_id = ha->tid_cnt;
4700 shp->max_lun = MAXLUN;
4701 shp->max_channel = virt_ctr ? 0 : ha->bus_cnt;
4702 if (virt_ctr) {
4703 virt_ctr = 1;
4704 /* register addit. SCSI channels as virtual controllers */
4705 for (b = 1; b < ha->bus_cnt + 1; ++b) {
4706 shp = scsi_register(shtp,sizeof(gdth_num_str));
4707 shp->unchecked_isa_dma = 0;
4708 shp->irq = ha->irq;
4709 shp->dma_channel = 0xff;
4710 gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
4711 NUMDATA(shp)->hanum = (ushort)hanum;
4712 NUMDATA(shp)->busnum = b;
4713 }
4714 }
4715
4716 spin_lock_init(&ha->smp_lock);
4717 gdth_enable_int(hanum);
4718 }
4719
4720 TRACE2(("gdth_detect() %d controller detected\n",gdth_ctr_count));
4721 if (gdth_ctr_count > 0) {
4722 #ifdef GDTH_STATISTICS
4723 TRACE2(("gdth_detect(): Initializing timer !\n"));
4724 init_timer(&gdth_timer);
4725 gdth_timer.expires = jiffies + HZ;
4726 gdth_timer.data = 0L;
4727 gdth_timer.function = gdth_timeout;
4728 add_timer(&gdth_timer);
4729 #endif
4730 major = register_chrdev(0,"gdth",&gdth_fops);
4731 notifier_disabled = 0;
4732 register_reboot_notifier(&gdth_notifier);
4733 }
4734 gdth_polling = FALSE;
4735 return gdth_ctr_vcount;
4736 }
4737
4738 static int gdth_release(struct Scsi_Host *shp)
4739 {
4740 int hanum;
4741 gdth_ha_str *ha;
4742
4743 TRACE2(("gdth_release()\n"));
4744 if (NUMDATA(shp)->busnum == 0) {
4745 hanum = NUMDATA(shp)->hanum;
4746 ha = HADATA(gdth_ctr_tab[hanum]);
4747 if (ha->sdev) {
4748 scsi_free_host_dev(ha->sdev);
4749 ha->sdev = NULL;
4750 }
4751 gdth_flush(hanum);
4752
4753 if (shp->irq) {
4754 free_irq(shp->irq,ha);
4755 }
4756 #ifndef __ia64__
4757 if (shp->dma_channel != 0xff) {
4758 free_dma(shp->dma_channel);
4759 }
4760 #endif
4761 #ifdef INT_COAL
4762 if (ha->coal_stat)
4763 pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
4764 MAXOFFSETS, ha->coal_stat, ha->coal_stat_phys);
4765 #endif
4766 if (ha->pscratch)
4767 pci_free_consistent(ha->pdev, GDTH_SCRATCH,
4768 ha->pscratch, ha->scratch_phys);
4769 if (ha->pmsg)
4770 pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
4771 ha->pmsg, ha->msg_phys);
4772 if (ha->ccb_phys)
4773 pci_unmap_single(ha->pdev,ha->ccb_phys,
4774 sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
4775 gdth_ctr_released++;
4776 TRACE2(("gdth_release(): HA %d of %d\n",
4777 gdth_ctr_released, gdth_ctr_count));
4778
4779 if (gdth_ctr_released == gdth_ctr_count) {
4780 #ifdef GDTH_STATISTICS
4781 del_timer(&gdth_timer);
4782 #endif
4783 unregister_chrdev(major,"gdth");
4784 unregister_reboot_notifier(&gdth_notifier);
4785 }
4786 }
4787
4788 scsi_unregister(shp);
4789 return 0;
4790 }
4791
4792
4793 static const char *gdth_ctr_name(int hanum)
4794 {
4795 gdth_ha_str *ha;
4796
4797 TRACE2(("gdth_ctr_name()\n"));
4798
4799 ha = HADATA(gdth_ctr_tab[hanum]);
4800
4801 if (ha->type == GDT_EISA) {
4802 switch (ha->stype) {
4803 case GDT3_ID:
4804 return("GDT3000/3020");
4805 case GDT3A_ID:
4806 return("GDT3000A/3020A/3050A");
4807 case GDT3B_ID:
4808 return("GDT3000B/3010A");
4809 }
4810 } else if (ha->type == GDT_ISA) {
4811 return("GDT2000/2020");
4812 } else if (ha->type == GDT_PCI) {
4813 switch (ha->stype) {
4814 case PCI_DEVICE_ID_VORTEX_GDT60x0:
4815 return("GDT6000/6020/6050");
4816 case PCI_DEVICE_ID_VORTEX_GDT6000B:
4817 return("GDT6000B/6010");
4818 }
4819 }
4820 /* new controllers (GDT_PCINEW, GDT_PCIMPR, ..) use board_info IOCTL! */
4821
4822 return("");
4823 }
4824
4825 static const char *gdth_info(struct Scsi_Host *shp)
4826 {
4827 int hanum;
4828 gdth_ha_str *ha;
4829
4830 TRACE2(("gdth_info()\n"));
4831 hanum = NUMDATA(shp)->hanum;
4832 ha = HADATA(gdth_ctr_tab[hanum]);
4833
4834 return ((const char *)ha->binfo.type_string);
4835 }
4836
4837 static int gdth_eh_bus_reset(Scsi_Cmnd *scp)
4838 {
4839 int i, hanum;
4840 gdth_ha_str *ha;
4841 ulong flags;
4842 Scsi_Cmnd *cmnd;
4843 unchar b;
4844
4845 TRACE2(("gdth_eh_bus_reset()\n"));
4846
4847 hanum = NUMDATA(scp->device->host)->hanum;
4848 b = virt_ctr ? NUMDATA(scp->device->host)->busnum : scp->device->channel;
4849 ha = HADATA(gdth_ctr_tab[hanum]);
4850
4851 /* clear command tab */
4852 spin_lock_irqsave(&ha->smp_lock, flags);
4853 for (i = 0; i < GDTH_MAXCMDS; ++i) {
4854 cmnd = ha->cmd_tab[i].cmnd;
4855 if (!SPECIAL_SCP(cmnd) && cmnd->device->channel == b)
4856 ha->cmd_tab[i].cmnd = UNUSED_CMND;
4857 }
4858 spin_unlock_irqrestore(&ha->smp_lock, flags);
4859
4860 if (b == ha->virt_bus) {
4861 /* host drives */
4862 for (i = 0; i < MAX_HDRIVES; ++i) {
4863 if (ha->hdr[i].present) {
4864 spin_lock_irqsave(&ha->smp_lock, flags);
4865 gdth_polling = TRUE;
4866 while (gdth_test_busy(hanum))
4867 gdth_delay(0);
4868 if (gdth_internal_cmd(hanum, CACHESERVICE,
4869 GDT_CLUST_RESET, i, 0, 0))
4870 ha->hdr[i].cluster_type &= ~CLUSTER_RESERVED;
4871 gdth_polling = FALSE;
4872 spin_unlock_irqrestore(&ha->smp_lock, flags);
4873 }
4874 }
4875 } else {
4876 /* raw devices */
4877 spin_lock_irqsave(&ha->smp_lock, flags);
4878 for (i = 0; i < MAXID; ++i)
4879 ha->raw[BUS_L2P(ha,b)].io_cnt[i] = 0;
4880 gdth_polling = TRUE;
4881 while (gdth_test_busy(hanum))
4882 gdth_delay(0);
4883 gdth_internal_cmd(hanum, SCSIRAWSERVICE, GDT_RESET_BUS,
4884 BUS_L2P(ha,b), 0, 0);
4885 gdth_polling = FALSE;
4886 spin_unlock_irqrestore(&ha->smp_lock, flags);
4887 }
4888 return SUCCESS;
4889 }
4890
4891 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
4892 static int gdth_bios_param(struct scsi_device *sdev,struct block_device *bdev,sector_t cap,int *ip)
4893 #else
4894 static int gdth_bios_param(Disk *disk,kdev_t dev,int *ip)
4895 #endif
4896 {
4897 unchar b, t;
4898 int hanum;
4899 gdth_ha_str *ha;
4900 struct scsi_device *sd;
4901 unsigned capacity;
4902
4903 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
4904 sd = sdev;
4905 capacity = cap;
4906 #else
4907 sd = disk->device;
4908 capacity = disk->capacity;
4909 #endif
4910 hanum = NUMDATA(sd->host)->hanum;
4911 b = virt_ctr ? NUMDATA(sd->host)->busnum : sd->channel;
4912 t = sd->id;
4913 TRACE2(("gdth_bios_param() ha %d bus %d target %d\n", hanum, b, t));
4914 ha = HADATA(gdth_ctr_tab[hanum]);
4915
4916 if (b != ha->virt_bus || ha->hdr[t].heads == 0) {
4917 /* raw device or host drive without mapping information */
4918 TRACE2(("Evaluate mapping\n"));
4919 gdth_eval_mapping(capacity,&ip[2],&ip[0],&ip[1]);
4920 } else {
4921 ip[0] = ha->hdr[t].heads;
4922 ip[1] = ha->hdr[t].secs;
4923 ip[2] = capacity / ip[0] / ip[1];
4924 }
4925
4926 TRACE2(("gdth_bios_param(): %d heads, %d secs, %d cyls\n",
4927 ip[0],ip[1],ip[2]));
4928 return 0;
4929 }
4930
4931
4932 static int gdth_queuecommand(Scsi_Cmnd *scp,void (*done)(Scsi_Cmnd *))
4933 {
4934 int hanum;
4935 int priority;
4936
4937 TRACE(("gdth_queuecommand() cmd 0x%x\n", scp->cmnd[0]));
4938
4939 scp->scsi_done = (void *)done;
4940 scp->SCp.have_data_in = 1;
4941 scp->SCp.phase = -1;
4942 scp->SCp.sent_command = -1;
4943 scp->SCp.Status = GDTH_MAP_NONE;
4944 scp->SCp.buffer = (struct scatterlist *)NULL;
4945
4946 hanum = NUMDATA(scp->device->host)->hanum;
4947 #ifdef GDTH_STATISTICS
4948 ++act_ios;
4949 #endif
4950
4951 priority = DEFAULT_PRI;
4952 if (scp->done == gdth_scsi_done)
4953 priority = scp->SCp.this_residual;
4954 else
4955 gdth_update_timeout(hanum, scp, scp->timeout_per_command * 6);
4956
4957 gdth_putq( hanum, scp, priority );
4958 gdth_next( hanum );
4959 return 0;
4960 }
4961
4962
4963 static int gdth_open(struct inode *inode, struct file *filep)
4964 {
4965 gdth_ha_str *ha;
4966 int i;
4967
4968 for (i = 0; i < gdth_ctr_count; i++) {
4969 ha = HADATA(gdth_ctr_tab[i]);
4970 if (!ha->sdev)
4971 ha->sdev = scsi_get_host_dev(gdth_ctr_tab[i]);
4972 }
4973
4974 TRACE(("gdth_open()\n"));
4975 return 0;
4976 }
4977
4978 static int gdth_close(struct inode *inode, struct file *filep)
4979 {
4980 TRACE(("gdth_close()\n"));
4981 return 0;
4982 }
4983
4984 static int ioc_event(void __user *arg)
4985 {
4986 gdth_ioctl_event evt;
4987 gdth_ha_str *ha;
4988 ulong flags;
4989
4990 if (copy_from_user(&evt, arg, sizeof(gdth_ioctl_event)) ||
4991 evt.ionode >= gdth_ctr_count)
4992 return -EFAULT;
4993 ha = HADATA(gdth_ctr_tab[evt.ionode]);
4994
4995 if (evt.erase == 0xff) {
4996 if (evt.event.event_source == ES_TEST)
4997 evt.event.event_data.size=sizeof(evt.event.event_data.eu.test);
4998 else if (evt.event.event_source == ES_DRIVER)
4999 evt.event.event_data.size=sizeof(evt.event.event_data.eu.driver);
5000 else if (evt.event.event_source == ES_SYNC)
5001 evt.event.event_data.size=sizeof(evt.event.event_data.eu.sync);
5002 else
5003 evt.event.event_data.size=sizeof(evt.event.event_data.eu.async);
5004 spin_lock_irqsave(&ha->smp_lock, flags);
5005 gdth_store_event(ha, evt.event.event_source, evt.event.event_idx,
5006 &evt.event.event_data);
5007 spin_unlock_irqrestore(&ha->smp_lock, flags);
5008 } else if (evt.erase == 0xfe) {
5009 gdth_clear_events();
5010 } else if (evt.erase == 0) {
5011 evt.handle = gdth_read_event(ha, evt.handle, &evt.event);
5012 } else {
5013 gdth_readapp_event(ha, evt.erase, &evt.event);
5014 }
5015 if (copy_to_user(arg, &evt, sizeof(gdth_ioctl_event)))
5016 return -EFAULT;
5017 return 0;
5018 }
5019
5020 static int ioc_lockdrv(void __user *arg)
5021 {
5022 gdth_ioctl_lockdrv ldrv;
5023 unchar i, j;
5024 ulong flags;
5025 gdth_ha_str *ha;
5026
5027 if (copy_from_user(&ldrv, arg, sizeof(gdth_ioctl_lockdrv)) ||
5028 ldrv.ionode >= gdth_ctr_count)
5029 return -EFAULT;
5030 ha = HADATA(gdth_ctr_tab[ldrv.ionode]);
5031
5032 for (i = 0; i < ldrv.drive_cnt && i < MAX_HDRIVES; ++i) {
5033 j = ldrv.drives[i];
5034 if (j >= MAX_HDRIVES || !ha->hdr[j].present)
5035 continue;
5036 if (ldrv.lock) {
5037 spin_lock_irqsave(&ha->smp_lock, flags);
5038 ha->hdr[j].lock = 1;
5039 spin_unlock_irqrestore(&ha->smp_lock, flags);
5040 gdth_wait_completion(ldrv.ionode, ha->bus_cnt, j);
5041 gdth_stop_timeout(ldrv.ionode, ha->bus_cnt, j);
5042 } else {
5043 spin_lock_irqsave(&ha->smp_lock, flags);
5044 ha->hdr[j].lock = 0;
5045 spin_unlock_irqrestore(&ha->smp_lock, flags);
5046 gdth_start_timeout(ldrv.ionode, ha->bus_cnt, j);
5047 gdth_next(ldrv.ionode);
5048 }
5049 }
5050 return 0;
5051 }
5052
5053 static int ioc_resetdrv(void __user *arg, char *cmnd)
5054 {
5055 gdth_ioctl_reset res;
5056 gdth_cmd_str cmd;
5057 int hanum;
5058 gdth_ha_str *ha;
5059 int rval;
5060
5061 if (copy_from_user(&res, arg, sizeof(gdth_ioctl_reset)) ||
5062 res.ionode >= gdth_ctr_count || res.number >= MAX_HDRIVES)
5063 return -EFAULT;
5064 hanum = res.ionode;
5065 ha = HADATA(gdth_ctr_tab[hanum]);
5066
5067 if (!ha->hdr[res.number].present)
5068 return 0;
5069 memset(&cmd, 0, sizeof(gdth_cmd_str));
5070 cmd.Service = CACHESERVICE;
5071 cmd.OpCode = GDT_CLUST_RESET;
5072 if (ha->cache_feat & GDT_64BIT)
5073 cmd.u.cache64.DeviceNo = res.number;
5074 else
5075 cmd.u.cache.DeviceNo = res.number;
5076
5077 rval = __gdth_execute(ha->sdev, &cmd, cmnd, 30, NULL);
5078 if (rval < 0)
5079 return rval;
5080 res.status = rval;
5081
5082 if (copy_to_user(arg, &res, sizeof(gdth_ioctl_reset)))
5083 return -EFAULT;
5084 return 0;
5085 }
5086
5087 static int ioc_general(void __user *arg, char *cmnd)
5088 {
5089 gdth_ioctl_general gen;
5090 char *buf = NULL;
5091 ulong64 paddr;
5092 int hanum;
5093 gdth_ha_str *ha;
5094 int rval;
5095
5096 if (copy_from_user(&gen, arg, sizeof(gdth_ioctl_general)) ||
5097 gen.ionode >= gdth_ctr_count)
5098 return -EFAULT;
5099 hanum = gen.ionode;
5100 ha = HADATA(gdth_ctr_tab[hanum]);
5101 if (gen.data_len + gen.sense_len != 0) {
5102 if (!(buf = gdth_ioctl_alloc(hanum, gen.data_len + gen.sense_len,
5103 FALSE, &paddr)))
5104 return -EFAULT;
5105 if (copy_from_user(buf, arg + sizeof(gdth_ioctl_general),
5106 gen.data_len + gen.sense_len)) {
5107 gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
5108 return -EFAULT;
5109 }
5110
5111 if (gen.command.OpCode == GDT_IOCTL) {
5112 gen.command.u.ioctl.p_param = paddr;
5113 } else if (gen.command.Service == CACHESERVICE) {
5114 if (ha->cache_feat & GDT_64BIT) {
5115 /* copy elements from 32-bit IOCTL structure */
5116 gen.command.u.cache64.BlockCnt = gen.command.u.cache.BlockCnt;
5117 gen.command.u.cache64.BlockNo = gen.command.u.cache.BlockNo;
5118 gen.command.u.cache64.DeviceNo = gen.command.u.cache.DeviceNo;
5119 /* addresses */
5120 if (ha->cache_feat & SCATTER_GATHER) {
5121 gen.command.u.cache64.DestAddr = (ulong64)-1;
5122 gen.command.u.cache64.sg_canz = 1;
5123 gen.command.u.cache64.sg_lst[0].sg_ptr = paddr;
5124 gen.command.u.cache64.sg_lst[0].sg_len = gen.data_len;
5125 gen.command.u.cache64.sg_lst[1].sg_len = 0;
5126 } else {
5127 gen.command.u.cache64.DestAddr = paddr;
5128 gen.command.u.cache64.sg_canz = 0;
5129 }
5130 } else {
5131 if (ha->cache_feat & SCATTER_GATHER) {
5132 gen.command.u.cache.DestAddr = 0xffffffff;
5133 gen.command.u.cache.sg_canz = 1;
5134 gen.command.u.cache.sg_lst[0].sg_ptr = (ulong32)paddr;
5135 gen.command.u.cache.sg_lst[0].sg_len = gen.data_len;
5136 gen.command.u.cache.sg_lst[1].sg_len = 0;
5137 } else {
5138 gen.command.u.cache.DestAddr = paddr;
5139 gen.command.u.cache.sg_canz = 0;
5140 }
5141 }
5142 } else if (gen.command.Service == SCSIRAWSERVICE) {
5143 if (ha->raw_feat & GDT_64BIT) {
5144 /* copy elements from 32-bit IOCTL structure */
5145 char cmd[16];
5146 gen.command.u.raw64.sense_len = gen.command.u.raw.sense_len;
5147 gen.command.u.raw64.bus = gen.command.u.raw.bus;
5148 gen.command.u.raw64.lun = gen.command.u.raw.lun;
5149 gen.command.u.raw64.target = gen.command.u.raw.target;
5150 memcpy(cmd, gen.command.u.raw.cmd, 16);
5151 memcpy(gen.command.u.raw64.cmd, cmd, 16);
5152 gen.command.u.raw64.clen = gen.command.u.raw.clen;
5153 gen.command.u.raw64.sdlen = gen.command.u.raw.sdlen;
5154 gen.command.u.raw64.direction = gen.command.u.raw.direction;
5155 /* addresses */
5156 if (ha->raw_feat & SCATTER_GATHER) {
5157 gen.command.u.raw64.sdata = (ulong64)-1;
5158 gen.command.u.raw64.sg_ranz = 1;
5159 gen.command.u.raw64.sg_lst[0].sg_ptr = paddr;
5160 gen.command.u.raw64.sg_lst[0].sg_len = gen.data_len;
5161 gen.command.u.raw64.sg_lst[1].sg_len = 0;
5162 } else {
5163 gen.command.u.raw64.sdata = paddr;
5164 gen.command.u.raw64.sg_ranz = 0;
5165 }
5166 gen.command.u.raw64.sense_data = paddr + gen.data_len;
5167 } else {
5168 if (ha->raw_feat & SCATTER_GATHER) {
5169 gen.command.u.raw.sdata = 0xffffffff;
5170 gen.command.u.raw.sg_ranz = 1;
5171 gen.command.u.raw.sg_lst[0].sg_ptr = (ulong32)paddr;
5172 gen.command.u.raw.sg_lst[0].sg_len = gen.data_len;
5173 gen.command.u.raw.sg_lst[1].sg_len = 0;
5174 } else {
5175 gen.command.u.raw.sdata = paddr;
5176 gen.command.u.raw.sg_ranz = 0;
5177 }
5178 gen.command.u.raw.sense_data = (ulong32)paddr + gen.data_len;
5179 }
5180 } else {
5181 gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
5182 return -EFAULT;
5183 }
5184 }
5185
5186 rval = __gdth_execute(ha->sdev, &gen.command, cmnd, gen.timeout, &gen.info);
5187 if (rval < 0)
5188 return rval;
5189 gen.status = rval;
5190
5191 if (copy_to_user(arg + sizeof(gdth_ioctl_general), buf,
5192 gen.data_len + gen.sense_len)) {
5193 gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
5194 return -EFAULT;
5195 }
5196 if (copy_to_user(arg, &gen,
5197 sizeof(gdth_ioctl_general) - sizeof(gdth_cmd_str))) {
5198 gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
5199 return -EFAULT;
5200 }
5201 gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
5202 return 0;
5203 }
5204
5205 static int ioc_hdrlist(void __user *arg, char *cmnd)
5206 {
5207 gdth_ioctl_rescan *rsc;
5208 gdth_cmd_str *cmd;
5209 gdth_ha_str *ha;
5210 unchar i;
5211 int hanum, rc = -ENOMEM;
5212 u32 cluster_type = 0;
5213
5214 rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
5215 cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
5216 if (!rsc || !cmd)
5217 goto free_fail;
5218
5219 if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
5220 rsc->ionode >= gdth_ctr_count) {
5221 rc = -EFAULT;
5222 goto free_fail;
5223 }
5224 hanum = rsc->ionode;
5225 ha = HADATA(gdth_ctr_tab[hanum]);
5226 memset(cmd, 0, sizeof(gdth_cmd_str));
5227
5228 for (i = 0; i < MAX_HDRIVES; ++i) {
5229 if (!ha->hdr[i].present) {
5230 rsc->hdr_list[i].bus = 0xff;
5231 continue;
5232 }
5233 rsc->hdr_list[i].bus = ha->virt_bus;
5234 rsc->hdr_list[i].target = i;
5235 rsc->hdr_list[i].lun = 0;
5236 rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
5237 if (ha->hdr[i].cluster_type & CLUSTER_DRIVE) {
5238 cmd->Service = CACHESERVICE;
5239 cmd->OpCode = GDT_CLUST_INFO;
5240 if (ha->cache_feat & GDT_64BIT)
5241 cmd->u.cache64.DeviceNo = i;
5242 else
5243 cmd->u.cache.DeviceNo = i;
5244 if (__gdth_execute(ha->sdev, cmd, cmnd, 30, &cluster_type) == S_OK)
5245 rsc->hdr_list[i].cluster_type = cluster_type;
5246 }
5247 }
5248
5249 if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
5250 rc = -EFAULT;
5251 else
5252 rc = 0;
5253
5254 free_fail:
5255 kfree(rsc);
5256 kfree(cmd);
5257 return rc;
5258 }
5259
5260 static int ioc_rescan(void __user *arg, char *cmnd)
5261 {
5262 gdth_ioctl_rescan *rsc;
5263 gdth_cmd_str *cmd;
5264 ushort i, status, hdr_cnt;
5265 ulong32 info;
5266 int hanum, cyls, hds, secs;
5267 int rc = -ENOMEM;
5268 ulong flags;
5269 gdth_ha_str *ha;
5270
5271 rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
5272 cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
5273 if (!cmd || !rsc)
5274 goto free_fail;
5275
5276 if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
5277 rsc->ionode >= gdth_ctr_count) {
5278 rc = -EFAULT;
5279 goto free_fail;
5280 }
5281 hanum = rsc->ionode;
5282 ha = HADATA(gdth_ctr_tab[hanum]);
5283 memset(cmd, 0, sizeof(gdth_cmd_str));
5284
5285 if (rsc->flag == 0) {
5286 /* old method: re-init. cache service */
5287 cmd->Service = CACHESERVICE;
5288 if (ha->cache_feat & GDT_64BIT) {
5289 cmd->OpCode = GDT_X_INIT_HOST;
5290 cmd->u.cache64.DeviceNo = LINUX_OS;
5291 } else {
5292 cmd->OpCode = GDT_INIT;
5293 cmd->u.cache.DeviceNo = LINUX_OS;
5294 }
5295
5296 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
5297 i = 0;
5298 hdr_cnt = (status == S_OK ? (ushort)info : 0);
5299 } else {
5300 i = rsc->hdr_no;
5301 hdr_cnt = i + 1;
5302 }
5303
5304 for (; i < hdr_cnt && i < MAX_HDRIVES; ++i) {
5305 cmd->Service = CACHESERVICE;
5306 cmd->OpCode = GDT_INFO;
5307 if (ha->cache_feat & GDT_64BIT)
5308 cmd->u.cache64.DeviceNo = i;
5309 else
5310 cmd->u.cache.DeviceNo = i;
5311
5312 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
5313
5314 spin_lock_irqsave(&ha->smp_lock, flags);
5315 rsc->hdr_list[i].bus = ha->virt_bus;
5316 rsc->hdr_list[i].target = i;
5317 rsc->hdr_list[i].lun = 0;
5318 if (status != S_OK) {
5319 ha->hdr[i].present = FALSE;
5320 } else {
5321 ha->hdr[i].present = TRUE;
5322 ha->hdr[i].size = info;
5323 /* evaluate mapping */
5324 ha->hdr[i].size &= ~SECS32;
5325 gdth_eval_mapping(ha->hdr[i].size,&cyls,&hds,&secs);
5326 ha->hdr[i].heads = hds;
5327 ha->hdr[i].secs = secs;
5328 /* round size */
5329 ha->hdr[i].size = cyls * hds * secs;
5330 }
5331 spin_unlock_irqrestore(&ha->smp_lock, flags);
5332 if (status != S_OK)
5333 continue;
5334
5335 /* extended info, if GDT_64BIT, for drives > 2 TB */
5336 /* but we need ha->info2, not yet stored in scp->SCp */
5337
5338 /* devtype, cluster info, R/W attribs */
5339 cmd->Service = CACHESERVICE;
5340 cmd->OpCode = GDT_DEVTYPE;
5341 if (ha->cache_feat & GDT_64BIT)
5342 cmd->u.cache64.DeviceNo = i;
5343 else
5344 cmd->u.cache.DeviceNo = i;
5345
5346 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
5347
5348 spin_lock_irqsave(&ha->smp_lock, flags);
5349 ha->hdr[i].devtype = (status == S_OK ? (ushort)info : 0);
5350 spin_unlock_irqrestore(&ha->smp_lock, flags);
5351
5352 cmd->Service = CACHESERVICE;
5353 cmd->OpCode = GDT_CLUST_INFO;
5354 if (ha->cache_feat & GDT_64BIT)
5355 cmd->u.cache64.DeviceNo = i;
5356 else
5357 cmd->u.cache.DeviceNo = i;
5358
5359 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
5360
5361 spin_lock_irqsave(&ha->smp_lock, flags);
5362 ha->hdr[i].cluster_type =
5363 ((status == S_OK && !shared_access) ? (ushort)info : 0);
5364 spin_unlock_irqrestore(&ha->smp_lock, flags);
5365 rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
5366
5367 cmd->Service = CACHESERVICE;
5368 cmd->OpCode = GDT_RW_ATTRIBS;
5369 if (ha->cache_feat & GDT_64BIT)
5370 cmd->u.cache64.DeviceNo = i;
5371 else
5372 cmd->u.cache.DeviceNo = i;
5373
5374 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
5375
5376 spin_lock_irqsave(&ha->smp_lock, flags);
5377 ha->hdr[i].rw_attribs = (status == S_OK ? (ushort)info : 0);
5378 spin_unlock_irqrestore(&ha->smp_lock, flags);
5379 }
5380
5381 if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
5382 rc = -EFAULT;
5383 else
5384 rc = 0;
5385
5386 free_fail:
5387 kfree(rsc);
5388 kfree(cmd);
5389 return rc;
5390 }
5391
5392 static int gdth_ioctl(struct inode *inode, struct file *filep,
5393 unsigned int cmd, unsigned long arg)
5394 {
5395 gdth_ha_str *ha;
5396 Scsi_Cmnd *scp;
5397 ulong flags;
5398 char cmnd[MAX_COMMAND_SIZE];
5399 void __user *argp = (void __user *)arg;
5400
5401 memset(cmnd, 0xff, 12);
5402
5403 TRACE(("gdth_ioctl() cmd 0x%x\n", cmd));
5404
5405 switch (cmd) {
5406 case GDTIOCTL_CTRCNT:
5407 {
5408 int cnt = gdth_ctr_count;
5409 if (put_user(cnt, (int __user *)argp))
5410 return -EFAULT;
5411 break;
5412 }
5413
5414 case GDTIOCTL_DRVERS:
5415 {
5416 int ver = (GDTH_VERSION<<8) | GDTH_SUBVERSION;
5417 if (put_user(ver, (int __user *)argp))
5418 return -EFAULT;
5419 break;
5420 }
5421
5422 case GDTIOCTL_OSVERS:
5423 {
5424 gdth_ioctl_osvers osv;
5425
5426 osv.version = (unchar)(LINUX_VERSION_CODE >> 16);
5427 osv.subversion = (unchar)(LINUX_VERSION_CODE >> 8);
5428 osv.revision = (ushort)(LINUX_VERSION_CODE & 0xff);
5429 if (copy_to_user(argp, &osv, sizeof(gdth_ioctl_osvers)))
5430 return -EFAULT;
5431 break;
5432 }
5433
5434 case GDTIOCTL_CTRTYPE:
5435 {
5436 gdth_ioctl_ctrtype ctrt;
5437
5438 if (copy_from_user(&ctrt, argp, sizeof(gdth_ioctl_ctrtype)) ||
5439 ctrt.ionode >= gdth_ctr_count)
5440 return -EFAULT;
5441 ha = HADATA(gdth_ctr_tab[ctrt.ionode]);
5442 if (ha->type == GDT_ISA || ha->type == GDT_EISA) {
5443 ctrt.type = (unchar)((ha->stype>>20) - 0x10);
5444 } else {
5445 if (ha->type != GDT_PCIMPR) {
5446 ctrt.type = (unchar)((ha->stype<<4) + 6);
5447 } else {
5448 ctrt.type =
5449 (ha->oem_id == OEM_ID_INTEL ? 0xfd : 0xfe);
5450 if (ha->stype >= 0x300)
5451 ctrt.ext_type = 0x6000 | ha->subdevice_id;
5452 else
5453 ctrt.ext_type = 0x6000 | ha->stype;
5454 }
5455 ctrt.device_id = ha->stype;
5456 ctrt.sub_device_id = ha->subdevice_id;
5457 }
5458 ctrt.info = ha->brd_phys;
5459 ctrt.oem_id = ha->oem_id;
5460 if (copy_to_user(argp, &ctrt, sizeof(gdth_ioctl_ctrtype)))
5461 return -EFAULT;
5462 break;
5463 }
5464
5465 case GDTIOCTL_GENERAL:
5466 return ioc_general(argp, cmnd);
5467
5468 case GDTIOCTL_EVENT:
5469 return ioc_event(argp);
5470
5471 case GDTIOCTL_LOCKDRV:
5472 return ioc_lockdrv(argp);
5473
5474 case GDTIOCTL_LOCKCHN:
5475 {
5476 gdth_ioctl_lockchn lchn;
5477 unchar i, j;
5478
5479 if (copy_from_user(&lchn, argp, sizeof(gdth_ioctl_lockchn)) ||
5480 lchn.ionode >= gdth_ctr_count)
5481 return -EFAULT;
5482 ha = HADATA(gdth_ctr_tab[lchn.ionode]);
5483
5484 i = lchn.channel;
5485 if (i < ha->bus_cnt) {
5486 if (lchn.lock) {
5487 spin_lock_irqsave(&ha->smp_lock, flags);
5488 ha->raw[i].lock = 1;
5489 spin_unlock_irqrestore(&ha->smp_lock, flags);
5490 for (j = 0; j < ha->tid_cnt; ++j) {
5491 gdth_wait_completion(lchn.ionode, i, j);
5492 gdth_stop_timeout(lchn.ionode, i, j);
5493 }
5494 } else {
5495 spin_lock_irqsave(&ha->smp_lock, flags);
5496 ha->raw[i].lock = 0;
5497 spin_unlock_irqrestore(&ha->smp_lock, flags);
5498 for (j = 0; j < ha->tid_cnt; ++j) {
5499 gdth_start_timeout(lchn.ionode, i, j);
5500 gdth_next(lchn.ionode);
5501 }
5502 }
5503 }
5504 break;
5505 }
5506
5507 case GDTIOCTL_RESCAN:
5508 return ioc_rescan(argp, cmnd);
5509
5510 case GDTIOCTL_HDRLIST:
5511 return ioc_hdrlist(argp, cmnd);
5512
5513 case GDTIOCTL_RESET_BUS:
5514 {
5515 gdth_ioctl_reset res;
5516 int hanum, rval;
5517
5518 if (copy_from_user(&res, argp, sizeof(gdth_ioctl_reset)) ||
5519 res.ionode >= gdth_ctr_count)
5520 return -EFAULT;
5521 hanum = res.ionode;
5522 ha = HADATA(gdth_ctr_tab[hanum]);
5523
5524 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
5525 scp = kmalloc(sizeof(*scp), GFP_KERNEL);
5526 if (!scp)
5527 return -ENOMEM;
5528 memset(scp, 0, sizeof(*scp));
5529 scp->device = ha->sdev;
5530 scp->cmd_len = 12;
5531 scp->use_sg = 0;
5532 scp->device->channel = virt_ctr ? 0 : res.number;
5533 rval = gdth_eh_bus_reset(scp);
5534 res.status = (rval == SUCCESS ? S_OK : S_GENERR);
5535 kfree(scp);
5536 #else
5537 scp = scsi_allocate_device(ha->sdev, 1, FALSE);
5538 if (!scp)
5539 return -ENOMEM;
5540 scp->cmd_len = 12;
5541 scp->use_sg = 0;
5542 scp->channel = virt_ctr ? 0 : res.number;
5543 rval = gdth_eh_bus_reset(scp);
5544 res.status = (rval == SUCCESS ? S_OK : S_GENERR);
5545 scsi_release_command(scp);
5546 #endif
5547 if (copy_to_user(argp, &res, sizeof(gdth_ioctl_reset)))
5548 return -EFAULT;
5549 break;
5550 }
5551
5552 case GDTIOCTL_RESET_DRV:
5553 return ioc_resetdrv(argp, cmnd);
5554
5555 default:
5556 break;
5557 }
5558 return 0;
5559 }
5560
5561
5562 /* flush routine */
5563 static void gdth_flush(int hanum)
5564 {
5565 int i;
5566 gdth_ha_str *ha;
5567 gdth_cmd_str gdtcmd;
5568 char cmnd[MAX_COMMAND_SIZE];
5569 memset(cmnd, 0xff, MAX_COMMAND_SIZE);
5570
5571 TRACE2(("gdth_flush() hanum %d\n",hanum));
5572 ha = HADATA(gdth_ctr_tab[hanum]);
5573
5574 for (i = 0; i < MAX_HDRIVES; ++i) {
5575 if (ha->hdr[i].present) {
5576 gdtcmd.BoardNode = LOCALBOARD;
5577 gdtcmd.Service = CACHESERVICE;
5578 gdtcmd.OpCode = GDT_FLUSH;
5579 if (ha->cache_feat & GDT_64BIT) {
5580 gdtcmd.u.cache64.DeviceNo = i;
5581 gdtcmd.u.cache64.BlockNo = 1;
5582 gdtcmd.u.cache64.sg_canz = 0;
5583 } else {
5584 gdtcmd.u.cache.DeviceNo = i;
5585 gdtcmd.u.cache.BlockNo = 1;
5586 gdtcmd.u.cache.sg_canz = 0;
5587 }
5588 TRACE2(("gdth_flush(): flush ha %d drive %d\n", hanum, i));
5589
5590 gdth_execute(gdth_ctr_tab[hanum], &gdtcmd, cmnd, 30, NULL);
5591 }
5592 }
5593 }
5594
5595 /* shutdown routine */
5596 static int gdth_halt(struct notifier_block *nb, ulong event, void *buf)
5597 {
5598 int hanum;
5599 #ifndef __alpha__
5600 gdth_cmd_str gdtcmd;
5601 char cmnd[MAX_COMMAND_SIZE];
5602 #endif
5603
5604 if (notifier_disabled)
5605 return NOTIFY_OK;
5606
5607 TRACE2(("gdth_halt() event %d\n",(int)event));
5608 if (event != SYS_RESTART && event != SYS_HALT && event != SYS_POWER_OFF)
5609 return NOTIFY_DONE;
5610
5611 notifier_disabled = 1;
5612 printk("GDT-HA: Flushing all host drives .. ");
5613 for (hanum = 0; hanum < gdth_ctr_count; ++hanum) {
5614 gdth_flush(hanum);
5615
5616 #ifndef __alpha__
5617 /* controller reset */
5618 memset(cmnd, 0xff, MAX_COMMAND_SIZE);
5619 gdtcmd.BoardNode = LOCALBOARD;
5620 gdtcmd.Service = CACHESERVICE;
5621 gdtcmd.OpCode = GDT_RESET;
5622 TRACE2(("gdth_halt(): reset controller %d\n", hanum));
5623 gdth_execute(gdth_ctr_tab[hanum], &gdtcmd, cmnd, 10, NULL);
5624 #endif
5625 }
5626 printk("Done.\n");
5627
5628 #ifdef GDTH_STATISTICS
5629 del_timer(&gdth_timer);
5630 #endif
5631 return NOTIFY_OK;
5632 }
5633
5634 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
5635 /* configure lun */
5636 static int gdth_slave_configure(struct scsi_device *sdev)
5637 {
5638 scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
5639 sdev->skip_ms_page_3f = 1;
5640 sdev->skip_ms_page_8 = 1;
5641 return 0;
5642 }
5643 #endif
5644
5645 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
5646 static struct scsi_host_template driver_template = {
5647 #else
5648 static Scsi_Host_Template driver_template = {
5649 #endif
5650 .proc_name = "gdth",
5651 .proc_info = gdth_proc_info,
5652 .name = "GDT SCSI Disk Array Controller",
5653 .detect = gdth_detect,
5654 .release = gdth_release,
5655 .info = gdth_info,
5656 .queuecommand = gdth_queuecommand,
5657 .eh_bus_reset_handler = gdth_eh_bus_reset,
5658 .bios_param = gdth_bios_param,
5659 .can_queue = GDTH_MAXCMDS,
5660 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
5661 .slave_configure = gdth_slave_configure,
5662 #endif
5663 .this_id = -1,
5664 .sg_tablesize = GDTH_MAXSG,
5665 .cmd_per_lun = GDTH_MAXC_P_L,
5666 .unchecked_isa_dma = 1,
5667 .use_clustering = ENABLE_CLUSTERING,
5668 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
5669 .use_new_eh_code = 1,
5670 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,20)
5671 .highmem_io = 1,
5672 #endif
5673 #endif
5674 };
5675
5676 #include "scsi_module.c"
5677 #ifndef MODULE
5678 __setup("gdth=", option_setup);
5679 #endif
Mirror for ia64_pv_ops.git