drivers/dma/ioatdma.h

   1 /*
   2  * Copyright(c) 2004 - 2007 Intel Corporation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License as published by the Free
   6  * Software Foundation; either version 2 of the License, or (at your option)
   7  * any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc., 59
  16  * Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called COPYING.
  20  */
  21 #ifndef IOATDMA_H
  22 #define IOATDMA_H
  23
  24 #include <linux/dmaengine.h>
  25 #include "ioatdma_hw.h"
  26 #include <linux/init.h>
  27 #include <linux/dmapool.h>
  28 #include <linux/cache.h>
  29 #include <linux/pci_ids.h>
  30
  31 #define IOAT_DMA_VERSION  "2.04"
  32
  33 enum ioat_interrupt {
  34         none = 0,
  35         msix_multi_vector = 1,
  36         msix_single_vector = 2,
  37         msi = 3,
  38         intx = 4,
  39 };
  40
  41 #define IOAT_LOW_COMPLETION_MASK        0xffffffc0
  42 #define IOAT_DMA_DCA_ANY_CPU            ~0
  43
  44
  45 /**
  46  * struct ioatdma_device - internal representation of a IOAT device
  47  * @pdev: PCI-Express device
  48  * @reg_base: MMIO register space base address
  49  * @dma_pool: for allocating DMA descriptors
  50  * @common: embedded struct dma_device
  51  * @version: version of ioatdma device
  52  * @irq_mode: which style irq to use
  53  * @msix_entries: irq handlers
  54  * @idx: per channel data
  55  */
  56
  57 struct ioatdma_device {
  58         struct pci_dev *pdev;
  59         void __iomem *reg_base;
  60         struct pci_pool *dma_pool;
  61         struct pci_pool *completion_pool;
  62         struct dma_device common;
  63         u8 version;
  64         enum ioat_interrupt irq_mode;
  65         struct msix_entry msix_entries[4];
  66         struct ioat_dma_chan *idx[4];
  67 };
  68
  69 /**
  70  * struct ioat_dma_chan - internal representation of a DMA channel
  71  */
  72 struct ioat_dma_chan {
  73
  74         void __iomem *reg_base;
  75
  76         dma_cookie_t completed_cookie;
  77         unsigned long last_completion;
  78
  79         size_t xfercap; /* XFERCAP register value expanded out */
  80
  81         spinlock_t cleanup_lock;
  82         spinlock_t desc_lock;
  83         struct list_head free_desc;
  84         struct list_head used_desc;
  85
  86         int pending;
  87         int dmacount;
  88         int desccount;
  89
  90         struct ioatdma_device *device;
  91         struct dma_chan common;
  92
  93         dma_addr_t completion_addr;
  94         union {
  95                 u64 full; /* HW completion writeback */
  96                 struct {
  97                         u32 low;
  98                         u32 high;
  99                 };
 100         } *completion_virt;
 101         struct tasklet_struct cleanup_task;
 102 };
 103
 104 /* wrapper around hardware descriptor format + additional software fields */
 105
 106 /**
 107  * struct ioat_desc_sw - wrapper around hardware descriptor
 108  * @hw: hardware DMA descriptor
 109  * @node: this descriptor will either be on the free list,
 110  *     or attached to a transaction list (async_tx.tx_list)
 111  * @tx_cnt: number of descriptors required to complete the transaction
 112  * @async_tx: the generic software descriptor for all engines
 113  */
 114 struct ioat_desc_sw {
 115         struct ioat_dma_descriptor *hw;
 116         struct list_head node;
 117         int tx_cnt;
 118         size_t len;
 119         dma_addr_t src;
 120         dma_addr_t dst;
 121         struct dma_async_tx_descriptor async_tx;
 122 };
 123
 124 #if defined(CONFIG_INTEL_IOATDMA) || defined(CONFIG_INTEL_IOATDMA_MODULE)
 125 struct ioatdma_device *ioat_dma_probe(struct pci_dev *pdev,
 126                                       void __iomem *iobase);
 127 void ioat_dma_remove(struct ioatdma_device *device);
 128 struct dca_provider *ioat_dca_init(struct pci_dev *pdev, void __iomem *iobase);
 129 struct dca_provider *ioat2_dca_init(struct pci_dev *pdev, void __iomem *iobase);
 130 #else
 131 #define ioat_dma_probe(pdev, iobase)    NULL
 132 #define ioat_dma_remove(device)         do { } while (0)
 133 #define ioat_dca_init(pdev, iobase)     NULL
 134 #define ioat2_dca_init(pdev, iobase)    NULL
 135 #endif
 136
 137 #endif /* IOATDMA_H */