drivers/spi/spi_mpc83xx.c

   1 /*
   2  * MPC83xx SPI controller driver.
   3  *
   4  * Maintainer: Kumar Gala
   5  *
   6  * Copyright (C) 2006 Polycom, Inc.
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  */
  13 #include <linux/module.h>
  14 #include <linux/init.h>
  15 #include <linux/types.h>
  16 #include <linux/kernel.h>
  17 #include <linux/completion.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/delay.h>
  20 #include <linux/irq.h>
  21 #include <linux/device.h>
  22 #include <linux/spi/spi.h>
  23 #include <linux/spi/spi_bitbang.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/fsl_devices.h>
  26
  27 #include <asm/irq.h>
  28 #include <asm/io.h>
  29
  30 /* SPI Controller registers */
  31 struct mpc83xx_spi_reg {
  32         u8 res1[0x20];
  33         __be32 mode;
  34         __be32 event;
  35         __be32 mask;
  36         __be32 command;
  37         __be32 transmit;
  38         __be32 receive;
  39 };
  40
  41 /* SPI Controller mode register definitions */
  42 #define SPMODE_CI_INACTIVEHIGH  (1 << 29)
  43 #define SPMODE_CP_BEGIN_EDGECLK (1 << 28)
  44 #define SPMODE_DIV16            (1 << 27)
  45 #define SPMODE_REV              (1 << 26)
  46 #define SPMODE_MS               (1 << 25)
  47 #define SPMODE_ENABLE           (1 << 24)
  48 #define SPMODE_LEN(x)           ((x) << 20)
  49 #define SPMODE_PM(x)            ((x) << 16)
  50
  51 /*
  52  * Default for SPI Mode:
  53  *      SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk
  54  */
  55 #define SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \
  56                          SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf))
  57
  58 /* SPIE register values */
  59 #define SPIE_NE         0x00000200      /* Not empty */
  60 #define SPIE_NF         0x00000100      /* Not full */
  61
  62 /* SPIM register values */
  63 #define SPIM_NE         0x00000200      /* Not empty */
  64 #define SPIM_NF         0x00000100      /* Not full */
  65
  66 /* SPI Controller driver's private data. */
  67 struct mpc83xx_spi {
  68         /* bitbang has to be first */
  69         struct spi_bitbang bitbang;
  70         struct completion done;
  71
  72         struct mpc83xx_spi_reg __iomem *base;
  73
  74         /* rx & tx bufs from the spi_transfer */
  75         const void *tx;
  76         void *rx;
  77
  78         /* functions to deal with different sized buffers */
  79         void (*get_rx) (u32 rx_data, struct mpc83xx_spi *);
  80         u32(*get_tx) (struct mpc83xx_spi *);
  81
  82         unsigned int count;
  83         u32 irq;
  84
  85         unsigned nsecs;         /* (clock cycle time)/2 */
  86
  87         u32 sysclk;
  88         void (*activate_cs) (u8 cs, u8 polarity);
  89         void (*deactivate_cs) (u8 cs, u8 polarity);
  90 };
  91
  92 static inline void mpc83xx_spi_write_reg(__be32 __iomem * reg, u32 val)
  93 {
  94         out_be32(reg, val);
  95 }
  96
  97 static inline u32 mpc83xx_spi_read_reg(__be32 __iomem * reg)
  98 {
  99         return in_be32(reg);
 100 }
 101
 102 #define MPC83XX_SPI_RX_BUF(type)                                          \
 103 void mpc83xx_spi_rx_buf_##type(u32 data, struct mpc83xx_spi *mpc83xx_spi) \
 104 {                                                                         \
 105         type * rx = mpc83xx_spi->rx;                                      \
 106         *rx++ = (type)data;                                               \
 107         mpc83xx_spi->rx = rx;                                             \
 108 }
 109
 110 #define MPC83XX_SPI_TX_BUF(type)                                \
 111 u32 mpc83xx_spi_tx_buf_##type(struct mpc83xx_spi *mpc83xx_spi)  \
 112 {                                                               \
 113         u32 data;                                               \
 114         const type * tx = mpc83xx_spi->tx;                      \
 115         if (!tx)                                                \
 116                 return 0;                                       \
 117         data = *tx++;                                           \
 118         mpc83xx_spi->tx = tx;                                   \
 119         return data;                                            \
 120 }
 121
 122 MPC83XX_SPI_RX_BUF(u8)
 123 MPC83XX_SPI_RX_BUF(u16)
 124 MPC83XX_SPI_RX_BUF(u32)
 125 MPC83XX_SPI_TX_BUF(u8)
 126 MPC83XX_SPI_TX_BUF(u16)
 127 MPC83XX_SPI_TX_BUF(u32)
 128
 129 static void mpc83xx_spi_chipselect(struct spi_device *spi, int value)
 130 {
 131         struct mpc83xx_spi *mpc83xx_spi;
 132         u8 pol = spi->mode & SPI_CS_HIGH ? 1 : 0;
 133
 134         mpc83xx_spi = spi_master_get_devdata(spi->master);
 135
 136         if (value == BITBANG_CS_INACTIVE) {
 137                 if (mpc83xx_spi->deactivate_cs)
 138                         mpc83xx_spi->deactivate_cs(spi->chip_select, pol);
 139         }
 140
 141         if (value == BITBANG_CS_ACTIVE) {
 142                 u32 regval = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
 143                 u32 len = spi->bits_per_word;
 144                 if (len == 32)
 145                         len = 0;
 146                 else
 147                         len = len - 1;
 148
 149                 /* mask out bits we are going to set */
 150                 regval &= ~0x38ff0000;
 151
 152                 if (spi->mode & SPI_CPHA)
 153                         regval |= SPMODE_CP_BEGIN_EDGECLK;
 154                 if (spi->mode & SPI_CPOL)
 155                         regval |= SPMODE_CI_INACTIVEHIGH;
 156
 157                 regval |= SPMODE_LEN(len);
 158
 159                 if ((mpc83xx_spi->sysclk / spi->max_speed_hz) >= 64) {
 160                         u8 pm = mpc83xx_spi->sysclk / (spi->max_speed_hz * 64);
 161                         regval |= SPMODE_PM(pm) | SPMODE_DIV16;
 162                 } else {
 163                         u8 pm = mpc83xx_spi->sysclk / (spi->max_speed_hz * 4);
 164                         regval |= SPMODE_PM(pm);
 165                 }
 166
 167                 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval);
 168                 if (mpc83xx_spi->activate_cs)
 169                         mpc83xx_spi->activate_cs(spi->chip_select, pol);
 170         }
 171 }
 172
 173 static
 174 int mpc83xx_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
 175 {
 176         struct mpc83xx_spi *mpc83xx_spi;
 177         u32 regval;
 178         u8 bits_per_word;
 179         u32 hz;
 180
 181         mpc83xx_spi = spi_master_get_devdata(spi->master);
 182
 183         if (t) {
 184                 bits_per_word = t->bits_per_word;
 185                 hz = t->speed_hz;
 186         } else {
 187                 bits_per_word = 0;
 188                 hz = 0;
 189         }
 190
 191         /* spi_transfer level calls that work per-word */
 192         if (!bits_per_word)
 193                 bits_per_word = spi->bits_per_word;
 194
 195         /* Make sure its a bit width we support [4..16, 32] */
 196         if ((bits_per_word < 4)
 197             || ((bits_per_word > 16) && (bits_per_word != 32)))
 198                 return -EINVAL;
 199
 200         if (bits_per_word <= 8) {
 201                 mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u8;
 202                 mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u8;
 203         } else if (bits_per_word <= 16) {
 204                 mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u16;
 205                 mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u16;
 206         } else if (bits_per_word <= 32) {
 207                 mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u32;
 208                 mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u32;
 209         } else
 210                 return -EINVAL;
 211
 212         /* nsecs = (clock period)/2 */
 213         if (!hz)
 214                 hz = spi->max_speed_hz;
 215         mpc83xx_spi->nsecs = (1000000000 / 2) / hz;
 216         if (mpc83xx_spi->nsecs > MAX_UDELAY_MS * 1000)
 217                 return -EINVAL;
 218
 219         if (bits_per_word == 32)
 220                 bits_per_word = 0;
 221         else
 222                 bits_per_word = bits_per_word - 1;
 223
 224         regval = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
 225
 226         /* Mask out bits_per_wordgth */
 227         regval &= 0xff0fffff;
 228         regval |= SPMODE_LEN(bits_per_word);
 229
 230         mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval);
 231
 232         return 0;
 233 }
 234
 235 static int mpc83xx_spi_setup(struct spi_device *spi)
 236 {
 237         struct spi_bitbang *bitbang;
 238         struct mpc83xx_spi *mpc83xx_spi;
 239         int retval;
 240
 241         if (!spi->max_speed_hz)
 242                 return -EINVAL;
 243
 244         bitbang = spi_master_get_devdata(spi->master);
 245         mpc83xx_spi = spi_master_get_devdata(spi->master);
 246
 247         if (!spi->bits_per_word)
 248                 spi->bits_per_word = 8;
 249
 250         retval = mpc83xx_spi_setup_transfer(spi, NULL);
 251         if (retval < 0)
 252                 return retval;
 253
 254         dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec\n",
 255                 __FUNCTION__, spi->mode & (SPI_CPOL | SPI_CPHA),
 256                 spi->bits_per_word, 2 * mpc83xx_spi->nsecs);
 257
 258         /* NOTE we _need_ to call chipselect() early, ideally with adapter
 259          * setup, unless the hardware defaults cooperate to avoid confusion
 260          * between normal (active low) and inverted chipselects.
 261          */
 262
 263         /* deselect chip (low or high) */
 264         spin_lock(&bitbang->lock);
 265         if (!bitbang->busy) {
 266                 bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
 267                 ndelay(mpc83xx_spi->nsecs);
 268         }
 269         spin_unlock(&bitbang->lock);
 270
 271         return 0;
 272 }
 273
 274 static int mpc83xx_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
 275 {
 276         struct mpc83xx_spi *mpc83xx_spi;
 277         u32 word;
 278
 279         mpc83xx_spi = spi_master_get_devdata(spi->master);
 280
 281         mpc83xx_spi->tx = t->tx_buf;
 282         mpc83xx_spi->rx = t->rx_buf;
 283         mpc83xx_spi->count = t->len;
 284         INIT_COMPLETION(mpc83xx_spi->done);
 285
 286         /* enable rx ints */
 287         mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, SPIM_NE);
 288
 289         /* transmit word */
 290         word = mpc83xx_spi->get_tx(mpc83xx_spi);
 291         mpc83xx_spi_write_reg(&mpc83xx_spi->base->transmit, word);
 292
 293         wait_for_completion(&mpc83xx_spi->done);
 294
 295         /* disable rx ints */
 296         mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, 0);
 297
 298         return t->len - mpc83xx_spi->count;
 299 }
 300
 301 irqreturn_t mpc83xx_spi_irq(s32 irq, void *context_data)
 302 {
 303         struct mpc83xx_spi *mpc83xx_spi = context_data;
 304         u32 event;
 305         irqreturn_t ret = IRQ_NONE;
 306
 307         /* Get interrupt events(tx/rx) */
 308         event = mpc83xx_spi_read_reg(&mpc83xx_spi->base->event);
 309
 310         /* We need handle RX first */
 311         if (event & SPIE_NE) {
 312                 u32 rx_data = mpc83xx_spi_read_reg(&mpc83xx_spi->base->receive);
 313
 314                 if (mpc83xx_spi->rx)
 315                         mpc83xx_spi->get_rx(rx_data, mpc83xx_spi);
 316
 317                 ret = IRQ_HANDLED;
 318         }
 319
 320         if ((event & SPIE_NF) == 0)
 321                 /* spin until TX is done */
 322                 while (((event =
 323                          mpc83xx_spi_read_reg(&mpc83xx_spi->base->event)) &
 324                                                 SPIE_NF) == 0)
 325                          cpu_relax();
 326
 327         mpc83xx_spi->count -= 1;
 328         if (mpc83xx_spi->count) {
 329                 if (mpc83xx_spi->tx) {
 330                         u32 word = mpc83xx_spi->get_tx(mpc83xx_spi);
 331                         mpc83xx_spi_write_reg(&mpc83xx_spi->base->transmit,
 332                                               word);
 333                 }
 334         } else {
 335                 complete(&mpc83xx_spi->done);
 336         }
 337
 338         /* Clear the events */
 339         mpc83xx_spi_write_reg(&mpc83xx_spi->base->event, event);
 340
 341         return ret;
 342 }
 343
 344 static int __init mpc83xx_spi_probe(struct platform_device *dev)
 345 {
 346         struct spi_master *master;
 347         struct mpc83xx_spi *mpc83xx_spi;
 348         struct fsl_spi_platform_data *pdata;
 349         struct resource *r;
 350         u32 regval;
 351         int ret = 0;
 352
 353         /* Get resources(memory, IRQ) associated with the device */
 354         master = spi_alloc_master(&dev->dev, sizeof(struct mpc83xx_spi));
 355
 356         if (master == NULL) {
 357                 ret = -ENOMEM;
 358                 goto err;
 359         }
 360
 361         platform_set_drvdata(dev, master);
 362         pdata = dev->dev.platform_data;
 363
 364         if (pdata == NULL) {
 365                 ret = -ENODEV;
 366                 goto free_master;
 367         }
 368
 369         r = platform_get_resource(dev, IORESOURCE_MEM, 0);
 370         if (r == NULL) {
 371                 ret = -ENODEV;
 372                 goto free_master;
 373         }
 374
 375         mpc83xx_spi = spi_master_get_devdata(master);
 376         mpc83xx_spi->bitbang.master = spi_master_get(master);
 377         mpc83xx_spi->bitbang.chipselect = mpc83xx_spi_chipselect;
 378         mpc83xx_spi->bitbang.setup_transfer = mpc83xx_spi_setup_transfer;
 379         mpc83xx_spi->bitbang.txrx_bufs = mpc83xx_spi_bufs;
 380         mpc83xx_spi->sysclk = pdata->sysclk;
 381         mpc83xx_spi->activate_cs = pdata->activate_cs;
 382         mpc83xx_spi->deactivate_cs = pdata->deactivate_cs;
 383         mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u8;
 384         mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u8;
 385
 386         mpc83xx_spi->bitbang.master->setup = mpc83xx_spi_setup;
 387         init_completion(&mpc83xx_spi->done);
 388
 389         mpc83xx_spi->base = ioremap(r->start, r->end - r->start + 1);
 390         if (mpc83xx_spi->base == NULL) {
 391                 ret = -ENOMEM;
 392                 goto put_master;
 393         }
 394
 395         mpc83xx_spi->irq = platform_get_irq(dev, 0);
 396
 397         if (mpc83xx_spi->irq < 0) {
 398                 ret = -ENXIO;
 399                 goto unmap_io;
 400         }
 401
 402         /* Register for SPI Interrupt */
 403         ret = request_irq(mpc83xx_spi->irq, mpc83xx_spi_irq,
 404                           0, "mpc83xx_spi", mpc83xx_spi);
 405
 406         if (ret != 0)
 407                 goto unmap_io;
 408
 409         master->bus_num = pdata->bus_num;
 410         master->num_chipselect = pdata->max_chipselect;
 411
 412         /* SPI controller initializations */
 413         mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, 0);
 414         mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, 0);
 415         mpc83xx_spi_write_reg(&mpc83xx_spi->base->command, 0);
 416         mpc83xx_spi_write_reg(&mpc83xx_spi->base->event, 0xffffffff);
 417
 418         /* Enable SPI interface */
 419         regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
 420         mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval);
 421
 422         ret = spi_bitbang_start(&mpc83xx_spi->bitbang);
 423
 424         if (ret != 0)
 425                 goto free_irq;
 426
 427         printk(KERN_INFO
 428                "%s: MPC83xx SPI Controller driver at 0x%p (irq = %d)\n",
 429                dev->dev.bus_id, mpc83xx_spi->base, mpc83xx_spi->irq);
 430
 431         return ret;
 432
 433 free_irq:
 434         free_irq(mpc83xx_spi->irq, mpc83xx_spi);
 435 unmap_io:
 436         iounmap(mpc83xx_spi->base);
 437 put_master:
 438         spi_master_put(master);
 439 free_master:
 440         kfree(master);
 441 err:
 442         return ret;
 443 }
 444
 445 static int __devexit mpc83xx_spi_remove(struct platform_device *dev)
 446 {
 447         struct mpc83xx_spi *mpc83xx_spi;
 448         struct spi_master *master;
 449
 450         master = platform_get_drvdata(dev);
 451         mpc83xx_spi = spi_master_get_devdata(master);
 452
 453         spi_bitbang_stop(&mpc83xx_spi->bitbang);
 454         free_irq(mpc83xx_spi->irq, mpc83xx_spi);
 455         iounmap(mpc83xx_spi->base);
 456         spi_master_put(mpc83xx_spi->bitbang.master);
 457
 458         return 0;
 459 }
 460
 461 static struct platform_driver mpc83xx_spi_driver = {
 462         .probe = mpc83xx_spi_probe,
 463         .remove = __devexit_p(mpc83xx_spi_remove),
 464         .driver = {
 465                    .name = "mpc83xx_spi",
 466         },
 467 };
 468
 469 static int __init mpc83xx_spi_init(void)
 470 {
 471         return platform_driver_register(&mpc83xx_spi_driver);
 472 }
 473
 474 static void __exit mpc83xx_spi_exit(void)
 475 {
 476         platform_driver_unregister(&mpc83xx_spi_driver);
 477 }
 478
 479 module_init(mpc83xx_spi_init);
 480 module_exit(mpc83xx_spi_exit);
 481
 482 MODULE_AUTHOR("Kumar Gala");
 483 MODULE_DESCRIPTION("Simple MPC83xx SPI Driver");
 484 MODULE_LICENSE("GPL");