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alpha: fix trivial section mismatch warnings
[pv_ops_mirror.git] / drivers / usb / host / r8a66597.h
blob97c2a71ac7a125dd38a4ce245ed2606d8200dfd4
1 /*
2 * R8A66597 HCD (Host Controller Driver)
3 *
4 * Copyright (C) 2006-2007 Renesas Solutions Corp.
5 * Portions Copyright (C) 2004 Psion Teklogix (for NetBook PRO)
6 * Portions Copyright (C) 2004-2005 David Brownell
7 * Portions Copyright (C) 1999 Roman Weissgaerber
8 *
9 * Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; version 2 of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 *
24 */
25
26 #ifndef __R8A66597_H__
27 #define __R8A66597_H__
28
29 #define SYSCFG0 0x00
30 #define SYSCFG1 0x02
31 #define SYSSTS0 0x04
32 #define SYSSTS1 0x06
33 #define DVSTCTR0 0x08
34 #define DVSTCTR1 0x0A
35 #define TESTMODE 0x0C
36 #define PINCFG 0x0E
37 #define DMA0CFG 0x10
38 #define DMA1CFG 0x12
39 #define CFIFO 0x14
40 #define D0FIFO 0x18
41 #define D1FIFO 0x1C
42 #define CFIFOSEL 0x20
43 #define CFIFOCTR 0x22
44 #define CFIFOSIE 0x24
45 #define D0FIFOSEL 0x28
46 #define D0FIFOCTR 0x2A
47 #define D1FIFOSEL 0x2C
48 #define D1FIFOCTR 0x2E
49 #define INTENB0 0x30
50 #define INTENB1 0x32
51 #define INTENB2 0x34
52 #define BRDYENB 0x36
53 #define NRDYENB 0x38
54 #define BEMPENB 0x3A
55 #define SOFCFG 0x3C
56 #define INTSTS0 0x40
57 #define INTSTS1 0x42
58 #define INTSTS2 0x44
59 #define BRDYSTS 0x46
60 #define NRDYSTS 0x48
61 #define BEMPSTS 0x4A
62 #define FRMNUM 0x4C
63 #define UFRMNUM 0x4E
64 #define USBADDR 0x50
65 #define USBREQ 0x54
66 #define USBVAL 0x56
67 #define USBINDX 0x58
68 #define USBLENG 0x5A
69 #define DCPCFG 0x5C
70 #define DCPMAXP 0x5E
71 #define DCPCTR 0x60
72 #define PIPESEL 0x64
73 #define PIPECFG 0x68
74 #define PIPEBUF 0x6A
75 #define PIPEMAXP 0x6C
76 #define PIPEPERI 0x6E
77 #define PIPE1CTR 0x70
78 #define PIPE2CTR 0x72
79 #define PIPE3CTR 0x74
80 #define PIPE4CTR 0x76
81 #define PIPE5CTR 0x78
82 #define PIPE6CTR 0x7A
83 #define PIPE7CTR 0x7C
84 #define PIPE8CTR 0x7E
85 #define PIPE9CTR 0x80
86 #define PIPE1TRE 0x90
87 #define PIPE1TRN 0x92
88 #define PIPE2TRE 0x94
89 #define PIPE2TRN 0x96
90 #define PIPE3TRE 0x98
91 #define PIPE3TRN 0x9A
92 #define PIPE4TRE 0x9C
93 #define PIPE4TRN 0x9E
94 #define PIPE5TRE 0xA0
95 #define PIPE5TRN 0xA2
96 #define DEVADD0 0xD0
97 #define DEVADD1 0xD2
98 #define DEVADD2 0xD4
99 #define DEVADD3 0xD6
100 #define DEVADD4 0xD8
101 #define DEVADD5 0xDA
102 #define DEVADD6 0xDC
103 #define DEVADD7 0xDE
104 #define DEVADD8 0xE0
105 #define DEVADD9 0xE2
106 #define DEVADDA 0xE4
107
108 /* System Configuration Control Register */
109 #define XTAL 0xC000 /* b15-14: Crystal selection */
110 #define XTAL48 0x8000 /* 48MHz */
111 #define XTAL24 0x4000 /* 24MHz */
112 #define XTAL12 0x0000 /* 12MHz */
113 #define XCKE 0x2000 /* b13: External clock enable */
114 #define PLLC 0x0800 /* b11: PLL control */
115 #define SCKE 0x0400 /* b10: USB clock enable */
116 #define PCSDIS 0x0200 /* b9: not CS wakeup */
117 #define LPSME 0x0100 /* b8: Low power sleep mode */
118 #define HSE 0x0080 /* b7: Hi-speed enable */
119 #define DCFM 0x0040 /* b6: Controller function select */
120 #define DRPD 0x0020 /* b5: D+/- pull down control */
121 #define DPRPU 0x0010 /* b4: D+ pull up control */
122 #define USBE 0x0001 /* b0: USB module operation enable */
123
124 /* System Configuration Status Register */
125 #define OVCBIT 0x8000 /* b15-14: Over-current bit */
126 #define OVCMON 0xC000 /* b15-14: Over-current monitor */
127 #define SOFEA 0x0020 /* b5: SOF monitor */
128 #define IDMON 0x0004 /* b3: ID-pin monitor */
129 #define LNST 0x0003 /* b1-0: D+, D- line status */
130 #define SE1 0x0003 /* SE1 */
131 #define FS_KSTS 0x0002 /* Full-Speed K State */
132 #define FS_JSTS 0x0001 /* Full-Speed J State */
133 #define LS_JSTS 0x0002 /* Low-Speed J State */
134 #define LS_KSTS 0x0001 /* Low-Speed K State */
135 #define SE0 0x0000 /* SE0 */
136
137 /* Device State Control Register */
138 #define EXTLP0 0x0400 /* b10: External port */
139 #define VBOUT 0x0200 /* b9: VBUS output */
140 #define WKUP 0x0100 /* b8: Remote wakeup */
141 #define RWUPE 0x0080 /* b7: Remote wakeup sense */
142 #define USBRST 0x0040 /* b6: USB reset enable */
143 #define RESUME 0x0020 /* b5: Resume enable */
144 #define UACT 0x0010 /* b4: USB bus enable */
145 #define RHST 0x0007 /* b1-0: Reset handshake status */
146 #define HSPROC 0x0004 /* HS handshake is processing */
147 #define HSMODE 0x0003 /* Hi-Speed mode */
148 #define FSMODE 0x0002 /* Full-Speed mode */
149 #define LSMODE 0x0001 /* Low-Speed mode */
150 #define UNDECID 0x0000 /* Undecided */
151
152 /* Test Mode Register */
153 #define UTST 0x000F /* b3-0: Test select */
154 #define H_TST_PACKET 0x000C /* HOST TEST Packet */
155 #define H_TST_SE0_NAK 0x000B /* HOST TEST SE0 NAK */
156 #define H_TST_K 0x000A /* HOST TEST K */
157 #define H_TST_J 0x0009 /* HOST TEST J */
158 #define H_TST_NORMAL 0x0000 /* HOST Normal Mode */
159 #define P_TST_PACKET 0x0004 /* PERI TEST Packet */
160 #define P_TST_SE0_NAK 0x0003 /* PERI TEST SE0 NAK */
161 #define P_TST_K 0x0002 /* PERI TEST K */
162 #define P_TST_J 0x0001 /* PERI TEST J */
163 #define P_TST_NORMAL 0x0000 /* PERI Normal Mode */
164
165 /* Data Pin Configuration Register */
166 #define LDRV 0x8000 /* b15: Drive Current Adjust */
167 #define VIF1 0x0000 /* VIF = 1.8V */
168 #define VIF3 0x8000 /* VIF = 3.3V */
169 #define INTA 0x0001 /* b1: USB INT-pin active */
170
171 /* DMAx Pin Configuration Register */
172 #define DREQA 0x4000 /* b14: Dreq active select */
173 #define BURST 0x2000 /* b13: Burst mode */
174 #define DACKA 0x0400 /* b10: Dack active select */
175 #define DFORM 0x0380 /* b9-7: DMA mode select */
176 #define CPU_ADR_RD_WR 0x0000 /* Address + RD/WR mode (CPU bus) */
177 #define CPU_DACK_RD_WR 0x0100 /* DACK + RD/WR mode (CPU bus) */
178 #define CPU_DACK_ONLY 0x0180 /* DACK only mode (CPU bus) */
179 #define SPLIT_DACK_ONLY 0x0200 /* DACK only mode (SPLIT bus) */
180 #define DENDA 0x0040 /* b6: Dend active select */
181 #define PKTM 0x0020 /* b5: Packet mode */
182 #define DENDE 0x0010 /* b4: Dend enable */
183 #define OBUS 0x0004 /* b2: OUTbus mode */
184
185 /* CFIFO/DxFIFO Port Select Register */
186 #define RCNT 0x8000 /* b15: Read count mode */
187 #define REW 0x4000 /* b14: Buffer rewind */
188 #define DCLRM 0x2000 /* b13: DMA buffer clear mode */
189 #define DREQE 0x1000 /* b12: DREQ output enable */
190 #define MBW 0x0400 /* b10: Maximum bit width for FIFO access */
191 #define MBW_8 0x0000 /* 8bit */
192 #define MBW_16 0x0400 /* 16bit */
193 #define BIGEND 0x0100 /* b8: Big endian mode */
194 #define BYTE_LITTLE 0x0000 /* little dendian */
195 #define BYTE_BIG 0x0100 /* big endifan */
196 #define ISEL 0x0020 /* b5: DCP FIFO port direction select */
197 #define CURPIPE 0x000F /* b2-0: PIPE select */
198
199 /* CFIFO/DxFIFO Port Control Register */
200 #define BVAL 0x8000 /* b15: Buffer valid flag */
201 #define BCLR 0x4000 /* b14: Buffer clear */
202 #define FRDY 0x2000 /* b13: FIFO ready */
203 #define DTLN 0x0FFF /* b11-0: FIFO received data length */
204
205 /* Interrupt Enable Register 0 */
206 #define VBSE 0x8000 /* b15: VBUS interrupt */
207 #define RSME 0x4000 /* b14: Resume interrupt */
208 #define SOFE 0x2000 /* b13: Frame update interrupt */
209 #define DVSE 0x1000 /* b12: Device state transition interrupt */
210 #define CTRE 0x0800 /* b11: Control transfer stage transition interrupt */
211 #define BEMPE 0x0400 /* b10: Buffer empty interrupt */
212 #define NRDYE 0x0200 /* b9: Buffer not ready interrupt */
213 #define BRDYE 0x0100 /* b8: Buffer ready interrupt */
214
215 /* Interrupt Enable Register 1 */
216 #define OVRCRE 0x8000 /* b15: Over-current interrupt */
217 #define BCHGE 0x4000 /* b14: USB us chenge interrupt */
218 #define DTCHE 0x1000 /* b12: Detach sense interrupt */
219 #define ATTCHE 0x0800 /* b11: Attach sense interrupt */
220 #define EOFERRE 0x0040 /* b6: EOF error interrupt */
221 #define SIGNE 0x0020 /* b5: SETUP IGNORE interrupt */
222 #define SACKE 0x0010 /* b4: SETUP ACK interrupt */
223
224 /* BRDY Interrupt Enable/Status Register */
225 #define BRDY9 0x0200 /* b9: PIPE9 */
226 #define BRDY8 0x0100 /* b8: PIPE8 */
227 #define BRDY7 0x0080 /* b7: PIPE7 */
228 #define BRDY6 0x0040 /* b6: PIPE6 */
229 #define BRDY5 0x0020 /* b5: PIPE5 */
230 #define BRDY4 0x0010 /* b4: PIPE4 */
231 #define BRDY3 0x0008 /* b3: PIPE3 */
232 #define BRDY2 0x0004 /* b2: PIPE2 */
233 #define BRDY1 0x0002 /* b1: PIPE1 */
234 #define BRDY0 0x0001 /* b1: PIPE0 */
235
236 /* NRDY Interrupt Enable/Status Register */
237 #define NRDY9 0x0200 /* b9: PIPE9 */
238 #define NRDY8 0x0100 /* b8: PIPE8 */
239 #define NRDY7 0x0080 /* b7: PIPE7 */
240 #define NRDY6 0x0040 /* b6: PIPE6 */
241 #define NRDY5 0x0020 /* b5: PIPE5 */
242 #define NRDY4 0x0010 /* b4: PIPE4 */
243 #define NRDY3 0x0008 /* b3: PIPE3 */
244 #define NRDY2 0x0004 /* b2: PIPE2 */
245 #define NRDY1 0x0002 /* b1: PIPE1 */
246 #define NRDY0 0x0001 /* b1: PIPE0 */
247
248 /* BEMP Interrupt Enable/Status Register */
249 #define BEMP9 0x0200 /* b9: PIPE9 */
250 #define BEMP8 0x0100 /* b8: PIPE8 */
251 #define BEMP7 0x0080 /* b7: PIPE7 */
252 #define BEMP6 0x0040 /* b6: PIPE6 */
253 #define BEMP5 0x0020 /* b5: PIPE5 */
254 #define BEMP4 0x0010 /* b4: PIPE4 */
255 #define BEMP3 0x0008 /* b3: PIPE3 */
256 #define BEMP2 0x0004 /* b2: PIPE2 */
257 #define BEMP1 0x0002 /* b1: PIPE1 */
258 #define BEMP0 0x0001 /* b0: PIPE0 */
259
260 /* SOF Pin Configuration Register */
261 #define TRNENSEL 0x0100 /* b8: Select transaction enable period */
262 #define BRDYM 0x0040 /* b6: BRDY clear timing */
263 #define INTL 0x0020 /* b5: Interrupt sense select */
264 #define EDGESTS 0x0010 /* b4: */
265 #define SOFMODE 0x000C /* b3-2: SOF pin select */
266 #define SOF_125US 0x0008 /* SOF OUT 125us Frame Signal */
267 #define SOF_1MS 0x0004 /* SOF OUT 1ms Frame Signal */
268 #define SOF_DISABLE 0x0000 /* SOF OUT Disable */
269
270 /* Interrupt Status Register 0 */
271 #define VBINT 0x8000 /* b15: VBUS interrupt */
272 #define RESM 0x4000 /* b14: Resume interrupt */
273 #define SOFR 0x2000 /* b13: SOF frame update interrupt */
274 #define DVST 0x1000 /* b12: Device state transition interrupt */
275 #define CTRT 0x0800 /* b11: Control transfer stage transition interrupt */
276 #define BEMP 0x0400 /* b10: Buffer empty interrupt */
277 #define NRDY 0x0200 /* b9: Buffer not ready interrupt */
278 #define BRDY 0x0100 /* b8: Buffer ready interrupt */
279 #define VBSTS 0x0080 /* b7: VBUS input port */
280 #define DVSQ 0x0070 /* b6-4: Device state */
281 #define DS_SPD_CNFG 0x0070 /* Suspend Configured */
282 #define DS_SPD_ADDR 0x0060 /* Suspend Address */
283 #define DS_SPD_DFLT 0x0050 /* Suspend Default */
284 #define DS_SPD_POWR 0x0040 /* Suspend Powered */
285 #define DS_SUSP 0x0040 /* Suspend */
286 #define DS_CNFG 0x0030 /* Configured */
287 #define DS_ADDS 0x0020 /* Address */
288 #define DS_DFLT 0x0010 /* Default */
289 #define DS_POWR 0x0000 /* Powered */
290 #define DVSQS 0x0030 /* b5-4: Device state */
291 #define VALID 0x0008 /* b3: Setup packet detected flag */
292 #define CTSQ 0x0007 /* b2-0: Control transfer stage */
293 #define CS_SQER 0x0006 /* Sequence error */
294 #define CS_WRND 0x0005 /* Control write nodata status stage */
295 #define CS_WRSS 0x0004 /* Control write status stage */
296 #define CS_WRDS 0x0003 /* Control write data stage */
297 #define CS_RDSS 0x0002 /* Control read status stage */
298 #define CS_RDDS 0x0001 /* Control read data stage */
299 #define CS_IDST 0x0000 /* Idle or setup stage */
300
301 /* Interrupt Status Register 1 */
302 #define OVRCR 0x8000 /* b15: Over-current interrupt */
303 #define BCHG 0x4000 /* b14: USB bus chenge interrupt */
304 #define DTCH 0x1000 /* b12: Detach sense interrupt */
305 #define ATTCH 0x0800 /* b11: Attach sense interrupt */
306 #define EOFERR 0x0040 /* b6: EOF-error interrupt */
307 #define SIGN 0x0020 /* b5: Setup ignore interrupt */
308 #define SACK 0x0010 /* b4: Setup acknowledge interrupt */
309
310 /* Frame Number Register */
311 #define OVRN 0x8000 /* b15: Overrun error */
312 #define CRCE 0x4000 /* b14: Received data error */
313 #define FRNM 0x07FF /* b10-0: Frame number */
314
315 /* Micro Frame Number Register */
316 #define UFRNM 0x0007 /* b2-0: Micro frame number */
317
318 /* USB Address / Low Power Status Recovery Register */
319 //#define USBADDR 0x007F /* b6-0: USB address */
320
321 /* Default Control Pipe Maxpacket Size Register */
322 /* Pipe Maxpacket Size Register */
323 #define DEVSEL 0xF000 /* b15-14: Device address select */
324 #define MAXP 0x007F /* b6-0: Maxpacket size of default control pipe */
325
326 /* Default Control Pipe Control Register */
327 #define BSTS 0x8000 /* b15: Buffer status */
328 #define SUREQ 0x4000 /* b14: Send USB request */
329 #define CSCLR 0x2000 /* b13: complete-split status clear */
330 #define CSSTS 0x1000 /* b12: complete-split status */
331 #define SUREQCLR 0x0800 /* b11: stop setup request */
332 #define SQCLR 0x0100 /* b8: Sequence toggle bit clear */
333 #define SQSET 0x0080 /* b7: Sequence toggle bit set */
334 #define SQMON 0x0040 /* b6: Sequence toggle bit monitor */
335 #define PBUSY 0x0020 /* b5: pipe busy */
336 #define PINGE 0x0010 /* b4: ping enable */
337 #define CCPL 0x0004 /* b2: Enable control transfer complete */
338 #define PID 0x0003 /* b1-0: Response PID */
339 #define PID_STALL11 0x0003 /* STALL */
340 #define PID_STALL 0x0002 /* STALL */
341 #define PID_BUF 0x0001 /* BUF */
342 #define PID_NAK 0x0000 /* NAK */
343
344 /* Pipe Window Select Register */
345 #define PIPENM 0x0007 /* b2-0: Pipe select */
346
347 /* Pipe Configuration Register */
348 #define R8A66597_TYP 0xC000 /* b15-14: Transfer type */
349 #define R8A66597_ISO 0xC000 /* Isochronous */
350 #define R8A66597_INT 0x8000 /* Interrupt */
351 #define R8A66597_BULK 0x4000 /* Bulk */
352 #define R8A66597_BFRE 0x0400 /* b10: Buffer ready interrupt mode select */
353 #define R8A66597_DBLB 0x0200 /* b9: Double buffer mode select */
354 #define R8A66597_CNTMD 0x0100 /* b8: Continuous transfer mode select */
355 #define R8A66597_SHTNAK 0x0080 /* b7: Transfer end NAK */
356 #define R8A66597_DIR 0x0010 /* b4: Transfer direction select */
357 #define R8A66597_EPNUM 0x000F /* b3-0: Eendpoint number select */
358
359 /* Pipe Buffer Configuration Register */
360 #define BUFSIZE 0x7C00 /* b14-10: Pipe buffer size */
361 #define BUFNMB 0x007F /* b6-0: Pipe buffer number */
362 #define PIPE0BUF 256
363 #define PIPExBUF 64
364
365 /* Pipe Maxpacket Size Register */
366 #define MXPS 0x07FF /* b10-0: Maxpacket size */
367
368 /* Pipe Cycle Configuration Register */
369 #define IFIS 0x1000 /* b12: Isochronous in-buffer flush mode select */
370 #define IITV 0x0007 /* b2-0: Isochronous interval */
371
372 /* Pipex Control Register */
373 #define BSTS 0x8000 /* b15: Buffer status */
374 #define INBUFM 0x4000 /* b14: IN buffer monitor (Only for PIPE1 to 5) */
375 #define CSCLR 0x2000 /* b13: complete-split status clear */
376 #define CSSTS 0x1000 /* b12: complete-split status */
377 #define ATREPM 0x0400 /* b10: Auto repeat mode */
378 #define ACLRM 0x0200 /* b9: Out buffer auto clear mode */
379 #define SQCLR 0x0100 /* b8: Sequence toggle bit clear */
380 #define SQSET 0x0080 /* b7: Sequence toggle bit set */
381 #define SQMON 0x0040 /* b6: Sequence toggle bit monitor */
382 #define PBUSY 0x0020 /* b5: pipe busy */
383 #define PID 0x0003 /* b1-0: Response PID */
384
385 /* PIPExTRE */
386 #define TRENB 0x0200 /* b9: Transaction counter enable */
387 #define TRCLR 0x0100 /* b8: Transaction counter clear */
388
389 /* PIPExTRN */
390 #define TRNCNT 0xFFFF /* b15-0: Transaction counter */
391
392 /* DEVADDx */
393 #define UPPHUB 0x7800
394 #define HUBPORT 0x0700
395 #define USBSPD 0x00C0
396 #define RTPORT 0x0001
397
398 #define R8A66597_MAX_NUM_PIPE 10
399 #define R8A66597_BUF_BSIZE 8
400 #define R8A66597_MAX_DEVICE 10
401 #define R8A66597_MAX_ROOT_HUB 2
402 #define R8A66597_MAX_SAMPLING 10
403 #define R8A66597_MAX_DMA_CHANNEL 2
404 #define R8A66597_PIPE_NO_DMA R8A66597_MAX_DMA_CHANNEL
405 #define check_bulk_or_isoc(pipenum) ((pipenum >= 1 && pipenum <= 5))
406 #define check_interrupt(pipenum) ((pipenum >= 6 && pipenum <= 9))
407 #define make_devsel(addr) (addr << 12)
408
409 struct r8a66597_pipe_info {
410 u16 pipenum;
411 u16 address; /* R8A66597 HCD usb addres */
412 u16 epnum;
413 u16 maxpacket;
414 u16 type;
415 u16 bufnum;
416 u16 buf_bsize;
417 u16 interval;
418 u16 dir_in;
419 };
420
421 struct r8a66597_pipe {
422 struct r8a66597_pipe_info info;
423
424 unsigned long fifoaddr;
425 unsigned long fifosel;
426 unsigned long fifoctr;
427 unsigned long pipectr;
428 unsigned long pipetre;
429 unsigned long pipetrn;
430 };
431
432 struct r8a66597_td {
433 struct r8a66597_pipe *pipe;
434 struct urb *urb;
435 struct list_head queue;
436
437 u16 type;
438 u16 pipenum;
439 int iso_cnt;
440
441 u16 address; /* R8A66597's USB address */
442 u16 maxpacket;
443
444 unsigned zero_packet:1;
445 unsigned short_packet:1;
446 unsigned set_address:1;
447 };
448
449 struct r8a66597_device {
450 u16 address; /* R8A66597's USB address */
451 u16 hub_port;
452 u16 root_port;
453
454 unsigned short ep_in_toggle;
455 unsigned short ep_out_toggle;
456 unsigned char pipe_cnt[R8A66597_MAX_NUM_PIPE];
457 unsigned char dma_map;
458
459 enum usb_device_state state;
460
461 struct usb_device *udev;
462 int usb_address;
463 struct list_head device_list;
464 };
465
466 struct r8a66597_root_hub {
467 u32 port;
468 u16 old_syssts;
469 int scount;
470
471 struct r8a66597_device *dev;
472 };
473
474 struct r8a66597 {
475 spinlock_t lock;
476 unsigned long reg;
477
478 struct r8a66597_device device0;
479 struct r8a66597_root_hub root_hub[R8A66597_MAX_ROOT_HUB];
480 struct list_head pipe_queue[R8A66597_MAX_NUM_PIPE];
481
482 struct timer_list rh_timer;
483 struct timer_list td_timer[R8A66597_MAX_NUM_PIPE];
484
485 unsigned short address_map;
486 unsigned short timeout_map;
487 unsigned char pipe_cnt[R8A66597_MAX_NUM_PIPE];
488 unsigned char dma_map;
489
490 struct list_head child_device;
491 unsigned long child_connect_map[4];
492 };
493
494 static inline struct r8a66597 *hcd_to_r8a66597(struct usb_hcd *hcd)
495 {
496 return (struct r8a66597 *)(hcd->hcd_priv);
497 }
498
499 static inline struct usb_hcd *r8a66597_to_hcd(struct r8a66597 *r8a66597)
500 {
501 return container_of((void *)r8a66597, struct usb_hcd, hcd_priv);
502 }
503
504 static inline struct r8a66597_td *r8a66597_get_td(struct r8a66597 *r8a66597,
505 u16 pipenum)
506 {
507 if (unlikely(list_empty(&r8a66597->pipe_queue[pipenum])))
508 return NULL;
509
510 return list_entry(r8a66597->pipe_queue[pipenum].next,
511 struct r8a66597_td, queue);
512 }
513
514 static inline struct urb *r8a66597_get_urb(struct r8a66597 *r8a66597,
515 u16 pipenum)
516 {
517 struct r8a66597_td *td;
518
519 td = r8a66597_get_td(r8a66597, pipenum);
520 return (td ? td->urb : NULL);
521 }
522
523 static inline u16 r8a66597_read(struct r8a66597 *r8a66597, unsigned long offset)
524 {
525 return inw(r8a66597->reg + offset);
526 }
527
528 static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
529 unsigned long offset, u16 *buf,
530 int len)
531 {
532 len = (len + 1) / 2;
533 insw(r8a66597->reg + offset, buf, len);
534 }
535
536 static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val,
537 unsigned long offset)
538 {
539 outw(val, r8a66597->reg + offset);
540 }
541
542 static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
543 unsigned long offset, u16 *buf,
544 int len)
545 {
546 unsigned long fifoaddr = r8a66597->reg + offset;
547 int odd = len & 0x0001;
548
549 len = len / 2;
550 outsw(fifoaddr, buf, len);
551 if (unlikely(odd)) {
552 buf = &buf[len];
553 outb((unsigned char)*buf, fifoaddr);
554 }
555 }
556
557 static inline void r8a66597_mdfy(struct r8a66597 *r8a66597,
558 u16 val, u16 pat, unsigned long offset)
559 {
560 u16 tmp;
561 tmp = r8a66597_read(r8a66597, offset);
562 tmp = tmp & (~pat);
563 tmp = tmp | val;
564 r8a66597_write(r8a66597, tmp, offset);
565 }
566
567 #define r8a66597_bclr(r8a66597, val, offset) \
568 r8a66597_mdfy(r8a66597, 0, val, offset)
569 #define r8a66597_bset(r8a66597, val, offset) \
570 r8a66597_mdfy(r8a66597, val, 0, offset)
571
572 static inline unsigned long get_syscfg_reg(int port)
573 {
574 return port == 0 ? SYSCFG0 : SYSCFG1;
575 }
576
577 static inline unsigned long get_syssts_reg(int port)
578 {
579 return port == 0 ? SYSSTS0 : SYSSTS1;
580 }
581
582 static inline unsigned long get_dvstctr_reg(int port)
583 {
584 return port == 0 ? DVSTCTR0 : DVSTCTR1;
585 }
586
587 static inline unsigned long get_intenb_reg(int port)
588 {
589 return port == 0 ? INTENB1 : INTENB2;
590 }
591
592 static inline unsigned long get_intsts_reg(int port)
593 {
594 return port == 0 ? INTSTS1 : INTSTS2;
595 }
596
597 static inline u16 get_rh_usb_speed(struct r8a66597 *r8a66597, int port)
598 {
599 unsigned long dvstctr_reg = get_dvstctr_reg(port);
600
601 return r8a66597_read(r8a66597, dvstctr_reg) & RHST;
602 }
603
604 static inline void r8a66597_port_power(struct r8a66597 *r8a66597, int port,
605 int power)
606 {
607 unsigned long dvstctr_reg = get_dvstctr_reg(port);
608
609 if (power)
610 r8a66597_bset(r8a66597, VBOUT, dvstctr_reg);
611 else
612 r8a66597_bclr(r8a66597, VBOUT, dvstctr_reg);
613 }
614
615 #define get_pipectr_addr(pipenum) (PIPE1CTR + (pipenum - 1) * 2)
616 #define get_pipetre_addr(pipenum) (PIPE1TRE + (pipenum - 1) * 4)
617 #define get_pipetrn_addr(pipenum) (PIPE1TRN + (pipenum - 1) * 4)
618 #define get_devadd_addr(address) (DEVADD0 + address * 2)
619
620 #define enable_irq_ready(r8a66597, pipenum) \
621 enable_pipe_irq(r8a66597, pipenum, BRDYENB)
622 #define disable_irq_ready(r8a66597, pipenum) \
623 disable_pipe_irq(r8a66597, pipenum, BRDYENB)
624 #define enable_irq_empty(r8a66597, pipenum) \
625 enable_pipe_irq(r8a66597, pipenum, BEMPENB)
626 #define disable_irq_empty(r8a66597, pipenum) \
627 disable_pipe_irq(r8a66597, pipenum, BEMPENB)
628 #define enable_irq_nrdy(r8a66597, pipenum) \
629 enable_pipe_irq(r8a66597, pipenum, NRDYENB)
630 #define disable_irq_nrdy(r8a66597, pipenum) \
631 disable_pipe_irq(r8a66597, pipenum, NRDYENB)
632
633 #endif /* __R8A66597_H__ */
634
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