alpha: fix trivial section mismatch warnings
[pv_ops_mirror.git] / drivers / usb / host / uhci-q.c
blob4aed305982ec3f8b1c9e90cce2b7b1e0885fe5c4
1 /*
2 * Universal Host Controller Interface driver for USB.
4 * Maintainer: Alan Stern <stern@rowland.harvard.edu>
6 * (C) Copyright 1999 Linus Torvalds
7 * (C) Copyright 1999-2002 Johannes Erdfelt, johannes@erdfelt.com
8 * (C) Copyright 1999 Randy Dunlap
9 * (C) Copyright 1999 Georg Acher, acher@in.tum.de
10 * (C) Copyright 1999 Deti Fliegl, deti@fliegl.de
11 * (C) Copyright 1999 Thomas Sailer, sailer@ife.ee.ethz.ch
12 * (C) Copyright 1999 Roman Weissgaerber, weissg@vienna.at
13 * (C) Copyright 2000 Yggdrasil Computing, Inc. (port of new PCI interface
14 * support from usb-ohci.c by Adam Richter, adam@yggdrasil.com).
15 * (C) Copyright 1999 Gregory P. Smith (from usb-ohci.c)
16 * (C) Copyright 2004-2007 Alan Stern, stern@rowland.harvard.edu
21 * Technically, updating td->status here is a race, but it's not really a
22 * problem. The worst that can happen is that we set the IOC bit again
23 * generating a spurious interrupt. We could fix this by creating another
24 * QH and leaving the IOC bit always set, but then we would have to play
25 * games with the FSBR code to make sure we get the correct order in all
26 * the cases. I don't think it's worth the effort
28 static void uhci_set_next_interrupt(struct uhci_hcd *uhci)
30 if (uhci->is_stopped)
31 mod_timer(&uhci_to_hcd(uhci)->rh_timer, jiffies);
32 uhci->term_td->status |= cpu_to_le32(TD_CTRL_IOC);
35 static inline void uhci_clear_next_interrupt(struct uhci_hcd *uhci)
37 uhci->term_td->status &= ~cpu_to_le32(TD_CTRL_IOC);
42 * Full-Speed Bandwidth Reclamation (FSBR).
43 * We turn on FSBR whenever a queue that wants it is advancing,
44 * and leave it on for a short time thereafter.
46 static void uhci_fsbr_on(struct uhci_hcd *uhci)
48 struct uhci_qh *lqh;
50 /* The terminating skeleton QH always points back to the first
51 * FSBR QH. Make the last async QH point to the terminating
52 * skeleton QH. */
53 uhci->fsbr_is_on = 1;
54 lqh = list_entry(uhci->skel_async_qh->node.prev,
55 struct uhci_qh, node);
56 lqh->link = LINK_TO_QH(uhci->skel_term_qh);
59 static void uhci_fsbr_off(struct uhci_hcd *uhci)
61 struct uhci_qh *lqh;
63 /* Remove the link from the last async QH to the terminating
64 * skeleton QH. */
65 uhci->fsbr_is_on = 0;
66 lqh = list_entry(uhci->skel_async_qh->node.prev,
67 struct uhci_qh, node);
68 lqh->link = UHCI_PTR_TERM;
71 static void uhci_add_fsbr(struct uhci_hcd *uhci, struct urb *urb)
73 struct urb_priv *urbp = urb->hcpriv;
75 if (!(urb->transfer_flags & URB_NO_FSBR))
76 urbp->fsbr = 1;
79 static void uhci_urbp_wants_fsbr(struct uhci_hcd *uhci, struct urb_priv *urbp)
81 if (urbp->fsbr) {
82 uhci->fsbr_is_wanted = 1;
83 if (!uhci->fsbr_is_on)
84 uhci_fsbr_on(uhci);
85 else if (uhci->fsbr_expiring) {
86 uhci->fsbr_expiring = 0;
87 del_timer(&uhci->fsbr_timer);
92 static void uhci_fsbr_timeout(unsigned long _uhci)
94 struct uhci_hcd *uhci = (struct uhci_hcd *) _uhci;
95 unsigned long flags;
97 spin_lock_irqsave(&uhci->lock, flags);
98 if (uhci->fsbr_expiring) {
99 uhci->fsbr_expiring = 0;
100 uhci_fsbr_off(uhci);
102 spin_unlock_irqrestore(&uhci->lock, flags);
106 static struct uhci_td *uhci_alloc_td(struct uhci_hcd *uhci)
108 dma_addr_t dma_handle;
109 struct uhci_td *td;
111 td = dma_pool_alloc(uhci->td_pool, GFP_ATOMIC, &dma_handle);
112 if (!td)
113 return NULL;
115 td->dma_handle = dma_handle;
116 td->frame = -1;
118 INIT_LIST_HEAD(&td->list);
119 INIT_LIST_HEAD(&td->fl_list);
121 return td;
124 static void uhci_free_td(struct uhci_hcd *uhci, struct uhci_td *td)
126 if (!list_empty(&td->list)) {
127 dev_warn(uhci_dev(uhci), "td %p still in list!\n", td);
128 WARN_ON(1);
130 if (!list_empty(&td->fl_list)) {
131 dev_warn(uhci_dev(uhci), "td %p still in fl_list!\n", td);
132 WARN_ON(1);
135 dma_pool_free(uhci->td_pool, td, td->dma_handle);
138 static inline void uhci_fill_td(struct uhci_td *td, u32 status,
139 u32 token, u32 buffer)
141 td->status = cpu_to_le32(status);
142 td->token = cpu_to_le32(token);
143 td->buffer = cpu_to_le32(buffer);
146 static void uhci_add_td_to_urbp(struct uhci_td *td, struct urb_priv *urbp)
148 list_add_tail(&td->list, &urbp->td_list);
151 static void uhci_remove_td_from_urbp(struct uhci_td *td)
153 list_del_init(&td->list);
157 * We insert Isochronous URBs directly into the frame list at the beginning
159 static inline void uhci_insert_td_in_frame_list(struct uhci_hcd *uhci,
160 struct uhci_td *td, unsigned framenum)
162 framenum &= (UHCI_NUMFRAMES - 1);
164 td->frame = framenum;
166 /* Is there a TD already mapped there? */
167 if (uhci->frame_cpu[framenum]) {
168 struct uhci_td *ftd, *ltd;
170 ftd = uhci->frame_cpu[framenum];
171 ltd = list_entry(ftd->fl_list.prev, struct uhci_td, fl_list);
173 list_add_tail(&td->fl_list, &ftd->fl_list);
175 td->link = ltd->link;
176 wmb();
177 ltd->link = LINK_TO_TD(td);
178 } else {
179 td->link = uhci->frame[framenum];
180 wmb();
181 uhci->frame[framenum] = LINK_TO_TD(td);
182 uhci->frame_cpu[framenum] = td;
186 static inline void uhci_remove_td_from_frame_list(struct uhci_hcd *uhci,
187 struct uhci_td *td)
189 /* If it's not inserted, don't remove it */
190 if (td->frame == -1) {
191 WARN_ON(!list_empty(&td->fl_list));
192 return;
195 if (uhci->frame_cpu[td->frame] == td) {
196 if (list_empty(&td->fl_list)) {
197 uhci->frame[td->frame] = td->link;
198 uhci->frame_cpu[td->frame] = NULL;
199 } else {
200 struct uhci_td *ntd;
202 ntd = list_entry(td->fl_list.next, struct uhci_td, fl_list);
203 uhci->frame[td->frame] = LINK_TO_TD(ntd);
204 uhci->frame_cpu[td->frame] = ntd;
206 } else {
207 struct uhci_td *ptd;
209 ptd = list_entry(td->fl_list.prev, struct uhci_td, fl_list);
210 ptd->link = td->link;
213 list_del_init(&td->fl_list);
214 td->frame = -1;
217 static inline void uhci_remove_tds_from_frame(struct uhci_hcd *uhci,
218 unsigned int framenum)
220 struct uhci_td *ftd, *ltd;
222 framenum &= (UHCI_NUMFRAMES - 1);
224 ftd = uhci->frame_cpu[framenum];
225 if (ftd) {
226 ltd = list_entry(ftd->fl_list.prev, struct uhci_td, fl_list);
227 uhci->frame[framenum] = ltd->link;
228 uhci->frame_cpu[framenum] = NULL;
230 while (!list_empty(&ftd->fl_list))
231 list_del_init(ftd->fl_list.prev);
236 * Remove all the TDs for an Isochronous URB from the frame list
238 static void uhci_unlink_isochronous_tds(struct uhci_hcd *uhci, struct urb *urb)
240 struct urb_priv *urbp = (struct urb_priv *) urb->hcpriv;
241 struct uhci_td *td;
243 list_for_each_entry(td, &urbp->td_list, list)
244 uhci_remove_td_from_frame_list(uhci, td);
247 static struct uhci_qh *uhci_alloc_qh(struct uhci_hcd *uhci,
248 struct usb_device *udev, struct usb_host_endpoint *hep)
250 dma_addr_t dma_handle;
251 struct uhci_qh *qh;
253 qh = dma_pool_alloc(uhci->qh_pool, GFP_ATOMIC, &dma_handle);
254 if (!qh)
255 return NULL;
257 memset(qh, 0, sizeof(*qh));
258 qh->dma_handle = dma_handle;
260 qh->element = UHCI_PTR_TERM;
261 qh->link = UHCI_PTR_TERM;
263 INIT_LIST_HEAD(&qh->queue);
264 INIT_LIST_HEAD(&qh->node);
266 if (udev) { /* Normal QH */
267 qh->type = hep->desc.bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
268 if (qh->type != USB_ENDPOINT_XFER_ISOC) {
269 qh->dummy_td = uhci_alloc_td(uhci);
270 if (!qh->dummy_td) {
271 dma_pool_free(uhci->qh_pool, qh, dma_handle);
272 return NULL;
275 qh->state = QH_STATE_IDLE;
276 qh->hep = hep;
277 qh->udev = udev;
278 hep->hcpriv = qh;
280 if (qh->type == USB_ENDPOINT_XFER_INT ||
281 qh->type == USB_ENDPOINT_XFER_ISOC)
282 qh->load = usb_calc_bus_time(udev->speed,
283 usb_endpoint_dir_in(&hep->desc),
284 qh->type == USB_ENDPOINT_XFER_ISOC,
285 le16_to_cpu(hep->desc.wMaxPacketSize))
286 / 1000 + 1;
288 } else { /* Skeleton QH */
289 qh->state = QH_STATE_ACTIVE;
290 qh->type = -1;
292 return qh;
295 static void uhci_free_qh(struct uhci_hcd *uhci, struct uhci_qh *qh)
297 WARN_ON(qh->state != QH_STATE_IDLE && qh->udev);
298 if (!list_empty(&qh->queue)) {
299 dev_warn(uhci_dev(uhci), "qh %p list not empty!\n", qh);
300 WARN_ON(1);
303 list_del(&qh->node);
304 if (qh->udev) {
305 qh->hep->hcpriv = NULL;
306 if (qh->dummy_td)
307 uhci_free_td(uhci, qh->dummy_td);
309 dma_pool_free(uhci->qh_pool, qh, qh->dma_handle);
313 * When a queue is stopped and a dequeued URB is given back, adjust
314 * the previous TD link (if the URB isn't first on the queue) or
315 * save its toggle value (if it is first and is currently executing).
317 * Returns 0 if the URB should not yet be given back, 1 otherwise.
319 static int uhci_cleanup_queue(struct uhci_hcd *uhci, struct uhci_qh *qh,
320 struct urb *urb)
322 struct urb_priv *urbp = urb->hcpriv;
323 struct uhci_td *td;
324 int ret = 1;
326 /* Isochronous pipes don't use toggles and their TD link pointers
327 * get adjusted during uhci_urb_dequeue(). But since their queues
328 * cannot truly be stopped, we have to watch out for dequeues
329 * occurring after the nominal unlink frame. */
330 if (qh->type == USB_ENDPOINT_XFER_ISOC) {
331 ret = (uhci->frame_number + uhci->is_stopped !=
332 qh->unlink_frame);
333 goto done;
336 /* If the URB isn't first on its queue, adjust the link pointer
337 * of the last TD in the previous URB. The toggle doesn't need
338 * to be saved since this URB can't be executing yet. */
339 if (qh->queue.next != &urbp->node) {
340 struct urb_priv *purbp;
341 struct uhci_td *ptd;
343 purbp = list_entry(urbp->node.prev, struct urb_priv, node);
344 WARN_ON(list_empty(&purbp->td_list));
345 ptd = list_entry(purbp->td_list.prev, struct uhci_td,
346 list);
347 td = list_entry(urbp->td_list.prev, struct uhci_td,
348 list);
349 ptd->link = td->link;
350 goto done;
353 /* If the QH element pointer is UHCI_PTR_TERM then then currently
354 * executing URB has already been unlinked, so this one isn't it. */
355 if (qh_element(qh) == UHCI_PTR_TERM)
356 goto done;
357 qh->element = UHCI_PTR_TERM;
359 /* Control pipes don't have to worry about toggles */
360 if (qh->type == USB_ENDPOINT_XFER_CONTROL)
361 goto done;
363 /* Save the next toggle value */
364 WARN_ON(list_empty(&urbp->td_list));
365 td = list_entry(urbp->td_list.next, struct uhci_td, list);
366 qh->needs_fixup = 1;
367 qh->initial_toggle = uhci_toggle(td_token(td));
369 done:
370 return ret;
374 * Fix up the data toggles for URBs in a queue, when one of them
375 * terminates early (short transfer, error, or dequeued).
377 static void uhci_fixup_toggles(struct uhci_qh *qh, int skip_first)
379 struct urb_priv *urbp = NULL;
380 struct uhci_td *td;
381 unsigned int toggle = qh->initial_toggle;
382 unsigned int pipe;
384 /* Fixups for a short transfer start with the second URB in the
385 * queue (the short URB is the first). */
386 if (skip_first)
387 urbp = list_entry(qh->queue.next, struct urb_priv, node);
389 /* When starting with the first URB, if the QH element pointer is
390 * still valid then we know the URB's toggles are okay. */
391 else if (qh_element(qh) != UHCI_PTR_TERM)
392 toggle = 2;
394 /* Fix up the toggle for the URBs in the queue. Normally this
395 * loop won't run more than once: When an error or short transfer
396 * occurs, the queue usually gets emptied. */
397 urbp = list_prepare_entry(urbp, &qh->queue, node);
398 list_for_each_entry_continue(urbp, &qh->queue, node) {
400 /* If the first TD has the right toggle value, we don't
401 * need to change any toggles in this URB */
402 td = list_entry(urbp->td_list.next, struct uhci_td, list);
403 if (toggle > 1 || uhci_toggle(td_token(td)) == toggle) {
404 td = list_entry(urbp->td_list.prev, struct uhci_td,
405 list);
406 toggle = uhci_toggle(td_token(td)) ^ 1;
408 /* Otherwise all the toggles in the URB have to be switched */
409 } else {
410 list_for_each_entry(td, &urbp->td_list, list) {
411 td->token ^= __constant_cpu_to_le32(
412 TD_TOKEN_TOGGLE);
413 toggle ^= 1;
418 wmb();
419 pipe = list_entry(qh->queue.next, struct urb_priv, node)->urb->pipe;
420 usb_settoggle(qh->udev, usb_pipeendpoint(pipe),
421 usb_pipeout(pipe), toggle);
422 qh->needs_fixup = 0;
426 * Link an Isochronous QH into its skeleton's list
428 static inline void link_iso(struct uhci_hcd *uhci, struct uhci_qh *qh)
430 list_add_tail(&qh->node, &uhci->skel_iso_qh->node);
432 /* Isochronous QHs aren't linked by the hardware */
436 * Link a high-period interrupt QH into the schedule at the end of its
437 * skeleton's list
439 static void link_interrupt(struct uhci_hcd *uhci, struct uhci_qh *qh)
441 struct uhci_qh *pqh;
443 list_add_tail(&qh->node, &uhci->skelqh[qh->skel]->node);
445 pqh = list_entry(qh->node.prev, struct uhci_qh, node);
446 qh->link = pqh->link;
447 wmb();
448 pqh->link = LINK_TO_QH(qh);
452 * Link a period-1 interrupt or async QH into the schedule at the
453 * correct spot in the async skeleton's list, and update the FSBR link
455 static void link_async(struct uhci_hcd *uhci, struct uhci_qh *qh)
457 struct uhci_qh *pqh;
458 __le32 link_to_new_qh;
460 /* Find the predecessor QH for our new one and insert it in the list.
461 * The list of QHs is expected to be short, so linear search won't
462 * take too long. */
463 list_for_each_entry_reverse(pqh, &uhci->skel_async_qh->node, node) {
464 if (pqh->skel <= qh->skel)
465 break;
467 list_add(&qh->node, &pqh->node);
469 /* Link it into the schedule */
470 qh->link = pqh->link;
471 wmb();
472 link_to_new_qh = LINK_TO_QH(qh);
473 pqh->link = link_to_new_qh;
475 /* If this is now the first FSBR QH, link the terminating skeleton
476 * QH to it. */
477 if (pqh->skel < SKEL_FSBR && qh->skel >= SKEL_FSBR)
478 uhci->skel_term_qh->link = link_to_new_qh;
482 * Put a QH on the schedule in both hardware and software
484 static void uhci_activate_qh(struct uhci_hcd *uhci, struct uhci_qh *qh)
486 WARN_ON(list_empty(&qh->queue));
488 /* Set the element pointer if it isn't set already.
489 * This isn't needed for Isochronous queues, but it doesn't hurt. */
490 if (qh_element(qh) == UHCI_PTR_TERM) {
491 struct urb_priv *urbp = list_entry(qh->queue.next,
492 struct urb_priv, node);
493 struct uhci_td *td = list_entry(urbp->td_list.next,
494 struct uhci_td, list);
496 qh->element = LINK_TO_TD(td);
499 /* Treat the queue as if it has just advanced */
500 qh->wait_expired = 0;
501 qh->advance_jiffies = jiffies;
503 if (qh->state == QH_STATE_ACTIVE)
504 return;
505 qh->state = QH_STATE_ACTIVE;
507 /* Move the QH from its old list to the correct spot in the appropriate
508 * skeleton's list */
509 if (qh == uhci->next_qh)
510 uhci->next_qh = list_entry(qh->node.next, struct uhci_qh,
511 node);
512 list_del(&qh->node);
514 if (qh->skel == SKEL_ISO)
515 link_iso(uhci, qh);
516 else if (qh->skel < SKEL_ASYNC)
517 link_interrupt(uhci, qh);
518 else
519 link_async(uhci, qh);
523 * Unlink a high-period interrupt QH from the schedule
525 static void unlink_interrupt(struct uhci_hcd *uhci, struct uhci_qh *qh)
527 struct uhci_qh *pqh;
529 pqh = list_entry(qh->node.prev, struct uhci_qh, node);
530 pqh->link = qh->link;
531 mb();
535 * Unlink a period-1 interrupt or async QH from the schedule
537 static void unlink_async(struct uhci_hcd *uhci, struct uhci_qh *qh)
539 struct uhci_qh *pqh;
540 __le32 link_to_next_qh = qh->link;
542 pqh = list_entry(qh->node.prev, struct uhci_qh, node);
543 pqh->link = link_to_next_qh;
545 /* If this was the old first FSBR QH, link the terminating skeleton
546 * QH to the next (new first FSBR) QH. */
547 if (pqh->skel < SKEL_FSBR && qh->skel >= SKEL_FSBR)
548 uhci->skel_term_qh->link = link_to_next_qh;
549 mb();
553 * Take a QH off the hardware schedule
555 static void uhci_unlink_qh(struct uhci_hcd *uhci, struct uhci_qh *qh)
557 if (qh->state == QH_STATE_UNLINKING)
558 return;
559 WARN_ON(qh->state != QH_STATE_ACTIVE || !qh->udev);
560 qh->state = QH_STATE_UNLINKING;
562 /* Unlink the QH from the schedule and record when we did it */
563 if (qh->skel == SKEL_ISO)
565 else if (qh->skel < SKEL_ASYNC)
566 unlink_interrupt(uhci, qh);
567 else
568 unlink_async(uhci, qh);
570 uhci_get_current_frame_number(uhci);
571 qh->unlink_frame = uhci->frame_number;
573 /* Force an interrupt so we know when the QH is fully unlinked */
574 if (list_empty(&uhci->skel_unlink_qh->node))
575 uhci_set_next_interrupt(uhci);
577 /* Move the QH from its old list to the end of the unlinking list */
578 if (qh == uhci->next_qh)
579 uhci->next_qh = list_entry(qh->node.next, struct uhci_qh,
580 node);
581 list_move_tail(&qh->node, &uhci->skel_unlink_qh->node);
585 * When we and the controller are through with a QH, it becomes IDLE.
586 * This happens when a QH has been off the schedule (on the unlinking
587 * list) for more than one frame, or when an error occurs while adding
588 * the first URB onto a new QH.
590 static void uhci_make_qh_idle(struct uhci_hcd *uhci, struct uhci_qh *qh)
592 WARN_ON(qh->state == QH_STATE_ACTIVE);
594 if (qh == uhci->next_qh)
595 uhci->next_qh = list_entry(qh->node.next, struct uhci_qh,
596 node);
597 list_move(&qh->node, &uhci->idle_qh_list);
598 qh->state = QH_STATE_IDLE;
600 /* Now that the QH is idle, its post_td isn't being used */
601 if (qh->post_td) {
602 uhci_free_td(uhci, qh->post_td);
603 qh->post_td = NULL;
606 /* If anyone is waiting for a QH to become idle, wake them up */
607 if (uhci->num_waiting)
608 wake_up_all(&uhci->waitqh);
612 * Find the highest existing bandwidth load for a given phase and period.
614 static int uhci_highest_load(struct uhci_hcd *uhci, int phase, int period)
616 int highest_load = uhci->load[phase];
618 for (phase += period; phase < MAX_PHASE; phase += period)
619 highest_load = max_t(int, highest_load, uhci->load[phase]);
620 return highest_load;
624 * Set qh->phase to the optimal phase for a periodic transfer and
625 * check whether the bandwidth requirement is acceptable.
627 static int uhci_check_bandwidth(struct uhci_hcd *uhci, struct uhci_qh *qh)
629 int minimax_load;
631 /* Find the optimal phase (unless it is already set) and get
632 * its load value. */
633 if (qh->phase >= 0)
634 minimax_load = uhci_highest_load(uhci, qh->phase, qh->period);
635 else {
636 int phase, load;
637 int max_phase = min_t(int, MAX_PHASE, qh->period);
639 qh->phase = 0;
640 minimax_load = uhci_highest_load(uhci, qh->phase, qh->period);
641 for (phase = 1; phase < max_phase; ++phase) {
642 load = uhci_highest_load(uhci, phase, qh->period);
643 if (load < minimax_load) {
644 minimax_load = load;
645 qh->phase = phase;
650 /* Maximum allowable periodic bandwidth is 90%, or 900 us per frame */
651 if (minimax_load + qh->load > 900) {
652 dev_dbg(uhci_dev(uhci), "bandwidth allocation failed: "
653 "period %d, phase %d, %d + %d us\n",
654 qh->period, qh->phase, minimax_load, qh->load);
655 return -ENOSPC;
657 return 0;
661 * Reserve a periodic QH's bandwidth in the schedule
663 static void uhci_reserve_bandwidth(struct uhci_hcd *uhci, struct uhci_qh *qh)
665 int i;
666 int load = qh->load;
667 char *p = "??";
669 for (i = qh->phase; i < MAX_PHASE; i += qh->period) {
670 uhci->load[i] += load;
671 uhci->total_load += load;
673 uhci_to_hcd(uhci)->self.bandwidth_allocated =
674 uhci->total_load / MAX_PHASE;
675 switch (qh->type) {
676 case USB_ENDPOINT_XFER_INT:
677 ++uhci_to_hcd(uhci)->self.bandwidth_int_reqs;
678 p = "INT";
679 break;
680 case USB_ENDPOINT_XFER_ISOC:
681 ++uhci_to_hcd(uhci)->self.bandwidth_isoc_reqs;
682 p = "ISO";
683 break;
685 qh->bandwidth_reserved = 1;
686 dev_dbg(uhci_dev(uhci),
687 "%s dev %d ep%02x-%s, period %d, phase %d, %d us\n",
688 "reserve", qh->udev->devnum,
689 qh->hep->desc.bEndpointAddress, p,
690 qh->period, qh->phase, load);
694 * Release a periodic QH's bandwidth reservation
696 static void uhci_release_bandwidth(struct uhci_hcd *uhci, struct uhci_qh *qh)
698 int i;
699 int load = qh->load;
700 char *p = "??";
702 for (i = qh->phase; i < MAX_PHASE; i += qh->period) {
703 uhci->load[i] -= load;
704 uhci->total_load -= load;
706 uhci_to_hcd(uhci)->self.bandwidth_allocated =
707 uhci->total_load / MAX_PHASE;
708 switch (qh->type) {
709 case USB_ENDPOINT_XFER_INT:
710 --uhci_to_hcd(uhci)->self.bandwidth_int_reqs;
711 p = "INT";
712 break;
713 case USB_ENDPOINT_XFER_ISOC:
714 --uhci_to_hcd(uhci)->self.bandwidth_isoc_reqs;
715 p = "ISO";
716 break;
718 qh->bandwidth_reserved = 0;
719 dev_dbg(uhci_dev(uhci),
720 "%s dev %d ep%02x-%s, period %d, phase %d, %d us\n",
721 "release", qh->udev->devnum,
722 qh->hep->desc.bEndpointAddress, p,
723 qh->period, qh->phase, load);
726 static inline struct urb_priv *uhci_alloc_urb_priv(struct uhci_hcd *uhci,
727 struct urb *urb)
729 struct urb_priv *urbp;
731 urbp = kmem_cache_zalloc(uhci_up_cachep, GFP_ATOMIC);
732 if (!urbp)
733 return NULL;
735 urbp->urb = urb;
736 urb->hcpriv = urbp;
738 INIT_LIST_HEAD(&urbp->node);
739 INIT_LIST_HEAD(&urbp->td_list);
741 return urbp;
744 static void uhci_free_urb_priv(struct uhci_hcd *uhci,
745 struct urb_priv *urbp)
747 struct uhci_td *td, *tmp;
749 if (!list_empty(&urbp->node)) {
750 dev_warn(uhci_dev(uhci), "urb %p still on QH's list!\n",
751 urbp->urb);
752 WARN_ON(1);
755 list_for_each_entry_safe(td, tmp, &urbp->td_list, list) {
756 uhci_remove_td_from_urbp(td);
757 uhci_free_td(uhci, td);
760 urbp->urb->hcpriv = NULL;
761 kmem_cache_free(uhci_up_cachep, urbp);
765 * Map status to standard result codes
767 * <status> is (td_status(td) & 0xF60000), a.k.a.
768 * uhci_status_bits(td_status(td)).
769 * Note: <status> does not include the TD_CTRL_NAK bit.
770 * <dir_out> is True for output TDs and False for input TDs.
772 static int uhci_map_status(int status, int dir_out)
774 if (!status)
775 return 0;
776 if (status & TD_CTRL_BITSTUFF) /* Bitstuff error */
777 return -EPROTO;
778 if (status & TD_CTRL_CRCTIMEO) { /* CRC/Timeout */
779 if (dir_out)
780 return -EPROTO;
781 else
782 return -EILSEQ;
784 if (status & TD_CTRL_BABBLE) /* Babble */
785 return -EOVERFLOW;
786 if (status & TD_CTRL_DBUFERR) /* Buffer error */
787 return -ENOSR;
788 if (status & TD_CTRL_STALLED) /* Stalled */
789 return -EPIPE;
790 return 0;
794 * Control transfers
796 static int uhci_submit_control(struct uhci_hcd *uhci, struct urb *urb,
797 struct uhci_qh *qh)
799 struct uhci_td *td;
800 unsigned long destination, status;
801 int maxsze = le16_to_cpu(qh->hep->desc.wMaxPacketSize);
802 int len = urb->transfer_buffer_length;
803 dma_addr_t data = urb->transfer_dma;
804 __le32 *plink;
805 struct urb_priv *urbp = urb->hcpriv;
806 int skel;
808 /* The "pipe" thing contains the destination in bits 8--18 */
809 destination = (urb->pipe & PIPE_DEVEP_MASK) | USB_PID_SETUP;
811 /* 3 errors, dummy TD remains inactive */
812 status = uhci_maxerr(3);
813 if (urb->dev->speed == USB_SPEED_LOW)
814 status |= TD_CTRL_LS;
817 * Build the TD for the control request setup packet
819 td = qh->dummy_td;
820 uhci_add_td_to_urbp(td, urbp);
821 uhci_fill_td(td, status, destination | uhci_explen(8),
822 urb->setup_dma);
823 plink = &td->link;
824 status |= TD_CTRL_ACTIVE;
827 * If direction is "send", change the packet ID from SETUP (0x2D)
828 * to OUT (0xE1). Else change it from SETUP to IN (0x69) and
829 * set Short Packet Detect (SPD) for all data packets.
831 if (usb_pipeout(urb->pipe))
832 destination ^= (USB_PID_SETUP ^ USB_PID_OUT);
833 else {
834 destination ^= (USB_PID_SETUP ^ USB_PID_IN);
835 status |= TD_CTRL_SPD;
839 * Build the DATA TDs
841 while (len > 0) {
842 int pktsze = min(len, maxsze);
844 td = uhci_alloc_td(uhci);
845 if (!td)
846 goto nomem;
847 *plink = LINK_TO_TD(td);
849 /* Alternate Data0/1 (start with Data1) */
850 destination ^= TD_TOKEN_TOGGLE;
852 uhci_add_td_to_urbp(td, urbp);
853 uhci_fill_td(td, status, destination | uhci_explen(pktsze),
854 data);
855 plink = &td->link;
857 data += pktsze;
858 len -= pktsze;
862 * Build the final TD for control status
864 td = uhci_alloc_td(uhci);
865 if (!td)
866 goto nomem;
867 *plink = LINK_TO_TD(td);
870 * It's IN if the pipe is an output pipe or we're not expecting
871 * data back.
873 destination &= ~TD_TOKEN_PID_MASK;
874 if (usb_pipeout(urb->pipe) || !urb->transfer_buffer_length)
875 destination |= USB_PID_IN;
876 else
877 destination |= USB_PID_OUT;
879 destination |= TD_TOKEN_TOGGLE; /* End in Data1 */
881 status &= ~TD_CTRL_SPD;
883 uhci_add_td_to_urbp(td, urbp);
884 uhci_fill_td(td, status | TD_CTRL_IOC,
885 destination | uhci_explen(0), 0);
886 plink = &td->link;
889 * Build the new dummy TD and activate the old one
891 td = uhci_alloc_td(uhci);
892 if (!td)
893 goto nomem;
894 *plink = LINK_TO_TD(td);
896 uhci_fill_td(td, 0, USB_PID_OUT | uhci_explen(0), 0);
897 wmb();
898 qh->dummy_td->status |= __constant_cpu_to_le32(TD_CTRL_ACTIVE);
899 qh->dummy_td = td;
901 /* Low-speed transfers get a different queue, and won't hog the bus.
902 * Also, some devices enumerate better without FSBR; the easiest way
903 * to do that is to put URBs on the low-speed queue while the device
904 * isn't in the CONFIGURED state. */
905 if (urb->dev->speed == USB_SPEED_LOW ||
906 urb->dev->state != USB_STATE_CONFIGURED)
907 skel = SKEL_LS_CONTROL;
908 else {
909 skel = SKEL_FS_CONTROL;
910 uhci_add_fsbr(uhci, urb);
912 if (qh->state != QH_STATE_ACTIVE)
913 qh->skel = skel;
915 urb->actual_length = -8; /* Account for the SETUP packet */
916 return 0;
918 nomem:
919 /* Remove the dummy TD from the td_list so it doesn't get freed */
920 uhci_remove_td_from_urbp(qh->dummy_td);
921 return -ENOMEM;
925 * Common submit for bulk and interrupt
927 static int uhci_submit_common(struct uhci_hcd *uhci, struct urb *urb,
928 struct uhci_qh *qh)
930 struct uhci_td *td;
931 unsigned long destination, status;
932 int maxsze = le16_to_cpu(qh->hep->desc.wMaxPacketSize);
933 int len = urb->transfer_buffer_length;
934 dma_addr_t data = urb->transfer_dma;
935 __le32 *plink;
936 struct urb_priv *urbp = urb->hcpriv;
937 unsigned int toggle;
939 if (len < 0)
940 return -EINVAL;
942 /* The "pipe" thing contains the destination in bits 8--18 */
943 destination = (urb->pipe & PIPE_DEVEP_MASK) | usb_packetid(urb->pipe);
944 toggle = usb_gettoggle(urb->dev, usb_pipeendpoint(urb->pipe),
945 usb_pipeout(urb->pipe));
947 /* 3 errors, dummy TD remains inactive */
948 status = uhci_maxerr(3);
949 if (urb->dev->speed == USB_SPEED_LOW)
950 status |= TD_CTRL_LS;
951 if (usb_pipein(urb->pipe))
952 status |= TD_CTRL_SPD;
955 * Build the DATA TDs
957 plink = NULL;
958 td = qh->dummy_td;
959 do { /* Allow zero length packets */
960 int pktsze = maxsze;
962 if (len <= pktsze) { /* The last packet */
963 pktsze = len;
964 if (!(urb->transfer_flags & URB_SHORT_NOT_OK))
965 status &= ~TD_CTRL_SPD;
968 if (plink) {
969 td = uhci_alloc_td(uhci);
970 if (!td)
971 goto nomem;
972 *plink = LINK_TO_TD(td);
974 uhci_add_td_to_urbp(td, urbp);
975 uhci_fill_td(td, status,
976 destination | uhci_explen(pktsze) |
977 (toggle << TD_TOKEN_TOGGLE_SHIFT),
978 data);
979 plink = &td->link;
980 status |= TD_CTRL_ACTIVE;
982 data += pktsze;
983 len -= maxsze;
984 toggle ^= 1;
985 } while (len > 0);
988 * URB_ZERO_PACKET means adding a 0-length packet, if direction
989 * is OUT and the transfer_length was an exact multiple of maxsze,
990 * hence (len = transfer_length - N * maxsze) == 0
991 * however, if transfer_length == 0, the zero packet was already
992 * prepared above.
994 if ((urb->transfer_flags & URB_ZERO_PACKET) &&
995 usb_pipeout(urb->pipe) && len == 0 &&
996 urb->transfer_buffer_length > 0) {
997 td = uhci_alloc_td(uhci);
998 if (!td)
999 goto nomem;
1000 *plink = LINK_TO_TD(td);
1002 uhci_add_td_to_urbp(td, urbp);
1003 uhci_fill_td(td, status,
1004 destination | uhci_explen(0) |
1005 (toggle << TD_TOKEN_TOGGLE_SHIFT),
1006 data);
1007 plink = &td->link;
1009 toggle ^= 1;
1012 /* Set the interrupt-on-completion flag on the last packet.
1013 * A more-or-less typical 4 KB URB (= size of one memory page)
1014 * will require about 3 ms to transfer; that's a little on the
1015 * fast side but not enough to justify delaying an interrupt
1016 * more than 2 or 3 URBs, so we will ignore the URB_NO_INTERRUPT
1017 * flag setting. */
1018 td->status |= __constant_cpu_to_le32(TD_CTRL_IOC);
1021 * Build the new dummy TD and activate the old one
1023 td = uhci_alloc_td(uhci);
1024 if (!td)
1025 goto nomem;
1026 *plink = LINK_TO_TD(td);
1028 uhci_fill_td(td, 0, USB_PID_OUT | uhci_explen(0), 0);
1029 wmb();
1030 qh->dummy_td->status |= __constant_cpu_to_le32(TD_CTRL_ACTIVE);
1031 qh->dummy_td = td;
1033 usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe),
1034 usb_pipeout(urb->pipe), toggle);
1035 return 0;
1037 nomem:
1038 /* Remove the dummy TD from the td_list so it doesn't get freed */
1039 uhci_remove_td_from_urbp(qh->dummy_td);
1040 return -ENOMEM;
1043 static int uhci_submit_bulk(struct uhci_hcd *uhci, struct urb *urb,
1044 struct uhci_qh *qh)
1046 int ret;
1048 /* Can't have low-speed bulk transfers */
1049 if (urb->dev->speed == USB_SPEED_LOW)
1050 return -EINVAL;
1052 if (qh->state != QH_STATE_ACTIVE)
1053 qh->skel = SKEL_BULK;
1054 ret = uhci_submit_common(uhci, urb, qh);
1055 if (ret == 0)
1056 uhci_add_fsbr(uhci, urb);
1057 return ret;
1060 static int uhci_submit_interrupt(struct uhci_hcd *uhci, struct urb *urb,
1061 struct uhci_qh *qh)
1063 int ret;
1065 /* USB 1.1 interrupt transfers only involve one packet per interval.
1066 * Drivers can submit URBs of any length, but longer ones will need
1067 * multiple intervals to complete.
1070 if (!qh->bandwidth_reserved) {
1071 int exponent;
1073 /* Figure out which power-of-two queue to use */
1074 for (exponent = 7; exponent >= 0; --exponent) {
1075 if ((1 << exponent) <= urb->interval)
1076 break;
1078 if (exponent < 0)
1079 return -EINVAL;
1080 qh->period = 1 << exponent;
1081 qh->skel = SKEL_INDEX(exponent);
1083 /* For now, interrupt phase is fixed by the layout
1084 * of the QH lists. */
1085 qh->phase = (qh->period / 2) & (MAX_PHASE - 1);
1086 ret = uhci_check_bandwidth(uhci, qh);
1087 if (ret)
1088 return ret;
1089 } else if (qh->period > urb->interval)
1090 return -EINVAL; /* Can't decrease the period */
1092 ret = uhci_submit_common(uhci, urb, qh);
1093 if (ret == 0) {
1094 urb->interval = qh->period;
1095 if (!qh->bandwidth_reserved)
1096 uhci_reserve_bandwidth(uhci, qh);
1098 return ret;
1102 * Fix up the data structures following a short transfer
1104 static int uhci_fixup_short_transfer(struct uhci_hcd *uhci,
1105 struct uhci_qh *qh, struct urb_priv *urbp)
1107 struct uhci_td *td;
1108 struct list_head *tmp;
1109 int ret;
1111 td = list_entry(urbp->td_list.prev, struct uhci_td, list);
1112 if (qh->type == USB_ENDPOINT_XFER_CONTROL) {
1114 /* When a control transfer is short, we have to restart
1115 * the queue at the status stage transaction, which is
1116 * the last TD. */
1117 WARN_ON(list_empty(&urbp->td_list));
1118 qh->element = LINK_TO_TD(td);
1119 tmp = td->list.prev;
1120 ret = -EINPROGRESS;
1122 } else {
1124 /* When a bulk/interrupt transfer is short, we have to
1125 * fix up the toggles of the following URBs on the queue
1126 * before restarting the queue at the next URB. */
1127 qh->initial_toggle = uhci_toggle(td_token(qh->post_td)) ^ 1;
1128 uhci_fixup_toggles(qh, 1);
1130 if (list_empty(&urbp->td_list))
1131 td = qh->post_td;
1132 qh->element = td->link;
1133 tmp = urbp->td_list.prev;
1134 ret = 0;
1137 /* Remove all the TDs we skipped over, from tmp back to the start */
1138 while (tmp != &urbp->td_list) {
1139 td = list_entry(tmp, struct uhci_td, list);
1140 tmp = tmp->prev;
1142 uhci_remove_td_from_urbp(td);
1143 uhci_free_td(uhci, td);
1145 return ret;
1149 * Common result for control, bulk, and interrupt
1151 static int uhci_result_common(struct uhci_hcd *uhci, struct urb *urb)
1153 struct urb_priv *urbp = urb->hcpriv;
1154 struct uhci_qh *qh = urbp->qh;
1155 struct uhci_td *td, *tmp;
1156 unsigned status;
1157 int ret = 0;
1159 list_for_each_entry_safe(td, tmp, &urbp->td_list, list) {
1160 unsigned int ctrlstat;
1161 int len;
1163 ctrlstat = td_status(td);
1164 status = uhci_status_bits(ctrlstat);
1165 if (status & TD_CTRL_ACTIVE)
1166 return -EINPROGRESS;
1168 len = uhci_actual_length(ctrlstat);
1169 urb->actual_length += len;
1171 if (status) {
1172 ret = uhci_map_status(status,
1173 uhci_packetout(td_token(td)));
1174 if ((debug == 1 && ret != -EPIPE) || debug > 1) {
1175 /* Some debugging code */
1176 dev_dbg(&urb->dev->dev,
1177 "%s: failed with status %x\n",
1178 __FUNCTION__, status);
1180 if (debug > 1 && errbuf) {
1181 /* Print the chain for debugging */
1182 uhci_show_qh(uhci, urbp->qh, errbuf,
1183 ERRBUF_LEN, 0);
1184 lprintk(errbuf);
1188 } else if (len < uhci_expected_length(td_token(td))) {
1190 /* We received a short packet */
1191 if (urb->transfer_flags & URB_SHORT_NOT_OK)
1192 ret = -EREMOTEIO;
1194 /* Fixup needed only if this isn't the URB's last TD */
1195 else if (&td->list != urbp->td_list.prev)
1196 ret = 1;
1199 uhci_remove_td_from_urbp(td);
1200 if (qh->post_td)
1201 uhci_free_td(uhci, qh->post_td);
1202 qh->post_td = td;
1204 if (ret != 0)
1205 goto err;
1207 return ret;
1209 err:
1210 if (ret < 0) {
1211 /* In case a control transfer gets an error
1212 * during the setup stage */
1213 urb->actual_length = max(urb->actual_length, 0);
1215 /* Note that the queue has stopped and save
1216 * the next toggle value */
1217 qh->element = UHCI_PTR_TERM;
1218 qh->is_stopped = 1;
1219 qh->needs_fixup = (qh->type != USB_ENDPOINT_XFER_CONTROL);
1220 qh->initial_toggle = uhci_toggle(td_token(td)) ^
1221 (ret == -EREMOTEIO);
1223 } else /* Short packet received */
1224 ret = uhci_fixup_short_transfer(uhci, qh, urbp);
1225 return ret;
1229 * Isochronous transfers
1231 static int uhci_submit_isochronous(struct uhci_hcd *uhci, struct urb *urb,
1232 struct uhci_qh *qh)
1234 struct uhci_td *td = NULL; /* Since urb->number_of_packets > 0 */
1235 int i, frame;
1236 unsigned long destination, status;
1237 struct urb_priv *urbp = (struct urb_priv *) urb->hcpriv;
1239 /* Values must not be too big (could overflow below) */
1240 if (urb->interval >= UHCI_NUMFRAMES ||
1241 urb->number_of_packets >= UHCI_NUMFRAMES)
1242 return -EFBIG;
1244 /* Check the period and figure out the starting frame number */
1245 if (!qh->bandwidth_reserved) {
1246 qh->period = urb->interval;
1247 if (urb->transfer_flags & URB_ISO_ASAP) {
1248 qh->phase = -1; /* Find the best phase */
1249 i = uhci_check_bandwidth(uhci, qh);
1250 if (i)
1251 return i;
1253 /* Allow a little time to allocate the TDs */
1254 uhci_get_current_frame_number(uhci);
1255 frame = uhci->frame_number + 10;
1257 /* Move forward to the first frame having the
1258 * correct phase */
1259 urb->start_frame = frame + ((qh->phase - frame) &
1260 (qh->period - 1));
1261 } else {
1262 i = urb->start_frame - uhci->last_iso_frame;
1263 if (i <= 0 || i >= UHCI_NUMFRAMES)
1264 return -EINVAL;
1265 qh->phase = urb->start_frame & (qh->period - 1);
1266 i = uhci_check_bandwidth(uhci, qh);
1267 if (i)
1268 return i;
1271 } else if (qh->period != urb->interval) {
1272 return -EINVAL; /* Can't change the period */
1274 } else { /* Pick up where the last URB leaves off */
1275 if (list_empty(&qh->queue)) {
1276 frame = qh->iso_frame;
1277 } else {
1278 struct urb *lurb;
1280 lurb = list_entry(qh->queue.prev,
1281 struct urb_priv, node)->urb;
1282 frame = lurb->start_frame +
1283 lurb->number_of_packets *
1284 lurb->interval;
1286 if (urb->transfer_flags & URB_ISO_ASAP)
1287 urb->start_frame = frame;
1288 else if (urb->start_frame != frame)
1289 return -EINVAL;
1292 /* Make sure we won't have to go too far into the future */
1293 if (uhci_frame_before_eq(uhci->last_iso_frame + UHCI_NUMFRAMES,
1294 urb->start_frame + urb->number_of_packets *
1295 urb->interval))
1296 return -EFBIG;
1298 status = TD_CTRL_ACTIVE | TD_CTRL_IOS;
1299 destination = (urb->pipe & PIPE_DEVEP_MASK) | usb_packetid(urb->pipe);
1301 for (i = 0; i < urb->number_of_packets; i++) {
1302 td = uhci_alloc_td(uhci);
1303 if (!td)
1304 return -ENOMEM;
1306 uhci_add_td_to_urbp(td, urbp);
1307 uhci_fill_td(td, status, destination |
1308 uhci_explen(urb->iso_frame_desc[i].length),
1309 urb->transfer_dma +
1310 urb->iso_frame_desc[i].offset);
1313 /* Set the interrupt-on-completion flag on the last packet. */
1314 td->status |= __constant_cpu_to_le32(TD_CTRL_IOC);
1316 /* Add the TDs to the frame list */
1317 frame = urb->start_frame;
1318 list_for_each_entry(td, &urbp->td_list, list) {
1319 uhci_insert_td_in_frame_list(uhci, td, frame);
1320 frame += qh->period;
1323 if (list_empty(&qh->queue)) {
1324 qh->iso_packet_desc = &urb->iso_frame_desc[0];
1325 qh->iso_frame = urb->start_frame;
1326 qh->iso_status = 0;
1329 qh->skel = SKEL_ISO;
1330 if (!qh->bandwidth_reserved)
1331 uhci_reserve_bandwidth(uhci, qh);
1332 return 0;
1335 static int uhci_result_isochronous(struct uhci_hcd *uhci, struct urb *urb)
1337 struct uhci_td *td, *tmp;
1338 struct urb_priv *urbp = urb->hcpriv;
1339 struct uhci_qh *qh = urbp->qh;
1341 list_for_each_entry_safe(td, tmp, &urbp->td_list, list) {
1342 unsigned int ctrlstat;
1343 int status;
1344 int actlength;
1346 if (uhci_frame_before_eq(uhci->cur_iso_frame, qh->iso_frame))
1347 return -EINPROGRESS;
1349 uhci_remove_tds_from_frame(uhci, qh->iso_frame);
1351 ctrlstat = td_status(td);
1352 if (ctrlstat & TD_CTRL_ACTIVE) {
1353 status = -EXDEV; /* TD was added too late? */
1354 } else {
1355 status = uhci_map_status(uhci_status_bits(ctrlstat),
1356 usb_pipeout(urb->pipe));
1357 actlength = uhci_actual_length(ctrlstat);
1359 urb->actual_length += actlength;
1360 qh->iso_packet_desc->actual_length = actlength;
1361 qh->iso_packet_desc->status = status;
1364 if (status) {
1365 urb->error_count++;
1366 qh->iso_status = status;
1369 uhci_remove_td_from_urbp(td);
1370 uhci_free_td(uhci, td);
1371 qh->iso_frame += qh->period;
1372 ++qh->iso_packet_desc;
1374 return qh->iso_status;
1377 static int uhci_urb_enqueue(struct usb_hcd *hcd,
1378 struct usb_host_endpoint *hep,
1379 struct urb *urb, gfp_t mem_flags)
1381 int ret;
1382 struct uhci_hcd *uhci = hcd_to_uhci(hcd);
1383 unsigned long flags;
1384 struct urb_priv *urbp;
1385 struct uhci_qh *qh;
1387 spin_lock_irqsave(&uhci->lock, flags);
1389 ret = urb->status;
1390 if (ret != -EINPROGRESS) /* URB already unlinked! */
1391 goto done;
1393 ret = -ENOMEM;
1394 urbp = uhci_alloc_urb_priv(uhci, urb);
1395 if (!urbp)
1396 goto done;
1398 if (hep->hcpriv)
1399 qh = (struct uhci_qh *) hep->hcpriv;
1400 else {
1401 qh = uhci_alloc_qh(uhci, urb->dev, hep);
1402 if (!qh)
1403 goto err_no_qh;
1405 urbp->qh = qh;
1407 switch (qh->type) {
1408 case USB_ENDPOINT_XFER_CONTROL:
1409 ret = uhci_submit_control(uhci, urb, qh);
1410 break;
1411 case USB_ENDPOINT_XFER_BULK:
1412 ret = uhci_submit_bulk(uhci, urb, qh);
1413 break;
1414 case USB_ENDPOINT_XFER_INT:
1415 ret = uhci_submit_interrupt(uhci, urb, qh);
1416 break;
1417 case USB_ENDPOINT_XFER_ISOC:
1418 urb->error_count = 0;
1419 ret = uhci_submit_isochronous(uhci, urb, qh);
1420 break;
1422 if (ret != 0)
1423 goto err_submit_failed;
1425 /* Add this URB to the QH */
1426 urbp->qh = qh;
1427 list_add_tail(&urbp->node, &qh->queue);
1429 /* If the new URB is the first and only one on this QH then either
1430 * the QH is new and idle or else it's unlinked and waiting to
1431 * become idle, so we can activate it right away. But only if the
1432 * queue isn't stopped. */
1433 if (qh->queue.next == &urbp->node && !qh->is_stopped) {
1434 uhci_activate_qh(uhci, qh);
1435 uhci_urbp_wants_fsbr(uhci, urbp);
1437 goto done;
1439 err_submit_failed:
1440 if (qh->state == QH_STATE_IDLE)
1441 uhci_make_qh_idle(uhci, qh); /* Reclaim unused QH */
1443 err_no_qh:
1444 uhci_free_urb_priv(uhci, urbp);
1446 done:
1447 spin_unlock_irqrestore(&uhci->lock, flags);
1448 return ret;
1451 static int uhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb)
1453 struct uhci_hcd *uhci = hcd_to_uhci(hcd);
1454 unsigned long flags;
1455 struct urb_priv *urbp;
1456 struct uhci_qh *qh;
1458 spin_lock_irqsave(&uhci->lock, flags);
1459 urbp = urb->hcpriv;
1460 if (!urbp) /* URB was never linked! */
1461 goto done;
1462 qh = urbp->qh;
1464 /* Remove Isochronous TDs from the frame list ASAP */
1465 if (qh->type == USB_ENDPOINT_XFER_ISOC) {
1466 uhci_unlink_isochronous_tds(uhci, urb);
1467 mb();
1469 /* If the URB has already started, update the QH unlink time */
1470 uhci_get_current_frame_number(uhci);
1471 if (uhci_frame_before_eq(urb->start_frame, uhci->frame_number))
1472 qh->unlink_frame = uhci->frame_number;
1475 uhci_unlink_qh(uhci, qh);
1477 done:
1478 spin_unlock_irqrestore(&uhci->lock, flags);
1479 return 0;
1483 * Finish unlinking an URB and give it back
1485 static void uhci_giveback_urb(struct uhci_hcd *uhci, struct uhci_qh *qh,
1486 struct urb *urb)
1487 __releases(uhci->lock)
1488 __acquires(uhci->lock)
1490 struct urb_priv *urbp = (struct urb_priv *) urb->hcpriv;
1492 /* When giving back the first URB in an Isochronous queue,
1493 * reinitialize the QH's iso-related members for the next URB. */
1494 if (qh->type == USB_ENDPOINT_XFER_ISOC &&
1495 urbp->node.prev == &qh->queue &&
1496 urbp->node.next != &qh->queue) {
1497 struct urb *nurb = list_entry(urbp->node.next,
1498 struct urb_priv, node)->urb;
1500 qh->iso_packet_desc = &nurb->iso_frame_desc[0];
1501 qh->iso_frame = nurb->start_frame;
1502 qh->iso_status = 0;
1505 /* Take the URB off the QH's queue. If the queue is now empty,
1506 * this is a perfect time for a toggle fixup. */
1507 list_del_init(&urbp->node);
1508 if (list_empty(&qh->queue) && qh->needs_fixup) {
1509 usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe),
1510 usb_pipeout(urb->pipe), qh->initial_toggle);
1511 qh->needs_fixup = 0;
1514 uhci_free_urb_priv(uhci, urbp);
1516 spin_unlock(&uhci->lock);
1517 usb_hcd_giveback_urb(uhci_to_hcd(uhci), urb);
1518 spin_lock(&uhci->lock);
1520 /* If the queue is now empty, we can unlink the QH and give up its
1521 * reserved bandwidth. */
1522 if (list_empty(&qh->queue)) {
1523 uhci_unlink_qh(uhci, qh);
1524 if (qh->bandwidth_reserved)
1525 uhci_release_bandwidth(uhci, qh);
1530 * Scan the URBs in a QH's queue
1532 #define QH_FINISHED_UNLINKING(qh) \
1533 (qh->state == QH_STATE_UNLINKING && \
1534 uhci->frame_number + uhci->is_stopped != qh->unlink_frame)
1536 static void uhci_scan_qh(struct uhci_hcd *uhci, struct uhci_qh *qh)
1538 struct urb_priv *urbp;
1539 struct urb *urb;
1540 int status;
1542 while (!list_empty(&qh->queue)) {
1543 urbp = list_entry(qh->queue.next, struct urb_priv, node);
1544 urb = urbp->urb;
1546 if (qh->type == USB_ENDPOINT_XFER_ISOC)
1547 status = uhci_result_isochronous(uhci, urb);
1548 else
1549 status = uhci_result_common(uhci, urb);
1550 if (status == -EINPROGRESS)
1551 break;
1553 spin_lock(&urb->lock);
1554 if (urb->status == -EINPROGRESS) /* Not dequeued */
1555 urb->status = status;
1556 else
1557 status = ECONNRESET; /* Not -ECONNRESET */
1558 spin_unlock(&urb->lock);
1560 /* Dequeued but completed URBs can't be given back unless
1561 * the QH is stopped or has finished unlinking. */
1562 if (status == ECONNRESET) {
1563 if (QH_FINISHED_UNLINKING(qh))
1564 qh->is_stopped = 1;
1565 else if (!qh->is_stopped)
1566 return;
1569 uhci_giveback_urb(uhci, qh, urb);
1570 if (status < 0 && qh->type != USB_ENDPOINT_XFER_ISOC)
1571 break;
1574 /* If the QH is neither stopped nor finished unlinking (normal case),
1575 * our work here is done. */
1576 if (QH_FINISHED_UNLINKING(qh))
1577 qh->is_stopped = 1;
1578 else if (!qh->is_stopped)
1579 return;
1581 /* Otherwise give back each of the dequeued URBs */
1582 restart:
1583 list_for_each_entry(urbp, &qh->queue, node) {
1584 urb = urbp->urb;
1585 if (urb->status != -EINPROGRESS) {
1587 /* Fix up the TD links and save the toggles for
1588 * non-Isochronous queues. For Isochronous queues,
1589 * test for too-recent dequeues. */
1590 if (!uhci_cleanup_queue(uhci, qh, urb)) {
1591 qh->is_stopped = 0;
1592 return;
1594 uhci_giveback_urb(uhci, qh, urb);
1595 goto restart;
1598 qh->is_stopped = 0;
1600 /* There are no more dequeued URBs. If there are still URBs on the
1601 * queue, the QH can now be re-activated. */
1602 if (!list_empty(&qh->queue)) {
1603 if (qh->needs_fixup)
1604 uhci_fixup_toggles(qh, 0);
1606 /* If the first URB on the queue wants FSBR but its time
1607 * limit has expired, set the next TD to interrupt on
1608 * completion before reactivating the QH. */
1609 urbp = list_entry(qh->queue.next, struct urb_priv, node);
1610 if (urbp->fsbr && qh->wait_expired) {
1611 struct uhci_td *td = list_entry(urbp->td_list.next,
1612 struct uhci_td, list);
1614 td->status |= __cpu_to_le32(TD_CTRL_IOC);
1617 uhci_activate_qh(uhci, qh);
1620 /* The queue is empty. The QH can become idle if it is fully
1621 * unlinked. */
1622 else if (QH_FINISHED_UNLINKING(qh))
1623 uhci_make_qh_idle(uhci, qh);
1627 * Check for queues that have made some forward progress.
1628 * Returns 0 if the queue is not Isochronous, is ACTIVE, and
1629 * has not advanced since last examined; 1 otherwise.
1631 * Early Intel controllers have a bug which causes qh->element sometimes
1632 * not to advance when a TD completes successfully. The queue remains
1633 * stuck on the inactive completed TD. We detect such cases and advance
1634 * the element pointer by hand.
1636 static int uhci_advance_check(struct uhci_hcd *uhci, struct uhci_qh *qh)
1638 struct urb_priv *urbp = NULL;
1639 struct uhci_td *td;
1640 int ret = 1;
1641 unsigned status;
1643 if (qh->type == USB_ENDPOINT_XFER_ISOC)
1644 goto done;
1646 /* Treat an UNLINKING queue as though it hasn't advanced.
1647 * This is okay because reactivation will treat it as though
1648 * it has advanced, and if it is going to become IDLE then
1649 * this doesn't matter anyway. Furthermore it's possible
1650 * for an UNLINKING queue not to have any URBs at all, or
1651 * for its first URB not to have any TDs (if it was dequeued
1652 * just as it completed). So it's not easy in any case to
1653 * test whether such queues have advanced. */
1654 if (qh->state != QH_STATE_ACTIVE) {
1655 urbp = NULL;
1656 status = 0;
1658 } else {
1659 urbp = list_entry(qh->queue.next, struct urb_priv, node);
1660 td = list_entry(urbp->td_list.next, struct uhci_td, list);
1661 status = td_status(td);
1662 if (!(status & TD_CTRL_ACTIVE)) {
1664 /* We're okay, the queue has advanced */
1665 qh->wait_expired = 0;
1666 qh->advance_jiffies = jiffies;
1667 goto done;
1669 ret = 0;
1672 /* The queue hasn't advanced; check for timeout */
1673 if (qh->wait_expired)
1674 goto done;
1676 if (time_after(jiffies, qh->advance_jiffies + QH_WAIT_TIMEOUT)) {
1678 /* Detect the Intel bug and work around it */
1679 if (qh->post_td && qh_element(qh) == LINK_TO_TD(qh->post_td)) {
1680 qh->element = qh->post_td->link;
1681 qh->advance_jiffies = jiffies;
1682 ret = 1;
1683 goto done;
1686 qh->wait_expired = 1;
1688 /* If the current URB wants FSBR, unlink it temporarily
1689 * so that we can safely set the next TD to interrupt on
1690 * completion. That way we'll know as soon as the queue
1691 * starts moving again. */
1692 if (urbp && urbp->fsbr && !(status & TD_CTRL_IOC))
1693 uhci_unlink_qh(uhci, qh);
1695 } else {
1696 /* Unmoving but not-yet-expired queues keep FSBR alive */
1697 if (urbp)
1698 uhci_urbp_wants_fsbr(uhci, urbp);
1701 done:
1702 return ret;
1706 * Process events in the schedule, but only in one thread at a time
1708 static void uhci_scan_schedule(struct uhci_hcd *uhci)
1710 int i;
1711 struct uhci_qh *qh;
1713 /* Don't allow re-entrant calls */
1714 if (uhci->scan_in_progress) {
1715 uhci->need_rescan = 1;
1716 return;
1718 uhci->scan_in_progress = 1;
1719 rescan:
1720 uhci->need_rescan = 0;
1721 uhci->fsbr_is_wanted = 0;
1723 uhci_clear_next_interrupt(uhci);
1724 uhci_get_current_frame_number(uhci);
1725 uhci->cur_iso_frame = uhci->frame_number;
1727 /* Go through all the QH queues and process the URBs in each one */
1728 for (i = 0; i < UHCI_NUM_SKELQH - 1; ++i) {
1729 uhci->next_qh = list_entry(uhci->skelqh[i]->node.next,
1730 struct uhci_qh, node);
1731 while ((qh = uhci->next_qh) != uhci->skelqh[i]) {
1732 uhci->next_qh = list_entry(qh->node.next,
1733 struct uhci_qh, node);
1735 if (uhci_advance_check(uhci, qh)) {
1736 uhci_scan_qh(uhci, qh);
1737 if (qh->state == QH_STATE_ACTIVE) {
1738 uhci_urbp_wants_fsbr(uhci,
1739 list_entry(qh->queue.next, struct urb_priv, node));
1745 uhci->last_iso_frame = uhci->cur_iso_frame;
1746 if (uhci->need_rescan)
1747 goto rescan;
1748 uhci->scan_in_progress = 0;
1750 if (uhci->fsbr_is_on && !uhci->fsbr_is_wanted &&
1751 !uhci->fsbr_expiring) {
1752 uhci->fsbr_expiring = 1;
1753 mod_timer(&uhci->fsbr_timer, jiffies + FSBR_OFF_DELAY);
1756 if (list_empty(&uhci->skel_unlink_qh->node))
1757 uhci_clear_next_interrupt(uhci);
1758 else
1759 uhci_set_next_interrupt(uhci);