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[MIPS] IP27: shutdown_bridge_irq: don't free irq.
[pv_ops_mirror.git] / drivers / ata / sata_sil24.c
blob46fbbe7f121c2da1ca115a383800ee9f3525da5c
1 /*
2 * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers
3 *
4 * Copyright 2005 Tejun Heo
5 *
6 * Based on preview driver from Silicon Image.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2, or (at your option) any
11 * later version.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 */
19
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/pci.h>
23 #include <linux/blkdev.h>
24 #include <linux/delay.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/device.h>
28 #include <scsi/scsi_host.h>
29 #include <scsi/scsi_cmnd.h>
30 #include <linux/libata.h>
31
32 #define DRV_NAME "sata_sil24"
33 #define DRV_VERSION "0.9"
34
35 /*
36 * Port request block (PRB) 32 bytes
37 */
38 struct sil24_prb {
39 __le16 ctrl;
40 __le16 prot;
41 __le32 rx_cnt;
42 u8 fis[6 * 4];
43 };
44
45 /*
46 * Scatter gather entry (SGE) 16 bytes
47 */
48 struct sil24_sge {
49 __le64 addr;
50 __le32 cnt;
51 __le32 flags;
52 };
53
54 /*
55 * Port multiplier
56 */
57 struct sil24_port_multiplier {
58 __le32 diag;
59 __le32 sactive;
60 };
61
62 enum {
63 SIL24_HOST_BAR = 0,
64 SIL24_PORT_BAR = 2,
65
66 /*
67 * Global controller registers (128 bytes @ BAR0)
68 */
69 /* 32 bit regs */
70 HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */
71 HOST_CTRL = 0x40,
72 HOST_IRQ_STAT = 0x44,
73 HOST_PHY_CFG = 0x48,
74 HOST_BIST_CTRL = 0x50,
75 HOST_BIST_PTRN = 0x54,
76 HOST_BIST_STAT = 0x58,
77 HOST_MEM_BIST_STAT = 0x5c,
78 HOST_FLASH_CMD = 0x70,
79 /* 8 bit regs */
80 HOST_FLASH_DATA = 0x74,
81 HOST_TRANSITION_DETECT = 0x75,
82 HOST_GPIO_CTRL = 0x76,
83 HOST_I2C_ADDR = 0x78, /* 32 bit */
84 HOST_I2C_DATA = 0x7c,
85 HOST_I2C_XFER_CNT = 0x7e,
86 HOST_I2C_CTRL = 0x7f,
87
88 /* HOST_SLOT_STAT bits */
89 HOST_SSTAT_ATTN = (1 << 31),
90
91 /* HOST_CTRL bits */
92 HOST_CTRL_M66EN = (1 << 16), /* M66EN PCI bus signal */
93 HOST_CTRL_TRDY = (1 << 17), /* latched PCI TRDY */
94 HOST_CTRL_STOP = (1 << 18), /* latched PCI STOP */
95 HOST_CTRL_DEVSEL = (1 << 19), /* latched PCI DEVSEL */
96 HOST_CTRL_REQ64 = (1 << 20), /* latched PCI REQ64 */
97 HOST_CTRL_GLOBAL_RST = (1 << 31), /* global reset */
98
99 /*
100 * Port registers
101 * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
102 */
103 PORT_REGS_SIZE = 0x2000,
104
105 PORT_LRAM = 0x0000, /* 31 LRAM slots and PMP regs */
106 PORT_LRAM_SLOT_SZ = 0x0080, /* 32 bytes PRB + 2 SGE, ACT... */
107
108 PORT_PMP = 0x0f80, /* 8 bytes PMP * 16 (128 bytes) */
109 PORT_PMP_STATUS = 0x0000, /* port device status offset */
110 PORT_PMP_QACTIVE = 0x0004, /* port device QActive offset */
111 PORT_PMP_SIZE = 0x0008, /* 8 bytes per PMP */
112
113 /* 32 bit regs */
114 PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */
115 PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */
116 PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */
117 PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */
118 PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */
119 PORT_ACTIVATE_UPPER_ADDR= 0x101c,
120 PORT_EXEC_FIFO = 0x1020, /* command execution fifo */
121 PORT_CMD_ERR = 0x1024, /* command error number */
122 PORT_FIS_CFG = 0x1028,
123 PORT_FIFO_THRES = 0x102c,
124 /* 16 bit regs */
125 PORT_DECODE_ERR_CNT = 0x1040,
126 PORT_DECODE_ERR_THRESH = 0x1042,
127 PORT_CRC_ERR_CNT = 0x1044,
128 PORT_CRC_ERR_THRESH = 0x1046,
129 PORT_HSHK_ERR_CNT = 0x1048,
130 PORT_HSHK_ERR_THRESH = 0x104a,
131 /* 32 bit regs */
132 PORT_PHY_CFG = 0x1050,
133 PORT_SLOT_STAT = 0x1800,
134 PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */
135 PORT_CONTEXT = 0x1e04,
136 PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */
137 PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */
138 PORT_SCONTROL = 0x1f00,
139 PORT_SSTATUS = 0x1f04,
140 PORT_SERROR = 0x1f08,
141 PORT_SACTIVE = 0x1f0c,
142
143 /* PORT_CTRL_STAT bits */
144 PORT_CS_PORT_RST = (1 << 0), /* port reset */
145 PORT_CS_DEV_RST = (1 << 1), /* device reset */
146 PORT_CS_INIT = (1 << 2), /* port initialize */
147 PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */
148 PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */
149 PORT_CS_PMP_RESUME = (1 << 6), /* PMP resume */
150 PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */
151 PORT_CS_PMP_EN = (1 << 13), /* port multiplier enable */
152 PORT_CS_RDY = (1 << 31), /* port ready to accept commands */
153
154 /* PORT_IRQ_STAT/ENABLE_SET/CLR */
155 /* bits[11:0] are masked */
156 PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */
157 PORT_IRQ_ERROR = (1 << 1), /* command execution error */
158 PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */
159 PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */
160 PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */
161 PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */
162 PORT_IRQ_UNK_FIS = (1 << 6), /* unknown FIS received */
163 PORT_IRQ_DEV_XCHG = (1 << 7), /* device exchanged */
164 PORT_IRQ_8B10B = (1 << 8), /* 8b/10b decode error threshold */
165 PORT_IRQ_CRC = (1 << 9), /* CRC error threshold */
166 PORT_IRQ_HANDSHAKE = (1 << 10), /* handshake error threshold */
167 PORT_IRQ_SDB_NOTIFY = (1 << 11), /* SDB notify received */
168
169 DEF_PORT_IRQ = PORT_IRQ_COMPLETE | PORT_IRQ_ERROR |
170 PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG |
171 PORT_IRQ_UNK_FIS,
172
173 /* bits[27:16] are unmasked (raw) */
174 PORT_IRQ_RAW_SHIFT = 16,
175 PORT_IRQ_MASKED_MASK = 0x7ff,
176 PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT),
177
178 /* ENABLE_SET/CLR specific, intr steering - 2 bit field */
179 PORT_IRQ_STEER_SHIFT = 30,
180 PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT),
181
182 /* PORT_CMD_ERR constants */
183 PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */
184 PORT_CERR_SDB = 2, /* Error bit in SDB FIS */
185 PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */
186 PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */
187 PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */
188 PORT_CERR_DIRECTION = 6, /* Data direction mismatch */
189 PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */
190 PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */
191 PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */
192 PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */
193 PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */
194 PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */
195 PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */
196 PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */
197 PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */
198 PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */
199 PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */
200 PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */
201 PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */
202 PORT_CERR_XFR_MSTABRT = 34, /* PSD ecode 10 - master abort */
203 PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */
204 PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */
205
206 /* bits of PRB control field */
207 PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */
208 PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */
209 PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */
210 PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */
211 PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */
212
213 /* PRB protocol field */
214 PRB_PROT_PACKET = (1 << 0),
215 PRB_PROT_TCQ = (1 << 1),
216 PRB_PROT_NCQ = (1 << 2),
217 PRB_PROT_READ = (1 << 3),
218 PRB_PROT_WRITE = (1 << 4),
219 PRB_PROT_TRANSPARENT = (1 << 5),
220
221 /*
222 * Other constants
223 */
224 SGE_TRM = (1 << 31), /* Last SGE in chain */
225 SGE_LNK = (1 << 30), /* linked list
226 Points to SGT, not SGE */
227 SGE_DRD = (1 << 29), /* discard data read (/dev/null)
228 data address ignored */
229
230 SIL24_MAX_CMDS = 31,
231
232 /* board id */
233 BID_SIL3124 = 0,
234 BID_SIL3132 = 1,
235 BID_SIL3131 = 2,
236
237 /* host flags */
238 SIL24_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
239 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
240 ATA_FLAG_NCQ | ATA_FLAG_SKIP_D2H_BSY |
241 ATA_FLAG_ACPI_SATA,
242 SIL24_FLAG_PCIX_IRQ_WOC = (1 << 24), /* IRQ loss errata on PCI-X */
243
244 IRQ_STAT_4PORTS = 0xf,
245 };
246
247 struct sil24_ata_block {
248 struct sil24_prb prb;
249 struct sil24_sge sge[LIBATA_MAX_PRD];
250 };
251
252 struct sil24_atapi_block {
253 struct sil24_prb prb;
254 u8 cdb[16];
255 struct sil24_sge sge[LIBATA_MAX_PRD - 1];
256 };
257
258 union sil24_cmd_block {
259 struct sil24_ata_block ata;
260 struct sil24_atapi_block atapi;
261 };
262
263 static struct sil24_cerr_info {
264 unsigned int err_mask, action;
265 const char *desc;
266 } sil24_cerr_db[] = {
267 [0] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
268 "device error" },
269 [PORT_CERR_DEV] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
270 "device error via D2H FIS" },
271 [PORT_CERR_SDB] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
272 "device error via SDB FIS" },
273 [PORT_CERR_DATA] = { AC_ERR_ATA_BUS, ATA_EH_SOFTRESET,
274 "error in data FIS" },
275 [PORT_CERR_SEND] = { AC_ERR_ATA_BUS, ATA_EH_SOFTRESET,
276 "failed to transmit command FIS" },
277 [PORT_CERR_INCONSISTENT] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
278 "protocol mismatch" },
279 [PORT_CERR_DIRECTION] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
280 "data directon mismatch" },
281 [PORT_CERR_UNDERRUN] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
282 "ran out of SGEs while writing" },
283 [PORT_CERR_OVERRUN] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
284 "ran out of SGEs while reading" },
285 [PORT_CERR_PKT_PROT] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
286 "invalid data directon for ATAPI CDB" },
287 [PORT_CERR_SGT_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_SOFTRESET,
288 "SGT no on qword boundary" },
289 [PORT_CERR_SGT_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
290 "PCI target abort while fetching SGT" },
291 [PORT_CERR_SGT_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
292 "PCI master abort while fetching SGT" },
293 [PORT_CERR_SGT_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
294 "PCI parity error while fetching SGT" },
295 [PORT_CERR_CMD_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_SOFTRESET,
296 "PRB not on qword boundary" },
297 [PORT_CERR_CMD_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
298 "PCI target abort while fetching PRB" },
299 [PORT_CERR_CMD_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
300 "PCI master abort while fetching PRB" },
301 [PORT_CERR_CMD_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
302 "PCI parity error while fetching PRB" },
303 [PORT_CERR_XFR_UNDEF] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
304 "undefined error while transferring data" },
305 [PORT_CERR_XFR_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
306 "PCI target abort while transferring data" },
307 [PORT_CERR_XFR_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
308 "PCI master abort while transferring data" },
309 [PORT_CERR_XFR_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
310 "PCI parity error while transferring data" },
311 [PORT_CERR_SENDSERVICE] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
312 "FIS received while sending service FIS" },
313 };
314
315 /*
316 * ap->private_data
317 *
318 * The preview driver always returned 0 for status. We emulate it
319 * here from the previous interrupt.
320 */
321 struct sil24_port_priv {
322 union sil24_cmd_block *cmd_block; /* 32 cmd blocks */
323 dma_addr_t cmd_block_dma; /* DMA base addr for them */
324 struct ata_taskfile tf; /* Cached taskfile registers */
325 };
326
327 static void sil24_dev_config(struct ata_device *dev);
328 static u8 sil24_check_status(struct ata_port *ap);
329 static int sil24_scr_read(struct ata_port *ap, unsigned sc_reg, u32 *val);
330 static int sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val);
331 static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
332 static void sil24_qc_prep(struct ata_queued_cmd *qc);
333 static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc);
334 static void sil24_irq_clear(struct ata_port *ap);
335 static void sil24_freeze(struct ata_port *ap);
336 static void sil24_thaw(struct ata_port *ap);
337 static void sil24_error_handler(struct ata_port *ap);
338 static void sil24_post_internal_cmd(struct ata_queued_cmd *qc);
339 static int sil24_port_start(struct ata_port *ap);
340 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
341 #ifdef CONFIG_PM
342 static int sil24_pci_device_resume(struct pci_dev *pdev);
343 #endif
344
345 static const struct pci_device_id sil24_pci_tbl[] = {
346 { PCI_VDEVICE(CMD, 0x3124), BID_SIL3124 },
347 { PCI_VDEVICE(INTEL, 0x3124), BID_SIL3124 },
348 { PCI_VDEVICE(CMD, 0x3132), BID_SIL3132 },
349 { PCI_VDEVICE(CMD, 0x0242), BID_SIL3132 },
350 { PCI_VDEVICE(CMD, 0x3131), BID_SIL3131 },
351 { PCI_VDEVICE(CMD, 0x3531), BID_SIL3131 },
352
353 { } /* terminate list */
354 };
355
356 static struct pci_driver sil24_pci_driver = {
357 .name = DRV_NAME,
358 .id_table = sil24_pci_tbl,
359 .probe = sil24_init_one,
360 .remove = ata_pci_remove_one,
361 #ifdef CONFIG_PM
362 .suspend = ata_pci_device_suspend,
363 .resume = sil24_pci_device_resume,
364 #endif
365 };
366
367 static struct scsi_host_template sil24_sht = {
368 .module = THIS_MODULE,
369 .name = DRV_NAME,
370 .ioctl = ata_scsi_ioctl,
371 .queuecommand = ata_scsi_queuecmd,
372 .change_queue_depth = ata_scsi_change_queue_depth,
373 .can_queue = SIL24_MAX_CMDS,
374 .this_id = ATA_SHT_THIS_ID,
375 .sg_tablesize = LIBATA_MAX_PRD,
376 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
377 .emulated = ATA_SHT_EMULATED,
378 .use_clustering = ATA_SHT_USE_CLUSTERING,
379 .proc_name = DRV_NAME,
380 .dma_boundary = ATA_DMA_BOUNDARY,
381 .slave_configure = ata_scsi_slave_config,
382 .slave_destroy = ata_scsi_slave_destroy,
383 .bios_param = ata_std_bios_param,
384 };
385
386 static const struct ata_port_operations sil24_ops = {
387 .port_disable = ata_port_disable,
388
389 .dev_config = sil24_dev_config,
390
391 .check_status = sil24_check_status,
392 .check_altstatus = sil24_check_status,
393 .dev_select = ata_noop_dev_select,
394
395 .tf_read = sil24_tf_read,
396
397 .qc_prep = sil24_qc_prep,
398 .qc_issue = sil24_qc_issue,
399
400 .irq_clear = sil24_irq_clear,
401 .irq_on = ata_dummy_irq_on,
402 .irq_ack = ata_dummy_irq_ack,
403
404 .scr_read = sil24_scr_read,
405 .scr_write = sil24_scr_write,
406
407 .freeze = sil24_freeze,
408 .thaw = sil24_thaw,
409 .error_handler = sil24_error_handler,
410 .post_internal_cmd = sil24_post_internal_cmd,
411
412 .port_start = sil24_port_start,
413 };
414
415 /*
416 * Use bits 30-31 of port_flags to encode available port numbers.
417 * Current maxium is 4.
418 */
419 #define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30)
420 #define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1)
421
422 static const struct ata_port_info sil24_port_info[] = {
423 /* sil_3124 */
424 {
425 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(4) |
426 SIL24_FLAG_PCIX_IRQ_WOC,
427 .pio_mask = 0x1f, /* pio0-4 */
428 .mwdma_mask = 0x07, /* mwdma0-2 */
429 .udma_mask = ATA_UDMA5, /* udma0-5 */
430 .port_ops = &sil24_ops,
431 },
432 /* sil_3132 */
433 {
434 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(2),
435 .pio_mask = 0x1f, /* pio0-4 */
436 .mwdma_mask = 0x07, /* mwdma0-2 */
437 .udma_mask = ATA_UDMA5, /* udma0-5 */
438 .port_ops = &sil24_ops,
439 },
440 /* sil_3131/sil_3531 */
441 {
442 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(1),
443 .pio_mask = 0x1f, /* pio0-4 */
444 .mwdma_mask = 0x07, /* mwdma0-2 */
445 .udma_mask = ATA_UDMA5, /* udma0-5 */
446 .port_ops = &sil24_ops,
447 },
448 };
449
450 static int sil24_tag(int tag)
451 {
452 if (unlikely(ata_tag_internal(tag)))
453 return 0;
454 return tag;
455 }
456
457 static void sil24_dev_config(struct ata_device *dev)
458 {
459 void __iomem *port = dev->ap->ioaddr.cmd_addr;
460
461 if (dev->cdb_len == 16)
462 writel(PORT_CS_CDB16, port + PORT_CTRL_STAT);
463 else
464 writel(PORT_CS_CDB16, port + PORT_CTRL_CLR);
465 }
466
467 static void sil24_read_tf(struct ata_port *ap, int tag, struct ata_taskfile *tf)
468 {
469 void __iomem *port = ap->ioaddr.cmd_addr;
470 struct sil24_prb __iomem *prb;
471 u8 fis[6 * 4];
472
473 prb = port + PORT_LRAM + sil24_tag(tag) * PORT_LRAM_SLOT_SZ;
474 memcpy_fromio(fis, prb->fis, sizeof(fis));
475 ata_tf_from_fis(fis, tf);
476 }
477
478 static u8 sil24_check_status(struct ata_port *ap)
479 {
480 struct sil24_port_priv *pp = ap->private_data;
481 return pp->tf.command;
482 }
483
484 static int sil24_scr_map[] = {
485 [SCR_CONTROL] = 0,
486 [SCR_STATUS] = 1,
487 [SCR_ERROR] = 2,
488 [SCR_ACTIVE] = 3,
489 };
490
491 static int sil24_scr_read(struct ata_port *ap, unsigned sc_reg, u32 *val)
492 {
493 void __iomem *scr_addr = ap->ioaddr.scr_addr;
494
495 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
496 void __iomem *addr;
497 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
498 *val = readl(scr_addr + sil24_scr_map[sc_reg] * 4);
499 return 0;
500 }
501 return -EINVAL;
502 }
503
504 static int sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val)
505 {
506 void __iomem *scr_addr = ap->ioaddr.scr_addr;
507
508 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
509 void __iomem *addr;
510 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
511 writel(val, scr_addr + sil24_scr_map[sc_reg] * 4);
512 return 0;
513 }
514 return -EINVAL;
515 }
516
517 static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
518 {
519 struct sil24_port_priv *pp = ap->private_data;
520 *tf = pp->tf;
521 }
522
523 static int sil24_init_port(struct ata_port *ap)
524 {
525 void __iomem *port = ap->ioaddr.cmd_addr;
526 u32 tmp;
527
528 writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
529 ata_wait_register(port + PORT_CTRL_STAT,
530 PORT_CS_INIT, PORT_CS_INIT, 10, 100);
531 tmp = ata_wait_register(port + PORT_CTRL_STAT,
532 PORT_CS_RDY, 0, 10, 100);
533
534 if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY)
535 return -EIO;
536 return 0;
537 }
538
539 static int sil24_exec_polled_cmd(struct ata_port *ap, int pmp,
540 const struct ata_taskfile *tf,
541 int is_cmd, u32 ctrl,
542 unsigned long timeout_msec)
543 {
544 void __iomem *port = ap->ioaddr.cmd_addr;
545 struct sil24_port_priv *pp = ap->private_data;
546 struct sil24_prb *prb = &pp->cmd_block[0].ata.prb;
547 dma_addr_t paddr = pp->cmd_block_dma;
548 u32 irq_enabled, irq_mask, irq_stat;
549 int rc;
550
551 prb->ctrl = cpu_to_le16(ctrl);
552 ata_tf_to_fis(tf, pmp, is_cmd, prb->fis);
553
554 /* temporarily plug completion and error interrupts */
555 irq_enabled = readl(port + PORT_IRQ_ENABLE_SET);
556 writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR, port + PORT_IRQ_ENABLE_CLR);
557
558 writel((u32)paddr, port + PORT_CMD_ACTIVATE);
559 writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4);
560
561 irq_mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT;
562 irq_stat = ata_wait_register(port + PORT_IRQ_STAT, irq_mask, 0x0,
563 10, timeout_msec);
564
565 writel(irq_mask, port + PORT_IRQ_STAT); /* clear IRQs */
566 irq_stat >>= PORT_IRQ_RAW_SHIFT;
567
568 if (irq_stat & PORT_IRQ_COMPLETE)
569 rc = 0;
570 else {
571 /* force port into known state */
572 sil24_init_port(ap);
573
574 if (irq_stat & PORT_IRQ_ERROR)
575 rc = -EIO;
576 else
577 rc = -EBUSY;
578 }
579
580 /* restore IRQ enabled */
581 writel(irq_enabled, port + PORT_IRQ_ENABLE_SET);
582
583 return rc;
584 }
585
586 static int sil24_do_softreset(struct ata_port *ap, unsigned int *class,
587 int pmp, unsigned long deadline)
588 {
589 unsigned long timeout_msec = 0;
590 struct ata_taskfile tf;
591 const char *reason;
592 int rc;
593
594 DPRINTK("ENTER\n");
595
596 if (ata_port_offline(ap)) {
597 DPRINTK("PHY reports no device\n");
598 *class = ATA_DEV_NONE;
599 goto out;
600 }
601
602 /* put the port into known state */
603 if (sil24_init_port(ap)) {
604 reason ="port not ready";
605 goto err;
606 }
607
608 /* do SRST */
609 if (time_after(deadline, jiffies))
610 timeout_msec = jiffies_to_msecs(deadline - jiffies);
611
612 ata_tf_init(ap->device, &tf); /* doesn't really matter */
613 rc = sil24_exec_polled_cmd(ap, pmp, &tf, 0, PRB_CTRL_SRST,
614 timeout_msec);
615 if (rc == -EBUSY) {
616 reason = "timeout";
617 goto err;
618 } else if (rc) {
619 reason = "SRST command error";
620 goto err;
621 }
622
623 sil24_read_tf(ap, 0, &tf);
624 *class = ata_dev_classify(&tf);
625
626 if (*class == ATA_DEV_UNKNOWN)
627 *class = ATA_DEV_NONE;
628
629 out:
630 DPRINTK("EXIT, class=%u\n", *class);
631 return 0;
632
633 err:
634 ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason);
635 return -EIO;
636 }
637
638 static int sil24_softreset(struct ata_port *ap, unsigned int *class,
639 unsigned long deadline)
640 {
641 return sil24_do_softreset(ap, class, 0, deadline);
642 }
643
644 static int sil24_hardreset(struct ata_port *ap, unsigned int *class,
645 unsigned long deadline)
646 {
647 void __iomem *port = ap->ioaddr.cmd_addr;
648 const char *reason;
649 int tout_msec, rc;
650 u32 tmp;
651
652 /* sil24 does the right thing(tm) without any protection */
653 sata_set_spd(ap);
654
655 tout_msec = 100;
656 if (ata_port_online(ap))
657 tout_msec = 5000;
658
659 writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
660 tmp = ata_wait_register(port + PORT_CTRL_STAT,
661 PORT_CS_DEV_RST, PORT_CS_DEV_RST, 10, tout_msec);
662
663 /* SStatus oscillates between zero and valid status after
664 * DEV_RST, debounce it.
665 */
666 rc = sata_phy_debounce(ap, sata_deb_timing_long, deadline);
667 if (rc) {
668 reason = "PHY debouncing failed";
669 goto err;
670 }
671
672 if (tmp & PORT_CS_DEV_RST) {
673 if (ata_port_offline(ap))
674 return 0;
675 reason = "link not ready";
676 goto err;
677 }
678
679 /* Sil24 doesn't store signature FIS after hardreset, so we
680 * can't wait for BSY to clear. Some devices take a long time
681 * to get ready and those devices will choke if we don't wait
682 * for BSY clearance here. Tell libata to perform follow-up
683 * softreset.
684 */
685 return -EAGAIN;
686
687 err:
688 ata_port_printk(ap, KERN_ERR, "hardreset failed (%s)\n", reason);
689 return -EIO;
690 }
691
692 static inline void sil24_fill_sg(struct ata_queued_cmd *qc,
693 struct sil24_sge *sge)
694 {
695 struct scatterlist *sg;
696
697 ata_for_each_sg(sg, qc) {
698 sge->addr = cpu_to_le64(sg_dma_address(sg));
699 sge->cnt = cpu_to_le32(sg_dma_len(sg));
700 if (ata_sg_is_last(sg, qc))
701 sge->flags = cpu_to_le32(SGE_TRM);
702 else
703 sge->flags = 0;
704 sge++;
705 }
706 }
707
708 static void sil24_qc_prep(struct ata_queued_cmd *qc)
709 {
710 struct ata_port *ap = qc->ap;
711 struct sil24_port_priv *pp = ap->private_data;
712 union sil24_cmd_block *cb;
713 struct sil24_prb *prb;
714 struct sil24_sge *sge;
715 u16 ctrl = 0;
716
717 cb = &pp->cmd_block[sil24_tag(qc->tag)];
718
719 switch (qc->tf.protocol) {
720 case ATA_PROT_PIO:
721 case ATA_PROT_DMA:
722 case ATA_PROT_NCQ:
723 case ATA_PROT_NODATA:
724 prb = &cb->ata.prb;
725 sge = cb->ata.sge;
726 break;
727
728 case ATA_PROT_ATAPI:
729 case ATA_PROT_ATAPI_DMA:
730 case ATA_PROT_ATAPI_NODATA:
731 prb = &cb->atapi.prb;
732 sge = cb->atapi.sge;
733 memset(cb->atapi.cdb, 0, 32);
734 memcpy(cb->atapi.cdb, qc->cdb, qc->dev->cdb_len);
735
736 if (qc->tf.protocol != ATA_PROT_ATAPI_NODATA) {
737 if (qc->tf.flags & ATA_TFLAG_WRITE)
738 ctrl = PRB_CTRL_PACKET_WRITE;
739 else
740 ctrl = PRB_CTRL_PACKET_READ;
741 }
742 break;
743
744 default:
745 prb = NULL; /* shut up, gcc */
746 sge = NULL;
747 BUG();
748 }
749
750 prb->ctrl = cpu_to_le16(ctrl);
751 ata_tf_to_fis(&qc->tf, 0, 1, prb->fis);
752
753 if (qc->flags & ATA_QCFLAG_DMAMAP)
754 sil24_fill_sg(qc, sge);
755 }
756
757 static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc)
758 {
759 struct ata_port *ap = qc->ap;
760 struct sil24_port_priv *pp = ap->private_data;
761 void __iomem *port = ap->ioaddr.cmd_addr;
762 unsigned int tag = sil24_tag(qc->tag);
763 dma_addr_t paddr;
764 void __iomem *activate;
765
766 paddr = pp->cmd_block_dma + tag * sizeof(*pp->cmd_block);
767 activate = port + PORT_CMD_ACTIVATE + tag * 8;
768
769 writel((u32)paddr, activate);
770 writel((u64)paddr >> 32, activate + 4);
771
772 return 0;
773 }
774
775 static void sil24_irq_clear(struct ata_port *ap)
776 {
777 /* unused */
778 }
779
780 static void sil24_freeze(struct ata_port *ap)
781 {
782 void __iomem *port = ap->ioaddr.cmd_addr;
783
784 /* Port-wide IRQ mask in HOST_CTRL doesn't really work, clear
785 * PORT_IRQ_ENABLE instead.
786 */
787 writel(0xffff, port + PORT_IRQ_ENABLE_CLR);
788 }
789
790 static void sil24_thaw(struct ata_port *ap)
791 {
792 void __iomem *port = ap->ioaddr.cmd_addr;
793 u32 tmp;
794
795 /* clear IRQ */
796 tmp = readl(port + PORT_IRQ_STAT);
797 writel(tmp, port + PORT_IRQ_STAT);
798
799 /* turn IRQ back on */
800 writel(DEF_PORT_IRQ, port + PORT_IRQ_ENABLE_SET);
801 }
802
803 static void sil24_error_intr(struct ata_port *ap)
804 {
805 void __iomem *port = ap->ioaddr.cmd_addr;
806 struct sil24_port_priv *pp = ap->private_data;
807 struct ata_eh_info *ehi = &ap->eh_info;
808 int freeze = 0;
809 u32 irq_stat;
810
811 /* on error, we need to clear IRQ explicitly */
812 irq_stat = readl(port + PORT_IRQ_STAT);
813 writel(irq_stat, port + PORT_IRQ_STAT);
814
815 /* first, analyze and record host port events */
816 ata_ehi_clear_desc(ehi);
817
818 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
819
820 if (irq_stat & (PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG)) {
821 ata_ehi_hotplugged(ehi);
822 ata_ehi_push_desc(ehi, "%s",
823 irq_stat & PORT_IRQ_PHYRDY_CHG ?
824 "PHY RDY changed" : "device exchanged");
825 freeze = 1;
826 }
827
828 if (irq_stat & PORT_IRQ_UNK_FIS) {
829 ehi->err_mask |= AC_ERR_HSM;
830 ehi->action |= ATA_EH_SOFTRESET;
831 ata_ehi_push_desc(ehi, "unknown FIS");
832 freeze = 1;
833 }
834
835 /* deal with command error */
836 if (irq_stat & PORT_IRQ_ERROR) {
837 struct sil24_cerr_info *ci = NULL;
838 unsigned int err_mask = 0, action = 0;
839 struct ata_queued_cmd *qc;
840 u32 cerr;
841
842 /* analyze CMD_ERR */
843 cerr = readl(port + PORT_CMD_ERR);
844 if (cerr < ARRAY_SIZE(sil24_cerr_db))
845 ci = &sil24_cerr_db[cerr];
846
847 if (ci && ci->desc) {
848 err_mask |= ci->err_mask;
849 action |= ci->action;
850 ata_ehi_push_desc(ehi, "%s", ci->desc);
851 } else {
852 err_mask |= AC_ERR_OTHER;
853 action |= ATA_EH_SOFTRESET;
854 ata_ehi_push_desc(ehi, "unknown command error %d",
855 cerr);
856 }
857
858 /* record error info */
859 qc = ata_qc_from_tag(ap, ap->active_tag);
860 if (qc) {
861 sil24_read_tf(ap, qc->tag, &pp->tf);
862 qc->err_mask |= err_mask;
863 } else
864 ehi->err_mask |= err_mask;
865
866 ehi->action |= action;
867 }
868
869 /* freeze or abort */
870 if (freeze)
871 ata_port_freeze(ap);
872 else
873 ata_port_abort(ap);
874 }
875
876 static void sil24_finish_qc(struct ata_queued_cmd *qc)
877 {
878 struct ata_port *ap = qc->ap;
879 struct sil24_port_priv *pp = ap->private_data;
880
881 if (qc->flags & ATA_QCFLAG_RESULT_TF)
882 sil24_read_tf(ap, qc->tag, &pp->tf);
883 }
884
885 static inline void sil24_host_intr(struct ata_port *ap)
886 {
887 void __iomem *port = ap->ioaddr.cmd_addr;
888 u32 slot_stat, qc_active;
889 int rc;
890
891 slot_stat = readl(port + PORT_SLOT_STAT);
892
893 if (unlikely(slot_stat & HOST_SSTAT_ATTN)) {
894 sil24_error_intr(ap);
895 return;
896 }
897
898 if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC)
899 writel(PORT_IRQ_COMPLETE, port + PORT_IRQ_STAT);
900
901 qc_active = slot_stat & ~HOST_SSTAT_ATTN;
902 rc = ata_qc_complete_multiple(ap, qc_active, sil24_finish_qc);
903 if (rc > 0)
904 return;
905 if (rc < 0) {
906 struct ata_eh_info *ehi = &ap->eh_info;
907 ehi->err_mask |= AC_ERR_HSM;
908 ehi->action |= ATA_EH_SOFTRESET;
909 ata_port_freeze(ap);
910 return;
911 }
912
913 if (ata_ratelimit())
914 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
915 "(slot_stat 0x%x active_tag %d sactive 0x%x)\n",
916 slot_stat, ap->active_tag, ap->sactive);
917 }
918
919 static irqreturn_t sil24_interrupt(int irq, void *dev_instance)
920 {
921 struct ata_host *host = dev_instance;
922 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
923 unsigned handled = 0;
924 u32 status;
925 int i;
926
927 status = readl(host_base + HOST_IRQ_STAT);
928
929 if (status == 0xffffffff) {
930 printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, "
931 "PCI fault or device removal?\n");
932 goto out;
933 }
934
935 if (!(status & IRQ_STAT_4PORTS))
936 goto out;
937
938 spin_lock(&host->lock);
939
940 for (i = 0; i < host->n_ports; i++)
941 if (status & (1 << i)) {
942 struct ata_port *ap = host->ports[i];
943 if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
944 sil24_host_intr(ap);
945 handled++;
946 } else
947 printk(KERN_ERR DRV_NAME
948 ": interrupt from disabled port %d\n", i);
949 }
950
951 spin_unlock(&host->lock);
952 out:
953 return IRQ_RETVAL(handled);
954 }
955
956 static void sil24_error_handler(struct ata_port *ap)
957 {
958 struct ata_eh_context *ehc = &ap->eh_context;
959
960 if (sil24_init_port(ap)) {
961 ata_eh_freeze_port(ap);
962 ehc->i.action |= ATA_EH_HARDRESET;
963 }
964
965 /* perform recovery */
966 ata_do_eh(ap, ata_std_prereset, sil24_softreset, sil24_hardreset,
967 ata_std_postreset);
968 }
969
970 static void sil24_post_internal_cmd(struct ata_queued_cmd *qc)
971 {
972 struct ata_port *ap = qc->ap;
973
974 /* make DMA engine forget about the failed command */
975 if (qc->flags & ATA_QCFLAG_FAILED)
976 sil24_init_port(ap);
977 }
978
979 static int sil24_port_start(struct ata_port *ap)
980 {
981 struct device *dev = ap->host->dev;
982 struct sil24_port_priv *pp;
983 union sil24_cmd_block *cb;
984 size_t cb_size = sizeof(*cb) * SIL24_MAX_CMDS;
985 dma_addr_t cb_dma;
986 int rc;
987
988 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
989 if (!pp)
990 return -ENOMEM;
991
992 pp->tf.command = ATA_DRDY;
993
994 cb = dmam_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL);
995 if (!cb)
996 return -ENOMEM;
997 memset(cb, 0, cb_size);
998
999 rc = ata_pad_alloc(ap, dev);
1000 if (rc)
1001 return rc;
1002
1003 pp->cmd_block = cb;
1004 pp->cmd_block_dma = cb_dma;
1005
1006 ap->private_data = pp;
1007
1008 return 0;
1009 }
1010
1011 static void sil24_init_controller(struct ata_host *host)
1012 {
1013 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
1014 void __iomem *port_base = host->iomap[SIL24_PORT_BAR];
1015 u32 tmp;
1016 int i;
1017
1018 /* GPIO off */
1019 writel(0, host_base + HOST_FLASH_CMD);
1020
1021 /* clear global reset & mask interrupts during initialization */
1022 writel(0, host_base + HOST_CTRL);
1023
1024 /* init ports */
1025 for (i = 0; i < host->n_ports; i++) {
1026 void __iomem *port = port_base + i * PORT_REGS_SIZE;
1027
1028 /* Initial PHY setting */
1029 writel(0x20c, port + PORT_PHY_CFG);
1030
1031 /* Clear port RST */
1032 tmp = readl(port + PORT_CTRL_STAT);
1033 if (tmp & PORT_CS_PORT_RST) {
1034 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
1035 tmp = ata_wait_register(port + PORT_CTRL_STAT,
1036 PORT_CS_PORT_RST,
1037 PORT_CS_PORT_RST, 10, 100);
1038 if (tmp & PORT_CS_PORT_RST)
1039 dev_printk(KERN_ERR, host->dev,
1040 "failed to clear port RST\n");
1041 }
1042
1043 /* Configure IRQ WoC */
1044 if (host->ports[0]->flags & SIL24_FLAG_PCIX_IRQ_WOC)
1045 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_STAT);
1046 else
1047 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
1048
1049 /* Zero error counters. */
1050 writel(0x8000, port + PORT_DECODE_ERR_THRESH);
1051 writel(0x8000, port + PORT_CRC_ERR_THRESH);
1052 writel(0x8000, port + PORT_HSHK_ERR_THRESH);
1053 writel(0x0000, port + PORT_DECODE_ERR_CNT);
1054 writel(0x0000, port + PORT_CRC_ERR_CNT);
1055 writel(0x0000, port + PORT_HSHK_ERR_CNT);
1056
1057 /* Always use 64bit activation */
1058 writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);
1059
1060 /* Clear port multiplier enable and resume bits */
1061 writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME,
1062 port + PORT_CTRL_CLR);
1063 }
1064
1065 /* Turn on interrupts */
1066 writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL);
1067 }
1068
1069 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1070 {
1071 static int printed_version = 0;
1072 struct ata_port_info pi = sil24_port_info[ent->driver_data];
1073 const struct ata_port_info *ppi[] = { &pi, NULL };
1074 void __iomem * const *iomap;
1075 struct ata_host *host;
1076 int i, rc;
1077 u32 tmp;
1078
1079 if (!printed_version++)
1080 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1081
1082 /* acquire resources */
1083 rc = pcim_enable_device(pdev);
1084 if (rc)
1085 return rc;
1086
1087 rc = pcim_iomap_regions(pdev,
1088 (1 << SIL24_HOST_BAR) | (1 << SIL24_PORT_BAR),
1089 DRV_NAME);
1090 if (rc)
1091 return rc;
1092 iomap = pcim_iomap_table(pdev);
1093
1094 /* apply workaround for completion IRQ loss on PCI-X errata */
1095 if (pi.flags & SIL24_FLAG_PCIX_IRQ_WOC) {
1096 tmp = readl(iomap[SIL24_HOST_BAR] + HOST_CTRL);
1097 if (tmp & (HOST_CTRL_TRDY | HOST_CTRL_STOP | HOST_CTRL_DEVSEL))
1098 dev_printk(KERN_INFO, &pdev->dev,
1099 "Applying completion IRQ loss on PCI-X "
1100 "errata fix\n");
1101 else
1102 pi.flags &= ~SIL24_FLAG_PCIX_IRQ_WOC;
1103 }
1104
1105 /* allocate and fill host */
1106 host = ata_host_alloc_pinfo(&pdev->dev, ppi,
1107 SIL24_FLAG2NPORTS(ppi[0]->flags));
1108 if (!host)
1109 return -ENOMEM;
1110 host->iomap = iomap;
1111
1112 for (i = 0; i < host->n_ports; i++) {
1113 void __iomem *port = iomap[SIL24_PORT_BAR] + i * PORT_REGS_SIZE;
1114
1115 host->ports[i]->ioaddr.cmd_addr = port;
1116 host->ports[i]->ioaddr.scr_addr = port + PORT_SCONTROL;
1117
1118 ata_std_ports(&host->ports[i]->ioaddr);
1119 }
1120
1121 /* configure and activate the device */
1122 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1123 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1124 if (rc) {
1125 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1126 if (rc) {
1127 dev_printk(KERN_ERR, &pdev->dev,
1128 "64-bit DMA enable failed\n");
1129 return rc;
1130 }
1131 }
1132 } else {
1133 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1134 if (rc) {
1135 dev_printk(KERN_ERR, &pdev->dev,
1136 "32-bit DMA enable failed\n");
1137 return rc;
1138 }
1139 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1140 if (rc) {
1141 dev_printk(KERN_ERR, &pdev->dev,
1142 "32-bit consistent DMA enable failed\n");
1143 return rc;
1144 }
1145 }
1146
1147 sil24_init_controller(host);
1148
1149 pci_set_master(pdev);
1150 return ata_host_activate(host, pdev->irq, sil24_interrupt, IRQF_SHARED,
1151 &sil24_sht);
1152 }
1153
1154 #ifdef CONFIG_PM
1155 static int sil24_pci_device_resume(struct pci_dev *pdev)
1156 {
1157 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1158 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
1159 int rc;
1160
1161 rc = ata_pci_device_do_resume(pdev);
1162 if (rc)
1163 return rc;
1164
1165 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND)
1166 writel(HOST_CTRL_GLOBAL_RST, host_base + HOST_CTRL);
1167
1168 sil24_init_controller(host);
1169
1170 ata_host_resume(host);
1171
1172 return 0;
1173 }
1174 #endif
1175
1176 static int __init sil24_init(void)
1177 {
1178 return pci_register_driver(&sil24_pci_driver);
1179 }
1180
1181 static void __exit sil24_exit(void)
1182 {
1183 pci_unregister_driver(&sil24_pci_driver);
1184 }
1185
1186 MODULE_AUTHOR("Tejun Heo");
1187 MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver");
1188 MODULE_LICENSE("GPL");
1189 MODULE_DEVICE_TABLE(pci, sil24_pci_tbl);
1190
1191 module_init(sil24_init);
1192 module_exit(sil24_exit);
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