2 * Copyright (C) 2004 Matthew Wilcox <matthew@wil.cx>
3 * Copyright (C) 2004 Intel Corp.
5 * This code is released under the GNU General Public License version 2.
9 * mmconfig.c - Low-level direct PCI config space access via MMCONFIG
12 #include <linux/pci.h>
13 #include <linux/init.h>
14 #include <linux/acpi.h>
18 /* Assume systems with more busses have correct MCFG */
19 #define mmcfg_virt_addr ((void __iomem *) fix_to_virt(FIX_PCIE_MCFG))
21 /* The base address of the last MMCONFIG device accessed */
22 static u32 mmcfg_last_accessed_device
;
23 static int mmcfg_last_accessed_cpu
;
26 * Functions for accessing PCI configuration space with MMCONFIG accesses
28 static u32
get_base_addr(unsigned int seg
, int bus
, unsigned devfn
)
30 struct acpi_mcfg_allocation
*cfg
;
33 if (seg
== 0 && bus
< PCI_MMCFG_MAX_CHECK_BUS
&&
34 test_bit(PCI_SLOT(devfn
) + 32*bus
, pci_mmcfg_fallback_slots
))
37 for (cfg_num
= 0; cfg_num
< pci_mmcfg_config_num
; cfg_num
++) {
38 cfg
= &pci_mmcfg_config
[cfg_num
];
39 if (cfg
->pci_segment
== seg
&&
40 (cfg
->start_bus_number
<= bus
) &&
41 (cfg
->end_bus_number
>= bus
))
45 /* Fall back to type 0 */
50 * This is always called under pci_config_lock
52 static void pci_exp_set_dev_base(unsigned int base
, int bus
, int devfn
)
54 u32 dev_base
= base
| (bus
<< 20) | (devfn
<< 12);
55 int cpu
= smp_processor_id();
56 if (dev_base
!= mmcfg_last_accessed_device
||
57 cpu
!= mmcfg_last_accessed_cpu
) {
58 mmcfg_last_accessed_device
= dev_base
;
59 mmcfg_last_accessed_cpu
= cpu
;
60 set_fixmap_nocache(FIX_PCIE_MCFG
, dev_base
);
64 static int pci_mmcfg_read(unsigned int seg
, unsigned int bus
,
65 unsigned int devfn
, int reg
, int len
, u32
*value
)
70 if ((bus
> 255) || (devfn
> 255) || (reg
> 4095)) {
75 base
= get_base_addr(seg
, bus
, devfn
);
77 return pci_conf1_read(seg
,bus
,devfn
,reg
,len
,value
);
79 spin_lock_irqsave(&pci_config_lock
, flags
);
81 pci_exp_set_dev_base(base
, bus
, devfn
);
85 *value
= mmio_config_readb(mmcfg_virt_addr
+ reg
);
88 *value
= mmio_config_readw(mmcfg_virt_addr
+ reg
);
91 *value
= mmio_config_readl(mmcfg_virt_addr
+ reg
);
94 spin_unlock_irqrestore(&pci_config_lock
, flags
);
99 static int pci_mmcfg_write(unsigned int seg
, unsigned int bus
,
100 unsigned int devfn
, int reg
, int len
, u32 value
)
105 if ((bus
> 255) || (devfn
> 255) || (reg
> 4095))
108 base
= get_base_addr(seg
, bus
, devfn
);
110 return pci_conf1_write(seg
,bus
,devfn
,reg
,len
,value
);
112 spin_lock_irqsave(&pci_config_lock
, flags
);
114 pci_exp_set_dev_base(base
, bus
, devfn
);
118 mmio_config_writeb(mmcfg_virt_addr
+ reg
, value
);
121 mmio_config_writew(mmcfg_virt_addr
+ reg
, value
);
124 mmio_config_writel(mmcfg_virt_addr
+ reg
, value
);
127 spin_unlock_irqrestore(&pci_config_lock
, flags
);
132 static struct pci_raw_ops pci_mmcfg
= {
133 .read
= pci_mmcfg_read
,
134 .write
= pci_mmcfg_write
,
137 int __init
pci_mmcfg_arch_reachable(unsigned int seg
, unsigned int bus
,
140 return get_base_addr(seg
, bus
, devfn
) != 0;
143 int __init
pci_mmcfg_arch_init(void)
145 printk(KERN_INFO
"PCI: Using MMCONFIG\n");
146 raw_pci_ops
= &pci_mmcfg
;