arch/i386/kernel/cpu/amd.c

   1 #include <linux/init.h>
   2 #include <linux/bitops.h>
   3 #include <linux/mm.h>
   4 #include <asm/io.h>
   5 #include <asm/processor.h>
   6
   7 #include "cpu.h"
   8
   9 /*
  10  *      B step AMD K6 before B 9730xxxx have hardware bugs that can cause
  11  *      misexecution of code under Linux. Owners of such processors should
  12  *      contact AMD for precise details and a CPU swap.
  13  *
  14  *      See     http://www.multimania.com/poulot/k6bug.html
  15  *              http://www.amd.com/K6/k6docs/revgd.html
  16  *
  17  *      The following test is erm.. interesting. AMD neglected to up
  18  *      the chip setting when fixing the bug but they also tweaked some
  19  *      performance at the same time..
  20  */
  21
  22 extern void vide(void);
  23 __asm__(".align 4\nvide: ret");
  24
  25 static void __cpuinit init_amd(struct cpuinfo_x86 *c)
  26 {
  27         u32 l, h;
  28         int mbytes = num_physpages >> (20-PAGE_SHIFT);
  29         int r;
  30
  31 #ifdef CONFIG_SMP
  32         unsigned long long value;
  33
  34         /* Disable TLB flush filter by setting HWCR.FFDIS on K8
  35          * bit 6 of msr C001_0015
  36          *
  37          * Errata 63 for SH-B3 steppings
  38          * Errata 122 for all steppings (F+ have it disabled by default)
  39          */
  40         if (c->x86 == 15) {
  41                 rdmsrl(MSR_K7_HWCR, value);
  42                 value |= 1 << 6;
  43                 wrmsrl(MSR_K7_HWCR, value);
  44         }
  45 #endif
  46
  47         /*
  48          *      FIXME: We should handle the K5 here. Set up the write
  49          *      range and also turn on MSR 83 bits 4 and 31 (write alloc,
  50          *      no bus pipeline)
  51          */
  52
  53         /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
  54            3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
  55         clear_bit(0*32+31, c->x86_capability);
  56
  57         r = get_model_name(c);
  58
  59         switch(c->x86)
  60         {
  61                 case 4:
  62                 /*
  63                  * General Systems BIOSen alias the cpu frequency registers
  64                  * of the Elan at 0x000df000. Unfortuantly, one of the Linux
  65                  * drivers subsequently pokes it, and changes the CPU speed.
  66                  * Workaround : Remove the unneeded alias.
  67                  */
  68 #define CBAR            (0xfffc) /* Configuration Base Address  (32-bit) */
  69 #define CBAR_ENB        (0x80000000)
  70 #define CBAR_KEY        (0X000000CB)
  71                         if (c->x86_model==9 || c->x86_model == 10) {
  72                                 if (inl (CBAR) & CBAR_ENB)
  73                                         outl (0 | CBAR_KEY, CBAR);
  74                         }
  75                         break;
  76                 case 5:
  77                         if( c->x86_model < 6 )
  78                         {
  79                                 /* Based on AMD doc 20734R - June 2000 */
  80                                 if ( c->x86_model == 0 ) {
  81                                         clear_bit(X86_FEATURE_APIC, c->x86_capability);
  82                                         set_bit(X86_FEATURE_PGE, c->x86_capability);
  83                                 }
  84                                 break;
  85                         }
  86
  87                         if ( c->x86_model == 6 && c->x86_mask == 1 ) {
  88                                 const int K6_BUG_LOOP = 1000000;
  89                                 int n;
  90                                 void (*f_vide)(void);
  91                                 unsigned long d, d2;
  92
  93                                 printk(KERN_INFO "AMD K6 stepping B detected - ");
  94
  95                                 /*
  96                                  * It looks like AMD fixed the 2.6.2 bug and improved indirect
  97                                  * calls at the same time.
  98                                  */
  99
 100                                 n = K6_BUG_LOOP;
 101                                 f_vide = vide;
 102                                 rdtscl(d);
 103                                 while (n--)
 104                                         f_vide();
 105                                 rdtscl(d2);
 106                                 d = d2-d;
 107
 108                                 if (d > 20*K6_BUG_LOOP)
 109                                         printk("system stability may be impaired when more than 32 MB are used.\n");
 110                                 else
 111                                         printk("probably OK (after B9730xxxx).\n");
 112                                 printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n");
 113                         }
 114
 115                         /* K6 with old style WHCR */
 116                         if (c->x86_model < 8 ||
 117                            (c->x86_model== 8 && c->x86_mask < 8)) {
 118                                 /* We can only write allocate on the low 508Mb */
 119                                 if(mbytes>508)
 120                                         mbytes=508;
 121
 122                                 rdmsr(MSR_K6_WHCR, l, h);
 123                                 if ((l&0x0000FFFF)==0) {
 124                                         unsigned long flags;
 125                                         l=(1<<0)|((mbytes/4)<<1);
 126                                         local_irq_save(flags);
 127                                         wbinvd();
 128                                         wrmsr(MSR_K6_WHCR, l, h);
 129                                         local_irq_restore(flags);
 130                                         printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n",
 131                                                 mbytes);
 132                                 }
 133                                 break;
 134                         }
 135
 136                         if ((c->x86_model == 8 && c->x86_mask >7) ||
 137                              c->x86_model == 9 || c->x86_model == 13) {
 138                                 /* The more serious chips .. */
 139
 140                                 if(mbytes>4092)
 141                                         mbytes=4092;
 142
 143                                 rdmsr(MSR_K6_WHCR, l, h);
 144                                 if ((l&0xFFFF0000)==0) {
 145                                         unsigned long flags;
 146                                         l=((mbytes>>2)<<22)|(1<<16);
 147                                         local_irq_save(flags);
 148                                         wbinvd();
 149                                         wrmsr(MSR_K6_WHCR, l, h);
 150                                         local_irq_restore(flags);
 151                                         printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n",
 152                                                 mbytes);
 153                                 }
 154
 155                                 /*  Set MTRR capability flag if appropriate */
 156                                 if (c->x86_model == 13 || c->x86_model == 9 ||
 157                                    (c->x86_model == 8 && c->x86_mask >= 8))
 158                                         set_bit(X86_FEATURE_K6_MTRR, c->x86_capability);
 159                                 break;
 160                         }
 161
 162                         if (c->x86_model == 10) {
 163                                 /* AMD Geode LX is model 10 */
 164                                 /* placeholder for any needed mods */
 165                                 break;
 166                         }
 167                         break;
 168                 case 6: /* An Athlon/Duron */
 169
 170                         /* Bit 15 of Athlon specific MSR 15, needs to be 0
 171                          * to enable SSE on Palomino/Morgan/Barton CPU's.
 172                          * If the BIOS didn't enable it already, enable it here.
 173                          */
 174                         if (c->x86_model >= 6 && c->x86_model <= 10) {
 175                                 if (!cpu_has(c, X86_FEATURE_XMM)) {
 176                                         printk(KERN_INFO "Enabling disabled K7/SSE Support.\n");
 177                                         rdmsr(MSR_K7_HWCR, l, h);
 178                                         l &= ~0x00008000;
 179                                         wrmsr(MSR_K7_HWCR, l, h);
 180                                         set_bit(X86_FEATURE_XMM, c->x86_capability);
 181                                 }
 182                         }
 183
 184                         /* It's been determined by AMD that Athlons since model 8 stepping 1
 185                          * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
 186                          * As per AMD technical note 27212 0.2
 187                          */
 188                         if ((c->x86_model == 8 && c->x86_mask>=1) || (c->x86_model > 8)) {
 189                                 rdmsr(MSR_K7_CLK_CTL, l, h);
 190                                 if ((l & 0xfff00000) != 0x20000000) {
 191                                         printk ("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", l,
 192                                                 ((l & 0x000fffff)|0x20000000));
 193                                         wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
 194                                 }
 195                         }
 196                         break;
 197         }
 198
 199         switch (c->x86) {
 200         case 15:
 201                 set_bit(X86_FEATURE_K8, c->x86_capability);
 202                 break;
 203         case 6:
 204                 set_bit(X86_FEATURE_K7, c->x86_capability);
 205                 break;
 206         }
 207         if (c->x86 >= 6)
 208                 set_bit(X86_FEATURE_FXSAVE_LEAK, c->x86_capability);
 209
 210         display_cacheinfo(c);
 211
 212         if (cpuid_eax(0x80000000) >= 0x80000008) {
 213                 c->x86_max_cores = (cpuid_ecx(0x80000008) & 0xff) + 1;
 214         }
 215
 216         if (cpuid_eax(0x80000000) >= 0x80000007) {
 217                 c->x86_power = cpuid_edx(0x80000007);
 218                 if (c->x86_power & (1<<8))
 219                         set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);
 220         }
 221
 222 #ifdef CONFIG_X86_HT
 223         /*
 224          * On a AMD multi core setup the lower bits of the APIC id
 225          * distingush the cores.
 226          */
 227         if (c->x86_max_cores > 1) {
 228                 int cpu = smp_processor_id();
 229                 unsigned bits = (cpuid_ecx(0x80000008) >> 12) & 0xf;
 230
 231                 if (bits == 0) {
 232                         while ((1 << bits) < c->x86_max_cores)
 233                                 bits++;
 234                 }
 235                 c->cpu_core_id = c->phys_proc_id & ((1<<bits)-1);
 236                 c->phys_proc_id >>= bits;
 237                 printk(KERN_INFO "CPU %d(%d) -> Core %d\n",
 238                        cpu, c->x86_max_cores, c->cpu_core_id);
 239         }
 240 #endif
 241
 242         if (cpuid_eax(0x80000000) >= 0x80000006)
 243                 num_cache_leaves = 3;
 244 }
 245
 246 static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 * c, unsigned int size)
 247 {
 248         /* AMD errata T13 (order #21922) */
 249         if ((c->x86 == 6)) {
 250                 if (c->x86_model == 3 && c->x86_mask == 0)      /* Duron Rev A0 */
 251                         size = 64;
 252                 if (c->x86_model == 4 &&
 253                     (c->x86_mask==0 || c->x86_mask==1)) /* Tbird rev A1/A2 */
 254                         size = 256;
 255         }
 256         return size;
 257 }
 258
 259 static struct cpu_dev amd_cpu_dev __cpuinitdata = {
 260         .c_vendor       = "AMD",
 261         .c_ident        = { "AuthenticAMD" },
 262         .c_models = {
 263                 { .vendor = X86_VENDOR_AMD, .family = 4, .model_names =
 264                   {
 265                           [3] = "486 DX/2",
 266                           [7] = "486 DX/2-WB",
 267                           [8] = "486 DX/4",
 268                           [9] = "486 DX/4-WB",
 269                           [14] = "Am5x86-WT",
 270                           [15] = "Am5x86-WB"
 271                   }
 272                 },
 273         },
 274         .c_init         = init_amd,
 275         .c_size_cache   = amd_size_cache,
 276 };
 277
 278 int __init amd_init_cpu(void)
 279 {
 280         cpu_devs[X86_VENDOR_AMD] = &amd_cpu_dev;
 281         return 0;
 282 }
 283
 284 //early_arch_initcall(amd_init_cpu);
 285
 286 static int __init amd_exit_cpu(void)
 287 {
 288         cpu_devs[X86_VENDOR_AMD] = NULL;
 289         return 0;
 290 }
 291
 292 late_initcall(amd_exit_cpu);