arch/arm/mach-pxa/irq.c

   1 /*
   2  *  linux/arch/arm/mach-pxa/irq.c
   3  *
   4  *  Generic PXA IRQ handling, GPIO IRQ demultiplexing, etc.
   5  *
   6  *  Author:     Nicolas Pitre
   7  *  Created:    Jun 15, 2001
   8  *  Copyright:  MontaVista Software Inc.
   9  *
  10  *  This program is free software; you can redistribute it and/or modify
  11  *  it under the terms of the GNU General Public License version 2 as
  12  *  published by the Free Software Foundation.
  13  */
  14
  15 #include <linux/init.h>
  16 #include <linux/module.h>
  17 #include <linux/interrupt.h>
  18
  19 #include <asm/hardware.h>
  20 #include <asm/irq.h>
  21 #include <asm/mach/irq.h>
  22 #include <asm/arch/pxa-regs.h>
  23
  24 #include "generic.h"
  25
  26
  27 /*
  28  * This is for peripheral IRQs internal to the PXA chip.
  29  */
  30
  31 static void pxa_mask_low_irq(unsigned int irq)
  32 {
  33         ICMR &= ~(1 << irq);
  34 }
  35
  36 static void pxa_unmask_low_irq(unsigned int irq)
  37 {
  38         ICMR |= (1 << irq);
  39 }
  40
  41 static int pxa_set_wake(unsigned int irq, unsigned int on)
  42 {
  43         u32     mask;
  44
  45         switch (irq) {
  46         case IRQ_RTCAlrm:
  47                 mask = PWER_RTC;
  48                 break;
  49 #ifdef CONFIG_PXA27x
  50         /* REVISIT can handle USBH1, USBH2, USB, MSL, USIM, ... */
  51 #endif
  52         default:
  53                 return -EINVAL;
  54         }
  55         if (on)
  56                 PWER |= mask;
  57         else
  58                 PWER &= ~mask;
  59         return 0;
  60 }
  61
  62 static struct irq_chip pxa_internal_chip_low = {
  63         .name           = "SC",
  64         .ack            = pxa_mask_low_irq,
  65         .mask           = pxa_mask_low_irq,
  66         .unmask         = pxa_unmask_low_irq,
  67         .set_wake       = pxa_set_wake,
  68 };
  69
  70 void __init pxa_init_irq_low(void)
  71 {
  72         int irq;
  73
  74         /* disable all IRQs */
  75         ICMR = 0;
  76
  77         /* all IRQs are IRQ, not FIQ */
  78         ICLR = 0;
  79
  80         /* only unmasked interrupts kick us out of idle */
  81         ICCR = 1;
  82
  83         for (irq = PXA_IRQ(0); irq <= PXA_IRQ(31); irq++) {
  84                 set_irq_chip(irq, &pxa_internal_chip_low);
  85                 set_irq_handler(irq, handle_level_irq);
  86                 set_irq_flags(irq, IRQF_VALID);
  87         }
  88 }
  89
  90 #ifdef CONFIG_PXA27x
  91
  92 /*
  93  * This is for the second set of internal IRQs as found on the PXA27x.
  94  */
  95
  96 static void pxa_mask_high_irq(unsigned int irq)
  97 {
  98         ICMR2 &= ~(1 << (irq - 32));
  99 }
 100
 101 static void pxa_unmask_high_irq(unsigned int irq)
 102 {
 103         ICMR2 |= (1 << (irq - 32));
 104 }
 105
 106 static struct irq_chip pxa_internal_chip_high = {
 107         .name           = "SC-hi",
 108         .ack            = pxa_mask_high_irq,
 109         .mask           = pxa_mask_high_irq,
 110         .unmask         = pxa_unmask_high_irq,
 111 };
 112
 113 void __init pxa_init_irq_high(void)
 114 {
 115         int irq;
 116
 117         ICMR2 = 0;
 118         ICLR2 = 0;
 119
 120         for (irq = PXA_IRQ(32); irq < PXA_IRQ(64); irq++) {
 121                 set_irq_chip(irq, &pxa_internal_chip_high);
 122                 set_irq_handler(irq, handle_level_irq);
 123                 set_irq_flags(irq, IRQF_VALID);
 124         }
 125 }
 126 #endif
 127
 128 /* Note that if an input/irq line ever gets changed to an output during
 129  * suspend, the relevant PWER, PRER, and PFER bits should be cleared.
 130  */
 131 #ifdef CONFIG_PXA27x
 132
 133 /* PXA27x:  Various gpios can issue wakeup events.  This logic only
 134  * handles the simple cases, not the WEMUX2 and WEMUX3 options
 135  */
 136 #define PXA27x_GPIO_NOWAKE_MASK \
 137         ((1 << 8) | (1 << 7) | (1 << 6) | (1 << 5) | (1 << 2))
 138 #define WAKEMASK(gpio) \
 139         (((gpio) <= 15) \
 140                 ? ((1 << (gpio)) & ~PXA27x_GPIO_NOWAKE_MASK) \
 141                 : ((gpio == 35) ? (1 << 24) : 0))
 142 #else
 143
 144 /* pxa 210, 250, 255, 26x:  gpios 0..15 can issue wakeups */
 145 #define WAKEMASK(gpio) (((gpio) <= 15) ? (1 << (gpio)) : 0)
 146 #endif
 147
 148 /*
 149  * PXA GPIO edge detection for IRQs:
 150  * IRQs are generated on Falling-Edge, Rising-Edge, or both.
 151  * Use this instead of directly setting GRER/GFER.
 152  */
 153
 154 static long GPIO_IRQ_rising_edge[4];
 155 static long GPIO_IRQ_falling_edge[4];
 156 static long GPIO_IRQ_mask[4];
 157
 158 static int pxa_gpio_irq_type(unsigned int irq, unsigned int type)
 159 {
 160         int gpio, idx;
 161         u32 mask;
 162
 163         gpio = IRQ_TO_GPIO(irq);
 164         idx = gpio >> 5;
 165         mask = WAKEMASK(gpio);
 166
 167         if (type == IRQT_PROBE) {
 168             /* Don't mess with enabled GPIOs using preconfigured edges or
 169                GPIOs set to alternate function or to output during probe */
 170                 if ((GPIO_IRQ_rising_edge[idx] | GPIO_IRQ_falling_edge[idx] | GPDR(gpio)) &
 171                     GPIO_bit(gpio))
 172                         return 0;
 173                 if (GAFR(gpio) & (0x3 << (((gpio) & 0xf)*2)))
 174                         return 0;
 175                 type = __IRQT_RISEDGE | __IRQT_FALEDGE;
 176         }
 177
 178         /* printk(KERN_DEBUG "IRQ%d (GPIO%d): ", irq, gpio); */
 179
 180         pxa_gpio_mode(gpio | GPIO_IN);
 181
 182         if (type & __IRQT_RISEDGE) {
 183                 /* printk("rising "); */
 184                 __set_bit (gpio, GPIO_IRQ_rising_edge);
 185                 PRER |= mask;
 186         } else {
 187                 __clear_bit (gpio, GPIO_IRQ_rising_edge);
 188                 PRER &= ~mask;
 189         }
 190
 191         if (type & __IRQT_FALEDGE) {
 192                 /* printk("falling "); */
 193                 __set_bit (gpio, GPIO_IRQ_falling_edge);
 194                 PFER |= mask;
 195         } else {
 196                 __clear_bit (gpio, GPIO_IRQ_falling_edge);
 197                 PFER &= ~mask;
 198         }
 199
 200         /* printk("edges\n"); */
 201
 202         GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx];
 203         GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx];
 204         return 0;
 205 }
 206
 207 /*
 208  * GPIO IRQs must be acknowledged.  This is for GPIO 0 and 1.
 209  */
 210
 211 static void pxa_ack_low_gpio(unsigned int irq)
 212 {
 213         GEDR0 = (1 << (irq - IRQ_GPIO0));
 214 }
 215
 216 static int pxa_set_gpio_wake(unsigned int irq, unsigned int on)
 217 {
 218         int     gpio = IRQ_TO_GPIO(irq);
 219         u32     mask = WAKEMASK(gpio);
 220
 221         if (!mask)
 222                 return -EINVAL;
 223
 224         if (on)
 225                 PWER |= mask;
 226         else
 227                 PWER &= ~mask;
 228         return 0;
 229 }
 230
 231
 232 static struct irq_chip pxa_low_gpio_chip = {
 233         .name           = "GPIO-l",
 234         .ack            = pxa_ack_low_gpio,
 235         .mask           = pxa_mask_low_irq,
 236         .unmask         = pxa_unmask_low_irq,
 237         .set_type       = pxa_gpio_irq_type,
 238         .set_wake       = pxa_set_gpio_wake,
 239 };
 240
 241 /*
 242  * Demux handler for GPIO>=2 edge detect interrupts
 243  */
 244
 245 static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
 246 {
 247         unsigned int mask;
 248         int loop;
 249
 250         do {
 251                 loop = 0;
 252
 253                 mask = GEDR0 & GPIO_IRQ_mask[0] & ~3;
 254                 if (mask) {
 255                         GEDR0 = mask;
 256                         irq = IRQ_GPIO(2);
 257                         desc = irq_desc + irq;
 258                         mask >>= 2;
 259                         do {
 260                                 if (mask & 1)
 261                                         desc_handle_irq(irq, desc);
 262                                 irq++;
 263                                 desc++;
 264                                 mask >>= 1;
 265                         } while (mask);
 266                         loop = 1;
 267                 }
 268
 269                 mask = GEDR1 & GPIO_IRQ_mask[1];
 270                 if (mask) {
 271                         GEDR1 = mask;
 272                         irq = IRQ_GPIO(32);
 273                         desc = irq_desc + irq;
 274                         do {
 275                                 if (mask & 1)
 276                                         desc_handle_irq(irq, desc);
 277                                 irq++;
 278                                 desc++;
 279                                 mask >>= 1;
 280                         } while (mask);
 281                         loop = 1;
 282                 }
 283
 284                 mask = GEDR2 & GPIO_IRQ_mask[2];
 285                 if (mask) {
 286                         GEDR2 = mask;
 287                         irq = IRQ_GPIO(64);
 288                         desc = irq_desc + irq;
 289                         do {
 290                                 if (mask & 1)
 291                                         desc_handle_irq(irq, desc);
 292                                 irq++;
 293                                 desc++;
 294                                 mask >>= 1;
 295                         } while (mask);
 296                         loop = 1;
 297                 }
 298
 299                 mask = GEDR3 & GPIO_IRQ_mask[3];
 300                 if (mask) {
 301                         GEDR3 = mask;
 302                         irq = IRQ_GPIO(96);
 303                         desc = irq_desc + irq;
 304                         do {
 305                                 if (mask & 1)
 306                                         desc_handle_irq(irq, desc);
 307                                 irq++;
 308                                 desc++;
 309                                 mask >>= 1;
 310                         } while (mask);
 311                         loop = 1;
 312                 }
 313         } while (loop);
 314 }
 315
 316 static void pxa_ack_muxed_gpio(unsigned int irq)
 317 {
 318         int gpio = irq - IRQ_GPIO(2) + 2;
 319         GEDR(gpio) = GPIO_bit(gpio);
 320 }
 321
 322 static void pxa_mask_muxed_gpio(unsigned int irq)
 323 {
 324         int gpio = irq - IRQ_GPIO(2) + 2;
 325         __clear_bit(gpio, GPIO_IRQ_mask);
 326         GRER(gpio) &= ~GPIO_bit(gpio);
 327         GFER(gpio) &= ~GPIO_bit(gpio);
 328 }
 329
 330 static void pxa_unmask_muxed_gpio(unsigned int irq)
 331 {
 332         int gpio = irq - IRQ_GPIO(2) + 2;
 333         int idx = gpio >> 5;
 334         __set_bit(gpio, GPIO_IRQ_mask);
 335         GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx];
 336         GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx];
 337 }
 338
 339 static struct irq_chip pxa_muxed_gpio_chip = {
 340         .name           = "GPIO",
 341         .ack            = pxa_ack_muxed_gpio,
 342         .mask           = pxa_mask_muxed_gpio,
 343         .unmask         = pxa_unmask_muxed_gpio,
 344         .set_type       = pxa_gpio_irq_type,
 345         .set_wake       = pxa_set_gpio_wake,
 346 };
 347
 348 void __init pxa_init_irq_gpio(int gpio_nr)
 349 {
 350         int irq, i;
 351
 352         /* clear all GPIO edge detects */
 353         for (i = 0; i < gpio_nr; i += 32) {
 354                 GFER(i) = 0;
 355                 GRER(i) = 0;
 356                 GEDR(i) = GEDR(i);
 357         }
 358
 359         /* GPIO 0 and 1 must have their mask bit always set */
 360         GPIO_IRQ_mask[0] = 3;
 361
 362         for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) {
 363                 set_irq_chip(irq, &pxa_low_gpio_chip);
 364                 set_irq_handler(irq, handle_edge_irq);
 365                 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
 366         }
 367
 368         for (irq = IRQ_GPIO(2); irq < IRQ_GPIO(gpio_nr); irq++) {
 369                 set_irq_chip(irq, &pxa_muxed_gpio_chip);
 370                 set_irq_handler(irq, handle_edge_irq);
 371                 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
 372         }
 373
 374         /* Install handler for GPIO>=2 edge detect interrupts */
 375         set_irq_chip(IRQ_GPIO_2_x, &pxa_internal_chip_low);
 376         set_irq_chained_handler(IRQ_GPIO_2_x, pxa_gpio_demux_handler);
 377 }