e1000: Add device IDs of blade version of the 82571 quad port
[pv_ops_mirror.git] / arch / arm / mach-s3c2440 / mach-rx3715.c
blobb59e6d39f2f267f8cd09508c729665437df2e424
1 /* linux/arch/arm/mach-s3c2440/mach-rx3715.c
3 * Copyright (c) 2003,2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * http://www.handhelds.org/projects/rx3715.html
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
14 #include <linux/kernel.h>
15 #include <linux/types.h>
16 #include <linux/interrupt.h>
17 #include <linux/list.h>
18 #include <linux/timer.h>
19 #include <linux/init.h>
20 #include <linux/tty.h>
21 #include <linux/console.h>
22 #include <linux/sysdev.h>
23 #include <linux/platform_device.h>
24 #include <linux/serial_core.h>
25 #include <linux/serial.h>
27 #include <linux/mtd/mtd.h>
28 #include <linux/mtd/nand.h>
29 #include <linux/mtd/nand_ecc.h>
30 #include <linux/mtd/partitions.h>
32 #include <asm/mach/arch.h>
33 #include <asm/mach/map.h>
34 #include <asm/mach/irq.h>
36 #include <asm/hardware.h>
37 #include <asm/io.h>
38 #include <asm/irq.h>
39 #include <asm/mach-types.h>
41 #include <asm/plat-s3c/regs-serial.h>
42 #include <asm/arch/regs-gpio.h>
43 #include <asm/arch/regs-lcd.h>
45 #include <asm/arch/h1940.h>
46 #include <asm/plat-s3c/nand.h>
47 #include <asm/arch/fb.h>
49 #include <asm/plat-s3c24xx/clock.h>
50 #include <asm/plat-s3c24xx/devs.h>
51 #include <asm/plat-s3c24xx/cpu.h>
52 #include <asm/plat-s3c24xx/pm.h>
54 static struct map_desc rx3715_iodesc[] __initdata = {
55 /* dump ISA space somewhere unused */
58 .virtual = (u32)S3C24XX_VA_ISA_WORD,
59 .pfn = __phys_to_pfn(S3C2410_CS3),
60 .length = SZ_1M,
61 .type = MT_DEVICE,
62 }, {
63 .virtual = (u32)S3C24XX_VA_ISA_BYTE,
64 .pfn = __phys_to_pfn(S3C2410_CS3),
65 .length = SZ_1M,
66 .type = MT_DEVICE,
71 static struct s3c24xx_uart_clksrc rx3715_serial_clocks[] = {
72 [0] = {
73 .name = "fclk",
74 .divisor = 0,
75 .min_baud = 0,
76 .max_baud = 0,
80 static struct s3c2410_uartcfg rx3715_uartcfgs[] = {
81 [0] = {
82 .hwport = 0,
83 .flags = 0,
84 .ucon = 0x3c5,
85 .ulcon = 0x03,
86 .ufcon = 0x51,
87 .clocks = rx3715_serial_clocks,
88 .clocks_size = ARRAY_SIZE(rx3715_serial_clocks),
90 [1] = {
91 .hwport = 1,
92 .flags = 0,
93 .ucon = 0x3c5,
94 .ulcon = 0x03,
95 .ufcon = 0x00,
96 .clocks = rx3715_serial_clocks,
97 .clocks_size = ARRAY_SIZE(rx3715_serial_clocks),
99 /* IR port */
100 [2] = {
101 .hwport = 2,
102 .uart_flags = UPF_CONS_FLOW,
103 .ucon = 0x3c5,
104 .ulcon = 0x43,
105 .ufcon = 0x51,
106 .clocks = rx3715_serial_clocks,
107 .clocks_size = ARRAY_SIZE(rx3715_serial_clocks),
111 /* framebuffer lcd controller information */
113 static struct s3c2410fb_mach_info rx3715_lcdcfg __initdata = {
114 .regs = {
115 .lcdcon1 = S3C2410_LCDCON1_TFT16BPP | \
116 S3C2410_LCDCON1_TFT | \
117 S3C2410_LCDCON1_CLKVAL(0x0C),
119 .lcdcon2 = S3C2410_LCDCON2_VBPD(5) | \
120 S3C2410_LCDCON2_LINEVAL(319) | \
121 S3C2410_LCDCON2_VFPD(6) | \
122 S3C2410_LCDCON2_VSPW(2),
124 .lcdcon3 = S3C2410_LCDCON3_HBPD(35) | \
125 S3C2410_LCDCON3_HOZVAL(239) | \
126 S3C2410_LCDCON3_HFPD(35),
128 .lcdcon4 = S3C2410_LCDCON4_MVAL(0) | \
129 S3C2410_LCDCON4_HSPW(7),
131 .lcdcon5 = S3C2410_LCDCON5_INVVLINE |
132 S3C2410_LCDCON5_FRM565 |
133 S3C2410_LCDCON5_HWSWP,
136 .lpcsel = 0xf82,
138 .gpccon = 0xaa955699,
139 .gpccon_mask = 0xffc003cc,
140 .gpcup = 0x0000ffff,
141 .gpcup_mask = 0xffffffff,
143 .gpdcon = 0xaa95aaa1,
144 .gpdcon_mask = 0xffc0fff0,
145 .gpdup = 0x0000faff,
146 .gpdup_mask = 0xffffffff,
148 .fixed_syncs = 1,
149 .width = 240,
150 .height = 320,
152 .xres = {
153 .min = 240,
154 .max = 240,
155 .defval = 240,
158 .yres = {
159 .max = 320,
160 .min = 320,
161 .defval = 320,
164 .bpp = {
165 .min = 16,
166 .max = 16,
167 .defval = 16,
171 static struct mtd_partition rx3715_nand_part[] = {
172 [0] = {
173 .name = "Whole Flash",
174 .offset = 0,
175 .size = MTDPART_SIZ_FULL,
176 .mask_flags = MTD_WRITEABLE,
180 static struct s3c2410_nand_set rx3715_nand_sets[] = {
181 [0] = {
182 .name = "Internal",
183 .nr_chips = 1,
184 .nr_partitions = ARRAY_SIZE(rx3715_nand_part),
185 .partitions = rx3715_nand_part,
189 static struct s3c2410_platform_nand rx3715_nand_info = {
190 .tacls = 25,
191 .twrph0 = 50,
192 .twrph1 = 15,
193 .nr_sets = ARRAY_SIZE(rx3715_nand_sets),
194 .sets = rx3715_nand_sets,
197 static struct platform_device *rx3715_devices[] __initdata = {
198 &s3c_device_usb,
199 &s3c_device_lcd,
200 &s3c_device_wdt,
201 &s3c_device_i2c,
202 &s3c_device_iis,
203 &s3c_device_nand,
206 static void __init rx3715_map_io(void)
208 s3c_device_nand.dev.platform_data = &rx3715_nand_info;
210 s3c24xx_init_io(rx3715_iodesc, ARRAY_SIZE(rx3715_iodesc));
211 s3c24xx_init_clocks(16934000);
212 s3c24xx_init_uarts(rx3715_uartcfgs, ARRAY_SIZE(rx3715_uartcfgs));
215 static void __init rx3715_init_irq(void)
217 s3c24xx_init_irq();
220 static void __init rx3715_init_machine(void)
222 #ifdef CONFIG_PM_H1940
223 memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 1024);
224 #endif
225 s3c2410_pm_init();
227 s3c24xx_fb_set_platdata(&rx3715_lcdcfg);
228 platform_add_devices(rx3715_devices, ARRAY_SIZE(rx3715_devices));
231 MACHINE_START(RX3715, "IPAQ-RX3715")
232 /* Maintainer: Ben Dooks <ben@fluff.org> */
233 .phys_io = S3C2410_PA_UART,
234 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
235 .boot_params = S3C2410_SDRAM_PA + 0x100,
236 .map_io = rx3715_map_io,
237 .init_irq = rx3715_init_irq,
238 .init_machine = rx3715_init_machine,
239 .timer = &s3c24xx_timer,
240 MACHINE_END