e1000: Add device IDs of blade version of the 82571 quad port
[pv_ops_mirror.git] / arch / arm / plat-omap / sram.c
blob1f23f0459e5f68dd4c4f363cae87c8ab5f919b5f
1 /*
2 * linux/arch/arm/plat-omap/sram.c
4 * OMAP SRAM detection and management
6 * Copyright (C) 2005 Nokia Corporation
7 * Written by Tony Lindgren <tony@atomide.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/init.h>
18 #include <asm/tlb.h>
19 #include <asm/io.h>
20 #include <asm/cacheflush.h>
22 #include <asm/mach/map.h>
24 #include <asm/arch/sram.h>
25 #include <asm/arch/board.h>
27 #define OMAP1_SRAM_PA 0x20000000
28 #define OMAP1_SRAM_VA 0xd0000000
29 #define OMAP2_SRAM_PA 0x40200000
30 #define OMAP2_SRAM_PUB_PA 0x4020f800
31 #define OMAP2_SRAM_VA 0xd0000000
32 #define OMAP2_SRAM_PUB_VA 0xd0000800
34 #if defined(CONFIG_ARCH_OMAP24XX)
35 #define SRAM_BOOTLOADER_SZ 0x00
36 #else
37 #define SRAM_BOOTLOADER_SZ 0x80
38 #endif
40 #define VA_REQINFOPERM0 IO_ADDRESS(0x68005048)
41 #define VA_READPERM0 IO_ADDRESS(0x68005050)
42 #define VA_WRITEPERM0 IO_ADDRESS(0x68005058)
43 #define VA_CONTROL_STAT IO_ADDRESS(0x480002F8)
44 #define GP_DEVICE 0x300
45 #define TYPE_MASK 0x700
47 #define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1)))
49 static unsigned long omap_sram_start;
50 static unsigned long omap_sram_base;
51 static unsigned long omap_sram_size;
52 static unsigned long omap_sram_ceil;
54 extern unsigned long omapfb_reserve_sram(unsigned long sram_pstart,
55 unsigned long sram_vstart,
56 unsigned long sram_size,
57 unsigned long pstart_avail,
58 unsigned long size_avail);
61 * Depending on the target RAMFS firewall setup, the public usable amount of
62 * SRAM varies. The default accessible size for all device types is 2k. A GP
63 * device allows ARM11 but not other initiators for full size. This
64 * functionality seems ok until some nice security API happens.
66 static int is_sram_locked(void)
68 int type = 0;
70 if (cpu_is_omap242x())
71 type = __raw_readl(VA_CONTROL_STAT) & TYPE_MASK;
73 if (type == GP_DEVICE) {
74 /* RAMFW: R/W access to all initiators for all qualifier sets */
75 if (cpu_is_omap242x()) {
76 __raw_writel(0xFF, VA_REQINFOPERM0); /* all q-vects */
77 __raw_writel(0xCFDE, VA_READPERM0); /* all i-read */
78 __raw_writel(0xCFDE, VA_WRITEPERM0); /* all i-write */
80 return 0;
81 } else
82 return 1; /* assume locked with no PPA or security driver */
86 * The amount of SRAM depends on the core type.
87 * Note that we cannot try to test for SRAM here because writes
88 * to secure SRAM will hang the system. Also the SRAM is not
89 * yet mapped at this point.
91 void __init omap_detect_sram(void)
93 unsigned long reserved;
95 if (cpu_is_omap24xx()) {
96 if (is_sram_locked()) {
97 omap_sram_base = OMAP2_SRAM_PUB_VA;
98 omap_sram_start = OMAP2_SRAM_PUB_PA;
99 omap_sram_size = 0x800; /* 2K */
100 } else {
101 omap_sram_base = OMAP2_SRAM_VA;
102 omap_sram_start = OMAP2_SRAM_PA;
103 if (cpu_is_omap242x())
104 omap_sram_size = 0xa0000; /* 640K */
105 else if (cpu_is_omap243x())
106 omap_sram_size = 0x10000; /* 64K */
108 } else {
109 omap_sram_base = OMAP1_SRAM_VA;
110 omap_sram_start = OMAP1_SRAM_PA;
112 if (cpu_is_omap730())
113 omap_sram_size = 0x32000; /* 200K */
114 else if (cpu_is_omap15xx())
115 omap_sram_size = 0x30000; /* 192K */
116 else if (cpu_is_omap1610() || cpu_is_omap1621() ||
117 cpu_is_omap1710())
118 omap_sram_size = 0x4000; /* 16K */
119 else if (cpu_is_omap1611())
120 omap_sram_size = 0x3e800; /* 250K */
121 else {
122 printk(KERN_ERR "Could not detect SRAM size\n");
123 omap_sram_size = 0x4000;
126 reserved = omapfb_reserve_sram(omap_sram_start, omap_sram_base,
127 omap_sram_size,
128 omap_sram_start + SRAM_BOOTLOADER_SZ,
129 omap_sram_size - SRAM_BOOTLOADER_SZ);
130 omap_sram_size -= reserved;
131 omap_sram_ceil = omap_sram_base + omap_sram_size;
134 static struct map_desc omap_sram_io_desc[] __initdata = {
135 { /* .length gets filled in at runtime */
136 .virtual = OMAP1_SRAM_VA,
137 .pfn = __phys_to_pfn(OMAP1_SRAM_PA),
138 .type = MT_MEMORY
143 * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
145 void __init omap_map_sram(void)
147 unsigned long base;
149 if (omap_sram_size == 0)
150 return;
152 if (cpu_is_omap24xx()) {
153 omap_sram_io_desc[0].virtual = OMAP2_SRAM_VA;
155 base = OMAP2_SRAM_PA;
156 base = ROUND_DOWN(base, PAGE_SIZE);
157 omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
160 omap_sram_io_desc[0].length = 1024 * 1024; /* Use section desc */
161 iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc));
163 printk(KERN_INFO "SRAM: Mapped pa 0x%08lx to va 0x%08lx size: 0x%lx\n",
164 __pfn_to_phys(omap_sram_io_desc[0].pfn),
165 omap_sram_io_desc[0].virtual,
166 omap_sram_io_desc[0].length);
169 * Normally devicemaps_init() would flush caches and tlb after
170 * mdesc->map_io(), but since we're called from map_io(), we
171 * must do it here.
173 local_flush_tlb_all();
174 flush_cache_all();
177 * Looks like we need to preserve some bootloader code at the
178 * beginning of SRAM for jumping to flash for reboot to work...
180 memset((void *)omap_sram_base + SRAM_BOOTLOADER_SZ, 0,
181 omap_sram_size - SRAM_BOOTLOADER_SZ);
184 void * omap_sram_push(void * start, unsigned long size)
186 if (size > (omap_sram_ceil - (omap_sram_base + SRAM_BOOTLOADER_SZ))) {
187 printk(KERN_ERR "Not enough space in SRAM\n");
188 return NULL;
191 omap_sram_ceil -= size;
192 omap_sram_ceil = ROUND_DOWN(omap_sram_ceil, sizeof(void *));
193 memcpy((void *)omap_sram_ceil, start, size);
195 return (void *)omap_sram_ceil;
198 static void omap_sram_error(void)
200 panic("Uninitialized SRAM function\n");
203 #ifdef CONFIG_ARCH_OMAP1
205 static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl);
207 void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl)
209 if (!_omap_sram_reprogram_clock)
210 omap_sram_error();
212 return _omap_sram_reprogram_clock(dpllctl, ckctl);
215 int __init omap1_sram_init(void)
217 _omap_sram_reprogram_clock = omap_sram_push(sram_reprogram_clock,
218 sram_reprogram_clock_sz);
220 return 0;
223 #else
224 #define omap1_sram_init() do {} while (0)
225 #endif
227 #ifdef CONFIG_ARCH_OMAP2
229 static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
230 u32 base_cs, u32 force_unlock);
232 void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
233 u32 base_cs, u32 force_unlock)
235 if (!_omap2_sram_ddr_init)
236 omap_sram_error();
238 return _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl,
239 base_cs, force_unlock);
242 static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val,
243 u32 mem_type);
245 void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type)
247 if (!_omap2_sram_reprogram_sdrc)
248 omap_sram_error();
250 return _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type);
253 static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
255 u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
257 if (!_omap2_set_prcm)
258 omap_sram_error();
260 return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass);
263 int __init omap2_sram_init(void)
265 _omap2_sram_ddr_init = omap_sram_push(sram_ddr_init, sram_ddr_init_sz);
267 _omap2_sram_reprogram_sdrc = omap_sram_push(sram_reprogram_sdrc,
268 sram_reprogram_sdrc_sz);
269 _omap2_set_prcm = omap_sram_push(sram_set_prcm, sram_set_prcm_sz);
271 return 0;
273 #else
274 #define omap2_sram_init() do {} while (0)
275 #endif
277 int __init omap_sram_init(void)
279 omap_detect_sram();
280 omap_map_sram();
282 if (!cpu_is_omap24xx())
283 omap1_sram_init();
284 else
285 omap2_sram_init();
287 return 0;