e1000: Add device IDs of blade version of the 82571 quad port
[pv_ops_mirror.git] / arch / avr32 / mach-at32ap / hsmc.h
blobd1d48e26e39378702eee37b4d7e148ddf76306ea
1 /*
2 * Register definitions for Atmel Static Memory Controller (SMC)
4 * Copyright (C) 2006 Atmel Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10 #ifndef __ASM_AVR32_HSMC_H__
11 #define __ASM_AVR32_HSMC_H__
13 /* HSMC register offsets */
14 #define HSMC_SETUP0 0x0000
15 #define HSMC_PULSE0 0x0004
16 #define HSMC_CYCLE0 0x0008
17 #define HSMC_MODE0 0x000c
18 #define HSMC_SETUP1 0x0010
19 #define HSMC_PULSE1 0x0014
20 #define HSMC_CYCLE1 0x0018
21 #define HSMC_MODE1 0x001c
22 #define HSMC_SETUP2 0x0020
23 #define HSMC_PULSE2 0x0024
24 #define HSMC_CYCLE2 0x0028
25 #define HSMC_MODE2 0x002c
26 #define HSMC_SETUP3 0x0030
27 #define HSMC_PULSE3 0x0034
28 #define HSMC_CYCLE3 0x0038
29 #define HSMC_MODE3 0x003c
30 #define HSMC_SETUP4 0x0040
31 #define HSMC_PULSE4 0x0044
32 #define HSMC_CYCLE4 0x0048
33 #define HSMC_MODE4 0x004c
34 #define HSMC_SETUP5 0x0050
35 #define HSMC_PULSE5 0x0054
36 #define HSMC_CYCLE5 0x0058
37 #define HSMC_MODE5 0x005c
39 /* Bitfields in SETUP0 */
40 #define HSMC_NWE_SETUP_OFFSET 0
41 #define HSMC_NWE_SETUP_SIZE 6
42 #define HSMC_NCS_WR_SETUP_OFFSET 8
43 #define HSMC_NCS_WR_SETUP_SIZE 6
44 #define HSMC_NRD_SETUP_OFFSET 16
45 #define HSMC_NRD_SETUP_SIZE 6
46 #define HSMC_NCS_RD_SETUP_OFFSET 24
47 #define HSMC_NCS_RD_SETUP_SIZE 6
49 /* Bitfields in PULSE0 */
50 #define HSMC_NWE_PULSE_OFFSET 0
51 #define HSMC_NWE_PULSE_SIZE 7
52 #define HSMC_NCS_WR_PULSE_OFFSET 8
53 #define HSMC_NCS_WR_PULSE_SIZE 7
54 #define HSMC_NRD_PULSE_OFFSET 16
55 #define HSMC_NRD_PULSE_SIZE 7
56 #define HSMC_NCS_RD_PULSE_OFFSET 24
57 #define HSMC_NCS_RD_PULSE_SIZE 7
59 /* Bitfields in CYCLE0 */
60 #define HSMC_NWE_CYCLE_OFFSET 0
61 #define HSMC_NWE_CYCLE_SIZE 9
62 #define HSMC_NRD_CYCLE_OFFSET 16
63 #define HSMC_NRD_CYCLE_SIZE 9
65 /* Bitfields in MODE0 */
66 #define HSMC_READ_MODE_OFFSET 0
67 #define HSMC_READ_MODE_SIZE 1
68 #define HSMC_WRITE_MODE_OFFSET 1
69 #define HSMC_WRITE_MODE_SIZE 1
70 #define HSMC_EXNW_MODE_OFFSET 4
71 #define HSMC_EXNW_MODE_SIZE 2
72 #define HSMC_BAT_OFFSET 8
73 #define HSMC_BAT_SIZE 1
74 #define HSMC_DBW_OFFSET 12
75 #define HSMC_DBW_SIZE 2
76 #define HSMC_TDF_CYCLES_OFFSET 16
77 #define HSMC_TDF_CYCLES_SIZE 4
78 #define HSMC_TDF_MODE_OFFSET 20
79 #define HSMC_TDF_MODE_SIZE 1
80 #define HSMC_PMEN_OFFSET 24
81 #define HSMC_PMEN_SIZE 1
82 #define HSMC_PS_OFFSET 28
83 #define HSMC_PS_SIZE 2
85 /* Constants for READ_MODE */
86 #define HSMC_READ_MODE_NCS_CONTROLLED 0
87 #define HSMC_READ_MODE_NRD_CONTROLLED 1
89 /* Constants for WRITE_MODE */
90 #define HSMC_WRITE_MODE_NCS_CONTROLLED 0
91 #define HSMC_WRITE_MODE_NWE_CONTROLLED 1
93 /* Constants for EXNW_MODE */
94 #define HSMC_EXNW_MODE_DISABLED 0
95 #define HSMC_EXNW_MODE_RESERVED 1
96 #define HSMC_EXNW_MODE_FROZEN 2
97 #define HSMC_EXNW_MODE_READY 3
99 /* Constants for BAT */
100 #define HSMC_BAT_BYTE_SELECT 0
101 #define HSMC_BAT_BYTE_WRITE 1
103 /* Constants for DBW */
104 #define HSMC_DBW_8_BITS 0
105 #define HSMC_DBW_16_BITS 1
106 #define HSMC_DBW_32_BITS 2
108 /* Bit manipulation macros */
109 #define HSMC_BIT(name) \
110 (1 << HSMC_##name##_OFFSET)
111 #define HSMC_BF(name,value) \
112 (((value) & ((1 << HSMC_##name##_SIZE) - 1)) \
113 << HSMC_##name##_OFFSET)
114 #define HSMC_BFEXT(name,value) \
115 (((value) >> HSMC_##name##_OFFSET) \
116 & ((1 << HSMC_##name##_SIZE) - 1))
117 #define HSMC_BFINS(name,value,old) \
118 (((old) & ~(((1 << HSMC_##name##_SIZE) - 1) \
119 << HSMC_##name##_OFFSET)) | HSMC_BF(name,value))
121 /* Register access macros */
122 #define hsmc_readl(port,reg) \
123 __raw_readl((port)->regs + HSMC_##reg)
124 #define hsmc_writel(port,reg,value) \
125 __raw_writel((value), (port)->regs + HSMC_##reg)
127 #endif /* __ASM_AVR32_HSMC_H__ */