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ACPI: Make _OSI(Linux) a special case
[pv_ops_mirror.git] / drivers / net / wireless / zd1211rw / zd_chip.c
blob95b4a2a26707b2f85cf6755d07092975450aa2a8
1 /* zd_chip.c
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License as published by
5 * the Free Software Foundation; either version 2 of the License, or
6 * (at your option) any later version.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
16 */
17
18 /* This file implements all the hardware specific functions for the ZD1211
19 * and ZD1211B chips. Support for the ZD1211B was possible after Timothy
20 * Legge sent me a ZD1211B device. Thank you Tim. -- Uli
21 */
22
23 #include <linux/kernel.h>
24 #include <linux/errno.h>
25
26 #include "zd_def.h"
27 #include "zd_chip.h"
28 #include "zd_ieee80211.h"
29 #include "zd_mac.h"
30 #include "zd_rf.h"
31 #include "zd_util.h"
32
33 void zd_chip_init(struct zd_chip *chip,
34 struct net_device *netdev,
35 struct usb_interface *intf)
36 {
37 memset(chip, 0, sizeof(*chip));
38 mutex_init(&chip->mutex);
39 zd_usb_init(&chip->usb, netdev, intf);
40 zd_rf_init(&chip->rf);
41 }
42
43 void zd_chip_clear(struct zd_chip *chip)
44 {
45 ZD_ASSERT(!mutex_is_locked(&chip->mutex));
46 zd_usb_clear(&chip->usb);
47 zd_rf_clear(&chip->rf);
48 mutex_destroy(&chip->mutex);
49 ZD_MEMCLEAR(chip, sizeof(*chip));
50 }
51
52 static int scnprint_mac_oui(const u8 *addr, char *buffer, size_t size)
53 {
54 return scnprintf(buffer, size, "%02x-%02x-%02x",
55 addr[0], addr[1], addr[2]);
56 }
57
58 /* Prints an identifier line, which will support debugging. */
59 static int scnprint_id(struct zd_chip *chip, char *buffer, size_t size)
60 {
61 int i = 0;
62
63 i = scnprintf(buffer, size, "zd1211%s chip ",
64 chip->is_zd1211b ? "b" : "");
65 i += zd_usb_scnprint_id(&chip->usb, buffer+i, size-i);
66 i += scnprintf(buffer+i, size-i, " ");
67 i += scnprint_mac_oui(chip->e2p_mac, buffer+i, size-i);
68 i += scnprintf(buffer+i, size-i, " ");
69 i += zd_rf_scnprint_id(&chip->rf, buffer+i, size-i);
70 i += scnprintf(buffer+i, size-i, " pa%1x %c%c%c%c%c", chip->pa_type,
71 chip->patch_cck_gain ? 'g' : '-',
72 chip->patch_cr157 ? '7' : '-',
73 chip->patch_6m_band_edge ? '6' : '-',
74 chip->new_phy_layout ? 'N' : '-',
75 chip->al2230s_bit ? 'S' : '-');
76 return i;
77 }
78
79 static void print_id(struct zd_chip *chip)
80 {
81 char buffer[80];
82
83 scnprint_id(chip, buffer, sizeof(buffer));
84 buffer[sizeof(buffer)-1] = 0;
85 dev_info(zd_chip_dev(chip), "%s\n", buffer);
86 }
87
88 static zd_addr_t inc_addr(zd_addr_t addr)
89 {
90 u16 a = (u16)addr;
91 /* Control registers use byte addressing, but everything else uses word
92 * addressing. */
93 if ((a & 0xf000) == CR_START)
94 a += 2;
95 else
96 a += 1;
97 return (zd_addr_t)a;
98 }
99
100 /* Read a variable number of 32-bit values. Parameter count is not allowed to
101 * exceed USB_MAX_IOREAD32_COUNT.
102 */
103 int zd_ioread32v_locked(struct zd_chip *chip, u32 *values, const zd_addr_t *addr,
104 unsigned int count)
105 {
106 int r;
107 int i;
108 zd_addr_t *a16 = (zd_addr_t *)NULL;
109 u16 *v16;
110 unsigned int count16;
111
112 if (count > USB_MAX_IOREAD32_COUNT)
113 return -EINVAL;
114
115 /* Allocate a single memory block for values and addresses. */
116 count16 = 2*count;
117 a16 = (zd_addr_t *) kmalloc(count16 * (sizeof(zd_addr_t) + sizeof(u16)),
118 GFP_KERNEL);
119 if (!a16) {
120 dev_dbg_f(zd_chip_dev(chip),
121 "error ENOMEM in allocation of a16\n");
122 r = -ENOMEM;
123 goto out;
124 }
125 v16 = (u16 *)(a16 + count16);
126
127 for (i = 0; i < count; i++) {
128 int j = 2*i;
129 /* We read the high word always first. */
130 a16[j] = inc_addr(addr[i]);
131 a16[j+1] = addr[i];
132 }
133
134 r = zd_ioread16v_locked(chip, v16, a16, count16);
135 if (r) {
136 dev_dbg_f(zd_chip_dev(chip),
137 "error: zd_ioread16v_locked. Error number %d\n", r);
138 goto out;
139 }
140
141 for (i = 0; i < count; i++) {
142 int j = 2*i;
143 values[i] = (v16[j] << 16) | v16[j+1];
144 }
145
146 out:
147 kfree((void *)a16);
148 return r;
149 }
150
151 int _zd_iowrite32v_locked(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs,
152 unsigned int count)
153 {
154 int i, j, r;
155 struct zd_ioreq16 *ioreqs16;
156 unsigned int count16;
157
158 ZD_ASSERT(mutex_is_locked(&chip->mutex));
159
160 if (count == 0)
161 return 0;
162 if (count > USB_MAX_IOWRITE32_COUNT)
163 return -EINVAL;
164
165 /* Allocate a single memory block for values and addresses. */
166 count16 = 2*count;
167 ioreqs16 = kmalloc(count16 * sizeof(struct zd_ioreq16), GFP_KERNEL);
168 if (!ioreqs16) {
169 r = -ENOMEM;
170 dev_dbg_f(zd_chip_dev(chip),
171 "error %d in ioreqs16 allocation\n", r);
172 goto out;
173 }
174
175 for (i = 0; i < count; i++) {
176 j = 2*i;
177 /* We write the high word always first. */
178 ioreqs16[j].value = ioreqs[i].value >> 16;
179 ioreqs16[j].addr = inc_addr(ioreqs[i].addr);
180 ioreqs16[j+1].value = ioreqs[i].value;
181 ioreqs16[j+1].addr = ioreqs[i].addr;
182 }
183
184 r = zd_usb_iowrite16v(&chip->usb, ioreqs16, count16);
185 #ifdef DEBUG
186 if (r) {
187 dev_dbg_f(zd_chip_dev(chip),
188 "error %d in zd_usb_write16v\n", r);
189 }
190 #endif /* DEBUG */
191 out:
192 kfree(ioreqs16);
193 return r;
194 }
195
196 int zd_iowrite16a_locked(struct zd_chip *chip,
197 const struct zd_ioreq16 *ioreqs, unsigned int count)
198 {
199 int r;
200 unsigned int i, j, t, max;
201
202 ZD_ASSERT(mutex_is_locked(&chip->mutex));
203 for (i = 0; i < count; i += j + t) {
204 t = 0;
205 max = count-i;
206 if (max > USB_MAX_IOWRITE16_COUNT)
207 max = USB_MAX_IOWRITE16_COUNT;
208 for (j = 0; j < max; j++) {
209 if (!ioreqs[i+j].addr) {
210 t = 1;
211 break;
212 }
213 }
214
215 r = zd_usb_iowrite16v(&chip->usb, &ioreqs[i], j);
216 if (r) {
217 dev_dbg_f(zd_chip_dev(chip),
218 "error zd_usb_iowrite16v. Error number %d\n",
219 r);
220 return r;
221 }
222 }
223
224 return 0;
225 }
226
227 /* Writes a variable number of 32 bit registers. The functions will split
228 * that in several USB requests. A split can be forced by inserting an IO
229 * request with an zero address field.
230 */
231 int zd_iowrite32a_locked(struct zd_chip *chip,
232 const struct zd_ioreq32 *ioreqs, unsigned int count)
233 {
234 int r;
235 unsigned int i, j, t, max;
236
237 for (i = 0; i < count; i += j + t) {
238 t = 0;
239 max = count-i;
240 if (max > USB_MAX_IOWRITE32_COUNT)
241 max = USB_MAX_IOWRITE32_COUNT;
242 for (j = 0; j < max; j++) {
243 if (!ioreqs[i+j].addr) {
244 t = 1;
245 break;
246 }
247 }
248
249 r = _zd_iowrite32v_locked(chip, &ioreqs[i], j);
250 if (r) {
251 dev_dbg_f(zd_chip_dev(chip),
252 "error _zd_iowrite32v_locked."
253 " Error number %d\n", r);
254 return r;
255 }
256 }
257
258 return 0;
259 }
260
261 int zd_ioread16(struct zd_chip *chip, zd_addr_t addr, u16 *value)
262 {
263 int r;
264
265 mutex_lock(&chip->mutex);
266 r = zd_ioread16_locked(chip, value, addr);
267 mutex_unlock(&chip->mutex);
268 return r;
269 }
270
271 int zd_ioread32(struct zd_chip *chip, zd_addr_t addr, u32 *value)
272 {
273 int r;
274
275 mutex_lock(&chip->mutex);
276 r = zd_ioread32_locked(chip, value, addr);
277 mutex_unlock(&chip->mutex);
278 return r;
279 }
280
281 int zd_iowrite16(struct zd_chip *chip, zd_addr_t addr, u16 value)
282 {
283 int r;
284
285 mutex_lock(&chip->mutex);
286 r = zd_iowrite16_locked(chip, value, addr);
287 mutex_unlock(&chip->mutex);
288 return r;
289 }
290
291 int zd_iowrite32(struct zd_chip *chip, zd_addr_t addr, u32 value)
292 {
293 int r;
294
295 mutex_lock(&chip->mutex);
296 r = zd_iowrite32_locked(chip, value, addr);
297 mutex_unlock(&chip->mutex);
298 return r;
299 }
300
301 int zd_ioread32v(struct zd_chip *chip, const zd_addr_t *addresses,
302 u32 *values, unsigned int count)
303 {
304 int r;
305
306 mutex_lock(&chip->mutex);
307 r = zd_ioread32v_locked(chip, values, addresses, count);
308 mutex_unlock(&chip->mutex);
309 return r;
310 }
311
312 int zd_iowrite32a(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs,
313 unsigned int count)
314 {
315 int r;
316
317 mutex_lock(&chip->mutex);
318 r = zd_iowrite32a_locked(chip, ioreqs, count);
319 mutex_unlock(&chip->mutex);
320 return r;
321 }
322
323 static int read_pod(struct zd_chip *chip, u8 *rf_type)
324 {
325 int r;
326 u32 value;
327
328 ZD_ASSERT(mutex_is_locked(&chip->mutex));
329 r = zd_ioread32_locked(chip, &value, E2P_POD);
330 if (r)
331 goto error;
332 dev_dbg_f(zd_chip_dev(chip), "E2P_POD %#010x\n", value);
333
334 /* FIXME: AL2230 handling (Bit 7 in POD) */
335 *rf_type = value & 0x0f;
336 chip->pa_type = (value >> 16) & 0x0f;
337 chip->patch_cck_gain = (value >> 8) & 0x1;
338 chip->patch_cr157 = (value >> 13) & 0x1;
339 chip->patch_6m_band_edge = (value >> 21) & 0x1;
340 chip->new_phy_layout = (value >> 31) & 0x1;
341 chip->al2230s_bit = (value >> 7) & 0x1;
342 chip->link_led = ((value >> 4) & 1) ? LED1 : LED2;
343 chip->supports_tx_led = 1;
344 if (value & (1 << 24)) { /* LED scenario */
345 if (value & (1 << 29))
346 chip->supports_tx_led = 0;
347 }
348
349 dev_dbg_f(zd_chip_dev(chip),
350 "RF %s %#01x PA type %#01x patch CCK %d patch CR157 %d "
351 "patch 6M %d new PHY %d link LED%d tx led %d\n",
352 zd_rf_name(*rf_type), *rf_type,
353 chip->pa_type, chip->patch_cck_gain,
354 chip->patch_cr157, chip->patch_6m_band_edge,
355 chip->new_phy_layout,
356 chip->link_led == LED1 ? 1 : 2,
357 chip->supports_tx_led);
358 return 0;
359 error:
360 *rf_type = 0;
361 chip->pa_type = 0;
362 chip->patch_cck_gain = 0;
363 chip->patch_cr157 = 0;
364 chip->patch_6m_band_edge = 0;
365 chip->new_phy_layout = 0;
366 return r;
367 }
368
369 static int _read_mac_addr(struct zd_chip *chip, u8 *mac_addr,
370 const zd_addr_t *addr)
371 {
372 int r;
373 u32 parts[2];
374
375 r = zd_ioread32v_locked(chip, parts, (const zd_addr_t *)addr, 2);
376 if (r) {
377 dev_dbg_f(zd_chip_dev(chip),
378 "error: couldn't read e2p macs. Error number %d\n", r);
379 return r;
380 }
381
382 mac_addr[0] = parts[0];
383 mac_addr[1] = parts[0] >> 8;
384 mac_addr[2] = parts[0] >> 16;
385 mac_addr[3] = parts[0] >> 24;
386 mac_addr[4] = parts[1];
387 mac_addr[5] = parts[1] >> 8;
388
389 return 0;
390 }
391
392 static int read_e2p_mac_addr(struct zd_chip *chip)
393 {
394 static const zd_addr_t addr[2] = { E2P_MAC_ADDR_P1, E2P_MAC_ADDR_P2 };
395
396 ZD_ASSERT(mutex_is_locked(&chip->mutex));
397 return _read_mac_addr(chip, chip->e2p_mac, (const zd_addr_t *)addr);
398 }
399
400 /* MAC address: if custom mac addresses are to to be used CR_MAC_ADDR_P1 and
401 * CR_MAC_ADDR_P2 must be overwritten
402 */
403 void zd_get_e2p_mac_addr(struct zd_chip *chip, u8 *mac_addr)
404 {
405 mutex_lock(&chip->mutex);
406 memcpy(mac_addr, chip->e2p_mac, ETH_ALEN);
407 mutex_unlock(&chip->mutex);
408 }
409
410 static int read_mac_addr(struct zd_chip *chip, u8 *mac_addr)
411 {
412 static const zd_addr_t addr[2] = { CR_MAC_ADDR_P1, CR_MAC_ADDR_P2 };
413 return _read_mac_addr(chip, mac_addr, (const zd_addr_t *)addr);
414 }
415
416 int zd_read_mac_addr(struct zd_chip *chip, u8 *mac_addr)
417 {
418 int r;
419
420 dev_dbg_f(zd_chip_dev(chip), "\n");
421 mutex_lock(&chip->mutex);
422 r = read_mac_addr(chip, mac_addr);
423 mutex_unlock(&chip->mutex);
424 return r;
425 }
426
427 int zd_write_mac_addr(struct zd_chip *chip, const u8 *mac_addr)
428 {
429 int r;
430 struct zd_ioreq32 reqs[2] = {
431 [0] = { .addr = CR_MAC_ADDR_P1 },
432 [1] = { .addr = CR_MAC_ADDR_P2 },
433 };
434
435 reqs[0].value = (mac_addr[3] << 24)
436 | (mac_addr[2] << 16)
437 | (mac_addr[1] << 8)
438 | mac_addr[0];
439 reqs[1].value = (mac_addr[5] << 8)
440 | mac_addr[4];
441
442 dev_dbg_f(zd_chip_dev(chip),
443 "mac addr " MAC_FMT "\n", MAC_ARG(mac_addr));
444
445 mutex_lock(&chip->mutex);
446 r = zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs));
447 #ifdef DEBUG
448 {
449 u8 tmp[ETH_ALEN];
450 read_mac_addr(chip, tmp);
451 }
452 #endif /* DEBUG */
453 mutex_unlock(&chip->mutex);
454 return r;
455 }
456
457 int zd_read_regdomain(struct zd_chip *chip, u8 *regdomain)
458 {
459 int r;
460 u32 value;
461
462 mutex_lock(&chip->mutex);
463 r = zd_ioread32_locked(chip, &value, E2P_SUBID);
464 mutex_unlock(&chip->mutex);
465 if (r)
466 return r;
467
468 *regdomain = value >> 16;
469 dev_dbg_f(zd_chip_dev(chip), "regdomain: %#04x\n", *regdomain);
470
471 return 0;
472 }
473
474 static int read_values(struct zd_chip *chip, u8 *values, size_t count,
475 zd_addr_t e2p_addr, u32 guard)
476 {
477 int r;
478 int i;
479 u32 v;
480
481 ZD_ASSERT(mutex_is_locked(&chip->mutex));
482 for (i = 0;;) {
483 r = zd_ioread32_locked(chip, &v,
484 (zd_addr_t)((u16)e2p_addr+i/2));
485 if (r)
486 return r;
487 v -= guard;
488 if (i+4 < count) {
489 values[i++] = v;
490 values[i++] = v >> 8;
491 values[i++] = v >> 16;
492 values[i++] = v >> 24;
493 continue;
494 }
495 for (;i < count; i++)
496 values[i] = v >> (8*(i%3));
497 return 0;
498 }
499 }
500
501 static int read_pwr_cal_values(struct zd_chip *chip)
502 {
503 return read_values(chip, chip->pwr_cal_values,
504 E2P_CHANNEL_COUNT, E2P_PWR_CAL_VALUE1,
505 0);
506 }
507
508 static int read_pwr_int_values(struct zd_chip *chip)
509 {
510 return read_values(chip, chip->pwr_int_values,
511 E2P_CHANNEL_COUNT, E2P_PWR_INT_VALUE1,
512 E2P_PWR_INT_GUARD);
513 }
514
515 static int read_ofdm_cal_values(struct zd_chip *chip)
516 {
517 int r;
518 int i;
519 static const zd_addr_t addresses[] = {
520 E2P_36M_CAL_VALUE1,
521 E2P_48M_CAL_VALUE1,
522 E2P_54M_CAL_VALUE1,
523 };
524
525 for (i = 0; i < 3; i++) {
526 r = read_values(chip, chip->ofdm_cal_values[i],
527 E2P_CHANNEL_COUNT, addresses[i], 0);
528 if (r)
529 return r;
530 }
531 return 0;
532 }
533
534 static int read_cal_int_tables(struct zd_chip *chip)
535 {
536 int r;
537
538 r = read_pwr_cal_values(chip);
539 if (r)
540 return r;
541 r = read_pwr_int_values(chip);
542 if (r)
543 return r;
544 r = read_ofdm_cal_values(chip);
545 if (r)
546 return r;
547 return 0;
548 }
549
550 /* phy means physical registers */
551 int zd_chip_lock_phy_regs(struct zd_chip *chip)
552 {
553 int r;
554 u32 tmp;
555
556 ZD_ASSERT(mutex_is_locked(&chip->mutex));
557 r = zd_ioread32_locked(chip, &tmp, CR_REG1);
558 if (r) {
559 dev_err(zd_chip_dev(chip), "error ioread32(CR_REG1): %d\n", r);
560 return r;
561 }
562
563 dev_dbg_f(zd_chip_dev(chip),
564 "CR_REG1: 0x%02x -> 0x%02x\n", tmp, tmp & ~UNLOCK_PHY_REGS);
565 tmp &= ~UNLOCK_PHY_REGS;
566
567 r = zd_iowrite32_locked(chip, tmp, CR_REG1);
568 if (r)
569 dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r);
570 return r;
571 }
572
573 int zd_chip_unlock_phy_regs(struct zd_chip *chip)
574 {
575 int r;
576 u32 tmp;
577
578 ZD_ASSERT(mutex_is_locked(&chip->mutex));
579 r = zd_ioread32_locked(chip, &tmp, CR_REG1);
580 if (r) {
581 dev_err(zd_chip_dev(chip),
582 "error ioread32(CR_REG1): %d\n", r);
583 return r;
584 }
585
586 dev_dbg_f(zd_chip_dev(chip),
587 "CR_REG1: 0x%02x -> 0x%02x\n", tmp, tmp | UNLOCK_PHY_REGS);
588 tmp |= UNLOCK_PHY_REGS;
589
590 r = zd_iowrite32_locked(chip, tmp, CR_REG1);
591 if (r)
592 dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r);
593 return r;
594 }
595
596 /* CR157 can be optionally patched by the EEPROM for original ZD1211 */
597 static int patch_cr157(struct zd_chip *chip)
598 {
599 int r;
600 u16 value;
601
602 if (!chip->patch_cr157)
603 return 0;
604
605 r = zd_ioread16_locked(chip, &value, E2P_PHY_REG);
606 if (r)
607 return r;
608
609 dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value >> 8);
610 return zd_iowrite32_locked(chip, value >> 8, CR157);
611 }
612
613 /*
614 * 6M band edge can be optionally overwritten for certain RF's
615 * Vendor driver says: for FCC regulation, enabled per HWFeature 6M band edge
616 * bit (for AL2230, AL2230S)
617 */
618 static int patch_6m_band_edge(struct zd_chip *chip, u8 channel)
619 {
620 ZD_ASSERT(mutex_is_locked(&chip->mutex));
621 if (!chip->patch_6m_band_edge)
622 return 0;
623
624 return zd_rf_patch_6m_band_edge(&chip->rf, channel);
625 }
626
627 /* Generic implementation of 6M band edge patching, used by most RFs via
628 * zd_rf_generic_patch_6m() */
629 int zd_chip_generic_patch_6m_band(struct zd_chip *chip, int channel)
630 {
631 struct zd_ioreq16 ioreqs[] = {
632 { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 },
633 { CR47, 0x1e },
634 };
635
636 /* FIXME: Channel 11 is not the edge for all regulatory domains. */
637 if (channel == 1 || channel == 11)
638 ioreqs[0].value = 0x12;
639
640 dev_dbg_f(zd_chip_dev(chip), "patching for channel %d\n", channel);
641 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
642 }
643
644 static int zd1211_hw_reset_phy(struct zd_chip *chip)
645 {
646 static const struct zd_ioreq16 ioreqs[] = {
647 { CR0, 0x0a }, { CR1, 0x06 }, { CR2, 0x26 },
648 { CR3, 0x38 }, { CR4, 0x80 }, { CR9, 0xa0 },
649 { CR10, 0x81 }, { CR11, 0x00 }, { CR12, 0x7f },
650 { CR13, 0x8c }, { CR14, 0x80 }, { CR15, 0x3d },
651 { CR16, 0x20 }, { CR17, 0x1e }, { CR18, 0x0a },
652 { CR19, 0x48 }, { CR20, 0x0c }, { CR21, 0x0c },
653 { CR22, 0x23 }, { CR23, 0x90 }, { CR24, 0x14 },
654 { CR25, 0x40 }, { CR26, 0x10 }, { CR27, 0x19 },
655 { CR28, 0x7f }, { CR29, 0x80 }, { CR30, 0x4b },
656 { CR31, 0x60 }, { CR32, 0x43 }, { CR33, 0x08 },
657 { CR34, 0x06 }, { CR35, 0x0a }, { CR36, 0x00 },
658 { CR37, 0x00 }, { CR38, 0x38 }, { CR39, 0x0c },
659 { CR40, 0x84 }, { CR41, 0x2a }, { CR42, 0x80 },
660 { CR43, 0x10 }, { CR44, 0x12 }, { CR46, 0xff },
661 { CR47, 0x1E }, { CR48, 0x26 }, { CR49, 0x5b },
662 { CR64, 0xd0 }, { CR65, 0x04 }, { CR66, 0x58 },
663 { CR67, 0xc9 }, { CR68, 0x88 }, { CR69, 0x41 },
664 { CR70, 0x23 }, { CR71, 0x10 }, { CR72, 0xff },
665 { CR73, 0x32 }, { CR74, 0x30 }, { CR75, 0x65 },
666 { CR76, 0x41 }, { CR77, 0x1b }, { CR78, 0x30 },
667 { CR79, 0x68 }, { CR80, 0x64 }, { CR81, 0x64 },
668 { CR82, 0x00 }, { CR83, 0x00 }, { CR84, 0x00 },
669 { CR85, 0x02 }, { CR86, 0x00 }, { CR87, 0x00 },
670 { CR88, 0xff }, { CR89, 0xfc }, { CR90, 0x00 },
671 { CR91, 0x00 }, { CR92, 0x00 }, { CR93, 0x08 },
672 { CR94, 0x00 }, { CR95, 0x00 }, { CR96, 0xff },
673 { CR97, 0xe7 }, { CR98, 0x00 }, { CR99, 0x00 },
674 { CR100, 0x00 }, { CR101, 0xae }, { CR102, 0x02 },
675 { CR103, 0x00 }, { CR104, 0x03 }, { CR105, 0x65 },
676 { CR106, 0x04 }, { CR107, 0x00 }, { CR108, 0x0a },
677 { CR109, 0xaa }, { CR110, 0xaa }, { CR111, 0x25 },
678 { CR112, 0x25 }, { CR113, 0x00 }, { CR119, 0x1e },
679 { CR125, 0x90 }, { CR126, 0x00 }, { CR127, 0x00 },
680 { },
681 { CR5, 0x00 }, { CR6, 0x00 }, { CR7, 0x00 },
682 { CR8, 0x00 }, { CR9, 0x20 }, { CR12, 0xf0 },
683 { CR20, 0x0e }, { CR21, 0x0e }, { CR27, 0x10 },
684 { CR44, 0x33 }, { CR47, 0x1E }, { CR83, 0x24 },
685 { CR84, 0x04 }, { CR85, 0x00 }, { CR86, 0x0C },
686 { CR87, 0x12 }, { CR88, 0x0C }, { CR89, 0x00 },
687 { CR90, 0x10 }, { CR91, 0x08 }, { CR93, 0x00 },
688 { CR94, 0x01 }, { CR95, 0x00 }, { CR96, 0x50 },
689 { CR97, 0x37 }, { CR98, 0x35 }, { CR101, 0x13 },
690 { CR102, 0x27 }, { CR103, 0x27 }, { CR104, 0x18 },
691 { CR105, 0x12 }, { CR109, 0x27 }, { CR110, 0x27 },
692 { CR111, 0x27 }, { CR112, 0x27 }, { CR113, 0x27 },
693 { CR114, 0x27 }, { CR115, 0x26 }, { CR116, 0x24 },
694 { CR117, 0xfc }, { CR118, 0xfa }, { CR120, 0x4f },
695 { CR125, 0xaa }, { CR127, 0x03 }, { CR128, 0x14 },
696 { CR129, 0x12 }, { CR130, 0x10 }, { CR131, 0x0C },
697 { CR136, 0xdf }, { CR137, 0x40 }, { CR138, 0xa0 },
698 { CR139, 0xb0 }, { CR140, 0x99 }, { CR141, 0x82 },
699 { CR142, 0x54 }, { CR143, 0x1c }, { CR144, 0x6c },
700 { CR147, 0x07 }, { CR148, 0x4c }, { CR149, 0x50 },
701 { CR150, 0x0e }, { CR151, 0x18 }, { CR160, 0xfe },
702 { CR161, 0xee }, { CR162, 0xaa }, { CR163, 0xfa },
703 { CR164, 0xfa }, { CR165, 0xea }, { CR166, 0xbe },
704 { CR167, 0xbe }, { CR168, 0x6a }, { CR169, 0xba },
705 { CR170, 0xba }, { CR171, 0xba },
706 /* Note: CR204 must lead the CR203 */
707 { CR204, 0x7d },
708 { },
709 { CR203, 0x30 },
710 };
711
712 int r, t;
713
714 dev_dbg_f(zd_chip_dev(chip), "\n");
715
716 r = zd_chip_lock_phy_regs(chip);
717 if (r)
718 goto out;
719
720 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
721 if (r)
722 goto unlock;
723
724 r = patch_cr157(chip);
725 unlock:
726 t = zd_chip_unlock_phy_regs(chip);
727 if (t && !r)
728 r = t;
729 out:
730 return r;
731 }
732
733 static int zd1211b_hw_reset_phy(struct zd_chip *chip)
734 {
735 static const struct zd_ioreq16 ioreqs[] = {
736 { CR0, 0x14 }, { CR1, 0x06 }, { CR2, 0x26 },
737 { CR3, 0x38 }, { CR4, 0x80 }, { CR9, 0xe0 },
738 { CR10, 0x81 },
739 /* power control { { CR11, 1 << 6 }, */
740 { CR11, 0x00 },
741 { CR12, 0xf0 }, { CR13, 0x8c }, { CR14, 0x80 },
742 { CR15, 0x3d }, { CR16, 0x20 }, { CR17, 0x1e },
743 { CR18, 0x0a }, { CR19, 0x48 },
744 { CR20, 0x10 }, /* Org:0x0E, ComTrend:RalLink AP */
745 { CR21, 0x0e }, { CR22, 0x23 }, { CR23, 0x90 },
746 { CR24, 0x14 }, { CR25, 0x40 }, { CR26, 0x10 },
747 { CR27, 0x10 }, { CR28, 0x7f }, { CR29, 0x80 },
748 { CR30, 0x4b }, /* ASIC/FWT, no jointly decoder */
749 { CR31, 0x60 }, { CR32, 0x43 }, { CR33, 0x08 },
750 { CR34, 0x06 }, { CR35, 0x0a }, { CR36, 0x00 },
751 { CR37, 0x00 }, { CR38, 0x38 }, { CR39, 0x0c },
752 { CR40, 0x84 }, { CR41, 0x2a }, { CR42, 0x80 },
753 { CR43, 0x10 }, { CR44, 0x33 }, { CR46, 0xff },
754 { CR47, 0x1E }, { CR48, 0x26 }, { CR49, 0x5b },
755 { CR64, 0xd0 }, { CR65, 0x04 }, { CR66, 0x58 },
756 { CR67, 0xc9 }, { CR68, 0x88 }, { CR69, 0x41 },
757 { CR70, 0x23 }, { CR71, 0x10 }, { CR72, 0xff },
758 { CR73, 0x32 }, { CR74, 0x30 }, { CR75, 0x65 },
759 { CR76, 0x41 }, { CR77, 0x1b }, { CR78, 0x30 },
760 { CR79, 0xf0 }, { CR80, 0x64 }, { CR81, 0x64 },
761 { CR82, 0x00 }, { CR83, 0x24 }, { CR84, 0x04 },
762 { CR85, 0x00 }, { CR86, 0x0c }, { CR87, 0x12 },
763 { CR88, 0x0c }, { CR89, 0x00 }, { CR90, 0x58 },
764 { CR91, 0x04 }, { CR92, 0x00 }, { CR93, 0x00 },
765 { CR94, 0x01 },
766 { CR95, 0x20 }, /* ZD1211B */
767 { CR96, 0x50 }, { CR97, 0x37 }, { CR98, 0x35 },
768 { CR99, 0x00 }, { CR100, 0x01 }, { CR101, 0x13 },
769 { CR102, 0x27 }, { CR103, 0x27 }, { CR104, 0x18 },
770 { CR105, 0x12 }, { CR106, 0x04 }, { CR107, 0x00 },
771 { CR108, 0x0a }, { CR109, 0x27 }, { CR110, 0x27 },
772 { CR111, 0x27 }, { CR112, 0x27 }, { CR113, 0x27 },
773 { CR114, 0x27 }, { CR115, 0x26 }, { CR116, 0x24 },
774 { CR117, 0xfc }, { CR118, 0xfa }, { CR119, 0x1e },
775 { CR125, 0x90 }, { CR126, 0x00 }, { CR127, 0x00 },
776 { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 },
777 { CR131, 0x0c }, { CR136, 0xdf }, { CR137, 0xa0 },
778 { CR138, 0xa8 }, { CR139, 0xb4 }, { CR140, 0x98 },
779 { CR141, 0x82 }, { CR142, 0x53 }, { CR143, 0x1c },
780 { CR144, 0x6c }, { CR147, 0x07 }, { CR148, 0x40 },
781 { CR149, 0x40 }, /* Org:0x50 ComTrend:RalLink AP */
782 { CR150, 0x14 }, /* Org:0x0E ComTrend:RalLink AP */
783 { CR151, 0x18 }, { CR159, 0x70 }, { CR160, 0xfe },
784 { CR161, 0xee }, { CR162, 0xaa }, { CR163, 0xfa },
785 { CR164, 0xfa }, { CR165, 0xea }, { CR166, 0xbe },
786 { CR167, 0xbe }, { CR168, 0x6a }, { CR169, 0xba },
787 { CR170, 0xba }, { CR171, 0xba },
788 /* Note: CR204 must lead the CR203 */
789 { CR204, 0x7d },
790 {},
791 { CR203, 0x30 },
792 };
793
794 int r, t;
795
796 dev_dbg_f(zd_chip_dev(chip), "\n");
797
798 r = zd_chip_lock_phy_regs(chip);
799 if (r)
800 goto out;
801
802 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
803 t = zd_chip_unlock_phy_regs(chip);
804 if (t && !r)
805 r = t;
806 out:
807 return r;
808 }
809
810 static int hw_reset_phy(struct zd_chip *chip)
811 {
812 return chip->is_zd1211b ? zd1211b_hw_reset_phy(chip) :
813 zd1211_hw_reset_phy(chip);
814 }
815
816 static int zd1211_hw_init_hmac(struct zd_chip *chip)
817 {
818 static const struct zd_ioreq32 ioreqs[] = {
819 { CR_ZD1211_RETRY_MAX, 0x2 },
820 { CR_RX_THRESHOLD, 0x000c0640 },
821 };
822
823 dev_dbg_f(zd_chip_dev(chip), "\n");
824 ZD_ASSERT(mutex_is_locked(&chip->mutex));
825 return zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
826 }
827
828 static int zd1211b_hw_init_hmac(struct zd_chip *chip)
829 {
830 static const struct zd_ioreq32 ioreqs[] = {
831 { CR_ZD1211B_RETRY_MAX, 0x02020202 },
832 { CR_ZD1211B_TX_PWR_CTL4, 0x007f003f },
833 { CR_ZD1211B_TX_PWR_CTL3, 0x007f003f },
834 { CR_ZD1211B_TX_PWR_CTL2, 0x003f001f },
835 { CR_ZD1211B_TX_PWR_CTL1, 0x001f000f },
836 { CR_ZD1211B_AIFS_CTL1, 0x00280028 },
837 { CR_ZD1211B_AIFS_CTL2, 0x008C003C },
838 { CR_ZD1211B_TXOP, 0x01800824 },
839 { CR_RX_THRESHOLD, 0x000c0eff, },
840 };
841
842 dev_dbg_f(zd_chip_dev(chip), "\n");
843 ZD_ASSERT(mutex_is_locked(&chip->mutex));
844 return zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
845 }
846
847 static int hw_init_hmac(struct zd_chip *chip)
848 {
849 int r;
850 static const struct zd_ioreq32 ioreqs[] = {
851 { CR_ACK_TIMEOUT_EXT, 0x20 },
852 { CR_ADDA_MBIAS_WARMTIME, 0x30000808 },
853 { CR_SNIFFER_ON, 0 },
854 { CR_RX_FILTER, STA_RX_FILTER },
855 { CR_GROUP_HASH_P1, 0x00 },
856 { CR_GROUP_HASH_P2, 0x80000000 },
857 { CR_REG1, 0xa4 },
858 { CR_ADDA_PWR_DWN, 0x7f },
859 { CR_BCN_PLCP_CFG, 0x00f00401 },
860 { CR_PHY_DELAY, 0x00 },
861 { CR_ACK_TIMEOUT_EXT, 0x80 },
862 { CR_ADDA_PWR_DWN, 0x00 },
863 { CR_ACK_TIME_80211, 0x100 },
864 { CR_RX_PE_DELAY, 0x70 },
865 { CR_PS_CTRL, 0x10000000 },
866 { CR_RTS_CTS_RATE, 0x02030203 },
867 { CR_AFTER_PNP, 0x1 },
868 { CR_WEP_PROTECT, 0x114 },
869 { CR_IFS_VALUE, IFS_VALUE_DEFAULT },
870 };
871
872 ZD_ASSERT(mutex_is_locked(&chip->mutex));
873 r = zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
874 if (r)
875 return r;
876
877 return chip->is_zd1211b ?
878 zd1211b_hw_init_hmac(chip) : zd1211_hw_init_hmac(chip);
879 }
880
881 struct aw_pt_bi {
882 u32 atim_wnd_period;
883 u32 pre_tbtt;
884 u32 beacon_interval;
885 };
886
887 static int get_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s)
888 {
889 int r;
890 static const zd_addr_t aw_pt_bi_addr[] =
891 { CR_ATIM_WND_PERIOD, CR_PRE_TBTT, CR_BCN_INTERVAL };
892 u32 values[3];
893
894 r = zd_ioread32v_locked(chip, values, (const zd_addr_t *)aw_pt_bi_addr,
895 ARRAY_SIZE(aw_pt_bi_addr));
896 if (r) {
897 memset(s, 0, sizeof(*s));
898 return r;
899 }
900
901 s->atim_wnd_period = values[0];
902 s->pre_tbtt = values[1];
903 s->beacon_interval = values[2];
904 dev_dbg_f(zd_chip_dev(chip), "aw %u pt %u bi %u\n",
905 s->atim_wnd_period, s->pre_tbtt, s->beacon_interval);
906 return 0;
907 }
908
909 static int set_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s)
910 {
911 struct zd_ioreq32 reqs[3];
912
913 if (s->beacon_interval <= 5)
914 s->beacon_interval = 5;
915 if (s->pre_tbtt < 4 || s->pre_tbtt >= s->beacon_interval)
916 s->pre_tbtt = s->beacon_interval - 1;
917 if (s->atim_wnd_period >= s->pre_tbtt)
918 s->atim_wnd_period = s->pre_tbtt - 1;
919
920 reqs[0].addr = CR_ATIM_WND_PERIOD;
921 reqs[0].value = s->atim_wnd_period;
922 reqs[1].addr = CR_PRE_TBTT;
923 reqs[1].value = s->pre_tbtt;
924 reqs[2].addr = CR_BCN_INTERVAL;
925 reqs[2].value = s->beacon_interval;
926
927 dev_dbg_f(zd_chip_dev(chip),
928 "aw %u pt %u bi %u\n", s->atim_wnd_period, s->pre_tbtt,
929 s->beacon_interval);
930 return zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs));
931 }
932
933
934 static int set_beacon_interval(struct zd_chip *chip, u32 interval)
935 {
936 int r;
937 struct aw_pt_bi s;
938
939 ZD_ASSERT(mutex_is_locked(&chip->mutex));
940 r = get_aw_pt_bi(chip, &s);
941 if (r)
942 return r;
943 s.beacon_interval = interval;
944 return set_aw_pt_bi(chip, &s);
945 }
946
947 int zd_set_beacon_interval(struct zd_chip *chip, u32 interval)
948 {
949 int r;
950
951 mutex_lock(&chip->mutex);
952 r = set_beacon_interval(chip, interval);
953 mutex_unlock(&chip->mutex);
954 return r;
955 }
956
957 static int hw_init(struct zd_chip *chip)
958 {
959 int r;
960
961 dev_dbg_f(zd_chip_dev(chip), "\n");
962 ZD_ASSERT(mutex_is_locked(&chip->mutex));
963 r = hw_reset_phy(chip);
964 if (r)
965 return r;
966
967 r = hw_init_hmac(chip);
968 if (r)
969 return r;
970
971 return set_beacon_interval(chip, 100);
972 }
973
974 static zd_addr_t fw_reg_addr(struct zd_chip *chip, u16 offset)
975 {
976 return (zd_addr_t)((u16)chip->fw_regs_base + offset);
977 }
978
979 #ifdef DEBUG
980 static int dump_cr(struct zd_chip *chip, const zd_addr_t addr,
981 const char *addr_string)
982 {
983 int r;
984 u32 value;
985
986 r = zd_ioread32_locked(chip, &value, addr);
987 if (r) {
988 dev_dbg_f(zd_chip_dev(chip),
989 "error reading %s. Error number %d\n", addr_string, r);
990 return r;
991 }
992
993 dev_dbg_f(zd_chip_dev(chip), "%s %#010x\n",
994 addr_string, (unsigned int)value);
995 return 0;
996 }
997
998 static int test_init(struct zd_chip *chip)
999 {
1000 int r;
1001
1002 r = dump_cr(chip, CR_AFTER_PNP, "CR_AFTER_PNP");
1003 if (r)
1004 return r;
1005 r = dump_cr(chip, CR_GPI_EN, "CR_GPI_EN");
1006 if (r)
1007 return r;
1008 return dump_cr(chip, CR_INTERRUPT, "CR_INTERRUPT");
1009 }
1010
1011 static void dump_fw_registers(struct zd_chip *chip)
1012 {
1013 const zd_addr_t addr[4] = {
1014 fw_reg_addr(chip, FW_REG_FIRMWARE_VER),
1015 fw_reg_addr(chip, FW_REG_USB_SPEED),
1016 fw_reg_addr(chip, FW_REG_FIX_TX_RATE),
1017 fw_reg_addr(chip, FW_REG_LED_LINK_STATUS),
1018 };
1019
1020 int r;
1021 u16 values[4];
1022
1023 r = zd_ioread16v_locked(chip, values, (const zd_addr_t*)addr,
1024 ARRAY_SIZE(addr));
1025 if (r) {
1026 dev_dbg_f(zd_chip_dev(chip), "error %d zd_ioread16v_locked\n",
1027 r);
1028 return;
1029 }
1030
1031 dev_dbg_f(zd_chip_dev(chip), "FW_FIRMWARE_VER %#06hx\n", values[0]);
1032 dev_dbg_f(zd_chip_dev(chip), "FW_USB_SPEED %#06hx\n", values[1]);
1033 dev_dbg_f(zd_chip_dev(chip), "FW_FIX_TX_RATE %#06hx\n", values[2]);
1034 dev_dbg_f(zd_chip_dev(chip), "FW_LINK_STATUS %#06hx\n", values[3]);
1035 }
1036 #endif /* DEBUG */
1037
1038 static int print_fw_version(struct zd_chip *chip)
1039 {
1040 int r;
1041 u16 version;
1042
1043 r = zd_ioread16_locked(chip, &version,
1044 fw_reg_addr(chip, FW_REG_FIRMWARE_VER));
1045 if (r)
1046 return r;
1047
1048 dev_info(zd_chip_dev(chip),"firmware version %04hx\n", version);
1049 return 0;
1050 }
1051
1052 static int set_mandatory_rates(struct zd_chip *chip, enum ieee80211_std std)
1053 {
1054 u32 rates;
1055 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1056 /* This sets the mandatory rates, which only depend from the standard
1057 * that the device is supporting. Until further notice we should try
1058 * to support 802.11g also for full speed USB.
1059 */
1060 switch (std) {
1061 case IEEE80211B:
1062 rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M;
1063 break;
1064 case IEEE80211G:
1065 rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M|
1066 CR_RATE_6M|CR_RATE_12M|CR_RATE_24M;
1067 break;
1068 default:
1069 return -EINVAL;
1070 }
1071 return zd_iowrite32_locked(chip, rates, CR_MANDATORY_RATE_TBL);
1072 }
1073
1074 int zd_chip_set_rts_cts_rate_locked(struct zd_chip *chip,
1075 u8 rts_rate, int preamble)
1076 {
1077 int rts_mod = ZD_RX_CCK;
1078 u32 value = 0;
1079
1080 /* Modulation bit */
1081 if (ZD_CS_TYPE(rts_rate) == ZD_CS_OFDM)
1082 rts_mod = ZD_RX_OFDM;
1083
1084 dev_dbg_f(zd_chip_dev(chip), "rts_rate=%x preamble=%x\n",
1085 rts_rate, preamble);
1086
1087 value |= rts_rate << RTSCTS_SH_RTS_RATE;
1088 value |= rts_mod << RTSCTS_SH_RTS_MOD_TYPE;
1089 value |= preamble << RTSCTS_SH_RTS_PMB_TYPE;
1090 value |= preamble << RTSCTS_SH_CTS_PMB_TYPE;
1091
1092 /* We always send 11M self-CTS messages, like the vendor driver. */
1093 value |= ZD_CCK_RATE_11M << RTSCTS_SH_CTS_RATE;
1094 value |= ZD_RX_CCK << RTSCTS_SH_CTS_MOD_TYPE;
1095
1096 return zd_iowrite32_locked(chip, value, CR_RTS_CTS_RATE);
1097 }
1098
1099 int zd_chip_enable_hwint(struct zd_chip *chip)
1100 {
1101 int r;
1102
1103 mutex_lock(&chip->mutex);
1104 r = zd_iowrite32_locked(chip, HWINT_ENABLED, CR_INTERRUPT);
1105 mutex_unlock(&chip->mutex);
1106 return r;
1107 }
1108
1109 static int disable_hwint(struct zd_chip *chip)
1110 {
1111 return zd_iowrite32_locked(chip, HWINT_DISABLED, CR_INTERRUPT);
1112 }
1113
1114 int zd_chip_disable_hwint(struct zd_chip *chip)
1115 {
1116 int r;
1117
1118 mutex_lock(&chip->mutex);
1119 r = disable_hwint(chip);
1120 mutex_unlock(&chip->mutex);
1121 return r;
1122 }
1123
1124 static int read_fw_regs_offset(struct zd_chip *chip)
1125 {
1126 int r;
1127
1128 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1129 r = zd_ioread16_locked(chip, (u16*)&chip->fw_regs_base,
1130 FWRAW_REGS_ADDR);
1131 if (r)
1132 return r;
1133 dev_dbg_f(zd_chip_dev(chip), "fw_regs_base: %#06hx\n",
1134 (u16)chip->fw_regs_base);
1135
1136 return 0;
1137 }
1138
1139
1140 int zd_chip_init_hw(struct zd_chip *chip, u8 device_type)
1141 {
1142 int r;
1143 u8 rf_type;
1144
1145 dev_dbg_f(zd_chip_dev(chip), "\n");
1146
1147 mutex_lock(&chip->mutex);
1148 chip->is_zd1211b = (device_type == DEVICE_ZD1211B) != 0;
1149
1150 #ifdef DEBUG
1151 r = test_init(chip);
1152 if (r)
1153 goto out;
1154 #endif
1155 r = zd_iowrite32_locked(chip, 1, CR_AFTER_PNP);
1156 if (r)
1157 goto out;
1158
1159 r = read_fw_regs_offset(chip);
1160 if (r)
1161 goto out;
1162
1163 /* GPI is always disabled, also in the other driver.
1164 */
1165 r = zd_iowrite32_locked(chip, 0, CR_GPI_EN);
1166 if (r)
1167 goto out;
1168 r = zd_iowrite32_locked(chip, CWIN_SIZE, CR_CWMIN_CWMAX);
1169 if (r)
1170 goto out;
1171 /* Currently we support IEEE 802.11g for full and high speed USB.
1172 * It might be discussed, whether we should suppport pure b mode for
1173 * full speed USB.
1174 */
1175 r = set_mandatory_rates(chip, IEEE80211G);
1176 if (r)
1177 goto out;
1178 /* Disabling interrupts is certainly a smart thing here.
1179 */
1180 r = disable_hwint(chip);
1181 if (r)
1182 goto out;
1183 r = read_pod(chip, &rf_type);
1184 if (r)
1185 goto out;
1186 r = hw_init(chip);
1187 if (r)
1188 goto out;
1189 r = zd_rf_init_hw(&chip->rf, rf_type);
1190 if (r)
1191 goto out;
1192
1193 r = print_fw_version(chip);
1194 if (r)
1195 goto out;
1196
1197 #ifdef DEBUG
1198 dump_fw_registers(chip);
1199 r = test_init(chip);
1200 if (r)
1201 goto out;
1202 #endif /* DEBUG */
1203
1204 r = read_e2p_mac_addr(chip);
1205 if (r)
1206 goto out;
1207
1208 r = read_cal_int_tables(chip);
1209 if (r)
1210 goto out;
1211
1212 print_id(chip);
1213 out:
1214 mutex_unlock(&chip->mutex);
1215 return r;
1216 }
1217
1218 static int update_pwr_int(struct zd_chip *chip, u8 channel)
1219 {
1220 u8 value = chip->pwr_int_values[channel - 1];
1221 dev_dbg_f(zd_chip_dev(chip), "channel %d pwr_int %#04x\n",
1222 channel, value);
1223 return zd_iowrite16_locked(chip, value, CR31);
1224 }
1225
1226 static int update_pwr_cal(struct zd_chip *chip, u8 channel)
1227 {
1228 u8 value = chip->pwr_cal_values[channel-1];
1229 dev_dbg_f(zd_chip_dev(chip), "channel %d pwr_cal %#04x\n",
1230 channel, value);
1231 return zd_iowrite16_locked(chip, value, CR68);
1232 }
1233
1234 static int update_ofdm_cal(struct zd_chip *chip, u8 channel)
1235 {
1236 struct zd_ioreq16 ioreqs[3];
1237
1238 ioreqs[0].addr = CR67;
1239 ioreqs[0].value = chip->ofdm_cal_values[OFDM_36M_INDEX][channel-1];
1240 ioreqs[1].addr = CR66;
1241 ioreqs[1].value = chip->ofdm_cal_values[OFDM_48M_INDEX][channel-1];
1242 ioreqs[2].addr = CR65;
1243 ioreqs[2].value = chip->ofdm_cal_values[OFDM_54M_INDEX][channel-1];
1244
1245 dev_dbg_f(zd_chip_dev(chip),
1246 "channel %d ofdm_cal 36M %#04x 48M %#04x 54M %#04x\n",
1247 channel, ioreqs[0].value, ioreqs[1].value, ioreqs[2].value);
1248 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1249 }
1250
1251 static int update_channel_integration_and_calibration(struct zd_chip *chip,
1252 u8 channel)
1253 {
1254 int r;
1255
1256 r = update_pwr_int(chip, channel);
1257 if (r)
1258 return r;
1259 if (chip->is_zd1211b) {
1260 static const struct zd_ioreq16 ioreqs[] = {
1261 { CR69, 0x28 },
1262 {},
1263 { CR69, 0x2a },
1264 };
1265
1266 r = update_ofdm_cal(chip, channel);
1267 if (r)
1268 return r;
1269 r = update_pwr_cal(chip, channel);
1270 if (r)
1271 return r;
1272 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1273 if (r)
1274 return r;
1275 }
1276
1277 return 0;
1278 }
1279
1280 /* The CCK baseband gain can be optionally patched by the EEPROM */
1281 static int patch_cck_gain(struct zd_chip *chip)
1282 {
1283 int r;
1284 u32 value;
1285
1286 if (!chip->patch_cck_gain)
1287 return 0;
1288
1289 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1290 r = zd_ioread32_locked(chip, &value, E2P_PHY_REG);
1291 if (r)
1292 return r;
1293 dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value & 0xff);
1294 return zd_iowrite16_locked(chip, value & 0xff, CR47);
1295 }
1296
1297 int zd_chip_set_channel(struct zd_chip *chip, u8 channel)
1298 {
1299 int r, t;
1300
1301 mutex_lock(&chip->mutex);
1302 r = zd_chip_lock_phy_regs(chip);
1303 if (r)
1304 goto out;
1305 r = zd_rf_set_channel(&chip->rf, channel);
1306 if (r)
1307 goto unlock;
1308 r = update_channel_integration_and_calibration(chip, channel);
1309 if (r)
1310 goto unlock;
1311 r = patch_cck_gain(chip);
1312 if (r)
1313 goto unlock;
1314 r = patch_6m_band_edge(chip, channel);
1315 if (r)
1316 goto unlock;
1317 r = zd_iowrite32_locked(chip, 0, CR_CONFIG_PHILIPS);
1318 unlock:
1319 t = zd_chip_unlock_phy_regs(chip);
1320 if (t && !r)
1321 r = t;
1322 out:
1323 mutex_unlock(&chip->mutex);
1324 return r;
1325 }
1326
1327 u8 zd_chip_get_channel(struct zd_chip *chip)
1328 {
1329 u8 channel;
1330
1331 mutex_lock(&chip->mutex);
1332 channel = chip->rf.channel;
1333 mutex_unlock(&chip->mutex);
1334 return channel;
1335 }
1336
1337 int zd_chip_control_leds(struct zd_chip *chip, enum led_status status)
1338 {
1339 const zd_addr_t a[] = {
1340 fw_reg_addr(chip, FW_REG_LED_LINK_STATUS),
1341 CR_LED,
1342 };
1343
1344 int r;
1345 u16 v[ARRAY_SIZE(a)];
1346 struct zd_ioreq16 ioreqs[ARRAY_SIZE(a)] = {
1347 [0] = { fw_reg_addr(chip, FW_REG_LED_LINK_STATUS) },
1348 [1] = { CR_LED },
1349 };
1350 u16 other_led;
1351
1352 mutex_lock(&chip->mutex);
1353 r = zd_ioread16v_locked(chip, v, (const zd_addr_t *)a, ARRAY_SIZE(a));
1354 if (r)
1355 goto out;
1356
1357 other_led = chip->link_led == LED1 ? LED2 : LED1;
1358
1359 switch (status) {
1360 case LED_OFF:
1361 ioreqs[0].value = FW_LINK_OFF;
1362 ioreqs[1].value = v[1] & ~(LED1|LED2);
1363 break;
1364 case LED_SCANNING:
1365 ioreqs[0].value = FW_LINK_OFF;
1366 ioreqs[1].value = v[1] & ~other_led;
1367 if (get_seconds() % 3 == 0) {
1368 ioreqs[1].value &= ~chip->link_led;
1369 } else {
1370 ioreqs[1].value |= chip->link_led;
1371 }
1372 break;
1373 case LED_ASSOCIATED:
1374 ioreqs[0].value = FW_LINK_TX;
1375 ioreqs[1].value = v[1] & ~other_led;
1376 ioreqs[1].value |= chip->link_led;
1377 break;
1378 default:
1379 r = -EINVAL;
1380 goto out;
1381 }
1382
1383 if (v[0] != ioreqs[0].value || v[1] != ioreqs[1].value) {
1384 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1385 if (r)
1386 goto out;
1387 }
1388 r = 0;
1389 out:
1390 mutex_unlock(&chip->mutex);
1391 return r;
1392 }
1393
1394 int zd_chip_set_basic_rates_locked(struct zd_chip *chip, u16 cr_rates)
1395 {
1396 ZD_ASSERT((cr_rates & ~(CR_RATES_80211B | CR_RATES_80211G)) == 0);
1397 dev_dbg_f(zd_chip_dev(chip), "%x\n", cr_rates);
1398
1399 return zd_iowrite32_locked(chip, cr_rates, CR_BASIC_RATE_TBL);
1400 }
1401
1402 static int ofdm_qual_db(u8 status_quality, u8 rate, unsigned int size)
1403 {
1404 static const u16 constants[] = {
1405 715, 655, 585, 540, 470, 410, 360, 315,
1406 270, 235, 205, 175, 150, 125, 105, 85,
1407 65, 50, 40, 25, 15
1408 };
1409
1410 int i;
1411 u32 x;
1412
1413 /* It seems that their quality parameter is somehow per signal
1414 * and is now transferred per bit.
1415 */
1416 switch (rate) {
1417 case ZD_OFDM_RATE_6M:
1418 case ZD_OFDM_RATE_12M:
1419 case ZD_OFDM_RATE_24M:
1420 size *= 2;
1421 break;
1422 case ZD_OFDM_RATE_9M:
1423 case ZD_OFDM_RATE_18M:
1424 case ZD_OFDM_RATE_36M:
1425 case ZD_OFDM_RATE_54M:
1426 size *= 4;
1427 size /= 3;
1428 break;
1429 case ZD_OFDM_RATE_48M:
1430 size *= 3;
1431 size /= 2;
1432 break;
1433 default:
1434 return -EINVAL;
1435 }
1436
1437 x = (10000 * status_quality)/size;
1438 for (i = 0; i < ARRAY_SIZE(constants); i++) {
1439 if (x > constants[i])
1440 break;
1441 }
1442
1443 switch (rate) {
1444 case ZD_OFDM_RATE_6M:
1445 case ZD_OFDM_RATE_9M:
1446 i += 3;
1447 break;
1448 case ZD_OFDM_RATE_12M:
1449 case ZD_OFDM_RATE_18M:
1450 i += 5;
1451 break;
1452 case ZD_OFDM_RATE_24M:
1453 case ZD_OFDM_RATE_36M:
1454 i += 9;
1455 break;
1456 case ZD_OFDM_RATE_48M:
1457 case ZD_OFDM_RATE_54M:
1458 i += 15;
1459 break;
1460 default:
1461 return -EINVAL;
1462 }
1463
1464 return i;
1465 }
1466
1467 static int ofdm_qual_percent(u8 status_quality, u8 rate, unsigned int size)
1468 {
1469 int r;
1470
1471 r = ofdm_qual_db(status_quality, rate, size);
1472 ZD_ASSERT(r >= 0);
1473 if (r < 0)
1474 r = 0;
1475
1476 r = (r * 100)/29;
1477 return r <= 100 ? r : 100;
1478 }
1479
1480 static unsigned int log10times100(unsigned int x)
1481 {
1482 static const u8 log10[] = {
1483 0,
1484 0, 30, 47, 60, 69, 77, 84, 90, 95, 100,
1485 104, 107, 111, 114, 117, 120, 123, 125, 127, 130,
1486 132, 134, 136, 138, 139, 141, 143, 144, 146, 147,
1487 149, 150, 151, 153, 154, 155, 156, 157, 159, 160,
1488 161, 162, 163, 164, 165, 166, 167, 168, 169, 169,
1489 170, 171, 172, 173, 174, 174, 175, 176, 177, 177,
1490 178, 179, 179, 180, 181, 181, 182, 183, 183, 184,
1491 185, 185, 186, 186, 187, 188, 188, 189, 189, 190,
1492 190, 191, 191, 192, 192, 193, 193, 194, 194, 195,
1493 195, 196, 196, 197, 197, 198, 198, 199, 199, 200,
1494 200, 200, 201, 201, 202, 202, 202, 203, 203, 204,
1495 204, 204, 205, 205, 206, 206, 206, 207, 207, 207,
1496 208, 208, 208, 209, 209, 210, 210, 210, 211, 211,
1497 211, 212, 212, 212, 213, 213, 213, 213, 214, 214,
1498 214, 215, 215, 215, 216, 216, 216, 217, 217, 217,
1499 217, 218, 218, 218, 219, 219, 219, 219, 220, 220,
1500 220, 220, 221, 221, 221, 222, 222, 222, 222, 223,
1501 223, 223, 223, 224, 224, 224, 224,
1502 };
1503
1504 return x < ARRAY_SIZE(log10) ? log10[x] : 225;
1505 }
1506
1507 enum {
1508 MAX_CCK_EVM_DB = 45,
1509 };
1510
1511 static int cck_evm_db(u8 status_quality)
1512 {
1513 return (20 * log10times100(status_quality)) / 100;
1514 }
1515
1516 static int cck_snr_db(u8 status_quality)
1517 {
1518 int r = MAX_CCK_EVM_DB - cck_evm_db(status_quality);
1519 ZD_ASSERT(r >= 0);
1520 return r;
1521 }
1522
1523 static int cck_qual_percent(u8 status_quality)
1524 {
1525 int r;
1526
1527 r = cck_snr_db(status_quality);
1528 r = (100*r)/17;
1529 return r <= 100 ? r : 100;
1530 }
1531
1532 u8 zd_rx_qual_percent(const void *rx_frame, unsigned int size,
1533 const struct rx_status *status)
1534 {
1535 return (status->frame_status&ZD_RX_OFDM) ?
1536 ofdm_qual_percent(status->signal_quality_ofdm,
1537 zd_ofdm_plcp_header_rate(rx_frame),
1538 size) :
1539 cck_qual_percent(status->signal_quality_cck);
1540 }
1541
1542 u8 zd_rx_strength_percent(u8 rssi)
1543 {
1544 int r = (rssi*100) / 41;
1545 if (r > 100)
1546 r = 100;
1547 return (u8) r;
1548 }
1549
1550 u16 zd_rx_rate(const void *rx_frame, const struct rx_status *status)
1551 {
1552 static const u16 ofdm_rates[] = {
1553 [ZD_OFDM_RATE_6M] = 60,
1554 [ZD_OFDM_RATE_9M] = 90,
1555 [ZD_OFDM_RATE_12M] = 120,
1556 [ZD_OFDM_RATE_18M] = 180,
1557 [ZD_OFDM_RATE_24M] = 240,
1558 [ZD_OFDM_RATE_36M] = 360,
1559 [ZD_OFDM_RATE_48M] = 480,
1560 [ZD_OFDM_RATE_54M] = 540,
1561 };
1562 u16 rate;
1563 if (status->frame_status & ZD_RX_OFDM) {
1564 u8 ofdm_rate = zd_ofdm_plcp_header_rate(rx_frame);
1565 rate = ofdm_rates[ofdm_rate & 0xf];
1566 } else {
1567 u8 cck_rate = zd_cck_plcp_header_rate(rx_frame);
1568 switch (cck_rate) {
1569 case ZD_CCK_SIGNAL_1M:
1570 rate = 10;
1571 break;
1572 case ZD_CCK_SIGNAL_2M:
1573 rate = 20;
1574 break;
1575 case ZD_CCK_SIGNAL_5M5:
1576 rate = 55;
1577 break;
1578 case ZD_CCK_SIGNAL_11M:
1579 rate = 110;
1580 break;
1581 default:
1582 rate = 0;
1583 }
1584 }
1585
1586 return rate;
1587 }
1588
1589 int zd_chip_switch_radio_on(struct zd_chip *chip)
1590 {
1591 int r;
1592
1593 mutex_lock(&chip->mutex);
1594 r = zd_switch_radio_on(&chip->rf);
1595 mutex_unlock(&chip->mutex);
1596 return r;
1597 }
1598
1599 int zd_chip_switch_radio_off(struct zd_chip *chip)
1600 {
1601 int r;
1602
1603 mutex_lock(&chip->mutex);
1604 r = zd_switch_radio_off(&chip->rf);
1605 mutex_unlock(&chip->mutex);
1606 return r;
1607 }
1608
1609 int zd_chip_enable_int(struct zd_chip *chip)
1610 {
1611 int r;
1612
1613 mutex_lock(&chip->mutex);
1614 r = zd_usb_enable_int(&chip->usb);
1615 mutex_unlock(&chip->mutex);
1616 return r;
1617 }
1618
1619 void zd_chip_disable_int(struct zd_chip *chip)
1620 {
1621 mutex_lock(&chip->mutex);
1622 zd_usb_disable_int(&chip->usb);
1623 mutex_unlock(&chip->mutex);
1624 }
1625
1626 int zd_chip_enable_rx(struct zd_chip *chip)
1627 {
1628 int r;
1629
1630 mutex_lock(&chip->mutex);
1631 r = zd_usb_enable_rx(&chip->usb);
1632 mutex_unlock(&chip->mutex);
1633 return r;
1634 }
1635
1636 void zd_chip_disable_rx(struct zd_chip *chip)
1637 {
1638 mutex_lock(&chip->mutex);
1639 zd_usb_disable_rx(&chip->usb);
1640 mutex_unlock(&chip->mutex);
1641 }
1642
1643 int zd_rfwritev_locked(struct zd_chip *chip,
1644 const u32* values, unsigned int count, u8 bits)
1645 {
1646 int r;
1647 unsigned int i;
1648
1649 for (i = 0; i < count; i++) {
1650 r = zd_rfwrite_locked(chip, values[i], bits);
1651 if (r)
1652 return r;
1653 }
1654
1655 return 0;
1656 }
1657
1658 /*
1659 * We can optionally program the RF directly through CR regs, if supported by
1660 * the hardware. This is much faster than the older method.
1661 */
1662 int zd_rfwrite_cr_locked(struct zd_chip *chip, u32 value)
1663 {
1664 struct zd_ioreq16 ioreqs[] = {
1665 { CR244, (value >> 16) & 0xff },
1666 { CR243, (value >> 8) & 0xff },
1667 { CR242, value & 0xff },
1668 };
1669 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1670 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1671 }
1672
1673 int zd_rfwritev_cr_locked(struct zd_chip *chip,
1674 const u32 *values, unsigned int count)
1675 {
1676 int r;
1677 unsigned int i;
1678
1679 for (i = 0; i < count; i++) {
1680 r = zd_rfwrite_cr_locked(chip, values[i]);
1681 if (r)
1682 return r;
1683 }
1684
1685 return 0;
1686 }
1687
1688 int zd_chip_set_multicast_hash(struct zd_chip *chip,
1689 struct zd_mc_hash *hash)
1690 {
1691 struct zd_ioreq32 ioreqs[] = {
1692 { CR_GROUP_HASH_P1, hash->low },
1693 { CR_GROUP_HASH_P2, hash->high },
1694 };
1695
1696 dev_dbg_f(zd_chip_dev(chip), "hash l 0x%08x h 0x%08x\n",
1697 ioreqs[0].value, ioreqs[1].value);
1698 return zd_iowrite32a(chip, ioreqs, ARRAY_SIZE(ioreqs));
1699 }
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