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ext3: add block bitmap validation
[pv_ops_mirror.git] / drivers / spi / pxa2xx_spi.c
blob365e0e355aea302e684451592d9315862f565275
1 /*
2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 */
18
19 #include <linux/init.h>
20 #include <linux/module.h>
21 #include <linux/device.h>
22 #include <linux/ioport.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/platform_device.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/spi/spi.h>
28 #include <linux/workqueue.h>
29 #include <linux/delay.h>
30 #include <linux/clk.h>
31
32 #include <asm/io.h>
33 #include <asm/irq.h>
34 #include <asm/hardware.h>
35 #include <asm/delay.h>
36 #include <asm/dma.h>
37
38 #include <asm/arch/hardware.h>
39 #include <asm/arch/pxa-regs.h>
40 #include <asm/arch/regs-ssp.h>
41 #include <asm/arch/ssp.h>
42 #include <asm/arch/pxa2xx_spi.h>
43
44 MODULE_AUTHOR("Stephen Street");
45 MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
46 MODULE_LICENSE("GPL");
47
48 #define MAX_BUSES 3
49
50 #define DMA_INT_MASK (DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERR)
51 #define RESET_DMA_CHANNEL (DCSR_NODESC | DMA_INT_MASK)
52 #define IS_DMA_ALIGNED(x) (((u32)(x)&0x07)==0)
53
54 /* for testing SSCR1 changes that require SSP restart, basically
55 * everything except the service and interrupt enables */
56 #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_EBCEI | SSCR1_SCFR \
57 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
58 | SSCR1_RWOT | SSCR1_TRAIL | SSCR1_PINTE \
59 | SSCR1_STRF | SSCR1_EFWR |SSCR1_RFT \
60 | SSCR1_TFT | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
61
62 #define DEFINE_SSP_REG(reg, off) \
63 static inline u32 read_##reg(void *p) { return __raw_readl(p + (off)); } \
64 static inline void write_##reg(u32 v, void *p) { __raw_writel(v, p + (off)); }
65
66 DEFINE_SSP_REG(SSCR0, 0x00)
67 DEFINE_SSP_REG(SSCR1, 0x04)
68 DEFINE_SSP_REG(SSSR, 0x08)
69 DEFINE_SSP_REG(SSITR, 0x0c)
70 DEFINE_SSP_REG(SSDR, 0x10)
71 DEFINE_SSP_REG(SSTO, 0x28)
72 DEFINE_SSP_REG(SSPSP, 0x2c)
73
74 #define START_STATE ((void*)0)
75 #define RUNNING_STATE ((void*)1)
76 #define DONE_STATE ((void*)2)
77 #define ERROR_STATE ((void*)-1)
78
79 #define QUEUE_RUNNING 0
80 #define QUEUE_STOPPED 1
81
82 struct driver_data {
83 /* Driver model hookup */
84 struct platform_device *pdev;
85
86 /* SSP Info */
87 struct ssp_device *ssp;
88
89 /* SPI framework hookup */
90 enum pxa_ssp_type ssp_type;
91 struct spi_master *master;
92
93 /* PXA hookup */
94 struct pxa2xx_spi_master *master_info;
95
96 /* DMA setup stuff */
97 int rx_channel;
98 int tx_channel;
99 u32 *null_dma_buf;
100
101 /* SSP register addresses */
102 void *ioaddr;
103 u32 ssdr_physical;
104
105 /* SSP masks*/
106 u32 dma_cr1;
107 u32 int_cr1;
108 u32 clear_sr;
109 u32 mask_sr;
110
111 /* Driver message queue */
112 struct workqueue_struct *workqueue;
113 struct work_struct pump_messages;
114 spinlock_t lock;
115 struct list_head queue;
116 int busy;
117 int run;
118
119 /* Message Transfer pump */
120 struct tasklet_struct pump_transfers;
121
122 /* Current message transfer state info */
123 struct spi_message* cur_msg;
124 struct spi_transfer* cur_transfer;
125 struct chip_data *cur_chip;
126 size_t len;
127 void *tx;
128 void *tx_end;
129 void *rx;
130 void *rx_end;
131 int dma_mapped;
132 dma_addr_t rx_dma;
133 dma_addr_t tx_dma;
134 size_t rx_map_len;
135 size_t tx_map_len;
136 u8 n_bytes;
137 u32 dma_width;
138 int cs_change;
139 int (*write)(struct driver_data *drv_data);
140 int (*read)(struct driver_data *drv_data);
141 irqreturn_t (*transfer_handler)(struct driver_data *drv_data);
142 void (*cs_control)(u32 command);
143 };
144
145 struct chip_data {
146 u32 cr0;
147 u32 cr1;
148 u32 psp;
149 u32 timeout;
150 u8 n_bytes;
151 u32 dma_width;
152 u32 dma_burst_size;
153 u32 threshold;
154 u32 dma_threshold;
155 u8 enable_dma;
156 u8 bits_per_word;
157 u32 speed_hz;
158 int (*write)(struct driver_data *drv_data);
159 int (*read)(struct driver_data *drv_data);
160 void (*cs_control)(u32 command);
161 };
162
163 static void pump_messages(struct work_struct *work);
164
165 static int flush(struct driver_data *drv_data)
166 {
167 unsigned long limit = loops_per_jiffy << 1;
168
169 void *reg = drv_data->ioaddr;
170
171 do {
172 while (read_SSSR(reg) & SSSR_RNE) {
173 read_SSDR(reg);
174 }
175 } while ((read_SSSR(reg) & SSSR_BSY) && limit--);
176 write_SSSR(SSSR_ROR, reg);
177
178 return limit;
179 }
180
181 static void null_cs_control(u32 command)
182 {
183 }
184
185 static int null_writer(struct driver_data *drv_data)
186 {
187 void *reg = drv_data->ioaddr;
188 u8 n_bytes = drv_data->n_bytes;
189
190 if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00)
191 || (drv_data->tx == drv_data->tx_end))
192 return 0;
193
194 write_SSDR(0, reg);
195 drv_data->tx += n_bytes;
196
197 return 1;
198 }
199
200 static int null_reader(struct driver_data *drv_data)
201 {
202 void *reg = drv_data->ioaddr;
203 u8 n_bytes = drv_data->n_bytes;
204
205 while ((read_SSSR(reg) & SSSR_RNE)
206 && (drv_data->rx < drv_data->rx_end)) {
207 read_SSDR(reg);
208 drv_data->rx += n_bytes;
209 }
210
211 return drv_data->rx == drv_data->rx_end;
212 }
213
214 static int u8_writer(struct driver_data *drv_data)
215 {
216 void *reg = drv_data->ioaddr;
217
218 if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00)
219 || (drv_data->tx == drv_data->tx_end))
220 return 0;
221
222 write_SSDR(*(u8 *)(drv_data->tx), reg);
223 ++drv_data->tx;
224
225 return 1;
226 }
227
228 static int u8_reader(struct driver_data *drv_data)
229 {
230 void *reg = drv_data->ioaddr;
231
232 while ((read_SSSR(reg) & SSSR_RNE)
233 && (drv_data->rx < drv_data->rx_end)) {
234 *(u8 *)(drv_data->rx) = read_SSDR(reg);
235 ++drv_data->rx;
236 }
237
238 return drv_data->rx == drv_data->rx_end;
239 }
240
241 static int u16_writer(struct driver_data *drv_data)
242 {
243 void *reg = drv_data->ioaddr;
244
245 if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00)
246 || (drv_data->tx == drv_data->tx_end))
247 return 0;
248
249 write_SSDR(*(u16 *)(drv_data->tx), reg);
250 drv_data->tx += 2;
251
252 return 1;
253 }
254
255 static int u16_reader(struct driver_data *drv_data)
256 {
257 void *reg = drv_data->ioaddr;
258
259 while ((read_SSSR(reg) & SSSR_RNE)
260 && (drv_data->rx < drv_data->rx_end)) {
261 *(u16 *)(drv_data->rx) = read_SSDR(reg);
262 drv_data->rx += 2;
263 }
264
265 return drv_data->rx == drv_data->rx_end;
266 }
267
268 static int u32_writer(struct driver_data *drv_data)
269 {
270 void *reg = drv_data->ioaddr;
271
272 if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00)
273 || (drv_data->tx == drv_data->tx_end))
274 return 0;
275
276 write_SSDR(*(u32 *)(drv_data->tx), reg);
277 drv_data->tx += 4;
278
279 return 1;
280 }
281
282 static int u32_reader(struct driver_data *drv_data)
283 {
284 void *reg = drv_data->ioaddr;
285
286 while ((read_SSSR(reg) & SSSR_RNE)
287 && (drv_data->rx < drv_data->rx_end)) {
288 *(u32 *)(drv_data->rx) = read_SSDR(reg);
289 drv_data->rx += 4;
290 }
291
292 return drv_data->rx == drv_data->rx_end;
293 }
294
295 static void *next_transfer(struct driver_data *drv_data)
296 {
297 struct spi_message *msg = drv_data->cur_msg;
298 struct spi_transfer *trans = drv_data->cur_transfer;
299
300 /* Move to next transfer */
301 if (trans->transfer_list.next != &msg->transfers) {
302 drv_data->cur_transfer =
303 list_entry(trans->transfer_list.next,
304 struct spi_transfer,
305 transfer_list);
306 return RUNNING_STATE;
307 } else
308 return DONE_STATE;
309 }
310
311 static int map_dma_buffers(struct driver_data *drv_data)
312 {
313 struct spi_message *msg = drv_data->cur_msg;
314 struct device *dev = &msg->spi->dev;
315
316 if (!drv_data->cur_chip->enable_dma)
317 return 0;
318
319 if (msg->is_dma_mapped)
320 return drv_data->rx_dma && drv_data->tx_dma;
321
322 if (!IS_DMA_ALIGNED(drv_data->rx) || !IS_DMA_ALIGNED(drv_data->tx))
323 return 0;
324
325 /* Modify setup if rx buffer is null */
326 if (drv_data->rx == NULL) {
327 *drv_data->null_dma_buf = 0;
328 drv_data->rx = drv_data->null_dma_buf;
329 drv_data->rx_map_len = 4;
330 } else
331 drv_data->rx_map_len = drv_data->len;
332
333
334 /* Modify setup if tx buffer is null */
335 if (drv_data->tx == NULL) {
336 *drv_data->null_dma_buf = 0;
337 drv_data->tx = drv_data->null_dma_buf;
338 drv_data->tx_map_len = 4;
339 } else
340 drv_data->tx_map_len = drv_data->len;
341
342 /* Stream map the rx buffer */
343 drv_data->rx_dma = dma_map_single(dev, drv_data->rx,
344 drv_data->rx_map_len,
345 DMA_FROM_DEVICE);
346 if (dma_mapping_error(drv_data->rx_dma))
347 return 0;
348
349 /* Stream map the tx buffer */
350 drv_data->tx_dma = dma_map_single(dev, drv_data->tx,
351 drv_data->tx_map_len,
352 DMA_TO_DEVICE);
353
354 if (dma_mapping_error(drv_data->tx_dma)) {
355 dma_unmap_single(dev, drv_data->rx_dma,
356 drv_data->rx_map_len, DMA_FROM_DEVICE);
357 return 0;
358 }
359
360 return 1;
361 }
362
363 static void unmap_dma_buffers(struct driver_data *drv_data)
364 {
365 struct device *dev;
366
367 if (!drv_data->dma_mapped)
368 return;
369
370 if (!drv_data->cur_msg->is_dma_mapped) {
371 dev = &drv_data->cur_msg->spi->dev;
372 dma_unmap_single(dev, drv_data->rx_dma,
373 drv_data->rx_map_len, DMA_FROM_DEVICE);
374 dma_unmap_single(dev, drv_data->tx_dma,
375 drv_data->tx_map_len, DMA_TO_DEVICE);
376 }
377
378 drv_data->dma_mapped = 0;
379 }
380
381 /* caller already set message->status; dma and pio irqs are blocked */
382 static void giveback(struct driver_data *drv_data)
383 {
384 struct spi_transfer* last_transfer;
385 unsigned long flags;
386 struct spi_message *msg;
387
388 spin_lock_irqsave(&drv_data->lock, flags);
389 msg = drv_data->cur_msg;
390 drv_data->cur_msg = NULL;
391 drv_data->cur_transfer = NULL;
392 drv_data->cur_chip = NULL;
393 queue_work(drv_data->workqueue, &drv_data->pump_messages);
394 spin_unlock_irqrestore(&drv_data->lock, flags);
395
396 last_transfer = list_entry(msg->transfers.prev,
397 struct spi_transfer,
398 transfer_list);
399
400 if (!last_transfer->cs_change)
401 drv_data->cs_control(PXA2XX_CS_DEASSERT);
402
403 msg->state = NULL;
404 if (msg->complete)
405 msg->complete(msg->context);
406 }
407
408 static int wait_ssp_rx_stall(void *ioaddr)
409 {
410 unsigned long limit = loops_per_jiffy << 1;
411
412 while ((read_SSSR(ioaddr) & SSSR_BSY) && limit--)
413 cpu_relax();
414
415 return limit;
416 }
417
418 static int wait_dma_channel_stop(int channel)
419 {
420 unsigned long limit = loops_per_jiffy << 1;
421
422 while (!(DCSR(channel) & DCSR_STOPSTATE) && limit--)
423 cpu_relax();
424
425 return limit;
426 }
427
428 void dma_error_stop(struct driver_data *drv_data, const char *msg)
429 {
430 void *reg = drv_data->ioaddr;
431
432 /* Stop and reset */
433 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
434 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
435 write_SSSR(drv_data->clear_sr, reg);
436 write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);
437 if (drv_data->ssp_type != PXA25x_SSP)
438 write_SSTO(0, reg);
439 flush(drv_data);
440 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
441
442 unmap_dma_buffers(drv_data);
443
444 dev_err(&drv_data->pdev->dev, "%s\n", msg);
445
446 drv_data->cur_msg->state = ERROR_STATE;
447 tasklet_schedule(&drv_data->pump_transfers);
448 }
449
450 static void dma_transfer_complete(struct driver_data *drv_data)
451 {
452 void *reg = drv_data->ioaddr;
453 struct spi_message *msg = drv_data->cur_msg;
454
455 /* Clear and disable interrupts on SSP and DMA channels*/
456 write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);
457 write_SSSR(drv_data->clear_sr, reg);
458 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
459 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
460
461 if (wait_dma_channel_stop(drv_data->rx_channel) == 0)
462 dev_err(&drv_data->pdev->dev,
463 "dma_handler: dma rx channel stop failed\n");
464
465 if (wait_ssp_rx_stall(drv_data->ioaddr) == 0)
466 dev_err(&drv_data->pdev->dev,
467 "dma_transfer: ssp rx stall failed\n");
468
469 unmap_dma_buffers(drv_data);
470
471 /* update the buffer pointer for the amount completed in dma */
472 drv_data->rx += drv_data->len -
473 (DCMD(drv_data->rx_channel) & DCMD_LENGTH);
474
475 /* read trailing data from fifo, it does not matter how many
476 * bytes are in the fifo just read until buffer is full
477 * or fifo is empty, which ever occurs first */
478 drv_data->read(drv_data);
479
480 /* return count of what was actually read */
481 msg->actual_length += drv_data->len -
482 (drv_data->rx_end - drv_data->rx);
483
484 /* Release chip select if requested, transfer delays are
485 * handled in pump_transfers */
486 if (drv_data->cs_change)
487 drv_data->cs_control(PXA2XX_CS_DEASSERT);
488
489 /* Move to next transfer */
490 msg->state = next_transfer(drv_data);
491
492 /* Schedule transfer tasklet */
493 tasklet_schedule(&drv_data->pump_transfers);
494 }
495
496 static void dma_handler(int channel, void *data)
497 {
498 struct driver_data *drv_data = data;
499 u32 irq_status = DCSR(channel) & DMA_INT_MASK;
500
501 if (irq_status & DCSR_BUSERR) {
502
503 if (channel == drv_data->tx_channel)
504 dma_error_stop(drv_data,
505 "dma_handler: "
506 "bad bus address on tx channel");
507 else
508 dma_error_stop(drv_data,
509 "dma_handler: "
510 "bad bus address on rx channel");
511 return;
512 }
513
514 /* PXA255x_SSP has no timeout interrupt, wait for tailing bytes */
515 if ((channel == drv_data->tx_channel)
516 && (irq_status & DCSR_ENDINTR)
517 && (drv_data->ssp_type == PXA25x_SSP)) {
518
519 /* Wait for rx to stall */
520 if (wait_ssp_rx_stall(drv_data->ioaddr) == 0)
521 dev_err(&drv_data->pdev->dev,
522 "dma_handler: ssp rx stall failed\n");
523
524 /* finish this transfer, start the next */
525 dma_transfer_complete(drv_data);
526 }
527 }
528
529 static irqreturn_t dma_transfer(struct driver_data *drv_data)
530 {
531 u32 irq_status;
532 void *reg = drv_data->ioaddr;
533
534 irq_status = read_SSSR(reg) & drv_data->mask_sr;
535 if (irq_status & SSSR_ROR) {
536 dma_error_stop(drv_data, "dma_transfer: fifo overrun");
537 return IRQ_HANDLED;
538 }
539
540 /* Check for false positive timeout */
541 if ((irq_status & SSSR_TINT)
542 && (DCSR(drv_data->tx_channel) & DCSR_RUN)) {
543 write_SSSR(SSSR_TINT, reg);
544 return IRQ_HANDLED;
545 }
546
547 if (irq_status & SSSR_TINT || drv_data->rx == drv_data->rx_end) {
548
549 /* Clear and disable timeout interrupt, do the rest in
550 * dma_transfer_complete */
551 if (drv_data->ssp_type != PXA25x_SSP)
552 write_SSTO(0, reg);
553
554 /* finish this transfer, start the next */
555 dma_transfer_complete(drv_data);
556
557 return IRQ_HANDLED;
558 }
559
560 /* Opps problem detected */
561 return IRQ_NONE;
562 }
563
564 static void int_error_stop(struct driver_data *drv_data, const char* msg)
565 {
566 void *reg = drv_data->ioaddr;
567
568 /* Stop and reset SSP */
569 write_SSSR(drv_data->clear_sr, reg);
570 write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
571 if (drv_data->ssp_type != PXA25x_SSP)
572 write_SSTO(0, reg);
573 flush(drv_data);
574 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
575
576 dev_err(&drv_data->pdev->dev, "%s\n", msg);
577
578 drv_data->cur_msg->state = ERROR_STATE;
579 tasklet_schedule(&drv_data->pump_transfers);
580 }
581
582 static void int_transfer_complete(struct driver_data *drv_data)
583 {
584 void *reg = drv_data->ioaddr;
585
586 /* Stop SSP */
587 write_SSSR(drv_data->clear_sr, reg);
588 write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
589 if (drv_data->ssp_type != PXA25x_SSP)
590 write_SSTO(0, reg);
591
592 /* Update total byte transfered return count actual bytes read */
593 drv_data->cur_msg->actual_length += drv_data->len -
594 (drv_data->rx_end - drv_data->rx);
595
596 /* Release chip select if requested, transfer delays are
597 * handled in pump_transfers */
598 if (drv_data->cs_change)
599 drv_data->cs_control(PXA2XX_CS_DEASSERT);
600
601 /* Move to next transfer */
602 drv_data->cur_msg->state = next_transfer(drv_data);
603
604 /* Schedule transfer tasklet */
605 tasklet_schedule(&drv_data->pump_transfers);
606 }
607
608 static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
609 {
610 void *reg = drv_data->ioaddr;
611
612 u32 irq_mask = (read_SSCR1(reg) & SSCR1_TIE) ?
613 drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
614
615 u32 irq_status = read_SSSR(reg) & irq_mask;
616
617 if (irq_status & SSSR_ROR) {
618 int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
619 return IRQ_HANDLED;
620 }
621
622 if (irq_status & SSSR_TINT) {
623 write_SSSR(SSSR_TINT, reg);
624 if (drv_data->read(drv_data)) {
625 int_transfer_complete(drv_data);
626 return IRQ_HANDLED;
627 }
628 }
629
630 /* Drain rx fifo, Fill tx fifo and prevent overruns */
631 do {
632 if (drv_data->read(drv_data)) {
633 int_transfer_complete(drv_data);
634 return IRQ_HANDLED;
635 }
636 } while (drv_data->write(drv_data));
637
638 if (drv_data->read(drv_data)) {
639 int_transfer_complete(drv_data);
640 return IRQ_HANDLED;
641 }
642
643 if (drv_data->tx == drv_data->tx_end) {
644 write_SSCR1(read_SSCR1(reg) & ~SSCR1_TIE, reg);
645 /* PXA25x_SSP has no timeout, read trailing bytes */
646 if (drv_data->ssp_type == PXA25x_SSP) {
647 if (!wait_ssp_rx_stall(reg))
648 {
649 int_error_stop(drv_data, "interrupt_transfer: "
650 "rx stall failed");
651 return IRQ_HANDLED;
652 }
653 if (!drv_data->read(drv_data))
654 {
655 int_error_stop(drv_data,
656 "interrupt_transfer: "
657 "trailing byte read failed");
658 return IRQ_HANDLED;
659 }
660 int_transfer_complete(drv_data);
661 }
662 }
663
664 /* We did something */
665 return IRQ_HANDLED;
666 }
667
668 static irqreturn_t ssp_int(int irq, void *dev_id)
669 {
670 struct driver_data *drv_data = dev_id;
671 void *reg = drv_data->ioaddr;
672
673 if (!drv_data->cur_msg) {
674
675 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
676 write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
677 if (drv_data->ssp_type != PXA25x_SSP)
678 write_SSTO(0, reg);
679 write_SSSR(drv_data->clear_sr, reg);
680
681 dev_err(&drv_data->pdev->dev, "bad message state "
682 "in interrupt handler\n");
683
684 /* Never fail */
685 return IRQ_HANDLED;
686 }
687
688 return drv_data->transfer_handler(drv_data);
689 }
690
691 int set_dma_burst_and_threshold(struct chip_data *chip, struct spi_device *spi,
692 u8 bits_per_word, u32 *burst_code,
693 u32 *threshold)
694 {
695 struct pxa2xx_spi_chip *chip_info =
696 (struct pxa2xx_spi_chip *)spi->controller_data;
697 int bytes_per_word;
698 int burst_bytes;
699 int thresh_words;
700 int req_burst_size;
701 int retval = 0;
702
703 /* Set the threshold (in registers) to equal the same amount of data
704 * as represented by burst size (in bytes). The computation below
705 * is (burst_size rounded up to nearest 8 byte, word or long word)
706 * divided by (bytes/register); the tx threshold is the inverse of
707 * the rx, so that there will always be enough data in the rx fifo
708 * to satisfy a burst, and there will always be enough space in the
709 * tx fifo to accept a burst (a tx burst will overwrite the fifo if
710 * there is not enough space), there must always remain enough empty
711 * space in the rx fifo for any data loaded to the tx fifo.
712 * Whenever burst_size (in bytes) equals bits/word, the fifo threshold
713 * will be 8, or half the fifo;
714 * The threshold can only be set to 2, 4 or 8, but not 16, because
715 * to burst 16 to the tx fifo, the fifo would have to be empty;
716 * however, the minimum fifo trigger level is 1, and the tx will
717 * request service when the fifo is at this level, with only 15 spaces.
718 */
719
720 /* find bytes/word */
721 if (bits_per_word <= 8)
722 bytes_per_word = 1;
723 else if (bits_per_word <= 16)
724 bytes_per_word = 2;
725 else
726 bytes_per_word = 4;
727
728 /* use struct pxa2xx_spi_chip->dma_burst_size if available */
729 if (chip_info)
730 req_burst_size = chip_info->dma_burst_size;
731 else {
732 switch (chip->dma_burst_size) {
733 default:
734 /* if the default burst size is not set,
735 * do it now */
736 chip->dma_burst_size = DCMD_BURST8;
737 case DCMD_BURST8:
738 req_burst_size = 8;
739 break;
740 case DCMD_BURST16:
741 req_burst_size = 16;
742 break;
743 case DCMD_BURST32:
744 req_burst_size = 32;
745 break;
746 }
747 }
748 if (req_burst_size <= 8) {
749 *burst_code = DCMD_BURST8;
750 burst_bytes = 8;
751 } else if (req_burst_size <= 16) {
752 if (bytes_per_word == 1) {
753 /* don't burst more than 1/2 the fifo */
754 *burst_code = DCMD_BURST8;
755 burst_bytes = 8;
756 retval = 1;
757 } else {
758 *burst_code = DCMD_BURST16;
759 burst_bytes = 16;
760 }
761 } else {
762 if (bytes_per_word == 1) {
763 /* don't burst more than 1/2 the fifo */
764 *burst_code = DCMD_BURST8;
765 burst_bytes = 8;
766 retval = 1;
767 } else if (bytes_per_word == 2) {
768 /* don't burst more than 1/2 the fifo */
769 *burst_code = DCMD_BURST16;
770 burst_bytes = 16;
771 retval = 1;
772 } else {
773 *burst_code = DCMD_BURST32;
774 burst_bytes = 32;
775 }
776 }
777
778 thresh_words = burst_bytes / bytes_per_word;
779
780 /* thresh_words will be between 2 and 8 */
781 *threshold = (SSCR1_RxTresh(thresh_words) & SSCR1_RFT)
782 | (SSCR1_TxTresh(16-thresh_words) & SSCR1_TFT);
783
784 return retval;
785 }
786
787 static unsigned int ssp_get_clk_div(struct ssp_device *ssp, int rate)
788 {
789 unsigned long ssp_clk = clk_get_rate(ssp->clk);
790
791 if (ssp->type == PXA25x_SSP)
792 return ((ssp_clk / (2 * rate) - 1) & 0xff) << 8;
793 else
794 return ((ssp_clk / rate - 1) & 0xfff) << 8;
795 }
796
797 static void pump_transfers(unsigned long data)
798 {
799 struct driver_data *drv_data = (struct driver_data *)data;
800 struct spi_message *message = NULL;
801 struct spi_transfer *transfer = NULL;
802 struct spi_transfer *previous = NULL;
803 struct chip_data *chip = NULL;
804 struct ssp_device *ssp = drv_data->ssp;
805 void *reg = drv_data->ioaddr;
806 u32 clk_div = 0;
807 u8 bits = 0;
808 u32 speed = 0;
809 u32 cr0;
810 u32 cr1;
811 u32 dma_thresh = drv_data->cur_chip->dma_threshold;
812 u32 dma_burst = drv_data->cur_chip->dma_burst_size;
813
814 /* Get current state information */
815 message = drv_data->cur_msg;
816 transfer = drv_data->cur_transfer;
817 chip = drv_data->cur_chip;
818
819 /* Handle for abort */
820 if (message->state == ERROR_STATE) {
821 message->status = -EIO;
822 giveback(drv_data);
823 return;
824 }
825
826 /* Handle end of message */
827 if (message->state == DONE_STATE) {
828 message->status = 0;
829 giveback(drv_data);
830 return;
831 }
832
833 /* Delay if requested at end of transfer*/
834 if (message->state == RUNNING_STATE) {
835 previous = list_entry(transfer->transfer_list.prev,
836 struct spi_transfer,
837 transfer_list);
838 if (previous->delay_usecs)
839 udelay(previous->delay_usecs);
840 }
841
842 /* Check transfer length */
843 if (transfer->len > 8191)
844 {
845 dev_warn(&drv_data->pdev->dev, "pump_transfers: transfer "
846 "length greater than 8191\n");
847 message->status = -EINVAL;
848 giveback(drv_data);
849 return;
850 }
851
852 /* Setup the transfer state based on the type of transfer */
853 if (flush(drv_data) == 0) {
854 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
855 message->status = -EIO;
856 giveback(drv_data);
857 return;
858 }
859 drv_data->n_bytes = chip->n_bytes;
860 drv_data->dma_width = chip->dma_width;
861 drv_data->cs_control = chip->cs_control;
862 drv_data->tx = (void *)transfer->tx_buf;
863 drv_data->tx_end = drv_data->tx + transfer->len;
864 drv_data->rx = transfer->rx_buf;
865 drv_data->rx_end = drv_data->rx + transfer->len;
866 drv_data->rx_dma = transfer->rx_dma;
867 drv_data->tx_dma = transfer->tx_dma;
868 drv_data->len = transfer->len & DCMD_LENGTH;
869 drv_data->write = drv_data->tx ? chip->write : null_writer;
870 drv_data->read = drv_data->rx ? chip->read : null_reader;
871 drv_data->cs_change = transfer->cs_change;
872
873 /* Change speed and bit per word on a per transfer */
874 cr0 = chip->cr0;
875 if (transfer->speed_hz || transfer->bits_per_word) {
876
877 bits = chip->bits_per_word;
878 speed = chip->speed_hz;
879
880 if (transfer->speed_hz)
881 speed = transfer->speed_hz;
882
883 if (transfer->bits_per_word)
884 bits = transfer->bits_per_word;
885
886 clk_div = ssp_get_clk_div(ssp, speed);
887
888 if (bits <= 8) {
889 drv_data->n_bytes = 1;
890 drv_data->dma_width = DCMD_WIDTH1;
891 drv_data->read = drv_data->read != null_reader ?
892 u8_reader : null_reader;
893 drv_data->write = drv_data->write != null_writer ?
894 u8_writer : null_writer;
895 } else if (bits <= 16) {
896 drv_data->n_bytes = 2;
897 drv_data->dma_width = DCMD_WIDTH2;
898 drv_data->read = drv_data->read != null_reader ?
899 u16_reader : null_reader;
900 drv_data->write = drv_data->write != null_writer ?
901 u16_writer : null_writer;
902 } else if (bits <= 32) {
903 drv_data->n_bytes = 4;
904 drv_data->dma_width = DCMD_WIDTH4;
905 drv_data->read = drv_data->read != null_reader ?
906 u32_reader : null_reader;
907 drv_data->write = drv_data->write != null_writer ?
908 u32_writer : null_writer;
909 }
910 /* if bits/word is changed in dma mode, then must check the
911 * thresholds and burst also */
912 if (chip->enable_dma) {
913 if (set_dma_burst_and_threshold(chip, message->spi,
914 bits, &dma_burst,
915 &dma_thresh))
916 if (printk_ratelimit())
917 dev_warn(&message->spi->dev,
918 "pump_transfer: "
919 "DMA burst size reduced to "
920 "match bits_per_word\n");
921 }
922
923 cr0 = clk_div
924 | SSCR0_Motorola
925 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
926 | SSCR0_SSE
927 | (bits > 16 ? SSCR0_EDSS : 0);
928 }
929
930 message->state = RUNNING_STATE;
931
932 /* Try to map dma buffer and do a dma transfer if successful */
933 if ((drv_data->dma_mapped = map_dma_buffers(drv_data))) {
934
935 /* Ensure we have the correct interrupt handler */
936 drv_data->transfer_handler = dma_transfer;
937
938 /* Setup rx DMA Channel */
939 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
940 DSADR(drv_data->rx_channel) = drv_data->ssdr_physical;
941 DTADR(drv_data->rx_channel) = drv_data->rx_dma;
942 if (drv_data->rx == drv_data->null_dma_buf)
943 /* No target address increment */
944 DCMD(drv_data->rx_channel) = DCMD_FLOWSRC
945 | drv_data->dma_width
946 | dma_burst
947 | drv_data->len;
948 else
949 DCMD(drv_data->rx_channel) = DCMD_INCTRGADDR
950 | DCMD_FLOWSRC
951 | drv_data->dma_width
952 | dma_burst
953 | drv_data->len;
954
955 /* Setup tx DMA Channel */
956 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
957 DSADR(drv_data->tx_channel) = drv_data->tx_dma;
958 DTADR(drv_data->tx_channel) = drv_data->ssdr_physical;
959 if (drv_data->tx == drv_data->null_dma_buf)
960 /* No source address increment */
961 DCMD(drv_data->tx_channel) = DCMD_FLOWTRG
962 | drv_data->dma_width
963 | dma_burst
964 | drv_data->len;
965 else
966 DCMD(drv_data->tx_channel) = DCMD_INCSRCADDR
967 | DCMD_FLOWTRG
968 | drv_data->dma_width
969 | dma_burst
970 | drv_data->len;
971
972 /* Enable dma end irqs on SSP to detect end of transfer */
973 if (drv_data->ssp_type == PXA25x_SSP)
974 DCMD(drv_data->tx_channel) |= DCMD_ENDIRQEN;
975
976 /* Fix me, need to handle cs polarity */
977 drv_data->cs_control(PXA2XX_CS_ASSERT);
978
979 /* Clear status and start DMA engine */
980 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
981 write_SSSR(drv_data->clear_sr, reg);
982 DCSR(drv_data->rx_channel) |= DCSR_RUN;
983 DCSR(drv_data->tx_channel) |= DCSR_RUN;
984 } else {
985 /* Ensure we have the correct interrupt handler */
986 drv_data->transfer_handler = interrupt_transfer;
987
988 /* Fix me, need to handle cs polarity */
989 drv_data->cs_control(PXA2XX_CS_ASSERT);
990
991 /* Clear status */
992 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
993 write_SSSR(drv_data->clear_sr, reg);
994 }
995
996 /* see if we need to reload the config registers */
997 if ((read_SSCR0(reg) != cr0)
998 || (read_SSCR1(reg) & SSCR1_CHANGE_MASK) !=
999 (cr1 & SSCR1_CHANGE_MASK)) {
1000
1001 write_SSCR0(cr0 & ~SSCR0_SSE, reg);
1002 if (drv_data->ssp_type != PXA25x_SSP)
1003 write_SSTO(chip->timeout, reg);
1004 write_SSCR1(cr1, reg);
1005 write_SSCR0(cr0, reg);
1006 } else {
1007 if (drv_data->ssp_type != PXA25x_SSP)
1008 write_SSTO(chip->timeout, reg);
1009 write_SSCR1(cr1, reg);
1010 }
1011 }
1012
1013 static void pump_messages(struct work_struct *work)
1014 {
1015 struct driver_data *drv_data =
1016 container_of(work, struct driver_data, pump_messages);
1017 unsigned long flags;
1018
1019 /* Lock queue and check for queue work */
1020 spin_lock_irqsave(&drv_data->lock, flags);
1021 if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
1022 drv_data->busy = 0;
1023 spin_unlock_irqrestore(&drv_data->lock, flags);
1024 return;
1025 }
1026
1027 /* Make sure we are not already running a message */
1028 if (drv_data->cur_msg) {
1029 spin_unlock_irqrestore(&drv_data->lock, flags);
1030 return;
1031 }
1032
1033 /* Extract head of queue */
1034 drv_data->cur_msg = list_entry(drv_data->queue.next,
1035 struct spi_message, queue);
1036 list_del_init(&drv_data->cur_msg->queue);
1037
1038 /* Initial message state*/
1039 drv_data->cur_msg->state = START_STATE;
1040 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
1041 struct spi_transfer,
1042 transfer_list);
1043
1044 /* prepare to setup the SSP, in pump_transfers, using the per
1045 * chip configuration */
1046 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
1047
1048 /* Mark as busy and launch transfers */
1049 tasklet_schedule(&drv_data->pump_transfers);
1050
1051 drv_data->busy = 1;
1052 spin_unlock_irqrestore(&drv_data->lock, flags);
1053 }
1054
1055 static int transfer(struct spi_device *spi, struct spi_message *msg)
1056 {
1057 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1058 unsigned long flags;
1059
1060 spin_lock_irqsave(&drv_data->lock, flags);
1061
1062 if (drv_data->run == QUEUE_STOPPED) {
1063 spin_unlock_irqrestore(&drv_data->lock, flags);
1064 return -ESHUTDOWN;
1065 }
1066
1067 msg->actual_length = 0;
1068 msg->status = -EINPROGRESS;
1069 msg->state = START_STATE;
1070
1071 list_add_tail(&msg->queue, &drv_data->queue);
1072
1073 if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
1074 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1075
1076 spin_unlock_irqrestore(&drv_data->lock, flags);
1077
1078 return 0;
1079 }
1080
1081 /* the spi->mode bits understood by this driver: */
1082 #define MODEBITS (SPI_CPOL | SPI_CPHA)
1083
1084 static int setup(struct spi_device *spi)
1085 {
1086 struct pxa2xx_spi_chip *chip_info = NULL;
1087 struct chip_data *chip;
1088 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1089 struct ssp_device *ssp = drv_data->ssp;
1090 unsigned int clk_div;
1091
1092 if (!spi->bits_per_word)
1093 spi->bits_per_word = 8;
1094
1095 if (drv_data->ssp_type != PXA25x_SSP
1096 && (spi->bits_per_word < 4 || spi->bits_per_word > 32)) {
1097 dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d "
1098 "b/w not 4-32 for type non-PXA25x_SSP\n",
1099 drv_data->ssp_type, spi->bits_per_word);
1100 return -EINVAL;
1101 }
1102 else if (drv_data->ssp_type == PXA25x_SSP
1103 && (spi->bits_per_word < 4
1104 || spi->bits_per_word > 16)) {
1105 dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d "
1106 "b/w not 4-16 for type PXA25x_SSP\n",
1107 drv_data->ssp_type, spi->bits_per_word);
1108 return -EINVAL;
1109 }
1110
1111 if (spi->mode & ~MODEBITS) {
1112 dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
1113 spi->mode & ~MODEBITS);
1114 return -EINVAL;
1115 }
1116
1117 /* Only alloc on first setup */
1118 chip = spi_get_ctldata(spi);
1119 if (!chip) {
1120 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1121 if (!chip) {
1122 dev_err(&spi->dev,
1123 "failed setup: can't allocate chip data\n");
1124 return -ENOMEM;
1125 }
1126
1127 chip->cs_control = null_cs_control;
1128 chip->enable_dma = 0;
1129 chip->timeout = 1000;
1130 chip->threshold = SSCR1_RxTresh(1) | SSCR1_TxTresh(1);
1131 chip->dma_burst_size = drv_data->master_info->enable_dma ?
1132 DCMD_BURST8 : 0;
1133 }
1134
1135 /* protocol drivers may change the chip settings, so...
1136 * if chip_info exists, use it */
1137 chip_info = spi->controller_data;
1138
1139 /* chip_info isn't always needed */
1140 chip->cr1 = 0;
1141 if (chip_info) {
1142 if (chip_info->cs_control)
1143 chip->cs_control = chip_info->cs_control;
1144
1145 chip->timeout = chip_info->timeout;
1146
1147 chip->threshold = (SSCR1_RxTresh(chip_info->rx_threshold) &
1148 SSCR1_RFT) |
1149 (SSCR1_TxTresh(chip_info->tx_threshold) &
1150 SSCR1_TFT);
1151
1152 chip->enable_dma = chip_info->dma_burst_size != 0
1153 && drv_data->master_info->enable_dma;
1154 chip->dma_threshold = 0;
1155
1156 if (chip_info->enable_loopback)
1157 chip->cr1 = SSCR1_LBM;
1158 }
1159
1160 /* set dma burst and threshold outside of chip_info path so that if
1161 * chip_info goes away after setting chip->enable_dma, the
1162 * burst and threshold can still respond to changes in bits_per_word */
1163 if (chip->enable_dma) {
1164 /* set up legal burst and threshold for dma */
1165 if (set_dma_burst_and_threshold(chip, spi, spi->bits_per_word,
1166 &chip->dma_burst_size,
1167 &chip->dma_threshold)) {
1168 dev_warn(&spi->dev, "in setup: DMA burst size reduced "
1169 "to match bits_per_word\n");
1170 }
1171 }
1172
1173 clk_div = ssp_get_clk_div(ssp, spi->max_speed_hz);
1174 chip->speed_hz = spi->max_speed_hz;
1175
1176 chip->cr0 = clk_div
1177 | SSCR0_Motorola
1178 | SSCR0_DataSize(spi->bits_per_word > 16 ?
1179 spi->bits_per_word - 16 : spi->bits_per_word)
1180 | SSCR0_SSE
1181 | (spi->bits_per_word > 16 ? SSCR0_EDSS : 0);
1182 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
1183 chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
1184 | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
1185
1186 /* NOTE: PXA25x_SSP _could_ use external clocking ... */
1187 if (drv_data->ssp_type != PXA25x_SSP)
1188 dev_dbg(&spi->dev, "%d bits/word, %ld Hz, mode %d\n",
1189 spi->bits_per_word,
1190 clk_get_rate(ssp->clk)
1191 / (1 + ((chip->cr0 & SSCR0_SCR) >> 8)),
1192 spi->mode & 0x3);
1193 else
1194 dev_dbg(&spi->dev, "%d bits/word, %ld Hz, mode %d\n",
1195 spi->bits_per_word,
1196 clk_get_rate(ssp->clk)
1197 / (1 + ((chip->cr0 & SSCR0_SCR) >> 8)),
1198 spi->mode & 0x3);
1199
1200 if (spi->bits_per_word <= 8) {
1201 chip->n_bytes = 1;
1202 chip->dma_width = DCMD_WIDTH1;
1203 chip->read = u8_reader;
1204 chip->write = u8_writer;
1205 } else if (spi->bits_per_word <= 16) {
1206 chip->n_bytes = 2;
1207 chip->dma_width = DCMD_WIDTH2;
1208 chip->read = u16_reader;
1209 chip->write = u16_writer;
1210 } else if (spi->bits_per_word <= 32) {
1211 chip->cr0 |= SSCR0_EDSS;
1212 chip->n_bytes = 4;
1213 chip->dma_width = DCMD_WIDTH4;
1214 chip->read = u32_reader;
1215 chip->write = u32_writer;
1216 } else {
1217 dev_err(&spi->dev, "invalid wordsize\n");
1218 return -ENODEV;
1219 }
1220 chip->bits_per_word = spi->bits_per_word;
1221
1222 spi_set_ctldata(spi, chip);
1223
1224 return 0;
1225 }
1226
1227 static void cleanup(struct spi_device *spi)
1228 {
1229 struct chip_data *chip = spi_get_ctldata(spi);
1230
1231 kfree(chip);
1232 }
1233
1234 static int __init init_queue(struct driver_data *drv_data)
1235 {
1236 INIT_LIST_HEAD(&drv_data->queue);
1237 spin_lock_init(&drv_data->lock);
1238
1239 drv_data->run = QUEUE_STOPPED;
1240 drv_data->busy = 0;
1241
1242 tasklet_init(&drv_data->pump_transfers,
1243 pump_transfers, (unsigned long)drv_data);
1244
1245 INIT_WORK(&drv_data->pump_messages, pump_messages);
1246 drv_data->workqueue = create_singlethread_workqueue(
1247 drv_data->master->dev.parent->bus_id);
1248 if (drv_data->workqueue == NULL)
1249 return -EBUSY;
1250
1251 return 0;
1252 }
1253
1254 static int start_queue(struct driver_data *drv_data)
1255 {
1256 unsigned long flags;
1257
1258 spin_lock_irqsave(&drv_data->lock, flags);
1259
1260 if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
1261 spin_unlock_irqrestore(&drv_data->lock, flags);
1262 return -EBUSY;
1263 }
1264
1265 drv_data->run = QUEUE_RUNNING;
1266 drv_data->cur_msg = NULL;
1267 drv_data->cur_transfer = NULL;
1268 drv_data->cur_chip = NULL;
1269 spin_unlock_irqrestore(&drv_data->lock, flags);
1270
1271 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1272
1273 return 0;
1274 }
1275
1276 static int stop_queue(struct driver_data *drv_data)
1277 {
1278 unsigned long flags;
1279 unsigned limit = 500;
1280 int status = 0;
1281
1282 spin_lock_irqsave(&drv_data->lock, flags);
1283
1284 /* This is a bit lame, but is optimized for the common execution path.
1285 * A wait_queue on the drv_data->busy could be used, but then the common
1286 * execution path (pump_messages) would be required to call wake_up or
1287 * friends on every SPI message. Do this instead */
1288 drv_data->run = QUEUE_STOPPED;
1289 while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1290 spin_unlock_irqrestore(&drv_data->lock, flags);
1291 msleep(10);
1292 spin_lock_irqsave(&drv_data->lock, flags);
1293 }
1294
1295 if (!list_empty(&drv_data->queue) || drv_data->busy)
1296 status = -EBUSY;
1297
1298 spin_unlock_irqrestore(&drv_data->lock, flags);
1299
1300 return status;
1301 }
1302
1303 static int destroy_queue(struct driver_data *drv_data)
1304 {
1305 int status;
1306
1307 status = stop_queue(drv_data);
1308 /* we are unloading the module or failing to load (only two calls
1309 * to this routine), and neither call can handle a return value.
1310 * However, destroy_workqueue calls flush_workqueue, and that will
1311 * block until all work is done. If the reason that stop_queue
1312 * timed out is that the work will never finish, then it does no
1313 * good to call destroy_workqueue, so return anyway. */
1314 if (status != 0)
1315 return status;
1316
1317 destroy_workqueue(drv_data->workqueue);
1318
1319 return 0;
1320 }
1321
1322 static int __init pxa2xx_spi_probe(struct platform_device *pdev)
1323 {
1324 struct device *dev = &pdev->dev;
1325 struct pxa2xx_spi_master *platform_info;
1326 struct spi_master *master;
1327 struct driver_data *drv_data = 0;
1328 struct ssp_device *ssp;
1329 int status = 0;
1330
1331 platform_info = dev->platform_data;
1332
1333 ssp = ssp_request(pdev->id, pdev->name);
1334 if (ssp == NULL) {
1335 dev_err(&pdev->dev, "failed to request SSP%d\n", pdev->id);
1336 return -ENODEV;
1337 }
1338
1339 /* Allocate master with space for drv_data and null dma buffer */
1340 master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1341 if (!master) {
1342 dev_err(&pdev->dev, "can not alloc spi_master\n");
1343 ssp_free(ssp);
1344 return -ENOMEM;
1345 }
1346 drv_data = spi_master_get_devdata(master);
1347 drv_data->master = master;
1348 drv_data->master_info = platform_info;
1349 drv_data->pdev = pdev;
1350 drv_data->ssp = ssp;
1351
1352 master->bus_num = pdev->id;
1353 master->num_chipselect = platform_info->num_chipselect;
1354 master->cleanup = cleanup;
1355 master->setup = setup;
1356 master->transfer = transfer;
1357
1358 drv_data->ssp_type = ssp->type;
1359 drv_data->null_dma_buf = (u32 *)ALIGN((u32)(drv_data +
1360 sizeof(struct driver_data)), 8);
1361
1362 drv_data->ioaddr = ssp->mmio_base;
1363 drv_data->ssdr_physical = ssp->phys_base + SSDR;
1364 if (ssp->type == PXA25x_SSP) {
1365 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1366 drv_data->dma_cr1 = 0;
1367 drv_data->clear_sr = SSSR_ROR;
1368 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1369 } else {
1370 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1371 drv_data->dma_cr1 = SSCR1_TSRE | SSCR1_RSRE | SSCR1_TINTE;
1372 drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1373 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR;
1374 }
1375
1376 status = request_irq(ssp->irq, ssp_int, 0, dev->bus_id, drv_data);
1377 if (status < 0) {
1378 dev_err(&pdev->dev, "can not get IRQ\n");
1379 goto out_error_master_alloc;
1380 }
1381
1382 /* Setup DMA if requested */
1383 drv_data->tx_channel = -1;
1384 drv_data->rx_channel = -1;
1385 if (platform_info->enable_dma) {
1386
1387 /* Get two DMA channels (rx and tx) */
1388 drv_data->rx_channel = pxa_request_dma("pxa2xx_spi_ssp_rx",
1389 DMA_PRIO_HIGH,
1390 dma_handler,
1391 drv_data);
1392 if (drv_data->rx_channel < 0) {
1393 dev_err(dev, "problem (%d) requesting rx channel\n",
1394 drv_data->rx_channel);
1395 status = -ENODEV;
1396 goto out_error_irq_alloc;
1397 }
1398 drv_data->tx_channel = pxa_request_dma("pxa2xx_spi_ssp_tx",
1399 DMA_PRIO_MEDIUM,
1400 dma_handler,
1401 drv_data);
1402 if (drv_data->tx_channel < 0) {
1403 dev_err(dev, "problem (%d) requesting tx channel\n",
1404 drv_data->tx_channel);
1405 status = -ENODEV;
1406 goto out_error_dma_alloc;
1407 }
1408
1409 DRCMR(ssp->drcmr_rx) = DRCMR_MAPVLD | drv_data->rx_channel;
1410 DRCMR(ssp->drcmr_tx) = DRCMR_MAPVLD | drv_data->tx_channel;
1411 }
1412
1413 /* Enable SOC clock */
1414 clk_enable(ssp->clk);
1415
1416 /* Load default SSP configuration */
1417 write_SSCR0(0, drv_data->ioaddr);
1418 write_SSCR1(SSCR1_RxTresh(4) | SSCR1_TxTresh(12), drv_data->ioaddr);
1419 write_SSCR0(SSCR0_SerClkDiv(2)
1420 | SSCR0_Motorola
1421 | SSCR0_DataSize(8),
1422 drv_data->ioaddr);
1423 if (drv_data->ssp_type != PXA25x_SSP)
1424 write_SSTO(0, drv_data->ioaddr);
1425 write_SSPSP(0, drv_data->ioaddr);
1426
1427 /* Initial and start queue */
1428 status = init_queue(drv_data);
1429 if (status != 0) {
1430 dev_err(&pdev->dev, "problem initializing queue\n");
1431 goto out_error_clock_enabled;
1432 }
1433 status = start_queue(drv_data);
1434 if (status != 0) {
1435 dev_err(&pdev->dev, "problem starting queue\n");
1436 goto out_error_clock_enabled;
1437 }
1438
1439 /* Register with the SPI framework */
1440 platform_set_drvdata(pdev, drv_data);
1441 status = spi_register_master(master);
1442 if (status != 0) {
1443 dev_err(&pdev->dev, "problem registering spi master\n");
1444 goto out_error_queue_alloc;
1445 }
1446
1447 return status;
1448
1449 out_error_queue_alloc:
1450 destroy_queue(drv_data);
1451
1452 out_error_clock_enabled:
1453 clk_disable(ssp->clk);
1454
1455 out_error_dma_alloc:
1456 if (drv_data->tx_channel != -1)
1457 pxa_free_dma(drv_data->tx_channel);
1458 if (drv_data->rx_channel != -1)
1459 pxa_free_dma(drv_data->rx_channel);
1460
1461 out_error_irq_alloc:
1462 free_irq(ssp->irq, drv_data);
1463
1464 out_error_master_alloc:
1465 spi_master_put(master);
1466 ssp_free(ssp);
1467 return status;
1468 }
1469
1470 static int pxa2xx_spi_remove(struct platform_device *pdev)
1471 {
1472 struct driver_data *drv_data = platform_get_drvdata(pdev);
1473 struct ssp_device *ssp = drv_data->ssp;
1474 int status = 0;
1475
1476 if (!drv_data)
1477 return 0;
1478
1479 /* Remove the queue */
1480 status = destroy_queue(drv_data);
1481 if (status != 0)
1482 /* the kernel does not check the return status of this
1483 * this routine (mod->exit, within the kernel). Therefore
1484 * nothing is gained by returning from here, the module is
1485 * going away regardless, and we should not leave any more
1486 * resources allocated than necessary. We cannot free the
1487 * message memory in drv_data->queue, but we can release the
1488 * resources below. I think the kernel should honor -EBUSY
1489 * returns but... */
1490 dev_err(&pdev->dev, "pxa2xx_spi_remove: workqueue will not "
1491 "complete, message memory not freed\n");
1492
1493 /* Disable the SSP at the peripheral and SOC level */
1494 write_SSCR0(0, drv_data->ioaddr);
1495 clk_disable(ssp->clk);
1496
1497 /* Release DMA */
1498 if (drv_data->master_info->enable_dma) {
1499 DRCMR(ssp->drcmr_rx) = 0;
1500 DRCMR(ssp->drcmr_tx) = 0;
1501 pxa_free_dma(drv_data->tx_channel);
1502 pxa_free_dma(drv_data->rx_channel);
1503 }
1504
1505 /* Release IRQ */
1506 free_irq(ssp->irq, drv_data);
1507
1508 /* Release SSP */
1509 ssp_free(ssp);
1510
1511 /* Disconnect from the SPI framework */
1512 spi_unregister_master(drv_data->master);
1513
1514 /* Prevent double remove */
1515 platform_set_drvdata(pdev, NULL);
1516
1517 return 0;
1518 }
1519
1520 static void pxa2xx_spi_shutdown(struct platform_device *pdev)
1521 {
1522 int status = 0;
1523
1524 if ((status = pxa2xx_spi_remove(pdev)) != 0)
1525 dev_err(&pdev->dev, "shutdown failed with %d\n", status);
1526 }
1527
1528 #ifdef CONFIG_PM
1529
1530 static int pxa2xx_spi_suspend(struct platform_device *pdev, pm_message_t state)
1531 {
1532 struct driver_data *drv_data = platform_get_drvdata(pdev);
1533 struct ssp_device *ssp = drv_data->ssp;
1534 int status = 0;
1535
1536 status = stop_queue(drv_data);
1537 if (status != 0)
1538 return status;
1539 write_SSCR0(0, drv_data->ioaddr);
1540 clk_disable(ssp->clk);
1541
1542 return 0;
1543 }
1544
1545 static int pxa2xx_spi_resume(struct platform_device *pdev)
1546 {
1547 struct driver_data *drv_data = platform_get_drvdata(pdev);
1548 struct ssp_device *ssp = drv_data->ssp;
1549 int status = 0;
1550
1551 /* Enable the SSP clock */
1552 clk_disable(ssp->clk);
1553
1554 /* Start the queue running */
1555 status = start_queue(drv_data);
1556 if (status != 0) {
1557 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1558 return status;
1559 }
1560
1561 return 0;
1562 }
1563 #else
1564 #define pxa2xx_spi_suspend NULL
1565 #define pxa2xx_spi_resume NULL
1566 #endif /* CONFIG_PM */
1567
1568 static struct platform_driver driver = {
1569 .driver = {
1570 .name = "pxa2xx-spi",
1571 .bus = &platform_bus_type,
1572 .owner = THIS_MODULE,
1573 },
1574 .remove = pxa2xx_spi_remove,
1575 .shutdown = pxa2xx_spi_shutdown,
1576 .suspend = pxa2xx_spi_suspend,
1577 .resume = pxa2xx_spi_resume,
1578 };
1579
1580 static int __init pxa2xx_spi_init(void)
1581 {
1582 return platform_driver_probe(&driver, pxa2xx_spi_probe);
1583 }
1584 module_init(pxa2xx_spi_init);
1585
1586 static void __exit pxa2xx_spi_exit(void)
1587 {
1588 platform_driver_unregister(&driver);
1589 }
1590 module_exit(pxa2xx_spi_exit);
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