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libata: stop being overjealous about non-IO commands
[pv_ops_mirror.git] / drivers / ata / sata_sil24.c
blob187dcb02c681907d859672eafab0e0c6e8d376c6
1 /*
2 * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers
3 *
4 * Copyright 2005 Tejun Heo
5 *
6 * Based on preview driver from Silicon Image.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2, or (at your option) any
11 * later version.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 */
19
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/pci.h>
23 #include <linux/blkdev.h>
24 #include <linux/delay.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/device.h>
28 #include <scsi/scsi_host.h>
29 #include <scsi/scsi_cmnd.h>
30 #include <linux/libata.h>
31
32 #define DRV_NAME "sata_sil24"
33 #define DRV_VERSION "1.1"
34
35 /*
36 * Port request block (PRB) 32 bytes
37 */
38 struct sil24_prb {
39 __le16 ctrl;
40 __le16 prot;
41 __le32 rx_cnt;
42 u8 fis[6 * 4];
43 };
44
45 /*
46 * Scatter gather entry (SGE) 16 bytes
47 */
48 struct sil24_sge {
49 __le64 addr;
50 __le32 cnt;
51 __le32 flags;
52 };
53
54 /*
55 * Port multiplier
56 */
57 struct sil24_port_multiplier {
58 __le32 diag;
59 __le32 sactive;
60 };
61
62 enum {
63 SIL24_HOST_BAR = 0,
64 SIL24_PORT_BAR = 2,
65
66 /*
67 * Global controller registers (128 bytes @ BAR0)
68 */
69 /* 32 bit regs */
70 HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */
71 HOST_CTRL = 0x40,
72 HOST_IRQ_STAT = 0x44,
73 HOST_PHY_CFG = 0x48,
74 HOST_BIST_CTRL = 0x50,
75 HOST_BIST_PTRN = 0x54,
76 HOST_BIST_STAT = 0x58,
77 HOST_MEM_BIST_STAT = 0x5c,
78 HOST_FLASH_CMD = 0x70,
79 /* 8 bit regs */
80 HOST_FLASH_DATA = 0x74,
81 HOST_TRANSITION_DETECT = 0x75,
82 HOST_GPIO_CTRL = 0x76,
83 HOST_I2C_ADDR = 0x78, /* 32 bit */
84 HOST_I2C_DATA = 0x7c,
85 HOST_I2C_XFER_CNT = 0x7e,
86 HOST_I2C_CTRL = 0x7f,
87
88 /* HOST_SLOT_STAT bits */
89 HOST_SSTAT_ATTN = (1 << 31),
90
91 /* HOST_CTRL bits */
92 HOST_CTRL_M66EN = (1 << 16), /* M66EN PCI bus signal */
93 HOST_CTRL_TRDY = (1 << 17), /* latched PCI TRDY */
94 HOST_CTRL_STOP = (1 << 18), /* latched PCI STOP */
95 HOST_CTRL_DEVSEL = (1 << 19), /* latched PCI DEVSEL */
96 HOST_CTRL_REQ64 = (1 << 20), /* latched PCI REQ64 */
97 HOST_CTRL_GLOBAL_RST = (1 << 31), /* global reset */
98
99 /*
100 * Port registers
101 * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
102 */
103 PORT_REGS_SIZE = 0x2000,
104
105 PORT_LRAM = 0x0000, /* 31 LRAM slots and PMP regs */
106 PORT_LRAM_SLOT_SZ = 0x0080, /* 32 bytes PRB + 2 SGE, ACT... */
107
108 PORT_PMP = 0x0f80, /* 8 bytes PMP * 16 (128 bytes) */
109 PORT_PMP_STATUS = 0x0000, /* port device status offset */
110 PORT_PMP_QACTIVE = 0x0004, /* port device QActive offset */
111 PORT_PMP_SIZE = 0x0008, /* 8 bytes per PMP */
112
113 /* 32 bit regs */
114 PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */
115 PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */
116 PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */
117 PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */
118 PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */
119 PORT_ACTIVATE_UPPER_ADDR= 0x101c,
120 PORT_EXEC_FIFO = 0x1020, /* command execution fifo */
121 PORT_CMD_ERR = 0x1024, /* command error number */
122 PORT_FIS_CFG = 0x1028,
123 PORT_FIFO_THRES = 0x102c,
124 /* 16 bit regs */
125 PORT_DECODE_ERR_CNT = 0x1040,
126 PORT_DECODE_ERR_THRESH = 0x1042,
127 PORT_CRC_ERR_CNT = 0x1044,
128 PORT_CRC_ERR_THRESH = 0x1046,
129 PORT_HSHK_ERR_CNT = 0x1048,
130 PORT_HSHK_ERR_THRESH = 0x104a,
131 /* 32 bit regs */
132 PORT_PHY_CFG = 0x1050,
133 PORT_SLOT_STAT = 0x1800,
134 PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */
135 PORT_CONTEXT = 0x1e04,
136 PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */
137 PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */
138 PORT_SCONTROL = 0x1f00,
139 PORT_SSTATUS = 0x1f04,
140 PORT_SERROR = 0x1f08,
141 PORT_SACTIVE = 0x1f0c,
142
143 /* PORT_CTRL_STAT bits */
144 PORT_CS_PORT_RST = (1 << 0), /* port reset */
145 PORT_CS_DEV_RST = (1 << 1), /* device reset */
146 PORT_CS_INIT = (1 << 2), /* port initialize */
147 PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */
148 PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */
149 PORT_CS_PMP_RESUME = (1 << 6), /* PMP resume */
150 PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */
151 PORT_CS_PMP_EN = (1 << 13), /* port multiplier enable */
152 PORT_CS_RDY = (1 << 31), /* port ready to accept commands */
153
154 /* PORT_IRQ_STAT/ENABLE_SET/CLR */
155 /* bits[11:0] are masked */
156 PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */
157 PORT_IRQ_ERROR = (1 << 1), /* command execution error */
158 PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */
159 PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */
160 PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */
161 PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */
162 PORT_IRQ_UNK_FIS = (1 << 6), /* unknown FIS received */
163 PORT_IRQ_DEV_XCHG = (1 << 7), /* device exchanged */
164 PORT_IRQ_8B10B = (1 << 8), /* 8b/10b decode error threshold */
165 PORT_IRQ_CRC = (1 << 9), /* CRC error threshold */
166 PORT_IRQ_HANDSHAKE = (1 << 10), /* handshake error threshold */
167 PORT_IRQ_SDB_NOTIFY = (1 << 11), /* SDB notify received */
168
169 DEF_PORT_IRQ = PORT_IRQ_COMPLETE | PORT_IRQ_ERROR |
170 PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG |
171 PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_NOTIFY,
172
173 /* bits[27:16] are unmasked (raw) */
174 PORT_IRQ_RAW_SHIFT = 16,
175 PORT_IRQ_MASKED_MASK = 0x7ff,
176 PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT),
177
178 /* ENABLE_SET/CLR specific, intr steering - 2 bit field */
179 PORT_IRQ_STEER_SHIFT = 30,
180 PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT),
181
182 /* PORT_CMD_ERR constants */
183 PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */
184 PORT_CERR_SDB = 2, /* Error bit in SDB FIS */
185 PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */
186 PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */
187 PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */
188 PORT_CERR_DIRECTION = 6, /* Data direction mismatch */
189 PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */
190 PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */
191 PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */
192 PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */
193 PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */
194 PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */
195 PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */
196 PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */
197 PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */
198 PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */
199 PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */
200 PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */
201 PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */
202 PORT_CERR_XFR_MSTABRT = 34, /* PSD ecode 10 - master abort */
203 PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */
204 PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */
205
206 /* bits of PRB control field */
207 PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */
208 PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */
209 PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */
210 PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */
211 PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */
212
213 /* PRB protocol field */
214 PRB_PROT_PACKET = (1 << 0),
215 PRB_PROT_TCQ = (1 << 1),
216 PRB_PROT_NCQ = (1 << 2),
217 PRB_PROT_READ = (1 << 3),
218 PRB_PROT_WRITE = (1 << 4),
219 PRB_PROT_TRANSPARENT = (1 << 5),
220
221 /*
222 * Other constants
223 */
224 SGE_TRM = (1 << 31), /* Last SGE in chain */
225 SGE_LNK = (1 << 30), /* linked list
226 Points to SGT, not SGE */
227 SGE_DRD = (1 << 29), /* discard data read (/dev/null)
228 data address ignored */
229
230 SIL24_MAX_CMDS = 31,
231
232 /* board id */
233 BID_SIL3124 = 0,
234 BID_SIL3132 = 1,
235 BID_SIL3131 = 2,
236
237 /* host flags */
238 SIL24_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
239 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
240 ATA_FLAG_NCQ | ATA_FLAG_ACPI_SATA |
241 ATA_FLAG_AN | ATA_FLAG_PMP,
242 SIL24_COMMON_LFLAGS = ATA_LFLAG_SKIP_D2H_BSY,
243 SIL24_FLAG_PCIX_IRQ_WOC = (1 << 24), /* IRQ loss errata on PCI-X */
244
245 IRQ_STAT_4PORTS = 0xf,
246 };
247
248 struct sil24_ata_block {
249 struct sil24_prb prb;
250 struct sil24_sge sge[LIBATA_MAX_PRD];
251 };
252
253 struct sil24_atapi_block {
254 struct sil24_prb prb;
255 u8 cdb[16];
256 struct sil24_sge sge[LIBATA_MAX_PRD - 1];
257 };
258
259 union sil24_cmd_block {
260 struct sil24_ata_block ata;
261 struct sil24_atapi_block atapi;
262 };
263
264 static struct sil24_cerr_info {
265 unsigned int err_mask, action;
266 const char *desc;
267 } sil24_cerr_db[] = {
268 [0] = { AC_ERR_DEV, 0,
269 "device error" },
270 [PORT_CERR_DEV] = { AC_ERR_DEV, 0,
271 "device error via D2H FIS" },
272 [PORT_CERR_SDB] = { AC_ERR_DEV, 0,
273 "device error via SDB FIS" },
274 [PORT_CERR_DATA] = { AC_ERR_ATA_BUS, ATA_EH_SOFTRESET,
275 "error in data FIS" },
276 [PORT_CERR_SEND] = { AC_ERR_ATA_BUS, ATA_EH_SOFTRESET,
277 "failed to transmit command FIS" },
278 [PORT_CERR_INCONSISTENT] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
279 "protocol mismatch" },
280 [PORT_CERR_DIRECTION] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
281 "data directon mismatch" },
282 [PORT_CERR_UNDERRUN] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
283 "ran out of SGEs while writing" },
284 [PORT_CERR_OVERRUN] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
285 "ran out of SGEs while reading" },
286 [PORT_CERR_PKT_PROT] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
287 "invalid data directon for ATAPI CDB" },
288 [PORT_CERR_SGT_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_SOFTRESET,
289 "SGT no on qword boundary" },
290 [PORT_CERR_SGT_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
291 "PCI target abort while fetching SGT" },
292 [PORT_CERR_SGT_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
293 "PCI master abort while fetching SGT" },
294 [PORT_CERR_SGT_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
295 "PCI parity error while fetching SGT" },
296 [PORT_CERR_CMD_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_SOFTRESET,
297 "PRB not on qword boundary" },
298 [PORT_CERR_CMD_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
299 "PCI target abort while fetching PRB" },
300 [PORT_CERR_CMD_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
301 "PCI master abort while fetching PRB" },
302 [PORT_CERR_CMD_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
303 "PCI parity error while fetching PRB" },
304 [PORT_CERR_XFR_UNDEF] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
305 "undefined error while transferring data" },
306 [PORT_CERR_XFR_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
307 "PCI target abort while transferring data" },
308 [PORT_CERR_XFR_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
309 "PCI master abort while transferring data" },
310 [PORT_CERR_XFR_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
311 "PCI parity error while transferring data" },
312 [PORT_CERR_SENDSERVICE] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
313 "FIS received while sending service FIS" },
314 };
315
316 /*
317 * ap->private_data
318 *
319 * The preview driver always returned 0 for status. We emulate it
320 * here from the previous interrupt.
321 */
322 struct sil24_port_priv {
323 union sil24_cmd_block *cmd_block; /* 32 cmd blocks */
324 dma_addr_t cmd_block_dma; /* DMA base addr for them */
325 struct ata_taskfile tf; /* Cached taskfile registers */
326 int do_port_rst;
327 };
328
329 static void sil24_dev_config(struct ata_device *dev);
330 static u8 sil24_check_status(struct ata_port *ap);
331 static int sil24_scr_read(struct ata_port *ap, unsigned sc_reg, u32 *val);
332 static int sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val);
333 static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
334 static int sil24_qc_defer(struct ata_queued_cmd *qc);
335 static void sil24_qc_prep(struct ata_queued_cmd *qc);
336 static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc);
337 static void sil24_irq_clear(struct ata_port *ap);
338 static void sil24_pmp_attach(struct ata_port *ap);
339 static void sil24_pmp_detach(struct ata_port *ap);
340 static void sil24_freeze(struct ata_port *ap);
341 static void sil24_thaw(struct ata_port *ap);
342 static void sil24_error_handler(struct ata_port *ap);
343 static void sil24_post_internal_cmd(struct ata_queued_cmd *qc);
344 static int sil24_port_start(struct ata_port *ap);
345 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
346 #ifdef CONFIG_PM
347 static int sil24_pci_device_resume(struct pci_dev *pdev);
348 static int sil24_port_resume(struct ata_port *ap);
349 #endif
350
351 static const struct pci_device_id sil24_pci_tbl[] = {
352 { PCI_VDEVICE(CMD, 0x3124), BID_SIL3124 },
353 { PCI_VDEVICE(INTEL, 0x3124), BID_SIL3124 },
354 { PCI_VDEVICE(CMD, 0x3132), BID_SIL3132 },
355 { PCI_VDEVICE(CMD, 0x0242), BID_SIL3132 },
356 { PCI_VDEVICE(CMD, 0x3131), BID_SIL3131 },
357 { PCI_VDEVICE(CMD, 0x3531), BID_SIL3131 },
358
359 { } /* terminate list */
360 };
361
362 static struct pci_driver sil24_pci_driver = {
363 .name = DRV_NAME,
364 .id_table = sil24_pci_tbl,
365 .probe = sil24_init_one,
366 .remove = ata_pci_remove_one,
367 #ifdef CONFIG_PM
368 .suspend = ata_pci_device_suspend,
369 .resume = sil24_pci_device_resume,
370 #endif
371 };
372
373 static struct scsi_host_template sil24_sht = {
374 .module = THIS_MODULE,
375 .name = DRV_NAME,
376 .ioctl = ata_scsi_ioctl,
377 .queuecommand = ata_scsi_queuecmd,
378 .change_queue_depth = ata_scsi_change_queue_depth,
379 .can_queue = SIL24_MAX_CMDS,
380 .this_id = ATA_SHT_THIS_ID,
381 .sg_tablesize = LIBATA_MAX_PRD,
382 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
383 .emulated = ATA_SHT_EMULATED,
384 .use_clustering = ATA_SHT_USE_CLUSTERING,
385 .proc_name = DRV_NAME,
386 .dma_boundary = ATA_DMA_BOUNDARY,
387 .slave_configure = ata_scsi_slave_config,
388 .slave_destroy = ata_scsi_slave_destroy,
389 .bios_param = ata_std_bios_param,
390 };
391
392 static const struct ata_port_operations sil24_ops = {
393 .dev_config = sil24_dev_config,
394
395 .check_status = sil24_check_status,
396 .check_altstatus = sil24_check_status,
397 .dev_select = ata_noop_dev_select,
398
399 .tf_read = sil24_tf_read,
400
401 .qc_defer = sil24_qc_defer,
402 .qc_prep = sil24_qc_prep,
403 .qc_issue = sil24_qc_issue,
404
405 .irq_clear = sil24_irq_clear,
406
407 .scr_read = sil24_scr_read,
408 .scr_write = sil24_scr_write,
409
410 .pmp_attach = sil24_pmp_attach,
411 .pmp_detach = sil24_pmp_detach,
412
413 .freeze = sil24_freeze,
414 .thaw = sil24_thaw,
415 .error_handler = sil24_error_handler,
416 .post_internal_cmd = sil24_post_internal_cmd,
417
418 .port_start = sil24_port_start,
419
420 #ifdef CONFIG_PM
421 .port_resume = sil24_port_resume,
422 #endif
423 };
424
425 /*
426 * Use bits 30-31 of port_flags to encode available port numbers.
427 * Current maxium is 4.
428 */
429 #define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30)
430 #define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1)
431
432 static const struct ata_port_info sil24_port_info[] = {
433 /* sil_3124 */
434 {
435 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(4) |
436 SIL24_FLAG_PCIX_IRQ_WOC,
437 .link_flags = SIL24_COMMON_LFLAGS,
438 .pio_mask = 0x1f, /* pio0-4 */
439 .mwdma_mask = 0x07, /* mwdma0-2 */
440 .udma_mask = ATA_UDMA5, /* udma0-5 */
441 .port_ops = &sil24_ops,
442 },
443 /* sil_3132 */
444 {
445 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(2),
446 .link_flags = SIL24_COMMON_LFLAGS,
447 .pio_mask = 0x1f, /* pio0-4 */
448 .mwdma_mask = 0x07, /* mwdma0-2 */
449 .udma_mask = ATA_UDMA5, /* udma0-5 */
450 .port_ops = &sil24_ops,
451 },
452 /* sil_3131/sil_3531 */
453 {
454 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(1),
455 .link_flags = SIL24_COMMON_LFLAGS,
456 .pio_mask = 0x1f, /* pio0-4 */
457 .mwdma_mask = 0x07, /* mwdma0-2 */
458 .udma_mask = ATA_UDMA5, /* udma0-5 */
459 .port_ops = &sil24_ops,
460 },
461 };
462
463 static int sil24_tag(int tag)
464 {
465 if (unlikely(ata_tag_internal(tag)))
466 return 0;
467 return tag;
468 }
469
470 static void sil24_dev_config(struct ata_device *dev)
471 {
472 void __iomem *port = dev->link->ap->ioaddr.cmd_addr;
473
474 if (dev->cdb_len == 16)
475 writel(PORT_CS_CDB16, port + PORT_CTRL_STAT);
476 else
477 writel(PORT_CS_CDB16, port + PORT_CTRL_CLR);
478 }
479
480 static void sil24_read_tf(struct ata_port *ap, int tag, struct ata_taskfile *tf)
481 {
482 void __iomem *port = ap->ioaddr.cmd_addr;
483 struct sil24_prb __iomem *prb;
484 u8 fis[6 * 4];
485
486 prb = port + PORT_LRAM + sil24_tag(tag) * PORT_LRAM_SLOT_SZ;
487 memcpy_fromio(fis, prb->fis, sizeof(fis));
488 ata_tf_from_fis(fis, tf);
489 }
490
491 static u8 sil24_check_status(struct ata_port *ap)
492 {
493 struct sil24_port_priv *pp = ap->private_data;
494 return pp->tf.command;
495 }
496
497 static int sil24_scr_map[] = {
498 [SCR_CONTROL] = 0,
499 [SCR_STATUS] = 1,
500 [SCR_ERROR] = 2,
501 [SCR_ACTIVE] = 3,
502 };
503
504 static int sil24_scr_read(struct ata_port *ap, unsigned sc_reg, u32 *val)
505 {
506 void __iomem *scr_addr = ap->ioaddr.scr_addr;
507
508 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
509 void __iomem *addr;
510 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
511 *val = readl(scr_addr + sil24_scr_map[sc_reg] * 4);
512 return 0;
513 }
514 return -EINVAL;
515 }
516
517 static int sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val)
518 {
519 void __iomem *scr_addr = ap->ioaddr.scr_addr;
520
521 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
522 void __iomem *addr;
523 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
524 writel(val, scr_addr + sil24_scr_map[sc_reg] * 4);
525 return 0;
526 }
527 return -EINVAL;
528 }
529
530 static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
531 {
532 struct sil24_port_priv *pp = ap->private_data;
533 *tf = pp->tf;
534 }
535
536 static void sil24_config_port(struct ata_port *ap)
537 {
538 void __iomem *port = ap->ioaddr.cmd_addr;
539
540 /* configure IRQ WoC */
541 if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC)
542 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_STAT);
543 else
544 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
545
546 /* zero error counters. */
547 writel(0x8000, port + PORT_DECODE_ERR_THRESH);
548 writel(0x8000, port + PORT_CRC_ERR_THRESH);
549 writel(0x8000, port + PORT_HSHK_ERR_THRESH);
550 writel(0x0000, port + PORT_DECODE_ERR_CNT);
551 writel(0x0000, port + PORT_CRC_ERR_CNT);
552 writel(0x0000, port + PORT_HSHK_ERR_CNT);
553
554 /* always use 64bit activation */
555 writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);
556
557 /* clear port multiplier enable and resume bits */
558 writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR);
559 }
560
561 static void sil24_config_pmp(struct ata_port *ap, int attached)
562 {
563 void __iomem *port = ap->ioaddr.cmd_addr;
564
565 if (attached)
566 writel(PORT_CS_PMP_EN, port + PORT_CTRL_STAT);
567 else
568 writel(PORT_CS_PMP_EN, port + PORT_CTRL_CLR);
569 }
570
571 static void sil24_clear_pmp(struct ata_port *ap)
572 {
573 void __iomem *port = ap->ioaddr.cmd_addr;
574 int i;
575
576 writel(PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR);
577
578 for (i = 0; i < SATA_PMP_MAX_PORTS; i++) {
579 void __iomem *pmp_base = port + PORT_PMP + i * PORT_PMP_SIZE;
580
581 writel(0, pmp_base + PORT_PMP_STATUS);
582 writel(0, pmp_base + PORT_PMP_QACTIVE);
583 }
584 }
585
586 static int sil24_init_port(struct ata_port *ap)
587 {
588 void __iomem *port = ap->ioaddr.cmd_addr;
589 struct sil24_port_priv *pp = ap->private_data;
590 u32 tmp;
591
592 /* clear PMP error status */
593 if (ap->nr_pmp_links)
594 sil24_clear_pmp(ap);
595
596 writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
597 ata_wait_register(port + PORT_CTRL_STAT,
598 PORT_CS_INIT, PORT_CS_INIT, 10, 100);
599 tmp = ata_wait_register(port + PORT_CTRL_STAT,
600 PORT_CS_RDY, 0, 10, 100);
601
602 if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY) {
603 pp->do_port_rst = 1;
604 ap->link.eh_context.i.action |= ATA_EH_HARDRESET;
605 return -EIO;
606 }
607
608 return 0;
609 }
610
611 static int sil24_exec_polled_cmd(struct ata_port *ap, int pmp,
612 const struct ata_taskfile *tf,
613 int is_cmd, u32 ctrl,
614 unsigned long timeout_msec)
615 {
616 void __iomem *port = ap->ioaddr.cmd_addr;
617 struct sil24_port_priv *pp = ap->private_data;
618 struct sil24_prb *prb = &pp->cmd_block[0].ata.prb;
619 dma_addr_t paddr = pp->cmd_block_dma;
620 u32 irq_enabled, irq_mask, irq_stat;
621 int rc;
622
623 prb->ctrl = cpu_to_le16(ctrl);
624 ata_tf_to_fis(tf, pmp, is_cmd, prb->fis);
625
626 /* temporarily plug completion and error interrupts */
627 irq_enabled = readl(port + PORT_IRQ_ENABLE_SET);
628 writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR, port + PORT_IRQ_ENABLE_CLR);
629
630 writel((u32)paddr, port + PORT_CMD_ACTIVATE);
631 writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4);
632
633 irq_mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT;
634 irq_stat = ata_wait_register(port + PORT_IRQ_STAT, irq_mask, 0x0,
635 10, timeout_msec);
636
637 writel(irq_mask, port + PORT_IRQ_STAT); /* clear IRQs */
638 irq_stat >>= PORT_IRQ_RAW_SHIFT;
639
640 if (irq_stat & PORT_IRQ_COMPLETE)
641 rc = 0;
642 else {
643 /* force port into known state */
644 sil24_init_port(ap);
645
646 if (irq_stat & PORT_IRQ_ERROR)
647 rc = -EIO;
648 else
649 rc = -EBUSY;
650 }
651
652 /* restore IRQ enabled */
653 writel(irq_enabled, port + PORT_IRQ_ENABLE_SET);
654
655 return rc;
656 }
657
658 static int sil24_do_softreset(struct ata_link *link, unsigned int *class,
659 int pmp, unsigned long deadline)
660 {
661 struct ata_port *ap = link->ap;
662 unsigned long timeout_msec = 0;
663 struct ata_taskfile tf;
664 const char *reason;
665 int rc;
666
667 DPRINTK("ENTER\n");
668
669 if (ata_link_offline(link)) {
670 DPRINTK("PHY reports no device\n");
671 *class = ATA_DEV_NONE;
672 goto out;
673 }
674
675 /* put the port into known state */
676 if (sil24_init_port(ap)) {
677 reason = "port not ready";
678 goto err;
679 }
680
681 /* do SRST */
682 if (time_after(deadline, jiffies))
683 timeout_msec = jiffies_to_msecs(deadline - jiffies);
684
685 ata_tf_init(link->device, &tf); /* doesn't really matter */
686 rc = sil24_exec_polled_cmd(ap, pmp, &tf, 0, PRB_CTRL_SRST,
687 timeout_msec);
688 if (rc == -EBUSY) {
689 reason = "timeout";
690 goto err;
691 } else if (rc) {
692 reason = "SRST command error";
693 goto err;
694 }
695
696 sil24_read_tf(ap, 0, &tf);
697 *class = ata_dev_classify(&tf);
698
699 if (*class == ATA_DEV_UNKNOWN)
700 *class = ATA_DEV_NONE;
701
702 out:
703 DPRINTK("EXIT, class=%u\n", *class);
704 return 0;
705
706 err:
707 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
708 return -EIO;
709 }
710
711 static int sil24_softreset(struct ata_link *link, unsigned int *class,
712 unsigned long deadline)
713 {
714 return sil24_do_softreset(link, class, SATA_PMP_CTRL_PORT, deadline);
715 }
716
717 static int sil24_hardreset(struct ata_link *link, unsigned int *class,
718 unsigned long deadline)
719 {
720 struct ata_port *ap = link->ap;
721 void __iomem *port = ap->ioaddr.cmd_addr;
722 struct sil24_port_priv *pp = ap->private_data;
723 int did_port_rst = 0;
724 const char *reason;
725 int tout_msec, rc;
726 u32 tmp;
727
728 retry:
729 /* Sometimes, DEV_RST is not enough to recover the controller.
730 * This happens often after PM DMA CS errata.
731 */
732 if (pp->do_port_rst) {
733 ata_port_printk(ap, KERN_WARNING, "controller in dubious "
734 "state, performing PORT_RST\n");
735
736 writel(PORT_CS_PORT_RST, port + PORT_CTRL_STAT);
737 msleep(10);
738 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
739 ata_wait_register(port + PORT_CTRL_STAT, PORT_CS_RDY, 0,
740 10, 5000);
741
742 /* restore port configuration */
743 sil24_config_port(ap);
744 sil24_config_pmp(ap, ap->nr_pmp_links);
745
746 pp->do_port_rst = 0;
747 did_port_rst = 1;
748 }
749
750 /* sil24 does the right thing(tm) without any protection */
751 sata_set_spd(link);
752
753 tout_msec = 100;
754 if (ata_link_online(link))
755 tout_msec = 5000;
756
757 writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
758 tmp = ata_wait_register(port + PORT_CTRL_STAT,
759 PORT_CS_DEV_RST, PORT_CS_DEV_RST, 10,
760 tout_msec);
761
762 /* SStatus oscillates between zero and valid status after
763 * DEV_RST, debounce it.
764 */
765 rc = sata_link_debounce(link, sata_deb_timing_long, deadline);
766 if (rc) {
767 reason = "PHY debouncing failed";
768 goto err;
769 }
770
771 if (tmp & PORT_CS_DEV_RST) {
772 if (ata_link_offline(link))
773 return 0;
774 reason = "link not ready";
775 goto err;
776 }
777
778 /* Sil24 doesn't store signature FIS after hardreset, so we
779 * can't wait for BSY to clear. Some devices take a long time
780 * to get ready and those devices will choke if we don't wait
781 * for BSY clearance here. Tell libata to perform follow-up
782 * softreset.
783 */
784 return -EAGAIN;
785
786 err:
787 if (!did_port_rst) {
788 pp->do_port_rst = 1;
789 goto retry;
790 }
791
792 ata_link_printk(link, KERN_ERR, "hardreset failed (%s)\n", reason);
793 return -EIO;
794 }
795
796 static inline void sil24_fill_sg(struct ata_queued_cmd *qc,
797 struct sil24_sge *sge)
798 {
799 struct scatterlist *sg;
800 struct sil24_sge *last_sge = NULL;
801
802 ata_for_each_sg(sg, qc) {
803 sge->addr = cpu_to_le64(sg_dma_address(sg));
804 sge->cnt = cpu_to_le32(sg_dma_len(sg));
805 sge->flags = 0;
806
807 last_sge = sge;
808 sge++;
809 }
810
811 if (likely(last_sge))
812 last_sge->flags = cpu_to_le32(SGE_TRM);
813 }
814
815 static int sil24_qc_defer(struct ata_queued_cmd *qc)
816 {
817 struct ata_link *link = qc->dev->link;
818 struct ata_port *ap = link->ap;
819 u8 prot = qc->tf.protocol;
820 int is_atapi = (prot == ATA_PROT_ATAPI ||
821 prot == ATA_PROT_ATAPI_NODATA ||
822 prot == ATA_PROT_ATAPI_DMA);
823
824 /* ATAPI commands completing with CHECK_SENSE cause various
825 * weird problems if other commands are active. PMP DMA CS
826 * errata doesn't cover all and HSM violation occurs even with
827 * only one other device active. Always run an ATAPI command
828 * by itself.
829 */
830 if (unlikely(ap->excl_link)) {
831 if (link == ap->excl_link) {
832 if (ap->nr_active_links)
833 return ATA_DEFER_PORT;
834 qc->flags |= ATA_QCFLAG_CLEAR_EXCL;
835 } else
836 return ATA_DEFER_PORT;
837 } else if (unlikely(is_atapi)) {
838 ap->excl_link = link;
839 if (ap->nr_active_links)
840 return ATA_DEFER_PORT;
841 qc->flags |= ATA_QCFLAG_CLEAR_EXCL;
842 }
843
844 return ata_std_qc_defer(qc);
845 }
846
847 static void sil24_qc_prep(struct ata_queued_cmd *qc)
848 {
849 struct ata_port *ap = qc->ap;
850 struct sil24_port_priv *pp = ap->private_data;
851 union sil24_cmd_block *cb;
852 struct sil24_prb *prb;
853 struct sil24_sge *sge;
854 u16 ctrl = 0;
855
856 cb = &pp->cmd_block[sil24_tag(qc->tag)];
857
858 switch (qc->tf.protocol) {
859 case ATA_PROT_PIO:
860 case ATA_PROT_DMA:
861 case ATA_PROT_NCQ:
862 case ATA_PROT_NODATA:
863 prb = &cb->ata.prb;
864 sge = cb->ata.sge;
865 break;
866
867 case ATA_PROT_ATAPI:
868 case ATA_PROT_ATAPI_DMA:
869 case ATA_PROT_ATAPI_NODATA:
870 prb = &cb->atapi.prb;
871 sge = cb->atapi.sge;
872 memset(cb->atapi.cdb, 0, 32);
873 memcpy(cb->atapi.cdb, qc->cdb, qc->dev->cdb_len);
874
875 if (qc->tf.protocol != ATA_PROT_ATAPI_NODATA) {
876 if (qc->tf.flags & ATA_TFLAG_WRITE)
877 ctrl = PRB_CTRL_PACKET_WRITE;
878 else
879 ctrl = PRB_CTRL_PACKET_READ;
880 }
881 break;
882
883 default:
884 prb = NULL; /* shut up, gcc */
885 sge = NULL;
886 BUG();
887 }
888
889 prb->ctrl = cpu_to_le16(ctrl);
890 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, prb->fis);
891
892 if (qc->flags & ATA_QCFLAG_DMAMAP)
893 sil24_fill_sg(qc, sge);
894 }
895
896 static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc)
897 {
898 struct ata_port *ap = qc->ap;
899 struct sil24_port_priv *pp = ap->private_data;
900 void __iomem *port = ap->ioaddr.cmd_addr;
901 unsigned int tag = sil24_tag(qc->tag);
902 dma_addr_t paddr;
903 void __iomem *activate;
904
905 paddr = pp->cmd_block_dma + tag * sizeof(*pp->cmd_block);
906 activate = port + PORT_CMD_ACTIVATE + tag * 8;
907
908 writel((u32)paddr, activate);
909 writel((u64)paddr >> 32, activate + 4);
910
911 return 0;
912 }
913
914 static void sil24_irq_clear(struct ata_port *ap)
915 {
916 /* unused */
917 }
918
919 static void sil24_pmp_attach(struct ata_port *ap)
920 {
921 sil24_config_pmp(ap, 1);
922 sil24_init_port(ap);
923 }
924
925 static void sil24_pmp_detach(struct ata_port *ap)
926 {
927 sil24_init_port(ap);
928 sil24_config_pmp(ap, 0);
929 }
930
931 static int sil24_pmp_softreset(struct ata_link *link, unsigned int *class,
932 unsigned long deadline)
933 {
934 return sil24_do_softreset(link, class, link->pmp, deadline);
935 }
936
937 static int sil24_pmp_hardreset(struct ata_link *link, unsigned int *class,
938 unsigned long deadline)
939 {
940 int rc;
941
942 rc = sil24_init_port(link->ap);
943 if (rc) {
944 ata_link_printk(link, KERN_ERR,
945 "hardreset failed (port not ready)\n");
946 return rc;
947 }
948
949 return sata_pmp_std_hardreset(link, class, deadline);
950 }
951
952 static void sil24_freeze(struct ata_port *ap)
953 {
954 void __iomem *port = ap->ioaddr.cmd_addr;
955
956 /* Port-wide IRQ mask in HOST_CTRL doesn't really work, clear
957 * PORT_IRQ_ENABLE instead.
958 */
959 writel(0xffff, port + PORT_IRQ_ENABLE_CLR);
960 }
961
962 static void sil24_thaw(struct ata_port *ap)
963 {
964 void __iomem *port = ap->ioaddr.cmd_addr;
965 u32 tmp;
966
967 /* clear IRQ */
968 tmp = readl(port + PORT_IRQ_STAT);
969 writel(tmp, port + PORT_IRQ_STAT);
970
971 /* turn IRQ back on */
972 writel(DEF_PORT_IRQ, port + PORT_IRQ_ENABLE_SET);
973 }
974
975 static void sil24_error_intr(struct ata_port *ap)
976 {
977 void __iomem *port = ap->ioaddr.cmd_addr;
978 struct sil24_port_priv *pp = ap->private_data;
979 struct ata_queued_cmd *qc = NULL;
980 struct ata_link *link;
981 struct ata_eh_info *ehi;
982 int abort = 0, freeze = 0;
983 u32 irq_stat;
984
985 /* on error, we need to clear IRQ explicitly */
986 irq_stat = readl(port + PORT_IRQ_STAT);
987 writel(irq_stat, port + PORT_IRQ_STAT);
988
989 /* first, analyze and record host port events */
990 link = &ap->link;
991 ehi = &link->eh_info;
992 ata_ehi_clear_desc(ehi);
993
994 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
995
996 if (irq_stat & PORT_IRQ_SDB_NOTIFY) {
997 ata_ehi_push_desc(ehi, "SDB notify");
998 sata_async_notification(ap);
999 }
1000
1001 if (irq_stat & (PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG)) {
1002 ata_ehi_hotplugged(ehi);
1003 ata_ehi_push_desc(ehi, "%s",
1004 irq_stat & PORT_IRQ_PHYRDY_CHG ?
1005 "PHY RDY changed" : "device exchanged");
1006 freeze = 1;
1007 }
1008
1009 if (irq_stat & PORT_IRQ_UNK_FIS) {
1010 ehi->err_mask |= AC_ERR_HSM;
1011 ehi->action |= ATA_EH_SOFTRESET;
1012 ata_ehi_push_desc(ehi, "unknown FIS");
1013 freeze = 1;
1014 }
1015
1016 /* deal with command error */
1017 if (irq_stat & PORT_IRQ_ERROR) {
1018 struct sil24_cerr_info *ci = NULL;
1019 unsigned int err_mask = 0, action = 0;
1020 u32 context, cerr;
1021 int pmp;
1022
1023 abort = 1;
1024
1025 /* DMA Context Switch Failure in Port Multiplier Mode
1026 * errata. If we have active commands to 3 or more
1027 * devices, any error condition on active devices can
1028 * corrupt DMA context switching.
1029 */
1030 if (ap->nr_active_links >= 3) {
1031 ehi->err_mask |= AC_ERR_OTHER;
1032 ehi->action |= ATA_EH_HARDRESET;
1033 ata_ehi_push_desc(ehi, "PMP DMA CS errata");
1034 pp->do_port_rst = 1;
1035 freeze = 1;
1036 }
1037
1038 /* find out the offending link and qc */
1039 if (ap->nr_pmp_links) {
1040 context = readl(port + PORT_CONTEXT);
1041 pmp = (context >> 5) & 0xf;
1042
1043 if (pmp < ap->nr_pmp_links) {
1044 link = &ap->pmp_link[pmp];
1045 ehi = &link->eh_info;
1046 qc = ata_qc_from_tag(ap, link->active_tag);
1047
1048 ata_ehi_clear_desc(ehi);
1049 ata_ehi_push_desc(ehi, "irq_stat 0x%08x",
1050 irq_stat);
1051 } else {
1052 err_mask |= AC_ERR_HSM;
1053 action |= ATA_EH_HARDRESET;
1054 freeze = 1;
1055 }
1056 } else
1057 qc = ata_qc_from_tag(ap, link->active_tag);
1058
1059 /* analyze CMD_ERR */
1060 cerr = readl(port + PORT_CMD_ERR);
1061 if (cerr < ARRAY_SIZE(sil24_cerr_db))
1062 ci = &sil24_cerr_db[cerr];
1063
1064 if (ci && ci->desc) {
1065 err_mask |= ci->err_mask;
1066 action |= ci->action;
1067 ata_ehi_push_desc(ehi, "%s", ci->desc);
1068 } else {
1069 err_mask |= AC_ERR_OTHER;
1070 action |= ATA_EH_SOFTRESET;
1071 ata_ehi_push_desc(ehi, "unknown command error %d",
1072 cerr);
1073 }
1074
1075 /* record error info */
1076 if (qc) {
1077 sil24_read_tf(ap, qc->tag, &pp->tf);
1078 qc->err_mask |= err_mask;
1079 } else
1080 ehi->err_mask |= err_mask;
1081
1082 ehi->action |= action;
1083
1084 /* if PMP, resume */
1085 if (ap->nr_pmp_links)
1086 writel(PORT_CS_PMP_RESUME, port + PORT_CTRL_STAT);
1087 }
1088
1089 /* freeze or abort */
1090 if (freeze)
1091 ata_port_freeze(ap);
1092 else if (abort) {
1093 if (qc)
1094 ata_link_abort(qc->dev->link);
1095 else
1096 ata_port_abort(ap);
1097 }
1098 }
1099
1100 static void sil24_finish_qc(struct ata_queued_cmd *qc)
1101 {
1102 struct ata_port *ap = qc->ap;
1103 struct sil24_port_priv *pp = ap->private_data;
1104
1105 if (qc->flags & ATA_QCFLAG_RESULT_TF)
1106 sil24_read_tf(ap, qc->tag, &pp->tf);
1107 }
1108
1109 static inline void sil24_host_intr(struct ata_port *ap)
1110 {
1111 void __iomem *port = ap->ioaddr.cmd_addr;
1112 u32 slot_stat, qc_active;
1113 int rc;
1114
1115 /* If PCIX_IRQ_WOC, there's an inherent race window between
1116 * clearing IRQ pending status and reading PORT_SLOT_STAT
1117 * which may cause spurious interrupts afterwards. This is
1118 * unavoidable and much better than losing interrupts which
1119 * happens if IRQ pending is cleared after reading
1120 * PORT_SLOT_STAT.
1121 */
1122 if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC)
1123 writel(PORT_IRQ_COMPLETE, port + PORT_IRQ_STAT);
1124
1125 slot_stat = readl(port + PORT_SLOT_STAT);
1126
1127 if (unlikely(slot_stat & HOST_SSTAT_ATTN)) {
1128 sil24_error_intr(ap);
1129 return;
1130 }
1131
1132 qc_active = slot_stat & ~HOST_SSTAT_ATTN;
1133 rc = ata_qc_complete_multiple(ap, qc_active, sil24_finish_qc);
1134 if (rc > 0)
1135 return;
1136 if (rc < 0) {
1137 struct ata_eh_info *ehi = &ap->link.eh_info;
1138 ehi->err_mask |= AC_ERR_HSM;
1139 ehi->action |= ATA_EH_SOFTRESET;
1140 ata_port_freeze(ap);
1141 return;
1142 }
1143
1144 /* spurious interrupts are expected if PCIX_IRQ_WOC */
1145 if (!(ap->flags & SIL24_FLAG_PCIX_IRQ_WOC) && ata_ratelimit())
1146 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
1147 "(slot_stat 0x%x active_tag %d sactive 0x%x)\n",
1148 slot_stat, ap->link.active_tag, ap->link.sactive);
1149 }
1150
1151 static irqreturn_t sil24_interrupt(int irq, void *dev_instance)
1152 {
1153 struct ata_host *host = dev_instance;
1154 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
1155 unsigned handled = 0;
1156 u32 status;
1157 int i;
1158
1159 status = readl(host_base + HOST_IRQ_STAT);
1160
1161 if (status == 0xffffffff) {
1162 printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, "
1163 "PCI fault or device removal?\n");
1164 goto out;
1165 }
1166
1167 if (!(status & IRQ_STAT_4PORTS))
1168 goto out;
1169
1170 spin_lock(&host->lock);
1171
1172 for (i = 0; i < host->n_ports; i++)
1173 if (status & (1 << i)) {
1174 struct ata_port *ap = host->ports[i];
1175 if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
1176 sil24_host_intr(ap);
1177 handled++;
1178 } else
1179 printk(KERN_ERR DRV_NAME
1180 ": interrupt from disabled port %d\n", i);
1181 }
1182
1183 spin_unlock(&host->lock);
1184 out:
1185 return IRQ_RETVAL(handled);
1186 }
1187
1188 static void sil24_error_handler(struct ata_port *ap)
1189 {
1190 struct sil24_port_priv *pp = ap->private_data;
1191
1192 if (sil24_init_port(ap))
1193 ata_eh_freeze_port(ap);
1194
1195 /* perform recovery */
1196 sata_pmp_do_eh(ap, ata_std_prereset, sil24_softreset, sil24_hardreset,
1197 ata_std_postreset, sata_pmp_std_prereset,
1198 sil24_pmp_softreset, sil24_pmp_hardreset,
1199 sata_pmp_std_postreset);
1200
1201 pp->do_port_rst = 0;
1202 }
1203
1204 static void sil24_post_internal_cmd(struct ata_queued_cmd *qc)
1205 {
1206 struct ata_port *ap = qc->ap;
1207
1208 /* make DMA engine forget about the failed command */
1209 if ((qc->flags & ATA_QCFLAG_FAILED) && sil24_init_port(ap))
1210 ata_eh_freeze_port(ap);
1211 }
1212
1213 static int sil24_port_start(struct ata_port *ap)
1214 {
1215 struct device *dev = ap->host->dev;
1216 struct sil24_port_priv *pp;
1217 union sil24_cmd_block *cb;
1218 size_t cb_size = sizeof(*cb) * SIL24_MAX_CMDS;
1219 dma_addr_t cb_dma;
1220 int rc;
1221
1222 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1223 if (!pp)
1224 return -ENOMEM;
1225
1226 pp->tf.command = ATA_DRDY;
1227
1228 cb = dmam_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL);
1229 if (!cb)
1230 return -ENOMEM;
1231 memset(cb, 0, cb_size);
1232
1233 rc = ata_pad_alloc(ap, dev);
1234 if (rc)
1235 return rc;
1236
1237 pp->cmd_block = cb;
1238 pp->cmd_block_dma = cb_dma;
1239
1240 ap->private_data = pp;
1241
1242 return 0;
1243 }
1244
1245 static void sil24_init_controller(struct ata_host *host)
1246 {
1247 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
1248 u32 tmp;
1249 int i;
1250
1251 /* GPIO off */
1252 writel(0, host_base + HOST_FLASH_CMD);
1253
1254 /* clear global reset & mask interrupts during initialization */
1255 writel(0, host_base + HOST_CTRL);
1256
1257 /* init ports */
1258 for (i = 0; i < host->n_ports; i++) {
1259 struct ata_port *ap = host->ports[i];
1260 void __iomem *port = ap->ioaddr.cmd_addr;
1261
1262 /* Initial PHY setting */
1263 writel(0x20c, port + PORT_PHY_CFG);
1264
1265 /* Clear port RST */
1266 tmp = readl(port + PORT_CTRL_STAT);
1267 if (tmp & PORT_CS_PORT_RST) {
1268 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
1269 tmp = ata_wait_register(port + PORT_CTRL_STAT,
1270 PORT_CS_PORT_RST,
1271 PORT_CS_PORT_RST, 10, 100);
1272 if (tmp & PORT_CS_PORT_RST)
1273 dev_printk(KERN_ERR, host->dev,
1274 "failed to clear port RST\n");
1275 }
1276
1277 /* configure port */
1278 sil24_config_port(ap);
1279 }
1280
1281 /* Turn on interrupts */
1282 writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL);
1283 }
1284
1285 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1286 {
1287 static int printed_version;
1288 struct ata_port_info pi = sil24_port_info[ent->driver_data];
1289 const struct ata_port_info *ppi[] = { &pi, NULL };
1290 void __iomem * const *iomap;
1291 struct ata_host *host;
1292 int i, rc;
1293 u32 tmp;
1294
1295 if (!printed_version++)
1296 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1297
1298 /* acquire resources */
1299 rc = pcim_enable_device(pdev);
1300 if (rc)
1301 return rc;
1302
1303 rc = pcim_iomap_regions(pdev,
1304 (1 << SIL24_HOST_BAR) | (1 << SIL24_PORT_BAR),
1305 DRV_NAME);
1306 if (rc)
1307 return rc;
1308 iomap = pcim_iomap_table(pdev);
1309
1310 /* apply workaround for completion IRQ loss on PCI-X errata */
1311 if (pi.flags & SIL24_FLAG_PCIX_IRQ_WOC) {
1312 tmp = readl(iomap[SIL24_HOST_BAR] + HOST_CTRL);
1313 if (tmp & (HOST_CTRL_TRDY | HOST_CTRL_STOP | HOST_CTRL_DEVSEL))
1314 dev_printk(KERN_INFO, &pdev->dev,
1315 "Applying completion IRQ loss on PCI-X "
1316 "errata fix\n");
1317 else
1318 pi.flags &= ~SIL24_FLAG_PCIX_IRQ_WOC;
1319 }
1320
1321 /* allocate and fill host */
1322 host = ata_host_alloc_pinfo(&pdev->dev, ppi,
1323 SIL24_FLAG2NPORTS(ppi[0]->flags));
1324 if (!host)
1325 return -ENOMEM;
1326 host->iomap = iomap;
1327
1328 for (i = 0; i < host->n_ports; i++) {
1329 struct ata_port *ap = host->ports[i];
1330 size_t offset = ap->port_no * PORT_REGS_SIZE;
1331 void __iomem *port = iomap[SIL24_PORT_BAR] + offset;
1332
1333 host->ports[i]->ioaddr.cmd_addr = port;
1334 host->ports[i]->ioaddr.scr_addr = port + PORT_SCONTROL;
1335
1336 ata_port_pbar_desc(ap, SIL24_HOST_BAR, -1, "host");
1337 ata_port_pbar_desc(ap, SIL24_PORT_BAR, offset, "port");
1338 }
1339
1340 /* configure and activate the device */
1341 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1342 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1343 if (rc) {
1344 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1345 if (rc) {
1346 dev_printk(KERN_ERR, &pdev->dev,
1347 "64-bit DMA enable failed\n");
1348 return rc;
1349 }
1350 }
1351 } else {
1352 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1353 if (rc) {
1354 dev_printk(KERN_ERR, &pdev->dev,
1355 "32-bit DMA enable failed\n");
1356 return rc;
1357 }
1358 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1359 if (rc) {
1360 dev_printk(KERN_ERR, &pdev->dev,
1361 "32-bit consistent DMA enable failed\n");
1362 return rc;
1363 }
1364 }
1365
1366 sil24_init_controller(host);
1367
1368 pci_set_master(pdev);
1369 return ata_host_activate(host, pdev->irq, sil24_interrupt, IRQF_SHARED,
1370 &sil24_sht);
1371 }
1372
1373 #ifdef CONFIG_PM
1374 static int sil24_pci_device_resume(struct pci_dev *pdev)
1375 {
1376 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1377 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
1378 int rc;
1379
1380 rc = ata_pci_device_do_resume(pdev);
1381 if (rc)
1382 return rc;
1383
1384 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND)
1385 writel(HOST_CTRL_GLOBAL_RST, host_base + HOST_CTRL);
1386
1387 sil24_init_controller(host);
1388
1389 ata_host_resume(host);
1390
1391 return 0;
1392 }
1393
1394 static int sil24_port_resume(struct ata_port *ap)
1395 {
1396 sil24_config_pmp(ap, ap->nr_pmp_links);
1397 return 0;
1398 }
1399 #endif
1400
1401 static int __init sil24_init(void)
1402 {
1403 return pci_register_driver(&sil24_pci_driver);
1404 }
1405
1406 static void __exit sil24_exit(void)
1407 {
1408 pci_unregister_driver(&sil24_pci_driver);
1409 }
1410
1411 MODULE_AUTHOR("Tejun Heo");
1412 MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver");
1413 MODULE_LICENSE("GPL");
1414 MODULE_DEVICE_TABLE(pci, sil24_pci_tbl);
1415
1416 module_init(sil24_init);
1417 module_exit(sil24_exit);
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