hw/acpi_piix4.c

   1 /*
   2  * ACPI implementation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License version 2 as published by the Free Software Foundation.
   9  *
  10  * This library is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * Lesser General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU Lesser General Public
  16  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  17  */
  18 #include "hw.h"
  19 #include "pc.h"
  20 #include "apm.h"
  21 #include "pm_smbus.h"
  22 #include "pci.h"
  23 #include "acpi.h"
  24 #include "sysemu.h"
  25 #include "range.h"
  26
  27 //#define DEBUG
  28
  29 #ifdef DEBUG
  30 # define PIIX4_DPRINTF(format, ...)     printf(format, ## __VA_ARGS__)
  31 #else
  32 # define PIIX4_DPRINTF(format, ...)     do { } while (0)
  33 #endif
  34
  35 #define ACPI_DBG_IO_ADDR  0xb044
  36
  37 #define GPE_BASE 0xafe0
  38 #define PROC_BASE 0xaf00
  39 #define GPE_LEN 4
  40 #define PCI_BASE 0xae00
  41 #define PCI_EJ_BASE 0xae08
  42 #define PCI_RMV_BASE 0xae0c
  43
  44 #define PIIX4_CPU_HOTPLUG_STATUS 4
  45 #define PIIX4_PCI_HOTPLUG_STATUS 2
  46
  47 struct gpe_regs {
  48     uint8_t cpus_sts[32];
  49 };
  50
  51 struct pci_status {
  52     uint32_t up;
  53     uint32_t down;
  54 };
  55
  56 typedef struct PIIX4PMState {
  57     PCIDevice dev;
  58     IORange ioport;
  59     ACPIPM1EVT pm1a;
  60     ACPIPM1CNT pm1_cnt;
  61
  62     APMState apm;
  63
  64     ACPIPMTimer tmr;
  65
  66     PMSMBus smb;
  67     uint32_t smb_io_base;
  68
  69     qemu_irq irq;
  70     qemu_irq smi_irq;
  71     int kvm_enabled;
  72
  73     /* for pci hotplug */
  74     ACPIGPE gpe;
  75     struct gpe_regs gpe_cpu;
  76     struct pci_status pci0_status;
  77     uint32_t pci0_hotplug_enable;
  78 } PIIX4PMState;
  79
  80 static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s);
  81
  82 #define ACPI_ENABLE 0xf1
  83 #define ACPI_DISABLE 0xf0
  84
  85 static void pm_update_sci(PIIX4PMState *s)
  86 {
  87     int sci_level, pmsts;
  88
  89     pmsts = acpi_pm1_evt_get_sts(&s->pm1a, s->tmr.overflow_time);
  90     sci_level = (((pmsts & s->pm1a.en) &
  91                   (ACPI_BITMASK_RT_CLOCK_ENABLE |
  92                    ACPI_BITMASK_POWER_BUTTON_ENABLE |
  93                    ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
  94                    ACPI_BITMASK_TIMER_ENABLE)) != 0) ||
  95         (((s->gpe.sts[0] & s->gpe.en[0]) & PIIX4_PCI_HOTPLUG_STATUS) != 0);
  96
  97     qemu_set_irq(s->irq, sci_level);
  98     /* schedule a timer interruption if needed */
  99     acpi_pm_tmr_update(&s->tmr, (s->pm1a.en & ACPI_BITMASK_TIMER_ENABLE) &&
 100                        !(pmsts & ACPI_BITMASK_TIMER_STATUS));
 101 }
 102
 103 static void pm_tmr_timer(ACPIPMTimer *tmr)
 104 {
 105     PIIX4PMState *s = container_of(tmr, PIIX4PMState, tmr);
 106     pm_update_sci(s);
 107 }
 108
 109 static void pm_ioport_write(IORange *ioport, uint64_t addr, unsigned width,
 110                             uint64_t val)
 111 {
 112     PIIX4PMState *s = container_of(ioport, PIIX4PMState, ioport);
 113
 114     if (width != 2) {
 115         PIIX4_DPRINTF("PM write port=0x%04x width=%d val=0x%08x\n",
 116                       (unsigned)addr, width, (unsigned)val);
 117     }
 118
 119     switch(addr) {
 120     case 0x00:
 121         acpi_pm1_evt_write_sts(&s->pm1a, &s->tmr, val);
 122         pm_update_sci(s);
 123         break;
 124     case 0x02:
 125         s->pm1a.en = val;
 126         pm_update_sci(s);
 127         break;
 128     case 0x04:
 129         acpi_pm1_cnt_write(&s->pm1a, &s->pm1_cnt, val);
 130         break;
 131     default:
 132         break;
 133     }
 134     PIIX4_DPRINTF("PM writew port=0x%04x val=0x%04x\n", (unsigned int)addr,
 135                   (unsigned int)val);
 136 }
 137
 138 static void pm_ioport_read(IORange *ioport, uint64_t addr, unsigned width,
 139                             uint64_t *data)
 140 {
 141     PIIX4PMState *s = container_of(ioport, PIIX4PMState, ioport);
 142     uint32_t val;
 143
 144     switch(addr) {
 145     case 0x00:
 146         val = acpi_pm1_evt_get_sts(&s->pm1a, s->tmr.overflow_time);
 147         break;
 148     case 0x02:
 149         val = s->pm1a.en;
 150         break;
 151     case 0x04:
 152         val = s->pm1_cnt.cnt;
 153         break;
 154     case 0x08:
 155         val = acpi_pm_tmr_get(&s->tmr);
 156         break;
 157     default:
 158         val = 0;
 159         break;
 160     }
 161     PIIX4_DPRINTF("PM readw port=0x%04x val=0x%04x\n", (unsigned int)addr, val);
 162     *data = val;
 163 }
 164
 165 static const IORangeOps pm_iorange_ops = {
 166     .read = pm_ioport_read,
 167     .write = pm_ioport_write,
 168 };
 169
 170 static void apm_ctrl_changed(uint32_t val, void *arg)
 171 {
 172     PIIX4PMState *s = arg;
 173
 174     /* ACPI specs 3.0, 4.7.2.5 */
 175     acpi_pm1_cnt_update(&s->pm1_cnt, val == ACPI_ENABLE, val == ACPI_DISABLE);
 176
 177     if (s->dev.config[0x5b] & (1 << 1)) {
 178         if (s->smi_irq) {
 179             qemu_irq_raise(s->smi_irq);
 180         }
 181     }
 182 }
 183
 184 static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
 185 {
 186     PIIX4_DPRINTF("ACPI: DBG: 0x%08x\n", val);
 187 }
 188
 189 static void pm_io_space_update(PIIX4PMState *s)
 190 {
 191     uint32_t pm_io_base;
 192
 193     if (s->dev.config[0x80] & 1) {
 194         pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
 195         pm_io_base &= 0xffc0;
 196
 197         /* XXX: need to improve memory and ioport allocation */
 198         PIIX4_DPRINTF("PM: mapping to 0x%x\n", pm_io_base);
 199         iorange_init(&s->ioport, &pm_iorange_ops, pm_io_base, 64);
 200         ioport_register(&s->ioport);
 201     }
 202 }
 203
 204 static void pm_write_config(PCIDevice *d,
 205                             uint32_t address, uint32_t val, int len)
 206 {
 207     pci_default_write_config(d, address, val, len);
 208     if (range_covers_byte(address, len, 0x80))
 209         pm_io_space_update((PIIX4PMState *)d);
 210 }
 211
 212 static int vmstate_acpi_post_load(void *opaque, int version_id)
 213 {
 214     PIIX4PMState *s = opaque;
 215
 216     pm_io_space_update(s);
 217     return 0;
 218 }
 219
 220 #define VMSTATE_GPE_ARRAY(_field, _state)                            \
 221  {                                                                   \
 222      .name       = (stringify(_field)),                              \
 223      .version_id = 0,                                                \
 224      .info       = &vmstate_info_uint16,                             \
 225      .size       = sizeof(uint16_t),                                 \
 226      .flags      = VMS_SINGLE | VMS_POINTER,                         \
 227      .offset     = vmstate_offset_pointer(_state, _field, uint8_t),  \
 228  }
 229
 230 static const VMStateDescription vmstate_gpe = {
 231     .name = "gpe",
 232     .version_id = 1,
 233     .minimum_version_id = 1,
 234     .minimum_version_id_old = 1,
 235     .fields      = (VMStateField []) {
 236         VMSTATE_GPE_ARRAY(sts, ACPIGPE),
 237         VMSTATE_GPE_ARRAY(en, ACPIGPE),
 238         VMSTATE_END_OF_LIST()
 239     }
 240 };
 241
 242 static const VMStateDescription vmstate_pci_status = {
 243     .name = "pci_status",
 244     .version_id = 1,
 245     .minimum_version_id = 1,
 246     .minimum_version_id_old = 1,
 247     .fields      = (VMStateField []) {
 248         VMSTATE_UINT32(up, struct pci_status),
 249         VMSTATE_UINT32(down, struct pci_status),
 250         VMSTATE_END_OF_LIST()
 251     }
 252 };
 253
 254 static const VMStateDescription vmstate_acpi = {
 255     .name = "piix4_pm",
 256     .version_id = 2,
 257     .minimum_version_id = 1,
 258     .minimum_version_id_old = 1,
 259     .post_load = vmstate_acpi_post_load,
 260     .fields      = (VMStateField []) {
 261         VMSTATE_PCI_DEVICE(dev, PIIX4PMState),
 262         VMSTATE_UINT16(pm1a.sts, PIIX4PMState),
 263         VMSTATE_UINT16(pm1a.en, PIIX4PMState),
 264         VMSTATE_UINT16(pm1_cnt.cnt, PIIX4PMState),
 265         VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState),
 266         VMSTATE_TIMER(tmr.timer, PIIX4PMState),
 267         VMSTATE_INT64(tmr.overflow_time, PIIX4PMState),
 268         VMSTATE_STRUCT(gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE),
 269         VMSTATE_STRUCT(pci0_status, PIIX4PMState, 2, vmstate_pci_status,
 270                        struct pci_status),
 271         VMSTATE_END_OF_LIST()
 272     }
 273 };
 274
 275 static void piix4_update_hotplug(PIIX4PMState *s)
 276 {
 277     PCIDevice *dev = &s->dev;
 278     BusState *bus = qdev_get_parent_bus(&dev->qdev);
 279     DeviceState *qdev, *next;
 280
 281     s->pci0_hotplug_enable = ~0;
 282
 283     QLIST_FOREACH_SAFE(qdev, &bus->children, sibling, next) {
 284         PCIDeviceInfo *info = container_of(qdev->info, PCIDeviceInfo, qdev);
 285         PCIDevice *pdev = DO_UPCAST(PCIDevice, qdev, qdev);
 286         int slot = PCI_SLOT(pdev->devfn);
 287
 288         if (info->no_hotplug) {
 289             s->pci0_hotplug_enable &= ~(1 << slot);
 290         }
 291     }
 292 }
 293
 294 static void piix4_reset(void *opaque)
 295 {
 296     PIIX4PMState *s = opaque;
 297     uint8_t *pci_conf = s->dev.config;
 298
 299     pci_conf[0x58] = 0;
 300     pci_conf[0x59] = 0;
 301     pci_conf[0x5a] = 0;
 302     pci_conf[0x5b] = 0;
 303
 304     if (s->kvm_enabled) {
 305         /* Mark SMM as already inited (until KVM supports SMM). */
 306         pci_conf[0x5B] = 0x02;
 307     }
 308     piix4_update_hotplug(s);
 309 }
 310
 311 static void piix4_powerdown(void *opaque, int irq, int power_failing)
 312 {
 313     PIIX4PMState *s = opaque;
 314     ACPIPM1EVT *pm1a = s? &s->pm1a: NULL;
 315     ACPIPMTimer *tmr = s? &s->tmr: NULL;
 316
 317     acpi_pm1_evt_power_down(pm1a, tmr);
 318 }
 319
 320 static PIIX4PMState *global_piix4_pm_state; /* cpu hotadd */
 321
 322 static int piix4_pm_initfn(PCIDevice *dev)
 323 {
 324     PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, dev);
 325     uint8_t *pci_conf;
 326
 327     /* for cpu hotadd */
 328     global_piix4_pm_state = s;
 329
 330     pci_conf = s->dev.config;
 331     pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
 332     pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_3);
 333     pci_conf[0x06] = 0x80;
 334     pci_conf[0x07] = 0x02;
 335     pci_conf[0x08] = 0x03; // revision number
 336     pci_conf[0x09] = 0x00;
 337     pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER);
 338     pci_conf[0x3d] = 0x01; // interrupt pin 1
 339
 340     pci_conf[0x40] = 0x01; /* PM io base read only bit */
 341
 342 #if defined(TARGET_IA64)
 343     pci_conf[0x40] = 0x41; /* PM io base read only bit */
 344     pci_conf[0x41] = 0x1f;
 345     pm_write_config(s, 0x80, 0x01, 1); /*Set default pm_io_base 0x1f40*/
 346     s->pmcntrl = SCI_EN;
 347 #endif
 348
 349     /* APM */
 350     apm_init(&s->apm, apm_ctrl_changed, s);
 351
 352     register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);
 353
 354     if (s->kvm_enabled) {
 355         /* Mark SMM as already inited to prevent SMM from running.  KVM does not
 356          * support SMM mode. */
 357         pci_conf[0x5B] = 0x02;
 358     }
 359
 360     /* XXX: which specification is used ? The i82731AB has different
 361        mappings */
 362     pci_conf[0x5f] = (parallel_hds[0] != NULL ? 0x80 : 0) | 0x10;
 363     pci_conf[0x63] = 0x60;
 364     pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) |
 365         (serial_hds[1] != NULL ? 0x90 : 0);
 366
 367     pci_conf[0x90] = s->smb_io_base | 1;
 368     pci_conf[0x91] = s->smb_io_base >> 8;
 369     pci_conf[0xd2] = 0x09;
 370     register_ioport_write(s->smb_io_base, 64, 1, smb_ioport_writeb, &s->smb);
 371     register_ioport_read(s->smb_io_base, 64, 1, smb_ioport_readb, &s->smb);
 372
 373     acpi_pm_tmr_init(&s->tmr, pm_tmr_timer);
 374     acpi_gpe_init(&s->gpe, GPE_LEN);
 375
 376     qemu_system_powerdown = *qemu_allocate_irqs(piix4_powerdown, s, 1);
 377
 378     pm_smbus_init(&s->dev.qdev, &s->smb);
 379     qemu_register_reset(piix4_reset, s);
 380     piix4_acpi_system_hot_add_init(dev->bus, s);
 381
 382     return 0;
 383 }
 384
 385 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 386                        qemu_irq sci_irq, qemu_irq cmos_s3, qemu_irq smi_irq,
 387                        int kvm_enabled)
 388 {
 389     PCIDevice *dev;
 390     PIIX4PMState *s;
 391
 392     dev = pci_create(bus, devfn, "PIIX4_PM");
 393     qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base);
 394
 395     s = DO_UPCAST(PIIX4PMState, dev, dev);
 396     s->irq = sci_irq;
 397     acpi_pm1_cnt_init(&s->pm1_cnt, cmos_s3);
 398     s->smi_irq = smi_irq;
 399     s->kvm_enabled = kvm_enabled;
 400
 401     qdev_init_nofail(&dev->qdev);
 402
 403     return s->smb.smbus;
 404 }
 405
 406 static PCIDeviceInfo piix4_pm_info = {
 407     .qdev.name          = "PIIX4_PM",
 408     .qdev.desc          = "PM",
 409     .qdev.size          = sizeof(PIIX4PMState),
 410     .qdev.vmsd          = &vmstate_acpi,
 411     .qdev.no_user       = 1,
 412     .no_hotplug         = 1,
 413     .init               = piix4_pm_initfn,
 414     .config_write       = pm_write_config,
 415     .qdev.props         = (Property[]) {
 416         DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
 417         DEFINE_PROP_END_OF_LIST(),
 418     }
 419 };
 420
 421 static void piix4_pm_register(void)
 422 {
 423     pci_qdev_register(&piix4_pm_info);
 424 }
 425
 426 device_init(piix4_pm_register);
 427
 428 static uint32_t gpe_readb(void *opaque, uint32_t addr)
 429 {
 430     PIIX4PMState *s = opaque;
 431     uint32_t val = 0;
 432     struct gpe_regs *g = &s->gpe_cpu;
 433
 434     switch (addr) {
 435         case PROC_BASE ... PROC_BASE+31:
 436             val = g->cpus_sts[addr - PROC_BASE];
 437             break;
 438         default:
 439             val = acpi_gpe_ioport_readb(&s->gpe, addr);
 440     }
 441
 442     PIIX4_DPRINTF("gpe read %x == %x\n", addr, val);
 443     return val;
 444 }
 445
 446 static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val)
 447 {
 448     PIIX4PMState *s = opaque;
 449
 450     acpi_gpe_ioport_writeb(&s->gpe, addr, val);
 451     pm_update_sci(s);
 452
 453     PIIX4_DPRINTF("gpe write %x <== %d\n", addr, val);
 454 }
 455
 456 static uint32_t pcihotplug_read(void *opaque, uint32_t addr)
 457 {
 458     uint32_t val = 0;
 459     struct pci_status *g = opaque;
 460     switch (addr) {
 461         case PCI_BASE:
 462             val = g->up;
 463             break;
 464         case PCI_BASE + 4:
 465             val = g->down;
 466             break;
 467         default:
 468             break;
 469     }
 470
 471     PIIX4_DPRINTF("pcihotplug read %x == %x\n", addr, val);
 472     return val;
 473 }
 474
 475 static void pcihotplug_write(void *opaque, uint32_t addr, uint32_t val)
 476 {
 477     struct pci_status *g = opaque;
 478     switch (addr) {
 479         case PCI_BASE:
 480             g->up = val;
 481             break;
 482         case PCI_BASE + 4:
 483             g->down = val;
 484             break;
 485    }
 486
 487     PIIX4_DPRINTF("pcihotplug write %x <== %d\n", addr, val);
 488 }
 489
 490 static uint32_t pciej_read(void *opaque, uint32_t addr)
 491 {
 492     PIIX4_DPRINTF("pciej read %x\n", addr);
 493     return 0;
 494 }
 495
 496 static void pciej_write(void *opaque, uint32_t addr, uint32_t val)
 497 {
 498     BusState *bus = opaque;
 499     DeviceState *qdev, *next;
 500     PCIDevice *dev;
 501     PCIDeviceInfo *info;
 502     int slot = ffs(val) - 1;
 503
 504     QLIST_FOREACH_SAFE(qdev, &bus->children, sibling, next) {
 505         dev = DO_UPCAST(PCIDevice, qdev, qdev);
 506         info = container_of(qdev->info, PCIDeviceInfo, qdev);
 507         if (PCI_SLOT(dev->devfn) == slot && !info->no_hotplug) {
 508             qdev_free(qdev);
 509         }
 510     }
 511
 512
 513     PIIX4_DPRINTF("pciej write %x <== %d\n", addr, val);
 514 }
 515
 516 static uint32_t pcirmv_read(void *opaque, uint32_t addr)
 517 {
 518     PIIX4PMState *s = opaque;
 519
 520     return s->pci0_hotplug_enable;
 521 }
 522
 523 static void pcirmv_write(void *opaque, uint32_t addr, uint32_t val)
 524 {
 525     return;
 526 }
 527
 528 extern const char *global_cpu_model;
 529
 530 static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev,
 531                                 PCIHotplugState state);
 532
 533 static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s)
 534 {
 535     struct pci_status *pci0_status = &s->pci0_status;
 536     int i = 0, cpus = smp_cpus;
 537
 538     while (cpus > 0) {
 539         s->gpe_cpu.cpus_sts[i++] = (cpus < 8) ? (1 << cpus) - 1 : 0xff;
 540         cpus -= 8;
 541     }
 542
 543     register_ioport_write(GPE_BASE, GPE_LEN, 1, gpe_writeb, s);
 544     register_ioport_read(GPE_BASE, GPE_LEN, 1,  gpe_readb, s);
 545     acpi_gpe_blk(&s->gpe, GPE_BASE);
 546
 547     register_ioport_write(PROC_BASE, 32, 1, gpe_writeb, s);
 548     register_ioport_read(PROC_BASE, 32, 1,  gpe_readb, s);
 549
 550     register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, pci0_status);
 551     register_ioport_read(PCI_BASE, 8, 4,  pcihotplug_read, pci0_status);
 552
 553     register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, bus);
 554     register_ioport_read(PCI_EJ_BASE, 4, 4,  pciej_read, bus);
 555
 556     register_ioport_write(PCI_RMV_BASE, 4, 4, pcirmv_write, s);
 557     register_ioport_read(PCI_RMV_BASE, 4, 4,  pcirmv_read, s);
 558
 559     pci_bus_hotplug(bus, piix4_device_hotplug, &s->dev.qdev);
 560 }
 561
 562 #if defined(TARGET_I386)
 563 static void enable_processor(PIIX4PMState *s, int cpu)
 564 {
 565     struct gpe_regs *g = &s->gpe_cpu;
 566     ACPIGPE *gpe = &s->gpe;
 567
 568     *gpe->sts = *gpe->sts | PIIX4_CPU_HOTPLUG_STATUS;
 569     g->cpus_sts[cpu/8] |= (1 << (cpu%8));
 570 }
 571
 572 static void disable_processor(PIIX4PMState *s, int cpu)
 573 {
 574     struct gpe_regs *g = &s->gpe_cpu;
 575     ACPIGPE *gpe = &s->gpe;
 576
 577     *gpe->sts = *gpe->sts | PIIX4_CPU_HOTPLUG_STATUS;
 578     g->cpus_sts[cpu/8] &= ~(1 << (cpu%8));
 579 }
 580
 581 void qemu_system_cpu_hot_add(int cpu, int state)
 582 {
 583     CPUState *env;
 584     PIIX4PMState *s = global_piix4_pm_state;
 585
 586     if (state && !qemu_get_cpu(cpu)) {
 587         env = pc_new_cpu(global_cpu_model);
 588         if (!env) {
 589             fprintf(stderr, "cpu %d creation failed\n", cpu);
 590             return;
 591         }
 592         env->cpuid_apic_id = cpu;
 593     }
 594
 595     if (state)
 596         enable_processor(s, cpu);
 597     else
 598         disable_processor(s, cpu);
 599
 600     pm_update_sci(s);
 601 }
 602 #endif
 603
 604 static void enable_device(PIIX4PMState *s, int slot)
 605 {
 606     s->gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS;
 607     s->pci0_status.up |= (1 << slot);
 608 }
 609
 610 static void disable_device(PIIX4PMState *s, int slot)
 611 {
 612     s->gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS;
 613     s->pci0_status.down |= (1 << slot);
 614 }
 615
 616 static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev,
 617                                 PCIHotplugState state)
 618 {
 619     int slot = PCI_SLOT(dev->devfn);
 620     PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev,
 621                                 DO_UPCAST(PCIDevice, qdev, qdev));
 622
 623     /* Don't send event when device is enabled during qemu machine creation:
 624      * it is present on boot, no hotplug event is necessary. We do send an
 625      * event when the device is disabled later. */
 626     if (state == PCI_COLDPLUG_ENABLED) {
 627         return 0;
 628     }
 629
 630     s->pci0_status.up = 0;
 631     s->pci0_status.down = 0;
 632     if (state == PCI_HOTPLUG_ENABLED) {
 633         enable_device(s, slot);
 634     } else {
 635         disable_device(s, slot);
 636     }
 637
 638     pm_update_sci(s);
 639
 640     return 0;
 641 }