hw/i8259.c

   1 /*
   2  * QEMU 8259 interrupt controller emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pc.h"
  26 #include "isa.h"
  27 #include "monitor.h"
  28 #include "qemu-timer.h"
  29
  30 #include "kvm.h"
  31
  32 /* debug PIC */
  33 //#define DEBUG_PIC
  34
  35 #ifdef DEBUG_PIC
  36 #define DPRINTF(fmt, ...)                                       \
  37     do { printf("pic: " fmt , ## __VA_ARGS__); } while (0)
  38 #else
  39 #define DPRINTF(fmt, ...)
  40 #endif
  41
  42 //#define DEBUG_IRQ_LATENCY
  43 //#define DEBUG_IRQ_COUNT
  44
  45 typedef struct PicState {
  46     uint8_t last_irr; /* edge detection */
  47     uint8_t irr; /* interrupt request register */
  48     uint8_t imr; /* interrupt mask register */
  49     uint8_t isr; /* interrupt service register */
  50     uint8_t priority_add; /* highest irq priority */
  51     uint8_t irq_base;
  52     uint8_t read_reg_select;
  53     uint8_t poll;
  54     uint8_t special_mask;
  55     uint8_t init_state;
  56     uint8_t auto_eoi;
  57     uint8_t rotate_on_auto_eoi;
  58     uint8_t special_fully_nested_mode;
  59     uint8_t init4; /* true if 4 byte init */
  60     uint8_t single_mode; /* true if slave pic is not initialized */
  61     uint8_t elcr; /* PIIX edge/trigger selection*/
  62     uint8_t elcr_mask;
  63     PicState2 *pics_state;
  64 } PicState;
  65
  66 struct PicState2 {
  67     /* 0 is master pic, 1 is slave pic */
  68     /* XXX: better separation between the two pics */
  69     PicState pics[2];
  70     qemu_irq parent_irq;
  71     void *irq_request_opaque;
  72 };
  73
  74 #if defined(DEBUG_PIC) || defined (DEBUG_IRQ_COUNT)
  75 static int irq_level[16];
  76 #endif
  77 #ifdef DEBUG_IRQ_COUNT
  78 static uint64_t irq_count[16];
  79 #endif
  80 PicState2 *isa_pic;
  81
  82 /* set irq level. If an edge is detected, then the IRR is set to 1 */
  83 static inline void pic_set_irq1(PicState *s, int irq, int level)
  84 {
  85     int mask;
  86     mask = 1 << irq;
  87     if (s->elcr & mask) {
  88         /* level triggered */
  89         if (level) {
  90             s->irr |= mask;
  91             s->last_irr |= mask;
  92         } else {
  93             s->irr &= ~mask;
  94             s->last_irr &= ~mask;
  95         }
  96     } else {
  97         /* edge triggered */
  98         if (level) {
  99             if ((s->last_irr & mask) == 0)
 100                 s->irr |= mask;
 101             s->last_irr |= mask;
 102         } else {
 103             s->last_irr &= ~mask;
 104         }
 105     }
 106 }
 107
 108 /* return the highest priority found in mask (highest = smallest
 109    number). Return 8 if no irq */
 110 static inline int get_priority(PicState *s, int mask)
 111 {
 112     int priority;
 113     if (mask == 0)
 114         return 8;
 115     priority = 0;
 116     while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
 117         priority++;
 118     return priority;
 119 }
 120
 121 /* return the pic wanted interrupt. return -1 if none */
 122 static int pic_get_irq(PicState *s)
 123 {
 124     int mask, cur_priority, priority;
 125
 126     mask = s->irr & ~s->imr;
 127     priority = get_priority(s, mask);
 128     if (priority == 8)
 129         return -1;
 130     /* compute current priority. If special fully nested mode on the
 131        master, the IRQ coming from the slave is not taken into account
 132        for the priority computation. */
 133     mask = s->isr;
 134     if (s->special_mask)
 135         mask &= ~s->imr;
 136     if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
 137         mask &= ~(1 << 2);
 138     cur_priority = get_priority(s, mask);
 139     if (priority < cur_priority) {
 140         /* higher priority found: an irq should be generated */
 141         return (priority + s->priority_add) & 7;
 142     } else {
 143         return -1;
 144     }
 145 }
 146
 147 /* raise irq to CPU if necessary. must be called every time the active
 148    irq may change */
 149 /* XXX: should not export it, but it is needed for an APIC kludge */
 150 void pic_update_irq(PicState2 *s)
 151 {
 152     int irq2, irq;
 153
 154     /* first look at slave pic */
 155     irq2 = pic_get_irq(&s->pics[1]);
 156     if (irq2 >= 0) {
 157         /* if irq request by slave pic, signal master PIC */
 158         pic_set_irq1(&s->pics[0], 2, 1);
 159         pic_set_irq1(&s->pics[0], 2, 0);
 160     }
 161     /* look at requested irq */
 162     irq = pic_get_irq(&s->pics[0]);
 163     if (irq >= 0) {
 164 #if defined(DEBUG_PIC)
 165         {
 166             int i;
 167             for(i = 0; i < 2; i++) {
 168                 printf("pic%d: imr=%x irr=%x padd=%d\n",
 169                        i, s->pics[i].imr, s->pics[i].irr,
 170                        s->pics[i].priority_add);
 171
 172             }
 173         }
 174         printf("pic: cpu_interrupt\n");
 175 #endif
 176         qemu_irq_raise(s->parent_irq);
 177     }
 178
 179 /* all targets should do this rather than acking the IRQ in the cpu */
 180 #if defined(TARGET_MIPS) || defined(TARGET_PPC) || defined(TARGET_ALPHA)
 181     else {
 182         qemu_irq_lower(s->parent_irq);
 183     }
 184 #endif
 185 }
 186
 187 #ifdef DEBUG_IRQ_LATENCY
 188 int64_t irq_time[16];
 189 #endif
 190
 191 static void i8259_set_irq(void *opaque, int irq, int level)
 192 {
 193     PicState2 *s = opaque;
 194
 195 #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT)
 196     if (level != irq_level[irq]) {
 197         DPRINTF("i8259_set_irq: irq=%d level=%d\n", irq, level);
 198         irq_level[irq] = level;
 199 #ifdef DEBUG_IRQ_COUNT
 200         if (level == 1)
 201             irq_count[irq]++;
 202 #endif
 203     }
 204 #endif
 205 #ifdef DEBUG_IRQ_LATENCY
 206     if (level) {
 207         irq_time[irq] = qemu_get_clock_ns(vm_clock);
 208     }
 209 #endif
 210     pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
 211     pic_update_irq(s);
 212 }
 213
 214 /* acknowledge interrupt 'irq' */
 215 static inline void pic_intack(PicState *s, int irq)
 216 {
 217     if (s->auto_eoi) {
 218         if (s->rotate_on_auto_eoi)
 219             s->priority_add = (irq + 1) & 7;
 220     } else {
 221         s->isr |= (1 << irq);
 222     }
 223     /* We don't clear a level sensitive interrupt here */
 224     if (!(s->elcr & (1 << irq)))
 225         s->irr &= ~(1 << irq);
 226 }
 227
 228 extern int time_drift_fix;
 229 extern int64_t timer_acks, timer_ints_to_push;
 230
 231 int pic_read_irq(PicState2 *s)
 232 {
 233     int irq, irq2, intno;
 234
 235     irq = pic_get_irq(&s->pics[0]);
 236     if (irq >= 0) {
 237         pic_intack(&s->pics[0], irq);
 238 #ifdef TARGET_I386
 239         if (time_drift_fix && irq == 0) {
 240             timer_acks++;
 241             if (timer_ints_to_push > 0) {
 242                 timer_ints_to_push--;
 243                 /* simulate an edge irq0, like the one generated by i8254 */
 244                 pic_set_irq1(&s->pics[0], 0, 0);
 245                 pic_set_irq1(&s->pics[0], 0, 1);
 246             }
 247         }
 248 #endif
 249         if (irq == 2) {
 250             irq2 = pic_get_irq(&s->pics[1]);
 251             if (irq2 >= 0) {
 252                 pic_intack(&s->pics[1], irq2);
 253             } else {
 254                 /* spurious IRQ on slave controller */
 255                 irq2 = 7;
 256             }
 257             intno = s->pics[1].irq_base + irq2;
 258 #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_LATENCY)
 259             irq = irq2 + 8;
 260 #endif
 261         } else {
 262             intno = s->pics[0].irq_base + irq;
 263         }
 264     } else {
 265         /* spurious IRQ on host controller */
 266         irq = 7;
 267         intno = s->pics[0].irq_base + irq;
 268     }
 269     pic_update_irq(s);
 270
 271 #ifdef DEBUG_IRQ_LATENCY
 272     printf("IRQ%d latency=%0.3fus\n",
 273            irq,
 274            (double)(qemu_get_clock_ns(vm_clock) -
 275                     irq_time[irq]) * 1000000.0 / get_ticks_per_sec());
 276 #endif
 277     DPRINTF("pic_interrupt: irq=%d\n", irq);
 278     return intno;
 279 }
 280
 281 static void pic_reset(void *opaque)
 282 {
 283     PicState *s = opaque;
 284
 285     s->last_irr = 0;
 286     s->irr = 0;
 287     s->imr = 0;
 288     s->isr = 0;
 289     s->priority_add = 0;
 290     s->irq_base = 0;
 291     s->read_reg_select = 0;
 292     s->poll = 0;
 293     s->special_mask = 0;
 294     s->init_state = 0;
 295     s->auto_eoi = 0;
 296     s->rotate_on_auto_eoi = 0;
 297     s->special_fully_nested_mode = 0;
 298     s->init4 = 0;
 299     s->single_mode = 0;
 300     /* Note: ELCR is not reset */
 301 }
 302
 303 static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 304 {
 305     PicState *s = opaque;
 306     int priority, cmd, irq;
 307
 308     DPRINTF("write: addr=0x%02x val=0x%02x\n", addr, val);
 309     addr &= 1;
 310     if (addr == 0) {
 311         if (val & 0x10) {
 312             /* init */
 313             pic_reset(s);
 314             /* deassert a pending interrupt */
 315             qemu_irq_lower(s->pics_state->parent_irq);
 316             s->init_state = 1;
 317             s->init4 = val & 1;
 318             s->single_mode = val & 2;
 319             if (val & 0x08)
 320                 hw_error("level sensitive irq not supported");
 321         } else if (val & 0x08) {
 322             if (val & 0x04)
 323                 s->poll = 1;
 324             if (val & 0x02)
 325                 s->read_reg_select = val & 1;
 326             if (val & 0x40)
 327                 s->special_mask = (val >> 5) & 1;
 328         } else {
 329             cmd = val >> 5;
 330             switch(cmd) {
 331             case 0:
 332             case 4:
 333                 s->rotate_on_auto_eoi = cmd >> 2;
 334                 break;
 335             case 1: /* end of interrupt */
 336             case 5:
 337                 priority = get_priority(s, s->isr);
 338                 if (priority != 8) {
 339                     irq = (priority + s->priority_add) & 7;
 340                     s->isr &= ~(1 << irq);
 341                     if (cmd == 5)
 342                         s->priority_add = (irq + 1) & 7;
 343                     pic_update_irq(s->pics_state);
 344                 }
 345                 break;
 346             case 3:
 347                 irq = val & 7;
 348                 s->isr &= ~(1 << irq);
 349                 pic_update_irq(s->pics_state);
 350                 break;
 351             case 6:
 352                 s->priority_add = (val + 1) & 7;
 353                 pic_update_irq(s->pics_state);
 354                 break;
 355             case 7:
 356                 irq = val & 7;
 357                 s->isr &= ~(1 << irq);
 358                 s->priority_add = (irq + 1) & 7;
 359                 pic_update_irq(s->pics_state);
 360                 break;
 361             default:
 362                 /* no operation */
 363                 break;
 364             }
 365         }
 366     } else {
 367         switch(s->init_state) {
 368         case 0:
 369             /* normal mode */
 370             s->imr = val;
 371             pic_update_irq(s->pics_state);
 372             break;
 373         case 1:
 374             s->irq_base = val & 0xf8;
 375             s->init_state = s->single_mode ? (s->init4 ? 3 : 0) : 2;
 376             break;
 377         case 2:
 378             if (s->init4) {
 379                 s->init_state = 3;
 380             } else {
 381                 s->init_state = 0;
 382             }
 383             break;
 384         case 3:
 385             s->special_fully_nested_mode = (val >> 4) & 1;
 386             s->auto_eoi = (val >> 1) & 1;
 387             s->init_state = 0;
 388             break;
 389         }
 390     }
 391 }
 392
 393 static uint32_t pic_poll_read (PicState *s, uint32_t addr1)
 394 {
 395     int ret;
 396
 397     ret = pic_get_irq(s);
 398     if (ret >= 0) {
 399         if (addr1 >> 7) {
 400             s->pics_state->pics[0].isr &= ~(1 << 2);
 401             s->pics_state->pics[0].irr &= ~(1 << 2);
 402         }
 403         s->irr &= ~(1 << ret);
 404         s->isr &= ~(1 << ret);
 405         if (addr1 >> 7 || ret != 2)
 406             pic_update_irq(s->pics_state);
 407     } else {
 408         ret = 0x07;
 409         pic_update_irq(s->pics_state);
 410     }
 411
 412     return ret;
 413 }
 414
 415 static uint32_t pic_ioport_read(void *opaque, uint32_t addr1)
 416 {
 417     PicState *s = opaque;
 418     unsigned int addr;
 419     int ret;
 420
 421     addr = addr1;
 422     addr &= 1;
 423     if (s->poll) {
 424         ret = pic_poll_read(s, addr1);
 425         s->poll = 0;
 426     } else {
 427         if (addr == 0) {
 428             if (s->read_reg_select)
 429                 ret = s->isr;
 430             else
 431                 ret = s->irr;
 432         } else {
 433             ret = s->imr;
 434         }
 435     }
 436     DPRINTF("read: addr=0x%02x val=0x%02x\n", addr1, ret);
 437     return ret;
 438 }
 439
 440 /* memory mapped interrupt status */
 441 /* XXX: may be the same than pic_read_irq() */
 442 uint32_t pic_intack_read(PicState2 *s)
 443 {
 444     int ret;
 445
 446     ret = pic_poll_read(&s->pics[0], 0x00);
 447     if (ret == 2)
 448         ret = pic_poll_read(&s->pics[1], 0x80) + 8;
 449     /* Prepare for ISR read */
 450     s->pics[0].read_reg_select = 1;
 451
 452     return ret;
 453 }
 454
 455 static void elcr_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 456 {
 457     PicState *s = opaque;
 458     s->elcr = val & s->elcr_mask;
 459 }
 460
 461 static uint32_t elcr_ioport_read(void *opaque, uint32_t addr1)
 462 {
 463     PicState *s = opaque;
 464     return s->elcr;
 465 }
 466
 467 static void kvm_kernel_pic_save_to_user(PicState *s);
 468 static int kvm_kernel_pic_load_from_user(PicState *s);
 469
 470 static void pic_pre_save(void *opaque)
 471 {
 472     PicState *s = opaque;
 473
 474     if (kvm_enabled() && kvm_irqchip_in_kernel()) {
 475         kvm_kernel_pic_save_to_user(s);
 476     }
 477 }
 478
 479 static int pic_post_load(void *opaque, int version_id)
 480 {
 481     PicState *s = opaque;
 482
 483     if (kvm_enabled() && kvm_irqchip_in_kernel()) {
 484         kvm_kernel_pic_load_from_user(s);
 485     }
 486     return 0;
 487 }
 488
 489 static const VMStateDescription vmstate_pic = {
 490     .name = "i8259",
 491     .version_id = 1,
 492     .pre_save = pic_pre_save,
 493     .post_load = pic_post_load,
 494     .minimum_version_id = 1,
 495     .minimum_version_id_old = 1,
 496     .fields      = (VMStateField []) {
 497         VMSTATE_UINT8(last_irr, PicState),
 498         VMSTATE_UINT8(irr, PicState),
 499         VMSTATE_UINT8(imr, PicState),
 500         VMSTATE_UINT8(isr, PicState),
 501         VMSTATE_UINT8(priority_add, PicState),
 502         VMSTATE_UINT8(irq_base, PicState),
 503         VMSTATE_UINT8(read_reg_select, PicState),
 504         VMSTATE_UINT8(poll, PicState),
 505         VMSTATE_UINT8(special_mask, PicState),
 506         VMSTATE_UINT8(init_state, PicState),
 507         VMSTATE_UINT8(auto_eoi, PicState),
 508         VMSTATE_UINT8(rotate_on_auto_eoi, PicState),
 509         VMSTATE_UINT8(special_fully_nested_mode, PicState),
 510         VMSTATE_UINT8(init4, PicState),
 511         VMSTATE_UINT8(single_mode, PicState),
 512         VMSTATE_UINT8(elcr, PicState),
 513         VMSTATE_END_OF_LIST()
 514     }
 515 };
 516
 517 /* XXX: add generic master/slave system */
 518 static void pic_init1(int io_addr, int elcr_addr, PicState *s)
 519 {
 520     register_ioport_write(io_addr, 2, 1, pic_ioport_write, s);
 521     register_ioport_read(io_addr, 2, 1, pic_ioport_read, s);
 522     if (elcr_addr >= 0) {
 523         register_ioport_write(elcr_addr, 1, 1, elcr_ioport_write, s);
 524         register_ioport_read(elcr_addr, 1, 1, elcr_ioport_read, s);
 525     }
 526     vmstate_register(NULL, io_addr, &vmstate_pic, s);
 527     qemu_register_reset(pic_reset, s);
 528 }
 529
 530 void pic_info(Monitor *mon)
 531 {
 532     int i;
 533     PicState *s;
 534
 535     if (!isa_pic)
 536         return;
 537
 538     for(i=0;i<2;i++) {
 539         s = &isa_pic->pics[i];
 540         monitor_printf(mon, "pic%d: irr=%02x imr=%02x isr=%02x hprio=%d "
 541                        "irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n",
 542                        i, s->irr, s->imr, s->isr, s->priority_add,
 543                        s->irq_base, s->read_reg_select, s->elcr,
 544                        s->special_fully_nested_mode);
 545     }
 546 }
 547
 548 void irq_info(Monitor *mon)
 549 {
 550 #ifndef DEBUG_IRQ_COUNT
 551     monitor_printf(mon, "irq statistic code not compiled.\n");
 552 #else
 553     int i;
 554     int64_t count;
 555
 556     monitor_printf(mon, "IRQ statistics:\n");
 557     for (i = 0; i < 16; i++) {
 558         count = irq_count[i];
 559         if (count > 0)
 560             monitor_printf(mon, "%2d: %" PRId64 "\n", i, count);
 561     }
 562 #endif
 563 }
 564
 565 qemu_irq *i8259_init(qemu_irq parent_irq)
 566 {
 567     PicState2 *s;
 568
 569     s = qemu_mallocz(sizeof(PicState2));
 570     pic_init1(0x20, 0x4d0, &s->pics[0]);
 571     pic_init1(0xa0, 0x4d1, &s->pics[1]);
 572     s->pics[0].elcr_mask = 0xf8;
 573     s->pics[1].elcr_mask = 0xde;
 574     s->parent_irq = parent_irq;
 575     s->pics[0].pics_state = s;
 576     s->pics[1].pics_state = s;
 577     isa_pic = s;
 578     return qemu_allocate_irqs(i8259_set_irq, s, 16);
 579 }
 580
 581 static void kvm_kernel_pic_save_to_user(PicState *s)
 582 {
 583 #ifdef KVM_CAP_IRQCHIP
 584     struct kvm_irqchip chip;
 585     struct kvm_pic_state *kpic;
 586
 587     chip.chip_id = (&s->pics_state->pics[0] == s) ?
 588                    KVM_IRQCHIP_PIC_MASTER :
 589                    KVM_IRQCHIP_PIC_SLAVE;
 590     kvm_get_irqchip(kvm_state, &chip);
 591     kpic = &chip.chip.pic;
 592
 593     s->last_irr = kpic->last_irr;
 594     s->irr = kpic->irr;
 595     s->imr = kpic->imr;
 596     s->isr = kpic->isr;
 597     s->priority_add = kpic->priority_add;
 598     s->irq_base = kpic->irq_base;
 599     s->read_reg_select = kpic->read_reg_select;
 600     s->poll = kpic->poll;
 601     s->special_mask = kpic->special_mask;
 602     s->init_state = kpic->init_state;
 603     s->auto_eoi = kpic->auto_eoi;
 604     s->rotate_on_auto_eoi = kpic->rotate_on_auto_eoi;
 605     s->special_fully_nested_mode = kpic->special_fully_nested_mode;
 606     s->init4 = kpic->init4;
 607     s->elcr = kpic->elcr;
 608     s->elcr_mask = kpic->elcr_mask;
 609 #endif
 610 }
 611
 612 static int kvm_kernel_pic_load_from_user(PicState *s)
 613 {
 614 #ifdef KVM_CAP_IRQCHIP
 615     struct kvm_irqchip chip;
 616     struct kvm_pic_state *kpic;
 617
 618     chip.chip_id = (&s->pics_state->pics[0] == s) ?
 619                    KVM_IRQCHIP_PIC_MASTER :
 620                    KVM_IRQCHIP_PIC_SLAVE;
 621     kpic = &chip.chip.pic;
 622
 623     kpic->last_irr = s->last_irr;
 624     kpic->irr = s->irr;
 625     kpic->imr = s->imr;
 626     kpic->isr = s->isr;
 627     kpic->priority_add = s->priority_add;
 628     kpic->irq_base = s->irq_base;
 629     kpic->read_reg_select = s->read_reg_select;
 630     kpic->poll = s->poll;
 631     kpic->special_mask = s->special_mask;
 632     kpic->init_state = s->init_state;
 633     kpic->auto_eoi = s->auto_eoi;
 634     kpic->rotate_on_auto_eoi = s->rotate_on_auto_eoi;
 635     kpic->special_fully_nested_mode = s->special_fully_nested_mode;
 636     kpic->init4 = s->init4;
 637     kpic->elcr = s->elcr;
 638     kpic->elcr_mask = s->elcr_mask;
 639
 640     kvm_set_irqchip(kvm_state, &chip);
 641 #endif
 642     return 0;
 643 }
 644
 645 #ifdef KVM_CAP_IRQCHIP
 646 static void kvm_i8259_set_irq(void *opaque, int irq, int level)
 647 {
 648     int pic_ret;
 649     if (kvm_set_irq(irq, level, &pic_ret)) {
 650         if (pic_ret != 0)
 651             apic_set_irq_delivered();
 652         return;
 653     }
 654 }
 655
 656 static void kvm_pic_init1(int io_addr, PicState *s)
 657 {
 658     vmstate_register(NULL, io_addr, &vmstate_pic, s);
 659     qemu_register_reset(pic_reset, s);
 660 }
 661
 662 qemu_irq *kvm_i8259_init(qemu_irq parent_irq)
 663 {
 664     PicState2 *s;
 665
 666     s = qemu_mallocz(sizeof(PicState2));
 667
 668     kvm_pic_init1(0x20, &s->pics[0]);
 669     kvm_pic_init1(0xa0, &s->pics[1]);
 670     s->parent_irq = parent_irq;
 671     s->pics[0].pics_state = s;
 672     s->pics[1].pics_state = s;
 673     isa_pic = s;
 674     return qemu_allocate_irqs(kvm_i8259_set_irq, s, 24);
 675 }
 676 #endif
 677
 678
 679