hw/piix_pci.c

   1 /*
   2  * QEMU i440FX/PIIX3 PCI Bridge Emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw.h"
  26 #include "pc.h"
  27 #include "pci.h"
  28 #include "pci_host.h"
  29 #include "isa.h"
  30 #include "sysbus.h"
  31 #include "range.h"
  32 #include "xen.h"
  33 #include "kvm.h"
  34
  35 /*
  36  * I440FX chipset data sheet.
  37  * http://download.intel.com/design/chipsets/datashts/29054901.pdf
  38  */
  39
  40 typedef PCIHostState I440FXState;
  41
  42 #define PIIX_NUM_PIC_IRQS       16      /* i8259 * 2 */
  43 #define PIIX_NUM_PIRQS          4ULL    /* PIRQ[A-D] */
  44 #define PIIX_PIRQC              0x60
  45
  46 typedef struct PIIX3State {
  47     PCIDevice dev;
  48
  49     /*
  50      * bitmap to track pic levels.
  51      * The pic level is the logical OR of all the PCI irqs mapped to it
  52      * So one PIC level is tracked by PIIX_NUM_PIRQS bits.
  53      *
  54      * PIRQ is mapped to PIC pins, we track it by
  55      * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
  56      * pic_irq * PIIX_NUM_PIRQS + pirq
  57      */
  58 #if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
  59 #error "unable to encode pic state in 64bit in pic_levels."
  60 #endif
  61     uint64_t pic_levels;
  62
  63     qemu_irq *pic;
  64
  65     /* This member isn't used. Just for save/load compatibility */
  66     int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
  67 } PIIX3State;
  68
  69 struct PCII440FXState {
  70     PCIDevice dev;
  71     target_phys_addr_t isa_page_descs[384 / 4];
  72     uint8_t smm_enabled;
  73     PIIX3State *piix3;
  74 };
  75
  76
  77 #define I440FX_PAM      0x59
  78 #define I440FX_PAM_SIZE 7
  79 #define I440FX_SMRAM    0x72
  80
  81 static void piix3_set_irq(void *opaque, int pirq, int level);
  82
  83 /* return the global irq number corresponding to a given device irq
  84    pin. We could also use the bus number to have a more precise
  85    mapping. */
  86 static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
  87 {
  88     int slot_addend;
  89     slot_addend = (pci_dev->devfn >> 3) - 1;
  90     return (pci_intx + slot_addend) & 3;
  91 }
  92
  93 static void update_pam(PCII440FXState *d, uint32_t start, uint32_t end, int r)
  94 {
  95     uint32_t addr;
  96
  97     //    printf("ISA mapping %08x-0x%08x: %d\n", start, end, r);
  98     switch(r) {
  99     case 3:
 100         /* RAM */
 101         cpu_register_physical_memory(start, end - start,
 102                                      start);
 103         break;
 104     case 1:
 105         /* ROM (XXX: not quite correct) */
 106         cpu_register_physical_memory(start, end - start,
 107                                      start | IO_MEM_ROM);
 108         break;
 109     case 2:
 110     case 0:
 111         /* XXX: should distinguish read/write cases */
 112         for(addr = start; addr < end; addr += 4096) {
 113             cpu_register_physical_memory(addr, 4096,
 114                                          d->isa_page_descs[(addr - 0xa0000) >> 12]);
 115         }
 116         break;
 117     }
 118 }
 119
 120 static void i440fx_update_memory_mappings(PCII440FXState *d)
 121 {
 122     int i, r;
 123     uint32_t smram, addr;
 124
 125     update_pam(d, 0xf0000, 0x100000, (d->dev.config[I440FX_PAM] >> 4) & 3);
 126     for(i = 0; i < 12; i++) {
 127         r = (d->dev.config[(i >> 1) + (I440FX_PAM + 1)] >> ((i & 1) * 4)) & 3;
 128         update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r);
 129     }
 130     smram = d->dev.config[I440FX_SMRAM];
 131     if ((d->smm_enabled && (smram & 0x08)) || (smram & 0x40)) {
 132         cpu_register_physical_memory(0xa0000, 0x20000, 0xa0000);
 133     } else {
 134         for(addr = 0xa0000; addr < 0xc0000; addr += 4096) {
 135             cpu_register_physical_memory(addr, 4096,
 136                                          d->isa_page_descs[(addr - 0xa0000) >> 12]);
 137         }
 138     }
 139 }
 140
 141 static void i440fx_set_smm(int val, void *arg)
 142 {
 143     PCII440FXState *d = arg;
 144
 145     val = (val != 0);
 146     if (d->smm_enabled != val) {
 147         d->smm_enabled = val;
 148         i440fx_update_memory_mappings(d);
 149     }
 150 }
 151
 152
 153 /* XXX: suppress when better memory API. We make the assumption that
 154    no device (in particular the VGA) changes the memory mappings in
 155    the 0xa0000-0x100000 range */
 156 void i440fx_init_memory_mappings(PCII440FXState *d)
 157 {
 158     int i;
 159     for(i = 0; i < 96; i++) {
 160         d->isa_page_descs[i] = cpu_get_physical_page_desc(0xa0000 + i * 0x1000);
 161     }
 162 }
 163
 164 static void i440fx_write_config(PCIDevice *dev,
 165                                 uint32_t address, uint32_t val, int len)
 166 {
 167     PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
 168
 169     /* XXX: implement SMRAM.D_LOCK */
 170     pci_default_write_config(dev, address, val, len);
 171     if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) ||
 172         range_covers_byte(address, len, I440FX_SMRAM)) {
 173         i440fx_update_memory_mappings(d);
 174     }
 175 }
 176
 177 static void i440fx_write_config_xen(PCIDevice *dev,
 178                                     uint32_t address, uint32_t val, int len)
 179 {
 180     xen_piix_pci_write_config_client(address, val, len);
 181     i440fx_write_config(dev, address, val, len);
 182 }
 183
 184 static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
 185 {
 186     PCII440FXState *d = opaque;
 187     int ret, i;
 188
 189     ret = pci_device_load(&d->dev, f);
 190     if (ret < 0)
 191         return ret;
 192     i440fx_update_memory_mappings(d);
 193     qemu_get_8s(f, &d->smm_enabled);
 194
 195     if (version_id == 2) {
 196         for (i = 0; i < PIIX_NUM_PIRQS; i++) {
 197             qemu_get_be32(f); /* dummy load for compatibility */
 198         }
 199     }
 200
 201     return 0;
 202 }
 203
 204 static int i440fx_post_load(void *opaque, int version_id)
 205 {
 206     PCII440FXState *d = opaque;
 207
 208     i440fx_update_memory_mappings(d);
 209     return 0;
 210 }
 211
 212 static const VMStateDescription vmstate_i440fx = {
 213     .name = "I440FX",
 214     .version_id = 3,
 215     .minimum_version_id = 3,
 216     .minimum_version_id_old = 1,
 217     .load_state_old = i440fx_load_old,
 218     .post_load = i440fx_post_load,
 219     .fields      = (VMStateField []) {
 220         VMSTATE_PCI_DEVICE(dev, PCII440FXState),
 221         VMSTATE_UINT8(smm_enabled, PCII440FXState),
 222         VMSTATE_END_OF_LIST()
 223     }
 224 };
 225
 226 static int i440fx_pcihost_initfn(SysBusDevice *dev)
 227 {
 228     I440FXState *s = FROM_SYSBUS(I440FXState, dev);
 229
 230     pci_host_conf_register_ioport(0xcf8, s);
 231
 232     pci_host_data_register_ioport(0xcfc, s);
 233     return 0;
 234 }
 235
 236 static int i440fx_initfn(PCIDevice *dev)
 237 {
 238     PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
 239
 240     pci_config_set_vendor_id(d->dev.config, PCI_VENDOR_ID_INTEL);
 241     pci_config_set_device_id(d->dev.config, PCI_DEVICE_ID_INTEL_82441);
 242     d->dev.config[0x08] = 0x02; // revision
 243     pci_config_set_class(d->dev.config, PCI_CLASS_BRIDGE_HOST);
 244
 245     d->dev.config[I440FX_SMRAM] = 0x02;
 246
 247     cpu_smm_register(&i440fx_set_smm, d);
 248     return 0;
 249 }
 250
 251 static PIIX3State *piix3_dev;
 252
 253 static PCIBus *i440fx_common_init(const char *device_name,
 254                                   PCII440FXState **pi440fx_state,
 255                                   int *piix3_devfn,
 256                                   qemu_irq *pic, ram_addr_t ram_size)
 257 {
 258     DeviceState *dev;
 259     PCIBus *b;
 260     PCIDevice *d;
 261     I440FXState *s;
 262     PIIX3State *piix3;
 263
 264     dev = qdev_create(NULL, "i440FX-pcihost");
 265     s = FROM_SYSBUS(I440FXState, sysbus_from_qdev(dev));
 266     b = pci_bus_new(&s->busdev.qdev, NULL, 0);
 267     s->bus = b;
 268     qdev_init_nofail(dev);
 269
 270     d = pci_create_simple(b, 0, device_name);
 271     *pi440fx_state = DO_UPCAST(PCII440FXState, dev, d);
 272
 273     piix3 = DO_UPCAST(PIIX3State, dev,
 274                       pci_create_simple_multifunction(b, -1, true, "PIIX3"));
 275     piix3->pic = pic;
 276
 277     (*pi440fx_state)->piix3 = piix3;
 278
 279     *piix3_devfn = piix3->dev.devfn;
 280
 281     ram_size = ram_size / 8 / 1024 / 1024;
 282     if (ram_size > 255)
 283         ram_size = 255;
 284     (*pi440fx_state)->dev.config[0x57]=ram_size;
 285
 286     piix3_dev = piix3;
 287
 288     return b;
 289 }
 290
 291 PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn,
 292                     qemu_irq *pic, ram_addr_t ram_size)
 293 {
 294     PCIBus *b;
 295
 296     b = i440fx_common_init("i440FX", pi440fx_state, piix3_devfn, pic, ram_size);
 297     pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, (*pi440fx_state)->piix3,
 298                  PIIX_NUM_PIRQS);
 299
 300     return b;
 301 }
 302
 303 PCIBus *i440fx_xen_init(PCII440FXState **pi440fx_state, int *piix3_devfn,
 304                         qemu_irq *pic, ram_addr_t ram_size)
 305 {
 306     PCIBus *b;
 307
 308     b = i440fx_common_init("i440FX-xen", pi440fx_state, piix3_devfn, pic, ram_size);
 309     pci_bus_irqs(b, xen_piix3_set_irq, xen_pci_slot_get_pirq,
 310                  (*pi440fx_state)->piix3, PIIX_NUM_PIRQS);
 311
 312     return b;
 313 }
 314
 315 /* PIIX3 PCI to ISA bridge */
 316 static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
 317 {
 318     qemu_set_irq(piix3->pic[pic_irq],
 319                  !!(piix3->pic_levels &
 320                     (((1ULL << PIIX_NUM_PIRQS) - 1) <<
 321                      (pic_irq * PIIX_NUM_PIRQS))));
 322 }
 323
 324 static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
 325 {
 326     int pic_irq;
 327     uint64_t mask;
 328
 329     pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
 330     if (pic_irq >= PIIX_NUM_PIC_IRQS) {
 331         return;
 332     }
 333
 334     mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
 335     piix3->pic_levels &= ~mask;
 336     piix3->pic_levels |= mask * !!level;
 337
 338     piix3_set_irq_pic(piix3, pic_irq);
 339 }
 340
 341 static void piix3_set_irq(void *opaque, int pirq, int level)
 342 {
 343     PIIX3State *piix3 = opaque;
 344     piix3_set_irq_level(piix3, pirq, level);
 345 }
 346
 347 /* irq routing is changed. so rebuild bitmap */
 348 static void piix3_update_irq_levels(PIIX3State *piix3)
 349 {
 350     int pirq;
 351
 352     piix3->pic_levels = 0;
 353     for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
 354         piix3_set_irq_level(piix3, pirq,
 355                             pci_bus_get_irq_level(piix3->dev.bus, pirq));
 356     }
 357 }
 358
 359 static void piix3_write_config(PCIDevice *dev,
 360                                uint32_t address, uint32_t val, int len)
 361 {
 362     pci_default_write_config(dev, address, val, len);
 363     if (ranges_overlap(address, len, PIIX_PIRQC, 4)) {
 364         PIIX3State *piix3 = DO_UPCAST(PIIX3State, dev, dev);
 365         int pic_irq;
 366         piix3_update_irq_levels(piix3);
 367         for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
 368             piix3_set_irq_pic(piix3, pic_irq);
 369         }
 370     }
 371 }
 372
 373 int piix_get_irq(int pin)
 374 {
 375     if (piix3_dev)
 376         return piix3_dev->dev.config[0x60+pin];
 377     return 0;
 378 }
 379
 380 static void piix3_reset(void *opaque)
 381 {
 382     PIIX3State *d = opaque;
 383     uint8_t *pci_conf = d->dev.config;
 384
 385     pci_conf[0x04] = 0x07; // master, memory and I/O
 386     pci_conf[0x05] = 0x00;
 387     pci_conf[0x06] = 0x00;
 388     pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
 389     pci_conf[0x4c] = 0x4d;
 390     pci_conf[0x4e] = 0x03;
 391     pci_conf[0x4f] = 0x00;
 392     pci_conf[0x60] = 0x80;
 393     pci_conf[0x61] = 0x80;
 394     pci_conf[0x62] = 0x80;
 395     pci_conf[0x63] = 0x80;
 396     pci_conf[0x69] = 0x02;
 397     pci_conf[0x70] = 0x80;
 398     pci_conf[0x76] = 0x0c;
 399     pci_conf[0x77] = 0x0c;
 400     pci_conf[0x78] = 0x02;
 401     pci_conf[0x79] = 0x00;
 402     pci_conf[0x80] = 0x00;
 403     pci_conf[0x82] = 0x00;
 404     pci_conf[0xa0] = 0x08;
 405     pci_conf[0xa2] = 0x00;
 406     pci_conf[0xa3] = 0x00;
 407     pci_conf[0xa4] = 0x00;
 408     pci_conf[0xa5] = 0x00;
 409     pci_conf[0xa6] = 0x00;
 410     pci_conf[0xa7] = 0x00;
 411     pci_conf[0xa8] = 0x0f;
 412     pci_conf[0xaa] = 0x00;
 413     pci_conf[0xab] = 0x00;
 414     pci_conf[0xac] = 0x00;
 415     pci_conf[0xae] = 0x00;
 416
 417     d->pic_levels = 0;
 418 }
 419
 420 static int piix3_post_load(void *opaque, int version_id)
 421 {
 422     PIIX3State *piix3 = opaque;
 423     piix3_update_irq_levels(piix3);
 424     return 0;
 425 }
 426
 427 static void piix3_pre_save(void *opaque)
 428 {
 429     int i;
 430     PIIX3State *piix3 = opaque;
 431
 432     for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
 433         piix3->pci_irq_levels_vmstate[i] =
 434             pci_bus_get_irq_level(piix3->dev.bus, i);
 435     }
 436 }
 437
 438 static const VMStateDescription vmstate_piix3 = {
 439     .name = "PIIX3",
 440     .version_id = 3,
 441     .minimum_version_id = 2,
 442     .minimum_version_id_old = 2,
 443     .post_load = piix3_post_load,
 444     .pre_save = piix3_pre_save,
 445     .fields      = (VMStateField []) {
 446         VMSTATE_PCI_DEVICE(dev, PIIX3State),
 447         VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
 448                               PIIX_NUM_PIRQS, 3),
 449         VMSTATE_END_OF_LIST()
 450     }
 451 };
 452
 453 static int piix3_initfn(PCIDevice *dev)
 454 {
 455     PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev);
 456     uint8_t *pci_conf;
 457
 458     isa_bus_new(&d->dev.qdev);
 459
 460     pci_conf = d->dev.config;
 461     pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
 462     pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_0); // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
 463     pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA);
 464
 465     qemu_register_reset(piix3_reset, d);
 466     return 0;
 467 }
 468
 469 static PCIDeviceInfo i440fx_info[] = {
 470     {
 471         .qdev.name    = "i440FX",
 472         .qdev.desc    = "Host bridge",
 473         .qdev.size    = sizeof(PCII440FXState),
 474         .qdev.vmsd    = &vmstate_i440fx,
 475         .qdev.no_user = 1,
 476         .no_hotplug   = 1,
 477         .init         = i440fx_initfn,
 478         .config_write = i440fx_write_config,
 479     },{
 480         .qdev.name    = "i440FX-xen",
 481         .qdev.desc    = "Host bridge",
 482         .qdev.size    = sizeof(PCII440FXState),
 483         .qdev.vmsd    = &vmstate_i440fx,
 484         .qdev.no_user = 1,
 485         .init         = i440fx_initfn,
 486         .config_write = i440fx_write_config_xen,
 487     },{
 488         .qdev.name    = "PIIX3",
 489         .qdev.desc    = "ISA bridge",
 490         .qdev.size    = sizeof(PIIX3State),
 491         .qdev.vmsd    = &vmstate_piix3,
 492         .qdev.no_user = 1,
 493         .no_hotplug   = 1,
 494         .init         = piix3_initfn,
 495         .config_write = piix3_write_config,
 496     },{
 497         /* end of list */
 498     }
 499 };
 500
 501 static SysBusDeviceInfo i440fx_pcihost_info = {
 502     .init         = i440fx_pcihost_initfn,
 503     .qdev.name    = "i440FX-pcihost",
 504     .qdev.fw_name = "pci",
 505     .qdev.size    = sizeof(I440FXState),
 506     .qdev.no_user = 1,
 507 };
 508
 509 static void i440fx_register(void)
 510 {
 511     sysbus_register_withprop(&i440fx_pcihost_info);
 512     pci_qdev_register_many(i440fx_info);
 513 }
 514 device_init(i440fx_register);