hw/sparc32_dma.c

   1 /*
   2  * QEMU Sparc32 DMA controller emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Modifications:
   7  *  2010-Feb-14 Artyom Tarasenko : reworked irq generation
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a copy
  10  * of this software and associated documentation files (the "Software"), to deal
  11  * in the Software without restriction, including without limitation the rights
  12  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  13  * copies of the Software, and to permit persons to whom the Software is
  14  * furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice shall be included in
  17  * all copies or substantial portions of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  24  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  25  * THE SOFTWARE.
  26  */
  27
  28 #include "hw.h"
  29 #include "sparc32_dma.h"
  30 #include "sun4m.h"
  31 #include "sysbus.h"
  32
  33 /* debug DMA */
  34 //#define DEBUG_DMA
  35
  36 /*
  37  * This is the DMA controller part of chip STP2000 (Master I/O), also
  38  * produced as NCR89C100. See
  39  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
  40  * and
  41  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/DMA2.txt
  42  */
  43
  44 #ifdef DEBUG_DMA
  45 #define DPRINTF(fmt, ...)                               \
  46     do { printf("DMA: " fmt , ## __VA_ARGS__); } while (0)
  47 #else
  48 #define DPRINTF(fmt, ...)
  49 #endif
  50
  51 #define DMA_REGS 4
  52 #define DMA_SIZE (4 * sizeof(uint32_t))
  53 /* We need the mask, because one instance of the device is not page
  54    aligned (ledma, start address 0x0010) */
  55 #define DMA_MASK (DMA_SIZE - 1)
  56
  57 #define DMA_VER 0xa0000000
  58 #define DMA_INTR 1
  59 #define DMA_INTREN 0x10
  60 #define DMA_WRITE_MEM 0x100
  61 #define DMA_EN 0x200
  62 #define DMA_LOADED 0x04000000
  63 #define DMA_DRAIN_FIFO 0x40
  64 #define DMA_RESET 0x80
  65
  66 /* XXX SCSI and ethernet should have different read-only bit masks */
  67 #define DMA_CSR_RO_MASK 0xfe000007
  68
  69 typedef struct DMAState DMAState;
  70
  71 struct DMAState {
  72     SysBusDevice busdev;
  73     uint32_t dmaregs[DMA_REGS];
  74     qemu_irq irq;
  75     void *iommu;
  76     qemu_irq gpio[2];
  77 };
  78
  79 enum {
  80     GPIO_RESET = 0,
  81     GPIO_DMA,
  82 };
  83
  84 /* Note: on sparc, the lance 16 bit bus is swapped */
  85 void ledma_memory_read(void *opaque, target_phys_addr_t addr,
  86                        uint8_t *buf, int len, int do_bswap)
  87 {
  88     DMAState *s = opaque;
  89     int i;
  90
  91     DPRINTF("DMA write, direction: %c, addr 0x%8.8x\n",
  92             s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]);
  93     addr |= s->dmaregs[3];
  94     if (do_bswap) {
  95         sparc_iommu_memory_read(s->iommu, addr, buf, len);
  96     } else {
  97         addr &= ~1;
  98         len &= ~1;
  99         sparc_iommu_memory_read(s->iommu, addr, buf, len);
 100         for(i = 0; i < len; i += 2) {
 101             bswap16s((uint16_t *)(buf + i));
 102         }
 103     }
 104 }
 105
 106 void ledma_memory_write(void *opaque, target_phys_addr_t addr,
 107                         uint8_t *buf, int len, int do_bswap)
 108 {
 109     DMAState *s = opaque;
 110     int l, i;
 111     uint16_t tmp_buf[32];
 112
 113     DPRINTF("DMA read, direction: %c, addr 0x%8.8x\n",
 114             s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]);
 115     addr |= s->dmaregs[3];
 116     if (do_bswap) {
 117         sparc_iommu_memory_write(s->iommu, addr, buf, len);
 118     } else {
 119         addr &= ~1;
 120         len &= ~1;
 121         while (len > 0) {
 122             l = len;
 123             if (l > sizeof(tmp_buf))
 124                 l = sizeof(tmp_buf);
 125             for(i = 0; i < l; i += 2) {
 126                 tmp_buf[i >> 1] = bswap16(*(uint16_t *)(buf + i));
 127             }
 128             sparc_iommu_memory_write(s->iommu, addr, (uint8_t *)tmp_buf, l);
 129             len -= l;
 130             buf += l;
 131             addr += l;
 132         }
 133     }
 134 }
 135
 136 static void dma_set_irq(void *opaque, int irq, int level)
 137 {
 138     DMAState *s = opaque;
 139     if (level) {
 140         s->dmaregs[0] |= DMA_INTR;
 141         if (s->dmaregs[0] & DMA_INTREN) {
 142             DPRINTF("Raise IRQ\n");
 143             qemu_irq_raise(s->irq);
 144         }
 145     } else {
 146         if (s->dmaregs[0] & DMA_INTR) {
 147             s->dmaregs[0] &= ~DMA_INTR;
 148             if (s->dmaregs[0] & DMA_INTREN) {
 149                 DPRINTF("Lower IRQ\n");
 150                 qemu_irq_lower(s->irq);
 151             }
 152         }
 153     }
 154 }
 155
 156 void espdma_memory_read(void *opaque, uint8_t *buf, int len)
 157 {
 158     DMAState *s = opaque;
 159
 160     DPRINTF("DMA read, direction: %c, addr 0x%8.8x\n",
 161             s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]);
 162     sparc_iommu_memory_read(s->iommu, s->dmaregs[1], buf, len);
 163     s->dmaregs[1] += len;
 164 }
 165
 166 void espdma_memory_write(void *opaque, uint8_t *buf, int len)
 167 {
 168     DMAState *s = opaque;
 169
 170     DPRINTF("DMA write, direction: %c, addr 0x%8.8x\n",
 171             s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]);
 172     sparc_iommu_memory_write(s->iommu, s->dmaregs[1], buf, len);
 173     s->dmaregs[1] += len;
 174 }
 175
 176 static uint32_t dma_mem_readl(void *opaque, target_phys_addr_t addr)
 177 {
 178     DMAState *s = opaque;
 179     uint32_t saddr;
 180
 181     saddr = (addr & DMA_MASK) >> 2;
 182     DPRINTF("read dmareg " TARGET_FMT_plx ": 0x%8.8x\n", addr,
 183             s->dmaregs[saddr]);
 184
 185     return s->dmaregs[saddr];
 186 }
 187
 188 static void dma_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 189 {
 190     DMAState *s = opaque;
 191     uint32_t saddr;
 192
 193     saddr = (addr & DMA_MASK) >> 2;
 194     DPRINTF("write dmareg " TARGET_FMT_plx ": 0x%8.8x -> 0x%8.8x\n", addr,
 195             s->dmaregs[saddr], val);
 196     switch (saddr) {
 197     case 0:
 198         if (val & DMA_INTREN) {
 199             if (s->dmaregs[0] & DMA_INTR) {
 200                 DPRINTF("Raise IRQ\n");
 201                 qemu_irq_raise(s->irq);
 202             }
 203         } else {
 204             if (s->dmaregs[0] & (DMA_INTR | DMA_INTREN)) {
 205                 DPRINTF("Lower IRQ\n");
 206                 qemu_irq_lower(s->irq);
 207             }
 208         }
 209         if (val & DMA_RESET) {
 210             qemu_irq_raise(s->gpio[GPIO_RESET]);
 211             qemu_irq_lower(s->gpio[GPIO_RESET]);
 212         } else if (val & DMA_DRAIN_FIFO) {
 213             val &= ~DMA_DRAIN_FIFO;
 214         } else if (val == 0)
 215             val = DMA_DRAIN_FIFO;
 216
 217         if (val & DMA_EN && !(s->dmaregs[0] & DMA_EN)) {
 218             DPRINTF("Raise DMA enable\n");
 219             qemu_irq_raise(s->gpio[GPIO_DMA]);
 220         } else if (!(val & DMA_EN) && !!(s->dmaregs[0] & DMA_EN)) {
 221             DPRINTF("Lower DMA enable\n");
 222             qemu_irq_lower(s->gpio[GPIO_DMA]);
 223         }
 224
 225         val &= ~DMA_CSR_RO_MASK;
 226         val |= DMA_VER;
 227         s->dmaregs[0] = (s->dmaregs[0] & DMA_CSR_RO_MASK) | val;
 228         break;
 229     case 1:
 230         s->dmaregs[0] |= DMA_LOADED;
 231         /* fall through */
 232     default:
 233         s->dmaregs[saddr] = val;
 234         break;
 235     }
 236 }
 237
 238 static CPUReadMemoryFunc * const dma_mem_read[3] = {
 239     NULL,
 240     NULL,
 241     dma_mem_readl,
 242 };
 243
 244 static CPUWriteMemoryFunc * const dma_mem_write[3] = {
 245     NULL,
 246     NULL,
 247     dma_mem_writel,
 248 };
 249
 250 static void dma_reset(DeviceState *d)
 251 {
 252     DMAState *s = container_of(d, DMAState, busdev.qdev);
 253
 254     memset(s->dmaregs, 0, DMA_SIZE);
 255     s->dmaregs[0] = DMA_VER;
 256 }
 257
 258 static const VMStateDescription vmstate_dma = {
 259     .name ="sparc32_dma",
 260     .version_id = 2,
 261     .minimum_version_id = 2,
 262     .minimum_version_id_old = 2,
 263     .fields      = (VMStateField []) {
 264         VMSTATE_UINT32_ARRAY(dmaregs, DMAState, DMA_REGS),
 265         VMSTATE_END_OF_LIST()
 266     }
 267 };
 268
 269 static int sparc32_dma_init1(SysBusDevice *dev)
 270 {
 271     DMAState *s = FROM_SYSBUS(DMAState, dev);
 272     int dma_io_memory;
 273
 274     sysbus_init_irq(dev, &s->irq);
 275
 276     dma_io_memory = cpu_register_io_memory(dma_mem_read, dma_mem_write, s);
 277     sysbus_init_mmio(dev, DMA_SIZE, dma_io_memory);
 278
 279     qdev_init_gpio_in(&dev->qdev, dma_set_irq, 1);
 280     qdev_init_gpio_out(&dev->qdev, s->gpio, 2);
 281
 282     return 0;
 283 }
 284
 285 static SysBusDeviceInfo sparc32_dma_info = {
 286     .init = sparc32_dma_init1,
 287     .qdev.name  = "sparc32_dma",
 288     .qdev.size  = sizeof(DMAState),
 289     .qdev.vmsd  = &vmstate_dma,
 290     .qdev.reset = dma_reset,
 291     .qdev.props = (Property[]) {
 292         DEFINE_PROP_PTR("iommu_opaque", DMAState, iommu),
 293         DEFINE_PROP_END_OF_LIST(),
 294     }
 295 };
 296
 297 static void sparc32_dma_register_devices(void)
 298 {
 299     sysbus_register_withprop(&sparc32_dma_info);
 300 }
 301
 302 device_init(sparc32_dma_register_devices)