cpu-exec.c

   1 /*
   2  *  i386 emulator main execution loop
   3  *
   4  *  Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA  02110-1301 USA
  19  */
  20 #include "config.h"
  21 #include "exec.h"
  22 #include "disas.h"
  23 #if !defined(TARGET_IA64)
  24 #include "tcg.h"
  25 #endif
  26 #include "kvm.h"
  27
  28 #if !defined(CONFIG_SOFTMMU)
  29 #undef EAX
  30 #undef ECX
  31 #undef EDX
  32 #undef EBX
  33 #undef ESP
  34 #undef EBP
  35 #undef ESI
  36 #undef EDI
  37 #undef EIP
  38 #include <signal.h>
  39 #ifdef __linux__
  40 #include <sys/ucontext.h>
  41 #endif
  42 #endif
  43
  44 #include "qemu-kvm.h"
  45
  46 #if defined(__sparc__) && !defined(HOST_SOLARIS)
  47 // Work around ugly bugs in glibc that mangle global register contents
  48 #undef env
  49 #define env cpu_single_env
  50 #endif
  51
  52 int tb_invalidated_flag;
  53
  54 //#define DEBUG_EXEC
  55 //#define DEBUG_SIGNAL
  56
  57 void cpu_loop_exit(void)
  58 {
  59     /* NOTE: the register at this point must be saved by hand because
  60        longjmp restore them */
  61     regs_to_env();
  62     longjmp(env->jmp_env, 1);
  63 }
  64
  65 /* exit the current TB from a signal handler. The host registers are
  66    restored in a state compatible with the CPU emulator
  67  */
  68 void cpu_resume_from_signal(CPUState *env1, void *puc)
  69 {
  70 #if !defined(CONFIG_SOFTMMU)
  71 #ifdef __linux__
  72     struct ucontext *uc = puc;
  73 #elif defined(__OpenBSD__)
  74     struct sigcontext *uc = puc;
  75 #endif
  76 #endif
  77
  78     env = env1;
  79
  80     /* XXX: restore cpu registers saved in host registers */
  81
  82 #if !defined(CONFIG_SOFTMMU)
  83     if (puc) {
  84         /* XXX: use siglongjmp ? */
  85 #ifdef __linux__
  86         sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
  87 #elif defined(__OpenBSD__)
  88         sigprocmask(SIG_SETMASK, &uc->sc_mask, NULL);
  89 #endif
  90     }
  91 #endif
  92     env->exception_index = -1;
  93     longjmp(env->jmp_env, 1);
  94 }
  95
  96 /* Execute the code without caching the generated code. An interpreter
  97    could be used if available. */
  98 static void cpu_exec_nocache(int max_cycles, TranslationBlock *orig_tb)
  99 {
 100     unsigned long next_tb;
 101     TranslationBlock *tb;
 102
 103     /* Should never happen.
 104        We only end up here when an existing TB is too long.  */
 105     if (max_cycles > CF_COUNT_MASK)
 106         max_cycles = CF_COUNT_MASK;
 107
 108     tb = tb_gen_code(env, orig_tb->pc, orig_tb->cs_base, orig_tb->flags,
 109                      max_cycles);
 110     env->current_tb = tb;
 111     /* execute the generated code */
 112     next_tb = tcg_qemu_tb_exec(tb->tc_ptr);
 113
 114     if ((next_tb & 3) == 2) {
 115         /* Restore PC.  This may happen if async event occurs before
 116            the TB starts executing.  */
 117         cpu_pc_from_tb(env, tb);
 118     }
 119     tb_phys_invalidate(tb, -1);
 120     tb_free(tb);
 121 }
 122
 123 static TranslationBlock *tb_find_slow(target_ulong pc,
 124                                       target_ulong cs_base,
 125                                       uint64_t flags)
 126 {
 127     TranslationBlock *tb, **ptb1;
 128     unsigned int h;
 129     target_ulong phys_pc, phys_page1, phys_page2, virt_page2;
 130
 131     tb_invalidated_flag = 0;
 132
 133     regs_to_env(); /* XXX: do it just before cpu_gen_code() */
 134
 135     /* find translated block using physical mappings */
 136     phys_pc = get_phys_addr_code(env, pc);
 137     phys_page1 = phys_pc & TARGET_PAGE_MASK;
 138     phys_page2 = -1;
 139     h = tb_phys_hash_func(phys_pc);
 140     ptb1 = &tb_phys_hash[h];
 141     for(;;) {
 142         tb = *ptb1;
 143         if (!tb)
 144             goto not_found;
 145         if (tb->pc == pc &&
 146             tb->page_addr[0] == phys_page1 &&
 147             tb->cs_base == cs_base &&
 148             tb->flags == flags) {
 149             /* check next page if needed */
 150             if (tb->page_addr[1] != -1) {
 151                 virt_page2 = (pc & TARGET_PAGE_MASK) +
 152                     TARGET_PAGE_SIZE;
 153                 phys_page2 = get_phys_addr_code(env, virt_page2);
 154                 if (tb->page_addr[1] == phys_page2)
 155                     goto found;
 156             } else {
 157                 goto found;
 158             }
 159         }
 160         ptb1 = &tb->phys_hash_next;
 161     }
 162  not_found:
 163    /* if no translated code available, then translate it now */
 164     tb = tb_gen_code(env, pc, cs_base, flags, 0);
 165
 166  found:
 167     /* we add the TB in the virtual pc hash table */
 168     env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
 169     return tb;
 170 }
 171
 172 static inline TranslationBlock *tb_find_fast(void)
 173 {
 174     TranslationBlock *tb;
 175     target_ulong cs_base, pc;
 176     int flags;
 177
 178     /* we record a subset of the CPU state. It will
 179        always be the same before a given translated block
 180        is executed. */
 181     cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
 182     tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
 183     if (unlikely(!tb || tb->pc != pc || tb->cs_base != cs_base ||
 184                  tb->flags != flags)) {
 185         tb = tb_find_slow(pc, cs_base, flags);
 186     }
 187     return tb;
 188 }
 189
 190 static CPUDebugExcpHandler *debug_excp_handler;
 191
 192 CPUDebugExcpHandler *cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler)
 193 {
 194     CPUDebugExcpHandler *old_handler = debug_excp_handler;
 195
 196     debug_excp_handler = handler;
 197     return old_handler;
 198 }
 199
 200 static void cpu_handle_debug_exception(CPUState *env)
 201 {
 202     CPUWatchpoint *wp;
 203
 204     if (!env->watchpoint_hit)
 205         TAILQ_FOREACH(wp, &env->watchpoints, entry)
 206             wp->flags &= ~BP_WATCHPOINT_HIT;
 207
 208     if (debug_excp_handler)
 209         debug_excp_handler(env);
 210 }
 211
 212 /* main execution loop */
 213
 214 int cpu_exec(CPUState *env1)
 215 {
 216 #define DECLARE_HOST_REGS 1
 217 #include "hostregs_helper.h"
 218     int ret, interrupt_request;
 219     TranslationBlock *tb;
 220     uint8_t *tc_ptr;
 221     unsigned long next_tb;
 222
 223     if (cpu_halted(env1) == EXCP_HALTED)
 224         return EXCP_HALTED;
 225
 226     cpu_single_env = env1;
 227
 228     /* first we save global registers */
 229 #define SAVE_HOST_REGS 1
 230 #include "hostregs_helper.h"
 231     env = env1;
 232
 233     env_to_regs();
 234 #if defined(TARGET_I386)
 235     /* put eflags in CPU temporary format */
 236     CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 237     DF = 1 - (2 * ((env->eflags >> 10) & 1));
 238     CC_OP = CC_OP_EFLAGS;
 239     env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 240 #elif defined(TARGET_SPARC)
 241 #elif defined(TARGET_M68K)
 242     env->cc_op = CC_OP_FLAGS;
 243     env->cc_dest = env->sr & 0xf;
 244     env->cc_x = (env->sr >> 4) & 1;
 245 #elif defined(TARGET_ALPHA)
 246 #elif defined(TARGET_ARM)
 247 #elif defined(TARGET_PPC)
 248 #elif defined(TARGET_MIPS)
 249 #elif defined(TARGET_SH4)
 250 #elif defined(TARGET_CRIS)
 251 #elif defined(TARGET_IA64)
 252     /* XXXXX */
 253 #else
 254 #error unsupported target CPU
 255 #endif
 256     env->exception_index = -1;
 257
 258     /* prepare setjmp context for exception handling */
 259     for(;;) {
 260         if (setjmp(env->jmp_env) == 0) {
 261             env->current_tb = NULL;
 262             /* if an exception is pending, we execute it here */
 263             if (env->exception_index >= 0) {
 264                 if (env->exception_index >= EXCP_INTERRUPT) {
 265                     /* exit request from the cpu execution loop */
 266                     ret = env->exception_index;
 267                     if (ret == EXCP_DEBUG)
 268                         cpu_handle_debug_exception(env);
 269                     break;
 270                 } else {
 271 #if defined(CONFIG_USER_ONLY)
 272                     /* if user mode only, we simulate a fake exception
 273                        which will be handled outside the cpu execution
 274                        loop */
 275 #if defined(TARGET_I386)
 276                     do_interrupt_user(env->exception_index,
 277                                       env->exception_is_int,
 278                                       env->error_code,
 279                                       env->exception_next_eip);
 280                     /* successfully delivered */
 281                     env->old_exception = -1;
 282 #endif
 283                     ret = env->exception_index;
 284                     break;
 285 #else
 286 #if defined(TARGET_I386)
 287                     /* simulate a real cpu exception. On i386, it can
 288                        trigger new exceptions, but we do not handle
 289                        double or triple faults yet. */
 290                     do_interrupt(env->exception_index,
 291                                  env->exception_is_int,
 292                                  env->error_code,
 293                                  env->exception_next_eip, 0);
 294                     /* successfully delivered */
 295                     env->old_exception = -1;
 296 #elif defined(TARGET_PPC)
 297                     do_interrupt(env);
 298 #elif defined(TARGET_MIPS)
 299                     do_interrupt(env);
 300 #elif defined(TARGET_SPARC)
 301                     do_interrupt(env);
 302 #elif defined(TARGET_ARM)
 303                     do_interrupt(env);
 304 #elif defined(TARGET_SH4)
 305                     do_interrupt(env);
 306 #elif defined(TARGET_ALPHA)
 307                     do_interrupt(env);
 308 #elif defined(TARGET_CRIS)
 309                     do_interrupt(env);
 310 #elif defined(TARGET_M68K)
 311                     do_interrupt(0);
 312 #elif defined(TARGET_IA64)
 313                     do_interrupt(env);
 314 #endif
 315 #endif
 316                 }
 317                 env->exception_index = -1;
 318             }
 319 #ifdef USE_KQEMU
 320             if (kqemu_is_ok(env) && env->interrupt_request == 0 && env->exit_request == 0) {
 321                 int ret;
 322                 env->eflags = env->eflags | helper_cc_compute_all(CC_OP) | (DF & DF_MASK);
 323                 ret = kqemu_cpu_exec(env);
 324                 /* put eflags in CPU temporary format */
 325                 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 326                 DF = 1 - (2 * ((env->eflags >> 10) & 1));
 327                 CC_OP = CC_OP_EFLAGS;
 328                 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 329                 if (ret == 1) {
 330                     /* exception */
 331                     longjmp(env->jmp_env, 1);
 332                 } else if (ret == 2) {
 333                     /* softmmu execution needed */
 334                 } else {
 335                     if (env->interrupt_request != 0 || env->exit_request != 0) {
 336                         /* hardware interrupt will be executed just after */
 337                     } else {
 338                         /* otherwise, we restart */
 339                         longjmp(env->jmp_env, 1);
 340                     }
 341                 }
 342             }
 343 #endif
 344
 345             /* kvm vcpu threads */
 346             if (kvm_enabled()) {
 347                 kvm_cpu_exec(env);
 348                 longjmp(env->jmp_env, 1);
 349             }
 350
 351             if (kvm_enabled()) {
 352                 kvm_cpu_exec(env);
 353                 longjmp(env->jmp_env, 1);
 354             }
 355
 356             next_tb = 0; /* force lookup of first TB */
 357             for(;;) {
 358                 interrupt_request = env->interrupt_request;
 359                 if (unlikely(interrupt_request)) {
 360                     if (unlikely(env->singlestep_enabled & SSTEP_NOIRQ)) {
 361                         /* Mask out external interrupts for this step. */
 362                         interrupt_request &= ~(CPU_INTERRUPT_HARD |
 363                                                CPU_INTERRUPT_FIQ |
 364                                                CPU_INTERRUPT_SMI |
 365                                                CPU_INTERRUPT_NMI);
 366                     }
 367                     if (interrupt_request & CPU_INTERRUPT_DEBUG) {
 368                         env->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
 369                         env->exception_index = EXCP_DEBUG;
 370                         cpu_loop_exit();
 371                     }
 372 #if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \
 373     defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS)
 374                     if (interrupt_request & CPU_INTERRUPT_HALT) {
 375                         env->interrupt_request &= ~CPU_INTERRUPT_HALT;
 376                         env->halted = 1;
 377                         env->exception_index = EXCP_HLT;
 378                         cpu_loop_exit();
 379                     }
 380 #endif
 381 #if defined(TARGET_I386)
 382                     if (env->hflags2 & HF2_GIF_MASK) {
 383                         if ((interrupt_request & CPU_INTERRUPT_SMI) &&
 384                             !(env->hflags & HF_SMM_MASK)) {
 385                             svm_check_intercept(SVM_EXIT_SMI);
 386                             env->interrupt_request &= ~CPU_INTERRUPT_SMI;
 387                             do_smm_enter();
 388                             next_tb = 0;
 389                         } else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
 390                                    !(env->hflags2 & HF2_NMI_MASK)) {
 391                             env->interrupt_request &= ~CPU_INTERRUPT_NMI;
 392                             env->hflags2 |= HF2_NMI_MASK;
 393                             do_interrupt(EXCP02_NMI, 0, 0, 0, 1);
 394                             next_tb = 0;
 395                         } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
 396                                    (((env->hflags2 & HF2_VINTR_MASK) &&
 397                                      (env->hflags2 & HF2_HIF_MASK)) ||
 398                                     (!(env->hflags2 & HF2_VINTR_MASK) &&
 399                                      (env->eflags & IF_MASK &&
 400                                       !(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
 401                             int intno;
 402                             svm_check_intercept(SVM_EXIT_INTR);
 403                             env->interrupt_request &= ~(CPU_INTERRUPT_HARD | CPU_INTERRUPT_VIRQ);
 404                             intno = cpu_get_pic_interrupt(env);
 405                             qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing hardware INT=0x%02x\n", intno);
 406                             do_interrupt(intno, 0, 0, 0, 1);
 407                             /* ensure that no TB jump will be modified as
 408                                the program flow was changed */
 409                             next_tb = 0;
 410 #if !defined(CONFIG_USER_ONLY)
 411                         } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
 412                                    (env->eflags & IF_MASK) &&
 413                                    !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
 414                             int intno;
 415                             /* FIXME: this should respect TPR */
 416                             svm_check_intercept(SVM_EXIT_VINTR);
 417                             intno = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_vector));
 418                             qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing virtual hardware INT=0x%02x\n", intno);
 419                             do_interrupt(intno, 0, 0, 0, 1);
 420                             env->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
 421                             next_tb = 0;
 422 #endif
 423                         }
 424                     }
 425 #elif defined(TARGET_PPC)
 426 #if 0
 427                     if ((interrupt_request & CPU_INTERRUPT_RESET)) {
 428                         cpu_ppc_reset(env);
 429                     }
 430 #endif
 431                     if (interrupt_request & CPU_INTERRUPT_HARD) {
 432                         ppc_hw_interrupt(env);
 433                         if (env->pending_interrupts == 0)
 434                             env->interrupt_request &= ~CPU_INTERRUPT_HARD;
 435                         next_tb = 0;
 436                     }
 437 #elif defined(TARGET_MIPS)
 438                     if ((interrupt_request & CPU_INTERRUPT_HARD) &&
 439                         (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask) &&
 440                         (env->CP0_Status & (1 << CP0St_IE)) &&
 441                         !(env->CP0_Status & (1 << CP0St_EXL)) &&
 442                         !(env->CP0_Status & (1 << CP0St_ERL)) &&
 443                         !(env->hflags & MIPS_HFLAG_DM)) {
 444                         /* Raise it */
 445                         env->exception_index = EXCP_EXT_INTERRUPT;
 446                         env->error_code = 0;
 447                         do_interrupt(env);
 448                         next_tb = 0;
 449                     }
 450 #elif defined(TARGET_SPARC)
 451                     if ((interrupt_request & CPU_INTERRUPT_HARD) &&
 452                         (env->psret != 0)) {
 453                         int pil = env->interrupt_index & 15;
 454                         int type = env->interrupt_index & 0xf0;
 455
 456                         if (((type == TT_EXTINT) &&
 457                              (pil == 15 || pil > env->psrpil)) ||
 458                             type != TT_EXTINT) {
 459                             env->interrupt_request &= ~CPU_INTERRUPT_HARD;
 460                             env->exception_index = env->interrupt_index;
 461                             do_interrupt(env);
 462                             env->interrupt_index = 0;
 463 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
 464                             cpu_check_irqs(env);
 465 #endif
 466                         next_tb = 0;
 467                         }
 468                     } else if (interrupt_request & CPU_INTERRUPT_TIMER) {
 469                         //do_interrupt(0, 0, 0, 0, 0);
 470                         env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
 471                     }
 472 #elif defined(TARGET_ARM)
 473                     if (interrupt_request & CPU_INTERRUPT_FIQ
 474                         && !(env->uncached_cpsr & CPSR_F)) {
 475                         env->exception_index = EXCP_FIQ;
 476                         do_interrupt(env);
 477                         next_tb = 0;
 478                     }
 479                     /* ARMv7-M interrupt return works by loading a magic value
 480                        into the PC.  On real hardware the load causes the
 481                        return to occur.  The qemu implementation performs the
 482                        jump normally, then does the exception return when the
 483                        CPU tries to execute code at the magic address.
 484                        This will cause the magic PC value to be pushed to
 485                        the stack if an interrupt occured at the wrong time.
 486                        We avoid this by disabling interrupts when
 487                        pc contains a magic address.  */
 488                     if (interrupt_request & CPU_INTERRUPT_HARD
 489                         && ((IS_M(env) && env->regs[15] < 0xfffffff0)
 490                             || !(env->uncached_cpsr & CPSR_I))) {
 491                         env->exception_index = EXCP_IRQ;
 492                         do_interrupt(env);
 493                         next_tb = 0;
 494                     }
 495 #elif defined(TARGET_SH4)
 496                     if (interrupt_request & CPU_INTERRUPT_HARD) {
 497                         do_interrupt(env);
 498                         next_tb = 0;
 499                     }
 500 #elif defined(TARGET_ALPHA)
 501                     if (interrupt_request & CPU_INTERRUPT_HARD) {
 502                         do_interrupt(env);
 503                         next_tb = 0;
 504                     }
 505 #elif defined(TARGET_CRIS)
 506                     if (interrupt_request & CPU_INTERRUPT_HARD
 507                         && (env->pregs[PR_CCS] & I_FLAG)) {
 508                         env->exception_index = EXCP_IRQ;
 509                         do_interrupt(env);
 510                         next_tb = 0;
 511                     }
 512                     if (interrupt_request & CPU_INTERRUPT_NMI
 513                         && (env->pregs[PR_CCS] & M_FLAG)) {
 514                         env->exception_index = EXCP_NMI;
 515                         do_interrupt(env);
 516                         next_tb = 0;
 517                     }
 518 #elif defined(TARGET_M68K)
 519                     if (interrupt_request & CPU_INTERRUPT_HARD
 520                         && ((env->sr & SR_I) >> SR_I_SHIFT)
 521                             < env->pending_level) {
 522                         /* Real hardware gets the interrupt vector via an
 523                            IACK cycle at this point.  Current emulated
 524                            hardware doesn't rely on this, so we
 525                            provide/save the vector when the interrupt is
 526                            first signalled.  */
 527                         env->exception_index = env->pending_vector;
 528                         do_interrupt(1);
 529                         next_tb = 0;
 530                     }
 531 #endif
 532                    /* Don't use the cached interupt_request value,
 533                       do_interrupt may have updated the EXITTB flag. */
 534                     if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
 535                         env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
 536                         /* ensure that no TB jump will be modified as
 537                            the program flow was changed */
 538                         next_tb = 0;
 539                     }
 540                 }
 541                 if (unlikely(env->exit_request)) {
 542                     env->exit_request = 0;
 543                     env->exception_index = EXCP_INTERRUPT;
 544                     cpu_loop_exit();
 545                 }
 546 #ifdef DEBUG_EXEC
 547                 if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) {
 548                     /* restore flags in standard format */
 549                     regs_to_env();
 550 #if defined(TARGET_I386)
 551                     env->eflags = env->eflags | helper_cc_compute_all(CC_OP) | (DF & DF_MASK);
 552                     log_cpu_state(env, X86_DUMP_CCOP);
 553                     env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 554 #elif defined(TARGET_ARM)
 555                     log_cpu_state(env, 0);
 556 #elif defined(TARGET_SPARC)
 557                     log_cpu_state(env, 0);
 558 #elif defined(TARGET_PPC)
 559                     log_cpu_state(env, 0);
 560 #elif defined(TARGET_M68K)
 561                     cpu_m68k_flush_flags(env, env->cc_op);
 562                     env->cc_op = CC_OP_FLAGS;
 563                     env->sr = (env->sr & 0xffe0)
 564                               | env->cc_dest | (env->cc_x << 4);
 565                     log_cpu_state(env, 0);
 566 #elif defined(TARGET_MIPS)
 567                     log_cpu_state(env, 0);
 568 #elif defined(TARGET_SH4)
 569                     log_cpu_state(env, 0);
 570 #elif defined(TARGET_ALPHA)
 571                     log_cpu_state(env, 0);
 572 #elif defined(TARGET_CRIS)
 573                     log_cpu_state(env, 0);
 574 #else
 575 #error unsupported target CPU
 576 #endif
 577                 }
 578 #endif
 579                 spin_lock(&tb_lock);
 580                 tb = tb_find_fast();
 581                 /* Note: we do it here to avoid a gcc bug on Mac OS X when
 582                    doing it in tb_find_slow */
 583                 if (tb_invalidated_flag) {
 584                     /* as some TB could have been invalidated because
 585                        of memory exceptions while generating the code, we
 586                        must recompute the hash index here */
 587                     next_tb = 0;
 588                     tb_invalidated_flag = 0;
 589                 }
 590 #ifdef DEBUG_EXEC
 591                 qemu_log_mask(CPU_LOG_EXEC, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n",
 592                              (long)tb->tc_ptr, tb->pc,
 593                              lookup_symbol(tb->pc));
 594 #endif
 595                 /* see if we can patch the calling TB. When the TB
 596                    spans two pages, we cannot safely do a direct
 597                    jump. */
 598                 {
 599                     if (next_tb != 0 &&
 600 #ifdef USE_KQEMU
 601                         (env->kqemu_enabled != 2) &&
 602 #endif
 603                         tb->page_addr[1] == -1) {
 604                     tb_add_jump((TranslationBlock *)(next_tb & ~3), next_tb & 3, tb);
 605                 }
 606                 }
 607                 spin_unlock(&tb_lock);
 608                 env->current_tb = tb;
 609
 610                 /* cpu_interrupt might be called while translating the
 611                    TB, but before it is linked into a potentially
 612                    infinite loop and becomes env->current_tb. Avoid
 613                    starting execution if there is a pending interrupt. */
 614                 if (unlikely (env->exit_request))
 615                     env->current_tb = NULL;
 616
 617                 while (env->current_tb) {
 618                     tc_ptr = tb->tc_ptr;
 619                 /* execute the generated code */
 620 #if defined(__sparc__) && !defined(HOST_SOLARIS)
 621 #undef env
 622                     env = cpu_single_env;
 623 #define env cpu_single_env
 624 #endif
 625                     next_tb = tcg_qemu_tb_exec(tc_ptr);
 626                     env->current_tb = NULL;
 627                     if ((next_tb & 3) == 2) {
 628                         /* Instruction counter expired.  */
 629                         int insns_left;
 630                         tb = (TranslationBlock *)(long)(next_tb & ~3);
 631                         /* Restore PC.  */
 632                         cpu_pc_from_tb(env, tb);
 633                         insns_left = env->icount_decr.u32;
 634                         if (env->icount_extra && insns_left >= 0) {
 635                             /* Refill decrementer and continue execution.  */
 636                             env->icount_extra += insns_left;
 637                             if (env->icount_extra > 0xffff) {
 638                                 insns_left = 0xffff;
 639                             } else {
 640                                 insns_left = env->icount_extra;
 641                             }
 642                             env->icount_extra -= insns_left;
 643                             env->icount_decr.u16.low = insns_left;
 644                         } else {
 645                             if (insns_left > 0) {
 646                                 /* Execute remaining instructions.  */
 647                                 cpu_exec_nocache(insns_left, tb);
 648                             }
 649                             env->exception_index = EXCP_INTERRUPT;
 650                             next_tb = 0;
 651                             cpu_loop_exit();
 652                         }
 653                     }
 654                 }
 655                 /* reset soft MMU for next block (it can currently
 656                    only be set by a memory fault) */
 657 #if defined(USE_KQEMU)
 658 #define MIN_CYCLE_BEFORE_SWITCH (100 * 1000)
 659                 if (kqemu_is_ok(env) &&
 660                     (cpu_get_time_fast() - env->last_io_time) >= MIN_CYCLE_BEFORE_SWITCH) {
 661                     cpu_loop_exit();
 662                 }
 663 #endif
 664             } /* for(;;) */
 665         } else {
 666             env_to_regs();
 667         }
 668     } /* for(;;) */
 669
 670
 671 #if defined(TARGET_I386)
 672     /* restore flags in standard format */
 673     env->eflags = env->eflags | helper_cc_compute_all(CC_OP) | (DF & DF_MASK);
 674 #elif defined(TARGET_ARM)
 675     /* XXX: Save/restore host fpu exception state?.  */
 676 #elif defined(TARGET_SPARC)
 677 #elif defined(TARGET_PPC)
 678 #elif defined(TARGET_M68K)
 679     cpu_m68k_flush_flags(env, env->cc_op);
 680     env->cc_op = CC_OP_FLAGS;
 681     env->sr = (env->sr & 0xffe0)
 682               | env->cc_dest | (env->cc_x << 4);
 683 #elif defined(TARGET_MIPS)
 684 #elif defined(TARGET_SH4)
 685 #elif defined(TARGET_IA64)
 686 #elif defined(TARGET_ALPHA)
 687 #elif defined(TARGET_CRIS)
 688     /* XXXXX */
 689 #else
 690 #error unsupported target CPU
 691 #endif
 692
 693     /* restore global registers */
 694 #include "hostregs_helper.h"
 695
 696     /* fail safe : never use cpu_single_env outside cpu_exec() */
 697     cpu_single_env = NULL;
 698     return ret;
 699 }
 700
 701 /* must only be called from the generated code as an exception can be
 702    generated */
 703 void tb_invalidate_page_range(target_ulong start, target_ulong end)
 704 {
 705     /* XXX: cannot enable it yet because it yields to MMU exception
 706        where NIP != read address on PowerPC */
 707 #if 0
 708     target_ulong phys_addr;
 709     phys_addr = get_phys_addr_code(env, start);
 710     tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
 711 #endif
 712 }
 713
 714 #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
 715
 716 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
 717 {
 718     CPUX86State *saved_env;
 719
 720     saved_env = env;
 721     env = s;
 722     if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
 723         selector &= 0xffff;
 724         cpu_x86_load_seg_cache(env, seg_reg, selector,
 725                                (selector << 4), 0xffff, 0);
 726     } else {
 727         helper_load_seg(seg_reg, selector);
 728     }
 729     env = saved_env;
 730 }
 731
 732 void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32)
 733 {
 734     CPUX86State *saved_env;
 735
 736     saved_env = env;
 737     env = s;
 738
 739     helper_fsave(ptr, data32);
 740
 741     env = saved_env;
 742 }
 743
 744 void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32)
 745 {
 746     CPUX86State *saved_env;
 747
 748     saved_env = env;
 749     env = s;
 750
 751     helper_frstor(ptr, data32);
 752
 753     env = saved_env;
 754 }
 755
 756 #endif /* TARGET_I386 */
 757
 758 #if !defined(CONFIG_SOFTMMU)
 759
 760 #if defined(TARGET_I386)
 761
 762 /* 'pc' is the host PC at which the exception was raised. 'address' is
 763    the effective address of the memory exception. 'is_write' is 1 if a
 764    write caused the exception and otherwise 0'. 'old_set' is the
 765    signal set which should be restored */
 766 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
 767                                     int is_write, sigset_t *old_set,
 768                                     void *puc)
 769 {
 770     TranslationBlock *tb;
 771     int ret;
 772
 773     if (cpu_single_env)
 774         env = cpu_single_env; /* XXX: find a correct solution for multithread */
 775 #if defined(DEBUG_SIGNAL)
 776     qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
 777                 pc, address, is_write, *(unsigned long *)old_set);
 778 #endif
 779     /* XXX: locking issue */
 780     if (is_write && page_unprotect(h2g(address), pc, puc)) {
 781         return 1;
 782     }
 783
 784     /* see if it is an MMU fault */
 785     ret = cpu_x86_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
 786     if (ret < 0)
 787         return 0; /* not an MMU fault */
 788     if (ret == 0)
 789         return 1; /* the MMU fault was handled without causing real CPU fault */
 790     /* now we have a real cpu fault */
 791     tb = tb_find_pc(pc);
 792     if (tb) {
 793         /* the PC is inside the translated code. It means that we have
 794            a virtual CPU fault */
 795         cpu_restore_state(tb, env, pc, puc);
 796     }
 797     if (ret == 1) {
 798 #if 0
 799         printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
 800                env->eip, env->cr[2], env->error_code);
 801 #endif
 802         /* we restore the process signal mask as the sigreturn should
 803            do it (XXX: use sigsetjmp) */
 804         sigprocmask(SIG_SETMASK, old_set, NULL);
 805         raise_exception_err(env->exception_index, env->error_code);
 806     } else {
 807         /* activate soft MMU for this block */
 808         env->hflags |= HF_SOFTMMU_MASK;
 809         cpu_resume_from_signal(env, puc);
 810     }
 811     /* never comes here */
 812     return 1;
 813 }
 814
 815 #elif defined(TARGET_ARM)
 816 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
 817                                     int is_write, sigset_t *old_set,
 818                                     void *puc)
 819 {
 820     TranslationBlock *tb;
 821     int ret;
 822
 823     if (cpu_single_env)
 824         env = cpu_single_env; /* XXX: find a correct solution for multithread */
 825 #if defined(DEBUG_SIGNAL)
 826     printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
 827            pc, address, is_write, *(unsigned long *)old_set);
 828 #endif
 829     /* XXX: locking issue */
 830     if (is_write && page_unprotect(h2g(address), pc, puc)) {
 831         return 1;
 832     }
 833     /* see if it is an MMU fault */
 834     ret = cpu_arm_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
 835     if (ret < 0)
 836         return 0; /* not an MMU fault */
 837     if (ret == 0)
 838         return 1; /* the MMU fault was handled without causing real CPU fault */
 839     /* now we have a real cpu fault */
 840     tb = tb_find_pc(pc);
 841     if (tb) {
 842         /* the PC is inside the translated code. It means that we have
 843            a virtual CPU fault */
 844         cpu_restore_state(tb, env, pc, puc);
 845     }
 846     /* we restore the process signal mask as the sigreturn should
 847        do it (XXX: use sigsetjmp) */
 848     sigprocmask(SIG_SETMASK, old_set, NULL);
 849     cpu_loop_exit();
 850     /* never comes here */
 851     return 1;
 852 }
 853 #elif defined(TARGET_SPARC)
 854 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
 855                                     int is_write, sigset_t *old_set,
 856                                     void *puc)
 857 {
 858     TranslationBlock *tb;
 859     int ret;
 860
 861     if (cpu_single_env)
 862         env = cpu_single_env; /* XXX: find a correct solution for multithread */
 863 #if defined(DEBUG_SIGNAL)
 864     printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
 865            pc, address, is_write, *(unsigned long *)old_set);
 866 #endif
 867     /* XXX: locking issue */
 868     if (is_write && page_unprotect(h2g(address), pc, puc)) {
 869         return 1;
 870     }
 871     /* see if it is an MMU fault */
 872     ret = cpu_sparc_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
 873     if (ret < 0)
 874         return 0; /* not an MMU fault */
 875     if (ret == 0)
 876         return 1; /* the MMU fault was handled without causing real CPU fault */
 877     /* now we have a real cpu fault */
 878     tb = tb_find_pc(pc);
 879     if (tb) {
 880         /* the PC is inside the translated code. It means that we have
 881            a virtual CPU fault */
 882         cpu_restore_state(tb, env, pc, puc);
 883     }
 884     /* we restore the process signal mask as the sigreturn should
 885        do it (XXX: use sigsetjmp) */
 886     sigprocmask(SIG_SETMASK, old_set, NULL);
 887     cpu_loop_exit();
 888     /* never comes here */
 889     return 1;
 890 }
 891 #elif defined (TARGET_PPC)
 892 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
 893                                     int is_write, sigset_t *old_set,
 894                                     void *puc)
 895 {
 896     TranslationBlock *tb;
 897     int ret;
 898
 899     if (cpu_single_env)
 900         env = cpu_single_env; /* XXX: find a correct solution for multithread */
 901 #if defined(DEBUG_SIGNAL)
 902     printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
 903            pc, address, is_write, *(unsigned long *)old_set);
 904 #endif
 905     /* XXX: locking issue */
 906     if (is_write && page_unprotect(h2g(address), pc, puc)) {
 907         return 1;
 908     }
 909
 910     /* see if it is an MMU fault */
 911     ret = cpu_ppc_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
 912     if (ret < 0)
 913         return 0; /* not an MMU fault */
 914     if (ret == 0)
 915         return 1; /* the MMU fault was handled without causing real CPU fault */
 916
 917     /* now we have a real cpu fault */
 918     tb = tb_find_pc(pc);
 919     if (tb) {
 920         /* the PC is inside the translated code. It means that we have
 921            a virtual CPU fault */
 922         cpu_restore_state(tb, env, pc, puc);
 923     }
 924     if (ret == 1) {
 925 #if 0
 926         printf("PF exception: NIP=0x%08x error=0x%x %p\n",
 927                env->nip, env->error_code, tb);
 928 #endif
 929     /* we restore the process signal mask as the sigreturn should
 930        do it (XXX: use sigsetjmp) */
 931         sigprocmask(SIG_SETMASK, old_set, NULL);
 932         cpu_loop_exit();
 933     } else {
 934         /* activate soft MMU for this block */
 935         cpu_resume_from_signal(env, puc);
 936     }
 937     /* never comes here */
 938     return 1;
 939 }
 940
 941 #elif defined(TARGET_M68K)
 942 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
 943                                     int is_write, sigset_t *old_set,
 944                                     void *puc)
 945 {
 946     TranslationBlock *tb;
 947     int ret;
 948
 949     if (cpu_single_env)
 950         env = cpu_single_env; /* XXX: find a correct solution for multithread */
 951 #if defined(DEBUG_SIGNAL)
 952     printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
 953            pc, address, is_write, *(unsigned long *)old_set);
 954 #endif
 955     /* XXX: locking issue */
 956     if (is_write && page_unprotect(address, pc, puc)) {
 957         return 1;
 958     }
 959     /* see if it is an MMU fault */
 960     ret = cpu_m68k_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
 961     if (ret < 0)
 962         return 0; /* not an MMU fault */
 963     if (ret == 0)
 964         return 1; /* the MMU fault was handled without causing real CPU fault */
 965     /* now we have a real cpu fault */
 966     tb = tb_find_pc(pc);
 967     if (tb) {
 968         /* the PC is inside the translated code. It means that we have
 969            a virtual CPU fault */
 970         cpu_restore_state(tb, env, pc, puc);
 971     }
 972     /* we restore the process signal mask as the sigreturn should
 973        do it (XXX: use sigsetjmp) */
 974     sigprocmask(SIG_SETMASK, old_set, NULL);
 975     cpu_loop_exit();
 976     /* never comes here */
 977     return 1;
 978 }
 979
 980 #elif defined (TARGET_MIPS)
 981 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
 982                                     int is_write, sigset_t *old_set,
 983                                     void *puc)
 984 {
 985     TranslationBlock *tb;
 986     int ret;
 987
 988     if (cpu_single_env)
 989         env = cpu_single_env; /* XXX: find a correct solution for multithread */
 990 #if defined(DEBUG_SIGNAL)
 991     printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
 992            pc, address, is_write, *(unsigned long *)old_set);
 993 #endif
 994     /* XXX: locking issue */
 995     if (is_write && page_unprotect(h2g(address), pc, puc)) {
 996         return 1;
 997     }
 998
 999     /* see if it is an MMU fault */
1000     ret = cpu_mips_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
1001     if (ret < 0)
1002         return 0; /* not an MMU fault */
1003     if (ret == 0)
1004         return 1; /* the MMU fault was handled without causing real CPU fault */
1005
1006     /* now we have a real cpu fault */
1007     tb = tb_find_pc(pc);
1008     if (tb) {
1009         /* the PC is inside the translated code. It means that we have
1010            a virtual CPU fault */
1011         cpu_restore_state(tb, env, pc, puc);
1012     }
1013     if (ret == 1) {
1014 #if 0
1015         printf("PF exception: PC=0x" TARGET_FMT_lx " error=0x%x %p\n",
1016                env->PC, env->error_code, tb);
1017 #endif
1018     /* we restore the process signal mask as the sigreturn should
1019        do it (XXX: use sigsetjmp) */
1020         sigprocmask(SIG_SETMASK, old_set, NULL);
1021         cpu_loop_exit();
1022     } else {
1023         /* activate soft MMU for this block */
1024         cpu_resume_from_signal(env, puc);
1025     }
1026     /* never comes here */
1027     return 1;
1028 }
1029
1030 #elif defined (TARGET_SH4)
1031 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1032                                     int is_write, sigset_t *old_set,
1033                                     void *puc)
1034 {
1035     TranslationBlock *tb;
1036     int ret;
1037
1038     if (cpu_single_env)
1039         env = cpu_single_env; /* XXX: find a correct solution for multithread */
1040 #if defined(DEBUG_SIGNAL)
1041     printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1042            pc, address, is_write, *(unsigned long *)old_set);
1043 #endif
1044     /* XXX: locking issue */
1045     if (is_write && page_unprotect(h2g(address), pc, puc)) {
1046         return 1;
1047     }
1048
1049     /* see if it is an MMU fault */
1050     ret = cpu_sh4_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
1051     if (ret < 0)
1052         return 0; /* not an MMU fault */
1053     if (ret == 0)
1054         return 1; /* the MMU fault was handled without causing real CPU fault */
1055
1056     /* now we have a real cpu fault */
1057     tb = tb_find_pc(pc);
1058     if (tb) {
1059         /* the PC is inside the translated code. It means that we have
1060            a virtual CPU fault */
1061         cpu_restore_state(tb, env, pc, puc);
1062     }
1063 #if 0
1064         printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1065                env->nip, env->error_code, tb);
1066 #endif
1067     /* we restore the process signal mask as the sigreturn should
1068        do it (XXX: use sigsetjmp) */
1069     sigprocmask(SIG_SETMASK, old_set, NULL);
1070     cpu_loop_exit();
1071     /* never comes here */
1072     return 1;
1073 }
1074
1075 #elif defined (TARGET_ALPHA)
1076 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1077                                     int is_write, sigset_t *old_set,
1078                                     void *puc)
1079 {
1080     TranslationBlock *tb;
1081     int ret;
1082
1083     if (cpu_single_env)
1084         env = cpu_single_env; /* XXX: find a correct solution for multithread */
1085 #if defined(DEBUG_SIGNAL)
1086     printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1087            pc, address, is_write, *(unsigned long *)old_set);
1088 #endif
1089     /* XXX: locking issue */
1090     if (is_write && page_unprotect(h2g(address), pc, puc)) {
1091         return 1;
1092     }
1093
1094     /* see if it is an MMU fault */
1095     ret = cpu_alpha_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
1096     if (ret < 0)
1097         return 0; /* not an MMU fault */
1098     if (ret == 0)
1099         return 1; /* the MMU fault was handled without causing real CPU fault */
1100
1101     /* now we have a real cpu fault */
1102     tb = tb_find_pc(pc);
1103     if (tb) {
1104         /* the PC is inside the translated code. It means that we have
1105            a virtual CPU fault */
1106         cpu_restore_state(tb, env, pc, puc);
1107     }
1108 #if 0
1109         printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1110                env->nip, env->error_code, tb);
1111 #endif
1112     /* we restore the process signal mask as the sigreturn should
1113        do it (XXX: use sigsetjmp) */
1114     sigprocmask(SIG_SETMASK, old_set, NULL);
1115     cpu_loop_exit();
1116     /* never comes here */
1117     return 1;
1118 }
1119 #elif defined (TARGET_CRIS)
1120 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1121                                     int is_write, sigset_t *old_set,
1122                                     void *puc)
1123 {
1124     TranslationBlock *tb;
1125     int ret;
1126
1127     if (cpu_single_env)
1128         env = cpu_single_env; /* XXX: find a correct solution for multithread */
1129 #if defined(DEBUG_SIGNAL)
1130     printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1131            pc, address, is_write, *(unsigned long *)old_set);
1132 #endif
1133     /* XXX: locking issue */
1134     if (is_write && page_unprotect(h2g(address), pc, puc)) {
1135         return 1;
1136     }
1137
1138     /* see if it is an MMU fault */
1139     ret = cpu_cris_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
1140     if (ret < 0)
1141         return 0; /* not an MMU fault */
1142     if (ret == 0)
1143         return 1; /* the MMU fault was handled without causing real CPU fault */
1144
1145     /* now we have a real cpu fault */
1146     tb = tb_find_pc(pc);
1147     if (tb) {
1148         /* the PC is inside the translated code. It means that we have
1149            a virtual CPU fault */
1150         cpu_restore_state(tb, env, pc, puc);
1151     }
1152     /* we restore the process signal mask as the sigreturn should
1153        do it (XXX: use sigsetjmp) */
1154     sigprocmask(SIG_SETMASK, old_set, NULL);
1155     cpu_loop_exit();
1156     /* never comes here */
1157     return 1;
1158 }
1159
1160 #else
1161 #error unsupported target CPU
1162 #endif
1163
1164 #if defined(__i386__)
1165
1166 #if defined(__APPLE__)
1167 # include <sys/ucontext.h>
1168
1169 # define EIP_sig(context)  (*((unsigned long*)&(context)->uc_mcontext->ss.eip))
1170 # define TRAP_sig(context)    ((context)->uc_mcontext->es.trapno)
1171 # define ERROR_sig(context)   ((context)->uc_mcontext->es.err)
1172 #else
1173 # define EIP_sig(context)     ((context)->uc_mcontext.gregs[REG_EIP])
1174 # define TRAP_sig(context)    ((context)->uc_mcontext.gregs[REG_TRAPNO])
1175 # define ERROR_sig(context)   ((context)->uc_mcontext.gregs[REG_ERR])
1176 #endif
1177
1178 int cpu_signal_handler(int host_signum, void *pinfo,
1179                        void *puc)
1180 {
1181     siginfo_t *info = pinfo;
1182     struct ucontext *uc = puc;
1183     unsigned long pc;
1184     int trapno;
1185
1186 #ifndef REG_EIP
1187 /* for glibc 2.1 */
1188 #define REG_EIP    EIP
1189 #define REG_ERR    ERR
1190 #define REG_TRAPNO TRAPNO
1191 #endif
1192     pc = EIP_sig(uc);
1193     trapno = TRAP_sig(uc);
1194     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1195                              trapno == 0xe ?
1196                              (ERROR_sig(uc) >> 1) & 1 : 0,
1197                              &uc->uc_sigmask, puc);
1198 }
1199
1200 #elif defined(__x86_64__)
1201
1202 #ifdef __NetBSD__
1203 #define REG_ERR _REG_ERR
1204 #define REG_TRAPNO _REG_TRAPNO
1205
1206 #define QEMU_UC_MCONTEXT_GREGS(uc, reg) (uc)->uc_mcontext.__gregs[(reg)]
1207 #define QEMU_UC_MACHINE_PC(uc)          _UC_MACHINE_PC(uc)
1208 #else
1209 #define QEMU_UC_MCONTEXT_GREGS(uc, reg) (uc)->uc_mcontext.gregs[(reg)]
1210 #define QEMU_UC_MACHINE_PC(uc)          QEMU_UC_MCONTEXT_GREGS(uc, REG_RIP)
1211 #endif
1212
1213 int cpu_signal_handler(int host_signum, void *pinfo,
1214                        void *puc)
1215 {
1216     siginfo_t *info = pinfo;
1217     unsigned long pc;
1218 #ifdef __NetBSD__
1219     ucontext_t *uc = puc;
1220 #else
1221     struct ucontext *uc = puc;
1222 #endif
1223
1224     pc = QEMU_UC_MACHINE_PC(uc);
1225     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1226                              QEMU_UC_MCONTEXT_GREGS(uc, REG_TRAPNO) == 0xe ?
1227                              (QEMU_UC_MCONTEXT_GREGS(uc, REG_ERR) >> 1) & 1 : 0,
1228                              &uc->uc_sigmask, puc);
1229 }
1230
1231 #elif defined(_ARCH_PPC)
1232
1233 /***********************************************************************
1234  * signal context platform-specific definitions
1235  * From Wine
1236  */
1237 #ifdef linux
1238 /* All Registers access - only for local access */
1239 # define REG_sig(reg_name, context)             ((context)->uc_mcontext.regs->reg_name)
1240 /* Gpr Registers access  */
1241 # define GPR_sig(reg_num, context)              REG_sig(gpr[reg_num], context)
1242 # define IAR_sig(context)                       REG_sig(nip, context)   /* Program counter */
1243 # define MSR_sig(context)                       REG_sig(msr, context)   /* Machine State Register (Supervisor) */
1244 # define CTR_sig(context)                       REG_sig(ctr, context)   /* Count register */
1245 # define XER_sig(context)                       REG_sig(xer, context) /* User's integer exception register */
1246 # define LR_sig(context)                        REG_sig(link, context) /* Link register */
1247 # define CR_sig(context)                        REG_sig(ccr, context) /* Condition register */
1248 /* Float Registers access  */
1249 # define FLOAT_sig(reg_num, context)            (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
1250 # define FPSCR_sig(context)                     (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
1251 /* Exception Registers access */
1252 # define DAR_sig(context)                       REG_sig(dar, context)
1253 # define DSISR_sig(context)                     REG_sig(dsisr, context)
1254 # define TRAP_sig(context)                      REG_sig(trap, context)
1255 #endif /* linux */
1256
1257 #ifdef __APPLE__
1258 # include <sys/ucontext.h>
1259 typedef struct ucontext SIGCONTEXT;
1260 /* All Registers access - only for local access */
1261 # define REG_sig(reg_name, context)             ((context)->uc_mcontext->ss.reg_name)
1262 # define FLOATREG_sig(reg_name, context)        ((context)->uc_mcontext->fs.reg_name)
1263 # define EXCEPREG_sig(reg_name, context)        ((context)->uc_mcontext->es.reg_name)
1264 # define VECREG_sig(reg_name, context)          ((context)->uc_mcontext->vs.reg_name)
1265 /* Gpr Registers access */
1266 # define GPR_sig(reg_num, context)              REG_sig(r##reg_num, context)
1267 # define IAR_sig(context)                       REG_sig(srr0, context)  /* Program counter */
1268 # define MSR_sig(context)                       REG_sig(srr1, context)  /* Machine State Register (Supervisor) */
1269 # define CTR_sig(context)                       REG_sig(ctr, context)
1270 # define XER_sig(context)                       REG_sig(xer, context) /* Link register */
1271 # define LR_sig(context)                        REG_sig(lr, context)  /* User's integer exception register */
1272 # define CR_sig(context)                        REG_sig(cr, context)  /* Condition register */
1273 /* Float Registers access */
1274 # define FLOAT_sig(reg_num, context)            FLOATREG_sig(fpregs[reg_num], context)
1275 # define FPSCR_sig(context)                     ((double)FLOATREG_sig(fpscr, context))
1276 /* Exception Registers access */
1277 # define DAR_sig(context)                       EXCEPREG_sig(dar, context)     /* Fault registers for coredump */
1278 # define DSISR_sig(context)                     EXCEPREG_sig(dsisr, context)
1279 # define TRAP_sig(context)                      EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
1280 #endif /* __APPLE__ */
1281
1282 int cpu_signal_handler(int host_signum, void *pinfo,
1283                        void *puc)
1284 {
1285     siginfo_t *info = pinfo;
1286     struct ucontext *uc = puc;
1287     unsigned long pc;
1288     int is_write;
1289
1290     pc = IAR_sig(uc);
1291     is_write = 0;
1292 #if 0
1293     /* ppc 4xx case */
1294     if (DSISR_sig(uc) & 0x00800000)
1295         is_write = 1;
1296 #else
1297     if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
1298         is_write = 1;
1299 #endif
1300     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1301                              is_write, &uc->uc_sigmask, puc);
1302 }
1303
1304 #elif defined(__alpha__)
1305
1306 int cpu_signal_handler(int host_signum, void *pinfo,
1307                            void *puc)
1308 {
1309     siginfo_t *info = pinfo;
1310     struct ucontext *uc = puc;
1311     uint32_t *pc = uc->uc_mcontext.sc_pc;
1312     uint32_t insn = *pc;
1313     int is_write = 0;
1314
1315     /* XXX: need kernel patch to get write flag faster */
1316     switch (insn >> 26) {
1317     case 0x0d: // stw
1318     case 0x0e: // stb
1319     case 0x0f: // stq_u
1320     case 0x24: // stf
1321     case 0x25: // stg
1322     case 0x26: // sts
1323     case 0x27: // stt
1324     case 0x2c: // stl
1325     case 0x2d: // stq
1326     case 0x2e: // stl_c
1327     case 0x2f: // stq_c
1328         is_write = 1;
1329     }
1330
1331     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1332                              is_write, &uc->uc_sigmask, puc);
1333 }
1334 #elif defined(__sparc__)
1335
1336 int cpu_signal_handler(int host_signum, void *pinfo,
1337                        void *puc)
1338 {
1339     siginfo_t *info = pinfo;
1340     int is_write;
1341     uint32_t insn;
1342 #if !defined(__arch64__) || defined(HOST_SOLARIS)
1343     uint32_t *regs = (uint32_t *)(info + 1);
1344     void *sigmask = (regs + 20);
1345     /* XXX: is there a standard glibc define ? */
1346     unsigned long pc = regs[1];
1347 #else
1348 #ifdef __linux__
1349     struct sigcontext *sc = puc;
1350     unsigned long pc = sc->sigc_regs.tpc;
1351     void *sigmask = (void *)sc->sigc_mask;
1352 #elif defined(__OpenBSD__)
1353     struct sigcontext *uc = puc;
1354     unsigned long pc = uc->sc_pc;
1355     void *sigmask = (void *)(long)uc->sc_mask;
1356 #endif
1357 #endif
1358
1359     /* XXX: need kernel patch to get write flag faster */
1360     is_write = 0;
1361     insn = *(uint32_t *)pc;
1362     if ((insn >> 30) == 3) {
1363       switch((insn >> 19) & 0x3f) {
1364       case 0x05: // stb
1365       case 0x06: // sth
1366       case 0x04: // st
1367       case 0x07: // std
1368       case 0x24: // stf
1369       case 0x27: // stdf
1370       case 0x25: // stfsr
1371         is_write = 1;
1372         break;
1373       }
1374     }
1375     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1376                              is_write, sigmask, NULL);
1377 }
1378
1379 #elif defined(__arm__)
1380
1381 int cpu_signal_handler(int host_signum, void *pinfo,
1382                        void *puc)
1383 {
1384     siginfo_t *info = pinfo;
1385     struct ucontext *uc = puc;
1386     unsigned long pc;
1387     int is_write;
1388
1389 #if (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3))
1390     pc = uc->uc_mcontext.gregs[R15];
1391 #else
1392     pc = uc->uc_mcontext.arm_pc;
1393 #endif
1394     /* XXX: compute is_write */
1395     is_write = 0;
1396     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1397                              is_write,
1398                              &uc->uc_sigmask, puc);
1399 }
1400
1401 #elif defined(__mc68000)
1402
1403 int cpu_signal_handler(int host_signum, void *pinfo,
1404                        void *puc)
1405 {
1406     siginfo_t *info = pinfo;
1407     struct ucontext *uc = puc;
1408     unsigned long pc;
1409     int is_write;
1410
1411     pc = uc->uc_mcontext.gregs[16];
1412     /* XXX: compute is_write */
1413     is_write = 0;
1414     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1415                              is_write,
1416                              &uc->uc_sigmask, puc);
1417 }
1418
1419 #elif defined(__ia64)
1420
1421 #ifndef __ISR_VALID
1422   /* This ought to be in <bits/siginfo.h>... */
1423 # define __ISR_VALID    1
1424 #endif
1425
1426 int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
1427 {
1428     siginfo_t *info = pinfo;
1429     struct ucontext *uc = puc;
1430     unsigned long ip;
1431     int is_write = 0;
1432
1433     ip = uc->uc_mcontext.sc_ip;
1434     switch (host_signum) {
1435       case SIGILL:
1436       case SIGFPE:
1437       case SIGSEGV:
1438       case SIGBUS:
1439       case SIGTRAP:
1440           if (info->si_code && (info->si_segvflags & __ISR_VALID))
1441               /* ISR.W (write-access) is bit 33:  */
1442               is_write = (info->si_isr >> 33) & 1;
1443           break;
1444
1445       default:
1446           break;
1447     }
1448     return handle_cpu_signal(ip, (unsigned long)info->si_addr,
1449                              is_write,
1450                              &uc->uc_sigmask, puc);
1451 }
1452
1453 #elif defined(__s390__)
1454
1455 int cpu_signal_handler(int host_signum, void *pinfo,
1456                        void *puc)
1457 {
1458     siginfo_t *info = pinfo;
1459     struct ucontext *uc = puc;
1460     unsigned long pc;
1461     int is_write;
1462
1463     pc = uc->uc_mcontext.psw.addr;
1464     /* XXX: compute is_write */
1465     is_write = 0;
1466     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1467                              is_write, &uc->uc_sigmask, puc);
1468 }
1469
1470 #elif defined(__mips__)
1471
1472 int cpu_signal_handler(int host_signum, void *pinfo,
1473                        void *puc)
1474 {
1475     siginfo_t *info = pinfo;
1476     struct ucontext *uc = puc;
1477     greg_t pc = uc->uc_mcontext.pc;
1478     int is_write;
1479
1480     /* XXX: compute is_write */
1481     is_write = 0;
1482     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1483                              is_write, &uc->uc_sigmask, puc);
1484 }
1485
1486 #elif defined(__hppa__)
1487
1488 int cpu_signal_handler(int host_signum, void *pinfo,
1489                        void *puc)
1490 {
1491     struct siginfo *info = pinfo;
1492     struct ucontext *uc = puc;
1493     unsigned long pc;
1494     int is_write;
1495
1496     pc = uc->uc_mcontext.sc_iaoq[0];
1497     /* FIXME: compute is_write */
1498     is_write = 0;
1499     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1500                              is_write,
1501                              &uc->uc_sigmask, puc);
1502 }
1503
1504 #else
1505
1506 #error host CPU specific signal handler needed
1507
1508 #endif
1509
1510 #endif /* !defined(CONFIG_SOFTMMU) */