hw/apic.c

   1 /*
   2  *  APIC support
   3  *
   4  *  Copyright (c) 2004-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  18  */
  19 #include "hw.h"
  20 #include "pc.h"
  21 #include "pci.h"
  22 #include "msix.h"
  23 #include "qemu-timer.h"
  24 #include "host-utils.h"
  25 #include "kvm.h"
  26
  27 #include "qemu-kvm.h"
  28
  29 //#define DEBUG_APIC
  30
  31 /* APIC Local Vector Table */
  32 #define APIC_LVT_TIMER   0
  33 #define APIC_LVT_THERMAL 1
  34 #define APIC_LVT_PERFORM 2
  35 #define APIC_LVT_LINT0   3
  36 #define APIC_LVT_LINT1   4
  37 #define APIC_LVT_ERROR   5
  38 #define APIC_LVT_NB      6
  39
  40 /* APIC delivery modes */
  41 #define APIC_DM_FIXED   0
  42 #define APIC_DM_LOWPRI  1
  43 #define APIC_DM_SMI     2
  44 #define APIC_DM_NMI     4
  45 #define APIC_DM_INIT    5
  46 #define APIC_DM_SIPI    6
  47 #define APIC_DM_EXTINT  7
  48
  49 /* APIC destination mode */
  50 #define APIC_DESTMODE_FLAT      0xf
  51 #define APIC_DESTMODE_CLUSTER   1
  52
  53 #define APIC_TRIGGER_EDGE  0
  54 #define APIC_TRIGGER_LEVEL 1
  55
  56 #define APIC_LVT_TIMER_PERIODIC         (1<<17)
  57 #define APIC_LVT_MASKED                 (1<<16)
  58 #define APIC_LVT_LEVEL_TRIGGER          (1<<15)
  59 #define APIC_LVT_REMOTE_IRR             (1<<14)
  60 #define APIC_INPUT_POLARITY             (1<<13)
  61 #define APIC_SEND_PENDING               (1<<12)
  62
  63 #define ESR_ILLEGAL_ADDRESS (1 << 7)
  64
  65 #define APIC_SV_ENABLE (1 << 8)
  66
  67 #define MAX_APICS 255
  68 #define MAX_APIC_WORDS 8
  69
  70 /* Intel APIC constants: from include/asm/msidef.h */
  71 #define MSI_DATA_VECTOR_SHIFT           0
  72 #define MSI_DATA_VECTOR_MASK            0x000000ff
  73 #define MSI_DATA_DELIVERY_MODE_SHIFT    8
  74 #define MSI_DATA_TRIGGER_SHIFT          15
  75 #define MSI_DATA_LEVEL_SHIFT            14
  76 #define MSI_ADDR_DEST_MODE_SHIFT        2
  77 #define MSI_ADDR_DEST_ID_SHIFT          12
  78 #define MSI_ADDR_DEST_ID_MASK           0x00ffff0
  79
  80 #define MSI_ADDR_BASE                   0xfee00000
  81 #define MSI_ADDR_SIZE                   0x100000
  82
  83 typedef struct APICState {
  84     CPUState *cpu_env;
  85     uint32_t apicbase;
  86     uint8_t id;
  87     uint8_t arb_id;
  88     uint8_t tpr;
  89     uint32_t spurious_vec;
  90     uint8_t log_dest;
  91     uint8_t dest_mode;
  92     uint32_t isr[8];  /* in service register */
  93     uint32_t tmr[8];  /* trigger mode register */
  94     uint32_t irr[8]; /* interrupt request register */
  95     uint32_t lvt[APIC_LVT_NB];
  96     uint32_t esr; /* error register */
  97     uint32_t icr[2];
  98
  99     uint32_t divide_conf;
 100     int count_shift;
 101     uint32_t initial_count;
 102     int64_t initial_count_load_time, next_time;
 103     uint32_t idx;
 104     QEMUTimer *timer;
 105     int sipi_vector;
 106     int wait_for_sipi;
 107 } APICState;
 108
 109 static int apic_io_memory;
 110 static APICState *local_apics[MAX_APICS + 1];
 111 static int last_apic_idx = 0;
 112 static int apic_irq_delivered;
 113
 114
 115 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode);
 116 static void apic_update_irq(APICState *s);
 117 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
 118                                       uint8_t dest, uint8_t dest_mode);
 119
 120 /* Find first bit starting from msb */
 121 static int fls_bit(uint32_t value)
 122 {
 123     return 31 - clz32(value);
 124 }
 125
 126 /* Find first bit starting from lsb */
 127 static int ffs_bit(uint32_t value)
 128 {
 129     return ctz32(value);
 130 }
 131
 132 static inline void set_bit(uint32_t *tab, int index)
 133 {
 134     int i, mask;
 135     i = index >> 5;
 136     mask = 1 << (index & 0x1f);
 137     tab[i] |= mask;
 138 }
 139
 140 static inline void reset_bit(uint32_t *tab, int index)
 141 {
 142     int i, mask;
 143     i = index >> 5;
 144     mask = 1 << (index & 0x1f);
 145     tab[i] &= ~mask;
 146 }
 147
 148 static inline int get_bit(uint32_t *tab, int index)
 149 {
 150     int i, mask;
 151     i = index >> 5;
 152     mask = 1 << (index & 0x1f);
 153     return !!(tab[i] & mask);
 154 }
 155
 156 static void apic_local_deliver(CPUState *env, int vector)
 157 {
 158     APICState *s = env->apic_state;
 159     uint32_t lvt = s->lvt[vector];
 160     int trigger_mode;
 161
 162     if (lvt & APIC_LVT_MASKED)
 163         return;
 164
 165     switch ((lvt >> 8) & 7) {
 166     case APIC_DM_SMI:
 167         cpu_interrupt(env, CPU_INTERRUPT_SMI);
 168         break;
 169
 170     case APIC_DM_NMI:
 171         cpu_interrupt(env, CPU_INTERRUPT_NMI);
 172         break;
 173
 174     case APIC_DM_EXTINT:
 175         cpu_interrupt(env, CPU_INTERRUPT_HARD);
 176         break;
 177
 178     case APIC_DM_FIXED:
 179         trigger_mode = APIC_TRIGGER_EDGE;
 180         if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) &&
 181             (lvt & APIC_LVT_LEVEL_TRIGGER))
 182             trigger_mode = APIC_TRIGGER_LEVEL;
 183         apic_set_irq(s, lvt & 0xff, trigger_mode);
 184     }
 185 }
 186
 187 void apic_deliver_pic_intr(CPUState *env, int level)
 188 {
 189     if (level)
 190         apic_local_deliver(env, APIC_LVT_LINT0);
 191     else {
 192         APICState *s = env->apic_state;
 193         uint32_t lvt = s->lvt[APIC_LVT_LINT0];
 194
 195         switch ((lvt >> 8) & 7) {
 196         case APIC_DM_FIXED:
 197             if (!(lvt & APIC_LVT_LEVEL_TRIGGER))
 198                 break;
 199             reset_bit(s->irr, lvt & 0xff);
 200             /* fall through */
 201         case APIC_DM_EXTINT:
 202             cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 203             break;
 204         }
 205     }
 206 }
 207
 208 #define foreach_apic(apic, deliver_bitmask, code) \
 209 {\
 210     int __i, __j, __mask;\
 211     for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\
 212         __mask = deliver_bitmask[__i];\
 213         if (__mask) {\
 214             for(__j = 0; __j < 32; __j++) {\
 215                 if (__mask & (1 << __j)) {\
 216                     apic = local_apics[__i * 32 + __j];\
 217                     if (apic) {\
 218                         code;\
 219                     }\
 220                 }\
 221             }\
 222         }\
 223     }\
 224 }
 225
 226 static void apic_bus_deliver(const uint32_t *deliver_bitmask,
 227                              uint8_t delivery_mode,
 228                              uint8_t vector_num, uint8_t polarity,
 229                              uint8_t trigger_mode)
 230 {
 231     APICState *apic_iter;
 232
 233     switch (delivery_mode) {
 234         case APIC_DM_LOWPRI:
 235             /* XXX: search for focus processor, arbitration */
 236             {
 237                 int i, d;
 238                 d = -1;
 239                 for(i = 0; i < MAX_APIC_WORDS; i++) {
 240                     if (deliver_bitmask[i]) {
 241                         d = i * 32 + ffs_bit(deliver_bitmask[i]);
 242                         break;
 243                     }
 244                 }
 245                 if (d >= 0) {
 246                     apic_iter = local_apics[d];
 247                     if (apic_iter) {
 248                         apic_set_irq(apic_iter, vector_num, trigger_mode);
 249                     }
 250                 }
 251             }
 252             return;
 253
 254         case APIC_DM_FIXED:
 255             break;
 256
 257         case APIC_DM_SMI:
 258             foreach_apic(apic_iter, deliver_bitmask,
 259                 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_SMI) );
 260             return;
 261
 262         case APIC_DM_NMI:
 263             foreach_apic(apic_iter, deliver_bitmask,
 264                 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_NMI) );
 265             return;
 266
 267         case APIC_DM_INIT:
 268             /* normal INIT IPI sent to processors */
 269             foreach_apic(apic_iter, deliver_bitmask,
 270                          cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_INIT) );
 271             return;
 272
 273         case APIC_DM_EXTINT:
 274             /* handled in I/O APIC code */
 275             break;
 276
 277         default:
 278             return;
 279     }
 280
 281     foreach_apic(apic_iter, deliver_bitmask,
 282                  apic_set_irq(apic_iter, vector_num, trigger_mode) );
 283 }
 284
 285 void apic_deliver_irq(uint8_t dest, uint8_t dest_mode,
 286                       uint8_t delivery_mode, uint8_t vector_num,
 287                       uint8_t polarity, uint8_t trigger_mode)
 288 {
 289     uint32_t deliver_bitmask[MAX_APIC_WORDS];
 290
 291     apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
 292     apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
 293                      trigger_mode);
 294 }
 295
 296 void cpu_set_apic_base(CPUState *env, uint64_t val)
 297 {
 298     APICState *s = env->apic_state;
 299 #ifdef DEBUG_APIC
 300     printf("cpu_set_apic_base: %016" PRIx64 "\n", val);
 301 #endif
 302     if (!s)
 303         return;
 304     if (kvm_enabled() && qemu_kvm_irqchip_in_kernel())
 305         s->apicbase = val;
 306     else
 307         s->apicbase = (val & 0xfffff000) |
 308             (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE));
 309     /* if disabled, cannot be enabled again */
 310     if (!(val & MSR_IA32_APICBASE_ENABLE)) {
 311         s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
 312         env->cpuid_features &= ~CPUID_APIC;
 313         s->spurious_vec &= ~APIC_SV_ENABLE;
 314     }
 315 }
 316
 317 uint64_t cpu_get_apic_base(CPUState *env)
 318 {
 319     APICState *s = env->apic_state;
 320 #ifdef DEBUG_APIC
 321     printf("cpu_get_apic_base: %016" PRIx64 "\n",
 322            s ? (uint64_t)s->apicbase: 0);
 323 #endif
 324     return s ? s->apicbase : 0;
 325 }
 326
 327 void cpu_set_apic_tpr(CPUX86State *env, uint8_t val)
 328 {
 329     APICState *s = env->apic_state;
 330     if (!s)
 331         return;
 332     s->tpr = (val & 0x0f) << 4;
 333     apic_update_irq(s);
 334 }
 335
 336 uint8_t cpu_get_apic_tpr(CPUX86State *env)
 337 {
 338     APICState *s = env->apic_state;
 339     return s ? s->tpr >> 4 : 0;
 340 }
 341
 342 /* return -1 if no bit is set */
 343 static int get_highest_priority_int(uint32_t *tab)
 344 {
 345     int i;
 346     for(i = 7; i >= 0; i--) {
 347         if (tab[i] != 0) {
 348             return i * 32 + fls_bit(tab[i]);
 349         }
 350     }
 351     return -1;
 352 }
 353
 354 static int apic_get_ppr(APICState *s)
 355 {
 356     int tpr, isrv, ppr;
 357
 358     tpr = (s->tpr >> 4);
 359     isrv = get_highest_priority_int(s->isr);
 360     if (isrv < 0)
 361         isrv = 0;
 362     isrv >>= 4;
 363     if (tpr >= isrv)
 364         ppr = s->tpr;
 365     else
 366         ppr = isrv << 4;
 367     return ppr;
 368 }
 369
 370 static int apic_get_arb_pri(APICState *s)
 371 {
 372     /* XXX: arbitration */
 373     return 0;
 374 }
 375
 376 /* signal the CPU if an irq is pending */
 377 static void apic_update_irq(APICState *s)
 378 {
 379     int irrv, ppr;
 380     if (!(s->spurious_vec & APIC_SV_ENABLE))
 381         return;
 382     irrv = get_highest_priority_int(s->irr);
 383     if (irrv < 0)
 384         return;
 385     ppr = apic_get_ppr(s);
 386     if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
 387         return;
 388     cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
 389 }
 390
 391 void apic_reset_irq_delivered(void)
 392 {
 393     apic_irq_delivered = 0;
 394 }
 395
 396 int apic_get_irq_delivered(void)
 397 {
 398     return apic_irq_delivered;
 399 }
 400
 401 void apic_set_irq_delivered(void)
 402 {
 403     apic_irq_delivered = 1;
 404 }
 405
 406 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode)
 407 {
 408     apic_irq_delivered += !get_bit(s->irr, vector_num);
 409
 410     set_bit(s->irr, vector_num);
 411     if (trigger_mode)
 412         set_bit(s->tmr, vector_num);
 413     else
 414         reset_bit(s->tmr, vector_num);
 415     apic_update_irq(s);
 416 }
 417
 418 static void apic_eoi(APICState *s)
 419 {
 420     int isrv;
 421     isrv = get_highest_priority_int(s->isr);
 422     if (isrv < 0)
 423         return;
 424     reset_bit(s->isr, isrv);
 425     /* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to
 426             set the remote IRR bit for level triggered interrupts. */
 427     apic_update_irq(s);
 428 }
 429
 430 static int apic_find_dest(uint8_t dest)
 431 {
 432     APICState *apic = local_apics[dest];
 433     int i;
 434
 435     if (apic && apic->id == dest)
 436         return dest;  /* shortcut in case apic->id == apic->idx */
 437
 438     for (i = 0; i < MAX_APICS; i++) {
 439         apic = local_apics[i];
 440         if (apic && apic->id == dest)
 441             return i;
 442     }
 443
 444     return -1;
 445 }
 446
 447 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
 448                                       uint8_t dest, uint8_t dest_mode)
 449 {
 450     APICState *apic_iter;
 451     int i;
 452
 453     if (dest_mode == 0) {
 454         if (dest == 0xff) {
 455             memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t));
 456         } else {
 457             int idx = apic_find_dest(dest);
 458             memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
 459             if (idx >= 0)
 460                 set_bit(deliver_bitmask, idx);
 461         }
 462     } else {
 463         /* XXX: cluster mode */
 464         memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
 465         for(i = 0; i < MAX_APICS; i++) {
 466             apic_iter = local_apics[i];
 467             if (apic_iter) {
 468                 if (apic_iter->dest_mode == 0xf) {
 469                     if (dest & apic_iter->log_dest)
 470                         set_bit(deliver_bitmask, i);
 471                 } else if (apic_iter->dest_mode == 0x0) {
 472                     if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) &&
 473                         (dest & apic_iter->log_dest & 0x0f)) {
 474                         set_bit(deliver_bitmask, i);
 475                     }
 476                 }
 477             }
 478         }
 479     }
 480 }
 481
 482
 483 void apic_init_reset(CPUState *env)
 484 {
 485     APICState *s = env->apic_state;
 486     int i;
 487
 488     if (!s)
 489         return;
 490
 491     s->tpr = 0;
 492     s->spurious_vec = 0xff;
 493     s->log_dest = 0;
 494     s->dest_mode = 0xf;
 495     memset(s->isr, 0, sizeof(s->isr));
 496     memset(s->tmr, 0, sizeof(s->tmr));
 497     memset(s->irr, 0, sizeof(s->irr));
 498     for(i = 0; i < APIC_LVT_NB; i++)
 499         s->lvt[i] = 1 << 16; /* mask LVT */
 500     s->esr = 0;
 501     memset(s->icr, 0, sizeof(s->icr));
 502     s->divide_conf = 0;
 503     s->count_shift = 0;
 504     s->initial_count = 0;
 505     s->initial_count_load_time = 0;
 506     s->next_time = 0;
 507     s->wait_for_sipi = 1;
 508
 509     env->halted = !(s->apicbase & MSR_IA32_APICBASE_BSP);
 510 }
 511
 512 static void apic_startup(APICState *s, int vector_num)
 513 {
 514     s->sipi_vector = vector_num;
 515     cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI);
 516 }
 517
 518 void apic_sipi(CPUState *env)
 519 {
 520     APICState *s = env->apic_state;
 521
 522     cpu_reset_interrupt(env, CPU_INTERRUPT_SIPI);
 523
 524     if (!s->wait_for_sipi)
 525         return;
 526
 527     env->eip = 0;
 528     cpu_x86_load_seg_cache(env, R_CS, s->sipi_vector << 8, s->sipi_vector << 12,
 529                            0xffff, 0);
 530     env->halted = 0;
 531     s->wait_for_sipi = 0;
 532 }
 533
 534 static void apic_deliver(APICState *s, uint8_t dest, uint8_t dest_mode,
 535                          uint8_t delivery_mode, uint8_t vector_num,
 536                          uint8_t polarity, uint8_t trigger_mode)
 537 {
 538     uint32_t deliver_bitmask[MAX_APIC_WORDS];
 539     int dest_shorthand = (s->icr[0] >> 18) & 3;
 540     APICState *apic_iter;
 541
 542     switch (dest_shorthand) {
 543     case 0:
 544         apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
 545         break;
 546     case 1:
 547         memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask));
 548         set_bit(deliver_bitmask, s->idx);
 549         break;
 550     case 2:
 551         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
 552         break;
 553     case 3:
 554         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
 555         reset_bit(deliver_bitmask, s->idx);
 556         break;
 557     }
 558
 559     switch (delivery_mode) {
 560         case APIC_DM_INIT:
 561             {
 562                 int trig_mode = (s->icr[0] >> 15) & 1;
 563                 int level = (s->icr[0] >> 14) & 1;
 564                 if (level == 0 && trig_mode == 1) {
 565                     foreach_apic(apic_iter, deliver_bitmask,
 566                                  apic_iter->arb_id = apic_iter->id );
 567                     return;
 568                 }
 569             }
 570             break;
 571
 572         case APIC_DM_SIPI:
 573             foreach_apic(apic_iter, deliver_bitmask,
 574                          apic_startup(apic_iter, vector_num) );
 575             return;
 576     }
 577
 578     apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
 579                      trigger_mode);
 580 }
 581
 582 int apic_get_interrupt(CPUState *env)
 583 {
 584     APICState *s = env->apic_state;
 585     int intno;
 586
 587     /* if the APIC is installed or enabled, we let the 8259 handle the
 588        IRQs */
 589     if (!s)
 590         return -1;
 591     if (!(s->spurious_vec & APIC_SV_ENABLE))
 592         return -1;
 593
 594     /* XXX: spurious IRQ handling */
 595     intno = get_highest_priority_int(s->irr);
 596     if (intno < 0)
 597         return -1;
 598     if (s->tpr && intno <= s->tpr)
 599         return s->spurious_vec & 0xff;
 600     reset_bit(s->irr, intno);
 601     set_bit(s->isr, intno);
 602     apic_update_irq(s);
 603     return intno;
 604 }
 605
 606 int apic_accept_pic_intr(CPUState *env)
 607 {
 608     APICState *s = env->apic_state;
 609     uint32_t lvt0;
 610
 611     if (!s)
 612         return -1;
 613
 614     lvt0 = s->lvt[APIC_LVT_LINT0];
 615
 616     if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 ||
 617         (lvt0 & APIC_LVT_MASKED) == 0)
 618         return 1;
 619
 620     return 0;
 621 }
 622
 623 static uint32_t apic_get_current_count(APICState *s)
 624 {
 625     int64_t d;
 626     uint32_t val;
 627     d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >>
 628         s->count_shift;
 629     if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
 630         /* periodic */
 631         val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
 632     } else {
 633         if (d >= s->initial_count)
 634             val = 0;
 635         else
 636             val = s->initial_count - d;
 637     }
 638     return val;
 639 }
 640
 641 static void apic_timer_update(APICState *s, int64_t current_time)
 642 {
 643     int64_t next_time, d;
 644
 645     if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
 646         d = (current_time - s->initial_count_load_time) >>
 647             s->count_shift;
 648         if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
 649             if (!s->initial_count)
 650                 goto no_timer;
 651             d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1);
 652         } else {
 653             if (d >= s->initial_count)
 654                 goto no_timer;
 655             d = (uint64_t)s->initial_count + 1;
 656         }
 657         next_time = s->initial_count_load_time + (d << s->count_shift);
 658         qemu_mod_timer(s->timer, next_time);
 659         s->next_time = next_time;
 660     } else {
 661     no_timer:
 662         qemu_del_timer(s->timer);
 663     }
 664 }
 665
 666 static void apic_timer(void *opaque)
 667 {
 668     APICState *s = opaque;
 669
 670     apic_local_deliver(s->cpu_env, APIC_LVT_TIMER);
 671     apic_timer_update(s, s->next_time);
 672 }
 673
 674 static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr)
 675 {
 676     return 0;
 677 }
 678
 679 static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr)
 680 {
 681     return 0;
 682 }
 683
 684 static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
 685 {
 686 }
 687
 688 static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
 689 {
 690 }
 691
 692 static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
 693 {
 694     CPUState *env;
 695     APICState *s;
 696     uint32_t val;
 697     int index;
 698
 699     env = cpu_single_env;
 700     if (!env)
 701         return 0;
 702     s = env->apic_state;
 703
 704     index = (addr >> 4) & 0xff;
 705     switch(index) {
 706     case 0x02: /* id */
 707         val = s->id << 24;
 708         break;
 709     case 0x03: /* version */
 710         val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */
 711         break;
 712     case 0x08:
 713         val = s->tpr;
 714         break;
 715     case 0x09:
 716         val = apic_get_arb_pri(s);
 717         break;
 718     case 0x0a:
 719         /* ppr */
 720         val = apic_get_ppr(s);
 721         break;
 722     case 0x0b:
 723         val = 0;
 724         break;
 725     case 0x0d:
 726         val = s->log_dest << 24;
 727         break;
 728     case 0x0e:
 729         val = s->dest_mode << 28;
 730         break;
 731     case 0x0f:
 732         val = s->spurious_vec;
 733         break;
 734     case 0x10 ... 0x17:
 735         val = s->isr[index & 7];
 736         break;
 737     case 0x18 ... 0x1f:
 738         val = s->tmr[index & 7];
 739         break;
 740     case 0x20 ... 0x27:
 741         val = s->irr[index & 7];
 742         break;
 743     case 0x28:
 744         val = s->esr;
 745         break;
 746     case 0x30:
 747     case 0x31:
 748         val = s->icr[index & 1];
 749         break;
 750     case 0x32 ... 0x37:
 751         val = s->lvt[index - 0x32];
 752         break;
 753     case 0x38:
 754         val = s->initial_count;
 755         break;
 756     case 0x39:
 757         val = apic_get_current_count(s);
 758         break;
 759     case 0x3e:
 760         val = s->divide_conf;
 761         break;
 762     default:
 763         s->esr |= ESR_ILLEGAL_ADDRESS;
 764         val = 0;
 765         break;
 766     }
 767 #ifdef DEBUG_APIC
 768     printf("APIC read: %08x = %08x\n", (uint32_t)addr, val);
 769 #endif
 770     return val;
 771 }
 772
 773 static void apic_send_msi(target_phys_addr_t addr, uint32 data)
 774 {
 775     uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT;
 776     uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT;
 777     uint8_t dest_mode = (addr >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1;
 778     uint8_t trigger_mode = (data >> MSI_DATA_TRIGGER_SHIFT) & 0x1;
 779     uint8_t delivery = (data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7;
 780     /* XXX: Ignore redirection hint. */
 781     apic_deliver_irq(dest, dest_mode, delivery, vector, 0, trigger_mode);
 782 }
 783
 784 static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 785 {
 786     CPUState *env;
 787     APICState *s;
 788     int index = (addr >> 4) & 0xff;
 789     if (addr > 0xfff || !index) {
 790         /* MSI and MMIO APIC are at the same memory location,
 791          * but actually not on the global bus: MSI is on PCI bus
 792          * APIC is connected directly to the CPU.
 793          * Mapping them on the global bus happens to work because
 794          * MSI registers are reserved in APIC MMIO and vice versa. */
 795         apic_send_msi(addr, val);
 796         return;
 797     }
 798
 799     env = cpu_single_env;
 800     if (!env)
 801         return;
 802     s = env->apic_state;
 803
 804 #ifdef DEBUG_APIC
 805     printf("APIC write: %08x = %08x\n", (uint32_t)addr, val);
 806 #endif
 807
 808     switch(index) {
 809     case 0x02:
 810         s->id = (val >> 24);
 811         break;
 812     case 0x03:
 813         break;
 814     case 0x08:
 815         s->tpr = val;
 816         apic_update_irq(s);
 817         break;
 818     case 0x09:
 819     case 0x0a:
 820         break;
 821     case 0x0b: /* EOI */
 822         apic_eoi(s);
 823         break;
 824     case 0x0d:
 825         s->log_dest = val >> 24;
 826         break;
 827     case 0x0e:
 828         s->dest_mode = val >> 28;
 829         break;
 830     case 0x0f:
 831         s->spurious_vec = val & 0x1ff;
 832         apic_update_irq(s);
 833         break;
 834     case 0x10 ... 0x17:
 835     case 0x18 ... 0x1f:
 836     case 0x20 ... 0x27:
 837     case 0x28:
 838         break;
 839     case 0x30:
 840         s->icr[0] = val;
 841         apic_deliver(s, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1,
 842                      (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),
 843                      (s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1);
 844         break;
 845     case 0x31:
 846         s->icr[1] = val;
 847         break;
 848     case 0x32 ... 0x37:
 849         {
 850             int n = index - 0x32;
 851             s->lvt[n] = val;
 852             if (n == APIC_LVT_TIMER)
 853                 apic_timer_update(s, qemu_get_clock(vm_clock));
 854         }
 855         break;
 856     case 0x38:
 857         s->initial_count = val;
 858         s->initial_count_load_time = qemu_get_clock(vm_clock);
 859         apic_timer_update(s, s->initial_count_load_time);
 860         break;
 861     case 0x39:
 862         break;
 863     case 0x3e:
 864         {
 865             int v;
 866             s->divide_conf = val & 0xb;
 867             v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
 868             s->count_shift = (v + 1) & 7;
 869         }
 870         break;
 871     default:
 872         s->esr |= ESR_ILLEGAL_ADDRESS;
 873         break;
 874     }
 875 }
 876
 877 #ifdef KVM_CAP_IRQCHIP
 878
 879 static inline uint32_t kapic_reg(struct kvm_lapic_state *kapic, int reg_id)
 880 {
 881     return *((uint32_t *) (kapic->regs + (reg_id << 4)));
 882 }
 883
 884 static inline void kapic_set_reg(struct kvm_lapic_state *kapic,
 885                                  int reg_id, uint32_t val)
 886 {
 887     *((uint32_t *) (kapic->regs + (reg_id << 4))) = val;
 888 }
 889
 890 static void kvm_kernel_lapic_save_to_user(APICState *s)
 891 {
 892     struct kvm_lapic_state apic;
 893     struct kvm_lapic_state *kapic = &apic;
 894     int i, v;
 895
 896     kvm_get_lapic(s->cpu_env->kvm_cpu_state.vcpu_ctx, kapic);
 897
 898     s->id = kapic_reg(kapic, 0x2) >> 24;
 899     s->tpr = kapic_reg(kapic, 0x8);
 900     s->arb_id = kapic_reg(kapic, 0x9);
 901     s->log_dest = kapic_reg(kapic, 0xd) >> 24;
 902     s->dest_mode = kapic_reg(kapic, 0xe) >> 28;
 903     s->spurious_vec = kapic_reg(kapic, 0xf);
 904     for (i = 0; i < 8; i++) {
 905         s->isr[i] = kapic_reg(kapic, 0x10 + i);
 906         s->tmr[i] = kapic_reg(kapic, 0x18 + i);
 907         s->irr[i] = kapic_reg(kapic, 0x20 + i);
 908     }
 909     s->esr = kapic_reg(kapic, 0x28);
 910     s->icr[0] = kapic_reg(kapic, 0x30);
 911     s->icr[1] = kapic_reg(kapic, 0x31);
 912     for (i = 0; i < APIC_LVT_NB; i++)
 913         s->lvt[i] = kapic_reg(kapic, 0x32 + i);
 914     s->initial_count = kapic_reg(kapic, 0x38);
 915     s->divide_conf = kapic_reg(kapic, 0x3e);
 916
 917     v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
 918     s->count_shift = (v + 1) & 7;
 919
 920     s->initial_count_load_time = qemu_get_clock(vm_clock);
 921     apic_timer_update(s, s->initial_count_load_time);
 922 }
 923
 924 static void kvm_kernel_lapic_load_from_user(APICState *s)
 925 {
 926     struct kvm_lapic_state apic;
 927     struct kvm_lapic_state *klapic = &apic;
 928     int i;
 929
 930     memset(klapic, 0, sizeof apic);
 931     kapic_set_reg(klapic, 0x2, s->id << 24);
 932     kapic_set_reg(klapic, 0x8, s->tpr);
 933     kapic_set_reg(klapic, 0xd, s->log_dest << 24);
 934     kapic_set_reg(klapic, 0xe, s->dest_mode << 28 | 0x0fffffff);
 935     kapic_set_reg(klapic, 0xf, s->spurious_vec);
 936     for (i = 0; i < 8; i++) {
 937         kapic_set_reg(klapic, 0x10 + i, s->isr[i]);
 938         kapic_set_reg(klapic, 0x18 + i, s->tmr[i]);
 939         kapic_set_reg(klapic, 0x20 + i, s->irr[i]);
 940     }
 941     kapic_set_reg(klapic, 0x28, s->esr);
 942     kapic_set_reg(klapic, 0x30, s->icr[0]);
 943     kapic_set_reg(klapic, 0x31, s->icr[1]);
 944     for (i = 0; i < APIC_LVT_NB; i++)
 945         kapic_set_reg(klapic, 0x32 + i, s->lvt[i]);
 946     kapic_set_reg(klapic, 0x38, s->initial_count);
 947     kapic_set_reg(klapic, 0x3e, s->divide_conf);
 948
 949     kvm_set_lapic(s->cpu_env->kvm_cpu_state.vcpu_ctx, klapic);
 950 }
 951
 952 #endif
 953
 954 void qemu_kvm_load_lapic(CPUState *env)
 955 {
 956 #ifdef KVM_CAP_IRQCHIP
 957     if (kvm_enabled() && kvm_vcpu_inited(env) && qemu_kvm_irqchip_in_kernel()) {
 958         kvm_kernel_lapic_load_from_user(env->apic_state);
 959     }
 960 #endif
 961 }
 962
 963 static void apic_save(QEMUFile *f, void *opaque)
 964 {
 965     APICState *s = opaque;
 966     int i;
 967
 968 #ifdef KVM_CAP_IRQCHIP
 969     if (kvm_enabled() && qemu_kvm_irqchip_in_kernel()) {
 970         kvm_kernel_lapic_save_to_user(s);
 971     }
 972 #endif
 973
 974     qemu_put_be32s(f, &s->apicbase);
 975     qemu_put_8s(f, &s->id);
 976     qemu_put_8s(f, &s->arb_id);
 977     qemu_put_8s(f, &s->tpr);
 978     qemu_put_be32s(f, &s->spurious_vec);
 979     qemu_put_8s(f, &s->log_dest);
 980     qemu_put_8s(f, &s->dest_mode);
 981     for (i = 0; i < 8; i++) {
 982         qemu_put_be32s(f, &s->isr[i]);
 983         qemu_put_be32s(f, &s->tmr[i]);
 984         qemu_put_be32s(f, &s->irr[i]);
 985     }
 986     for (i = 0; i < APIC_LVT_NB; i++) {
 987         qemu_put_be32s(f, &s->lvt[i]);
 988     }
 989     qemu_put_be32s(f, &s->esr);
 990     qemu_put_be32s(f, &s->icr[0]);
 991     qemu_put_be32s(f, &s->icr[1]);
 992     qemu_put_be32s(f, &s->divide_conf);
 993     qemu_put_be32(f, s->count_shift);
 994     qemu_put_be32s(f, &s->initial_count);
 995     qemu_put_be64(f, s->initial_count_load_time);
 996     qemu_put_be64(f, s->next_time);
 997
 998     qemu_put_timer(f, s->timer);
 999 }
1000
1001 static int apic_load(QEMUFile *f, void *opaque, int version_id)
1002 {
1003     APICState *s = opaque;
1004     int i;
1005
1006     if (version_id > 2)
1007         return -EINVAL;
1008
1009     /* XXX: what if the base changes? (registered memory regions) */
1010     qemu_get_be32s(f, &s->apicbase);
1011     qemu_get_8s(f, &s->id);
1012     qemu_get_8s(f, &s->arb_id);
1013     qemu_get_8s(f, &s->tpr);
1014     qemu_get_be32s(f, &s->spurious_vec);
1015     qemu_get_8s(f, &s->log_dest);
1016     qemu_get_8s(f, &s->dest_mode);
1017     for (i = 0; i < 8; i++) {
1018         qemu_get_be32s(f, &s->isr[i]);
1019         qemu_get_be32s(f, &s->tmr[i]);
1020         qemu_get_be32s(f, &s->irr[i]);
1021     }
1022     for (i = 0; i < APIC_LVT_NB; i++) {
1023         qemu_get_be32s(f, &s->lvt[i]);
1024     }
1025     qemu_get_be32s(f, &s->esr);
1026     qemu_get_be32s(f, &s->icr[0]);
1027     qemu_get_be32s(f, &s->icr[1]);
1028     qemu_get_be32s(f, &s->divide_conf);
1029     s->count_shift=qemu_get_be32(f);
1030     qemu_get_be32s(f, &s->initial_count);
1031     s->initial_count_load_time=qemu_get_be64(f);
1032     s->next_time=qemu_get_be64(f);
1033
1034     if (version_id >= 2)
1035         qemu_get_timer(f, s->timer);
1036
1037     qemu_kvm_load_lapic(s->cpu_env);
1038
1039     return 0;
1040 }
1041
1042 static void apic_reset(void *opaque)
1043 {
1044     APICState *s = opaque;
1045     int bsp = cpu_is_bsp(s->cpu_env);
1046
1047     s->apicbase = 0xfee00000 |
1048         (bsp ? MSR_IA32_APICBASE_BSP : 0) | MSR_IA32_APICBASE_ENABLE;
1049
1050     cpu_reset(s->cpu_env);
1051     apic_init_reset(s->cpu_env);
1052
1053     if (bsp) {
1054         /*
1055          * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization
1056          * time typically by BIOS, so PIC interrupt can be delivered to the
1057          * processor when local APIC is enabled.
1058          */
1059         s->lvt[APIC_LVT_LINT0] = 0x700;
1060     }
1061     cpu_synchronize_state(s->cpu_env, 1);
1062     qemu_kvm_load_lapic(s->cpu_env);
1063 }
1064
1065 static CPUReadMemoryFunc *apic_mem_read[3] = {
1066     apic_mem_readb,
1067     apic_mem_readw,
1068     apic_mem_readl,
1069 };
1070
1071 static CPUWriteMemoryFunc *apic_mem_write[3] = {
1072     apic_mem_writeb,
1073     apic_mem_writew,
1074     apic_mem_writel,
1075 };
1076
1077 int apic_init(CPUState *env)
1078 {
1079     APICState *s;
1080
1081     if (last_apic_idx >= MAX_APICS)
1082         return -1;
1083     s = qemu_mallocz(sizeof(APICState));
1084     env->apic_state = s;
1085     s->idx = last_apic_idx++;
1086     s->id = env->cpuid_apic_id;
1087     s->cpu_env = env;
1088
1089     apic_reset(s);
1090     msix_supported = 1;
1091
1092     /* XXX: mapping more APICs at the same memory location */
1093     if (apic_io_memory == 0) {
1094         /* NOTE: the APIC is directly connected to the CPU - it is not
1095            on the global memory bus. */
1096         apic_io_memory = cpu_register_io_memory(apic_mem_read,
1097                                                 apic_mem_write, NULL);
1098         /* XXX: what if the base changes? */
1099         cpu_register_physical_memory(MSI_ADDR_BASE, MSI_ADDR_SIZE,
1100                                      apic_io_memory);
1101     }
1102     s->timer = qemu_new_timer(vm_clock, apic_timer, s);
1103
1104     register_savevm("apic", s->idx, 2, apic_save, apic_load, s);
1105     qemu_register_reset(apic_reset, s);
1106
1107     local_apics[s->idx] = s;
1108     return 0;
1109 }