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Virtio: enable VIRTIO_ZERO_COPY
[qemu-kvm/fedora.git] / target-ppc / translate.c
blobb34de137c784d081ce521e9ed68c93427890b116
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #include <stdarg.h>
21 #include <stdlib.h>
22 #include <stdio.h>
23 #include <string.h>
24 #include <inttypes.h>
25
26 #include "cpu.h"
27 #include "exec-all.h"
28 #include "disas.h"
29 #include "tcg-op.h"
30 #include "qemu-common.h"
31
32 #include "helper.h"
33 #define GEN_HELPER 1
34 #include "helper.h"
35
36 #define CPU_SINGLE_STEP 0x1
37 #define CPU_BRANCH_STEP 0x2
38 #define GDBSTUB_SINGLE_STEP 0x4
39
40 /* Include definitions for instructions classes and implementations flags */
41 //#define DO_SINGLE_STEP
42 //#define PPC_DEBUG_DISAS
43 //#define DO_PPC_STATISTICS
44 //#define OPTIMIZE_FPRF_UPDATE
45
46 /*****************************************************************************/
47 /* Code translation helpers */
48
49 /* global register indexes */
50 static TCGv_ptr cpu_env;
51 static char cpu_reg_names[10*3 + 22*4 /* GPR */
52 #if !defined(TARGET_PPC64)
53 + 10*4 + 22*5 /* SPE GPRh */
54 #endif
55 + 10*4 + 22*5 /* FPR */
56 + 2*(10*6 + 22*7) /* AVRh, AVRl */
57 + 8*5 /* CRF */];
58 static TCGv cpu_gpr[32];
59 #if !defined(TARGET_PPC64)
60 static TCGv cpu_gprh[32];
61 #endif
62 static TCGv_i64 cpu_fpr[32];
63 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
64 static TCGv_i32 cpu_crf[8];
65 static TCGv cpu_nip;
66 static TCGv cpu_msr;
67 static TCGv cpu_ctr;
68 static TCGv cpu_lr;
69 static TCGv cpu_xer;
70 static TCGv cpu_reserve;
71 static TCGv_i32 cpu_fpscr;
72 static TCGv_i32 cpu_access_type;
73
74 /* dyngen register indexes */
75 static TCGv cpu_T[1];
76
77 #include "gen-icount.h"
78
79 void ppc_translate_init(void)
80 {
81 int i;
82 char* p;
83 static int done_init = 0;
84
85 if (done_init)
86 return;
87
88 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
89 #if TARGET_LONG_BITS > HOST_LONG_BITS
90 cpu_T[0] = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, t0), "T0");
91 #else
92 cpu_T[0] = tcg_global_reg_new(TCG_AREG1, "T0");
93 #endif
94
95 p = cpu_reg_names;
96
97 for (i = 0; i < 8; i++) {
98 sprintf(p, "crf%d", i);
99 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
100 offsetof(CPUState, crf[i]), p);
101 p += 5;
102 }
103
104 for (i = 0; i < 32; i++) {
105 sprintf(p, "r%d", i);
106 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
107 offsetof(CPUState, gpr[i]), p);
108 p += (i < 10) ? 3 : 4;
109 #if !defined(TARGET_PPC64)
110 sprintf(p, "r%dH", i);
111 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
112 offsetof(CPUState, gprh[i]), p);
113 p += (i < 10) ? 4 : 5;
114 #endif
115
116 sprintf(p, "fp%d", i);
117 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
118 offsetof(CPUState, fpr[i]), p);
119 p += (i < 10) ? 4 : 5;
120
121 sprintf(p, "avr%dH", i);
122 #ifdef WORDS_BIGENDIAN
123 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
124 offsetof(CPUState, avr[i].u64[0]), p);
125 #else
126 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
127 offsetof(CPUState, avr[i].u64[1]), p);
128 #endif
129 p += (i < 10) ? 6 : 7;
130
131 sprintf(p, "avr%dL", i);
132 #ifdef WORDS_BIGENDIAN
133 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
134 offsetof(CPUState, avr[i].u64[1]), p);
135 #else
136 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
137 offsetof(CPUState, avr[i].u64[0]), p);
138 #endif
139 p += (i < 10) ? 6 : 7;
140 }
141
142 cpu_nip = tcg_global_mem_new(TCG_AREG0,
143 offsetof(CPUState, nip), "nip");
144
145 cpu_msr = tcg_global_mem_new(TCG_AREG0,
146 offsetof(CPUState, msr), "msr");
147
148 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
149 offsetof(CPUState, ctr), "ctr");
150
151 cpu_lr = tcg_global_mem_new(TCG_AREG0,
152 offsetof(CPUState, lr), "lr");
153
154 cpu_xer = tcg_global_mem_new(TCG_AREG0,
155 offsetof(CPUState, xer), "xer");
156
157 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
158 offsetof(CPUState, reserve), "reserve");
159
160 cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,
161 offsetof(CPUState, fpscr), "fpscr");
162
163 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
164 offsetof(CPUState, access_type), "access_type");
165
166 /* register helpers */
167 #define GEN_HELPER 2
168 #include "helper.h"
169
170 done_init = 1;
171 }
172
173 #if defined(OPTIMIZE_FPRF_UPDATE)
174 static uint16_t *gen_fprf_buf[OPC_BUF_SIZE];
175 static uint16_t **gen_fprf_ptr;
176 #endif
177
178 /* internal defines */
179 typedef struct DisasContext {
180 struct TranslationBlock *tb;
181 target_ulong nip;
182 uint32_t opcode;
183 uint32_t exception;
184 /* Routine used to access memory */
185 int mem_idx;
186 /* Translation flags */
187 #if !defined(CONFIG_USER_ONLY)
188 int supervisor;
189 #endif
190 #if defined(TARGET_PPC64)
191 int sf_mode;
192 #endif
193 int fpu_enabled;
194 int altivec_enabled;
195 int spe_enabled;
196 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
197 int singlestep_enabled;
198 } DisasContext;
199
200 struct opc_handler_t {
201 /* invalid bits */
202 uint32_t inval;
203 /* instruction type */
204 uint64_t type;
205 /* handler */
206 void (*handler)(DisasContext *ctx);
207 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
208 const char *oname;
209 #endif
210 #if defined(DO_PPC_STATISTICS)
211 uint64_t count;
212 #endif
213 };
214
215 static always_inline void gen_reset_fpstatus (void)
216 {
217 #ifdef CONFIG_SOFTFLOAT
218 gen_op_reset_fpstatus();
219 #endif
220 }
221
222 static always_inline void gen_compute_fprf (TCGv_i64 arg, int set_fprf, int set_rc)
223 {
224 TCGv_i32 t0 = tcg_temp_new_i32();
225
226 if (set_fprf != 0) {
227 /* This case might be optimized later */
228 #if defined(OPTIMIZE_FPRF_UPDATE)
229 *gen_fprf_ptr++ = gen_opc_ptr;
230 #endif
231 tcg_gen_movi_i32(t0, 1);
232 gen_helper_compute_fprf(t0, arg, t0);
233 if (unlikely(set_rc)) {
234 tcg_gen_mov_i32(cpu_crf[1], t0);
235 }
236 gen_helper_float_check_status();
237 } else if (unlikely(set_rc)) {
238 /* We always need to compute fpcc */
239 tcg_gen_movi_i32(t0, 0);
240 gen_helper_compute_fprf(t0, arg, t0);
241 tcg_gen_mov_i32(cpu_crf[1], t0);
242 if (set_fprf)
243 gen_helper_float_check_status();
244 }
245
246 tcg_temp_free_i32(t0);
247 }
248
249 static always_inline void gen_optimize_fprf (void)
250 {
251 #if defined(OPTIMIZE_FPRF_UPDATE)
252 uint16_t **ptr;
253
254 for (ptr = gen_fprf_buf; ptr != (gen_fprf_ptr - 1); ptr++)
255 *ptr = INDEX_op_nop1;
256 gen_fprf_ptr = gen_fprf_buf;
257 #endif
258 }
259
260 static always_inline void gen_set_access_type(int access_type)
261 {
262 tcg_gen_movi_i32(cpu_access_type, access_type);
263 }
264
265 static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
266 {
267 #if defined(TARGET_PPC64)
268 if (ctx->sf_mode)
269 tcg_gen_movi_tl(cpu_nip, nip);
270 else
271 #endif
272 tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
273 }
274
275 #define GEN_EXCP(ctx, excp, error) \
276 do { \
277 TCGv_i32 t0 = tcg_const_i32(excp); \
278 TCGv_i32 t1 = tcg_const_i32(error); \
279 if ((ctx)->exception == POWERPC_EXCP_NONE) { \
280 gen_update_nip(ctx, (ctx)->nip); \
281 } \
282 gen_helper_raise_exception_err(t0, t1); \
283 tcg_temp_free_i32(t0); \
284 tcg_temp_free_i32(t1); \
285 ctx->exception = (excp); \
286 } while (0)
287
288 #define GEN_EXCP_INVAL(ctx) \
289 GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
290 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL)
291
292 #define GEN_EXCP_PRIVOPC(ctx) \
293 GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
294 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_OPC)
295
296 #define GEN_EXCP_PRIVREG(ctx) \
297 GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
298 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG)
299
300 #define GEN_EXCP_NO_FP(ctx) \
301 GEN_EXCP(ctx, POWERPC_EXCP_FPU, 0)
302
303 #define GEN_EXCP_NO_AP(ctx) \
304 GEN_EXCP(ctx, POWERPC_EXCP_APU, 0)
305
306 #define GEN_EXCP_NO_VR(ctx) \
307 GEN_EXCP(ctx, POWERPC_EXCP_VPU, 0)
308
309 /* Stop translation */
310 static always_inline void GEN_STOP (DisasContext *ctx)
311 {
312 gen_update_nip(ctx, ctx->nip);
313 ctx->exception = POWERPC_EXCP_STOP;
314 }
315
316 /* No need to update nip here, as execution flow will change */
317 static always_inline void GEN_SYNC (DisasContext *ctx)
318 {
319 ctx->exception = POWERPC_EXCP_SYNC;
320 }
321
322 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
323 static void gen_##name (DisasContext *ctx); \
324 GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
325 static void gen_##name (DisasContext *ctx)
326
327 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
328 static void gen_##name (DisasContext *ctx); \
329 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type); \
330 static void gen_##name (DisasContext *ctx)
331
332 typedef struct opcode_t {
333 unsigned char opc1, opc2, opc3;
334 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
335 unsigned char pad[5];
336 #else
337 unsigned char pad[1];
338 #endif
339 opc_handler_t handler;
340 const char *oname;
341 } opcode_t;
342
343 /*****************************************************************************/
344 /*** Instruction decoding ***/
345 #define EXTRACT_HELPER(name, shift, nb) \
346 static always_inline uint32_t name (uint32_t opcode) \
347 { \
348 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
349 }
350
351 #define EXTRACT_SHELPER(name, shift, nb) \
352 static always_inline int32_t name (uint32_t opcode) \
353 { \
354 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
355 }
356
357 /* Opcode part 1 */
358 EXTRACT_HELPER(opc1, 26, 6);
359 /* Opcode part 2 */
360 EXTRACT_HELPER(opc2, 1, 5);
361 /* Opcode part 3 */
362 EXTRACT_HELPER(opc3, 6, 5);
363 /* Update Cr0 flags */
364 EXTRACT_HELPER(Rc, 0, 1);
365 /* Destination */
366 EXTRACT_HELPER(rD, 21, 5);
367 /* Source */
368 EXTRACT_HELPER(rS, 21, 5);
369 /* First operand */
370 EXTRACT_HELPER(rA, 16, 5);
371 /* Second operand */
372 EXTRACT_HELPER(rB, 11, 5);
373 /* Third operand */
374 EXTRACT_HELPER(rC, 6, 5);
375 /*** Get CRn ***/
376 EXTRACT_HELPER(crfD, 23, 3);
377 EXTRACT_HELPER(crfS, 18, 3);
378 EXTRACT_HELPER(crbD, 21, 5);
379 EXTRACT_HELPER(crbA, 16, 5);
380 EXTRACT_HELPER(crbB, 11, 5);
381 /* SPR / TBL */
382 EXTRACT_HELPER(_SPR, 11, 10);
383 static always_inline uint32_t SPR (uint32_t opcode)
384 {
385 uint32_t sprn = _SPR(opcode);
386
387 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
388 }
389 /*** Get constants ***/
390 EXTRACT_HELPER(IMM, 12, 8);
391 /* 16 bits signed immediate value */
392 EXTRACT_SHELPER(SIMM, 0, 16);
393 /* 16 bits unsigned immediate value */
394 EXTRACT_HELPER(UIMM, 0, 16);
395 /* Bit count */
396 EXTRACT_HELPER(NB, 11, 5);
397 /* Shift count */
398 EXTRACT_HELPER(SH, 11, 5);
399 /* Mask start */
400 EXTRACT_HELPER(MB, 6, 5);
401 /* Mask end */
402 EXTRACT_HELPER(ME, 1, 5);
403 /* Trap operand */
404 EXTRACT_HELPER(TO, 21, 5);
405
406 EXTRACT_HELPER(CRM, 12, 8);
407 EXTRACT_HELPER(FM, 17, 8);
408 EXTRACT_HELPER(SR, 16, 4);
409 EXTRACT_HELPER(FPIMM, 12, 4);
410
411 /*** Jump target decoding ***/
412 /* Displacement */
413 EXTRACT_SHELPER(d, 0, 16);
414 /* Immediate address */
415 static always_inline target_ulong LI (uint32_t opcode)
416 {
417 return (opcode >> 0) & 0x03FFFFFC;
418 }
419
420 static always_inline uint32_t BD (uint32_t opcode)
421 {
422 return (opcode >> 0) & 0xFFFC;
423 }
424
425 EXTRACT_HELPER(BO, 21, 5);
426 EXTRACT_HELPER(BI, 16, 5);
427 /* Absolute/relative address */
428 EXTRACT_HELPER(AA, 1, 1);
429 /* Link */
430 EXTRACT_HELPER(LK, 0, 1);
431
432 /* Create a mask between <start> and <end> bits */
433 static always_inline target_ulong MASK (uint32_t start, uint32_t end)
434 {
435 target_ulong ret;
436
437 #if defined(TARGET_PPC64)
438 if (likely(start == 0)) {
439 ret = UINT64_MAX << (63 - end);
440 } else if (likely(end == 63)) {
441 ret = UINT64_MAX >> start;
442 }
443 #else
444 if (likely(start == 0)) {
445 ret = UINT32_MAX << (31 - end);
446 } else if (likely(end == 31)) {
447 ret = UINT32_MAX >> start;
448 }
449 #endif
450 else {
451 ret = (((target_ulong)(-1ULL)) >> (start)) ^
452 (((target_ulong)(-1ULL) >> (end)) >> 1);
453 if (unlikely(start > end))
454 return ~ret;
455 }
456
457 return ret;
458 }
459
460 /*****************************************************************************/
461 /* PowerPC Instructions types definitions */
462 enum {
463 PPC_NONE = 0x0000000000000000ULL,
464 /* PowerPC base instructions set */
465 PPC_INSNS_BASE = 0x0000000000000001ULL,
466 /* integer operations instructions */
467 #define PPC_INTEGER PPC_INSNS_BASE
468 /* flow control instructions */
469 #define PPC_FLOW PPC_INSNS_BASE
470 /* virtual memory instructions */
471 #define PPC_MEM PPC_INSNS_BASE
472 /* ld/st with reservation instructions */
473 #define PPC_RES PPC_INSNS_BASE
474 /* spr/msr access instructions */
475 #define PPC_MISC PPC_INSNS_BASE
476 /* Deprecated instruction sets */
477 /* Original POWER instruction set */
478 PPC_POWER = 0x0000000000000002ULL,
479 /* POWER2 instruction set extension */
480 PPC_POWER2 = 0x0000000000000004ULL,
481 /* Power RTC support */
482 PPC_POWER_RTC = 0x0000000000000008ULL,
483 /* Power-to-PowerPC bridge (601) */
484 PPC_POWER_BR = 0x0000000000000010ULL,
485 /* 64 bits PowerPC instruction set */
486 PPC_64B = 0x0000000000000020ULL,
487 /* New 64 bits extensions (PowerPC 2.0x) */
488 PPC_64BX = 0x0000000000000040ULL,
489 /* 64 bits hypervisor extensions */
490 PPC_64H = 0x0000000000000080ULL,
491 /* New wait instruction (PowerPC 2.0x) */
492 PPC_WAIT = 0x0000000000000100ULL,
493 /* Time base mftb instruction */
494 PPC_MFTB = 0x0000000000000200ULL,
495
496 /* Fixed-point unit extensions */
497 /* PowerPC 602 specific */
498 PPC_602_SPEC = 0x0000000000000400ULL,
499 /* isel instruction */
500 PPC_ISEL = 0x0000000000000800ULL,
501 /* popcntb instruction */
502 PPC_POPCNTB = 0x0000000000001000ULL,
503 /* string load / store */
504 PPC_STRING = 0x0000000000002000ULL,
505
506 /* Floating-point unit extensions */
507 /* Optional floating point instructions */
508 PPC_FLOAT = 0x0000000000010000ULL,
509 /* New floating-point extensions (PowerPC 2.0x) */
510 PPC_FLOAT_EXT = 0x0000000000020000ULL,
511 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
512 PPC_FLOAT_FRES = 0x0000000000080000ULL,
513 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
514 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
515 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
516 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
517
518 /* Vector/SIMD extensions */
519 /* Altivec support */
520 PPC_ALTIVEC = 0x0000000001000000ULL,
521 /* PowerPC 2.03 SPE extension */
522 PPC_SPE = 0x0000000002000000ULL,
523 /* PowerPC 2.03 SPE floating-point extension */
524 PPC_SPEFPU = 0x0000000004000000ULL,
525
526 /* Optional memory control instructions */
527 PPC_MEM_TLBIA = 0x0000000010000000ULL,
528 PPC_MEM_TLBIE = 0x0000000020000000ULL,
529 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
530 /* sync instruction */
531 PPC_MEM_SYNC = 0x0000000080000000ULL,
532 /* eieio instruction */
533 PPC_MEM_EIEIO = 0x0000000100000000ULL,
534
535 /* Cache control instructions */
536 PPC_CACHE = 0x0000000200000000ULL,
537 /* icbi instruction */
538 PPC_CACHE_ICBI = 0x0000000400000000ULL,
539 /* dcbz instruction with fixed cache line size */
540 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
541 /* dcbz instruction with tunable cache line size */
542 PPC_CACHE_DCBZT = 0x0000001000000000ULL,
543 /* dcba instruction */
544 PPC_CACHE_DCBA = 0x0000002000000000ULL,
545 /* Freescale cache locking instructions */
546 PPC_CACHE_LOCK = 0x0000004000000000ULL,
547
548 /* MMU related extensions */
549 /* external control instructions */
550 PPC_EXTERN = 0x0000010000000000ULL,
551 /* segment register access instructions */
552 PPC_SEGMENT = 0x0000020000000000ULL,
553 /* PowerPC 6xx TLB management instructions */
554 PPC_6xx_TLB = 0x0000040000000000ULL,
555 /* PowerPC 74xx TLB management instructions */
556 PPC_74xx_TLB = 0x0000080000000000ULL,
557 /* PowerPC 40x TLB management instructions */
558 PPC_40x_TLB = 0x0000100000000000ULL,
559 /* segment register access instructions for PowerPC 64 "bridge" */
560 PPC_SEGMENT_64B = 0x0000200000000000ULL,
561 /* SLB management */
562 PPC_SLBI = 0x0000400000000000ULL,
563
564 /* Embedded PowerPC dedicated instructions */
565 PPC_WRTEE = 0x0001000000000000ULL,
566 /* PowerPC 40x exception model */
567 PPC_40x_EXCP = 0x0002000000000000ULL,
568 /* PowerPC 405 Mac instructions */
569 PPC_405_MAC = 0x0004000000000000ULL,
570 /* PowerPC 440 specific instructions */
571 PPC_440_SPEC = 0x0008000000000000ULL,
572 /* BookE (embedded) PowerPC specification */
573 PPC_BOOKE = 0x0010000000000000ULL,
574 /* mfapidi instruction */
575 PPC_MFAPIDI = 0x0020000000000000ULL,
576 /* tlbiva instruction */
577 PPC_TLBIVA = 0x0040000000000000ULL,
578 /* tlbivax instruction */
579 PPC_TLBIVAX = 0x0080000000000000ULL,
580 /* PowerPC 4xx dedicated instructions */
581 PPC_4xx_COMMON = 0x0100000000000000ULL,
582 /* PowerPC 40x ibct instructions */
583 PPC_40x_ICBT = 0x0200000000000000ULL,
584 /* rfmci is not implemented in all BookE PowerPC */
585 PPC_RFMCI = 0x0400000000000000ULL,
586 /* rfdi instruction */
587 PPC_RFDI = 0x0800000000000000ULL,
588 /* DCR accesses */
589 PPC_DCR = 0x1000000000000000ULL,
590 /* DCR extended accesse */
591 PPC_DCRX = 0x2000000000000000ULL,
592 /* user-mode DCR access, implemented in PowerPC 460 */
593 PPC_DCRUX = 0x4000000000000000ULL,
594 };
595
596 /*****************************************************************************/
597 /* PowerPC instructions table */
598 #if HOST_LONG_BITS == 64
599 #define OPC_ALIGN 8
600 #else
601 #define OPC_ALIGN 4
602 #endif
603 #if defined(__APPLE__)
604 #define OPCODES_SECTION \
605 __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
606 #else
607 #define OPCODES_SECTION \
608 __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
609 #endif
610
611 #if defined(DO_PPC_STATISTICS)
612 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
613 OPCODES_SECTION opcode_t opc_##name = { \
614 .opc1 = op1, \
615 .opc2 = op2, \
616 .opc3 = op3, \
617 .pad = { 0, }, \
618 .handler = { \
619 .inval = invl, \
620 .type = _typ, \
621 .handler = &gen_##name, \
622 .oname = stringify(name), \
623 }, \
624 .oname = stringify(name), \
625 }
626 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
627 OPCODES_SECTION opcode_t opc_##name = { \
628 .opc1 = op1, \
629 .opc2 = op2, \
630 .opc3 = op3, \
631 .pad = { 0, }, \
632 .handler = { \
633 .inval = invl, \
634 .type = _typ, \
635 .handler = &gen_##name, \
636 .oname = onam, \
637 }, \
638 .oname = onam, \
639 }
640 #else
641 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
642 OPCODES_SECTION opcode_t opc_##name = { \
643 .opc1 = op1, \
644 .opc2 = op2, \
645 .opc3 = op3, \
646 .pad = { 0, }, \
647 .handler = { \
648 .inval = invl, \
649 .type = _typ, \
650 .handler = &gen_##name, \
651 }, \
652 .oname = stringify(name), \
653 }
654 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
655 OPCODES_SECTION opcode_t opc_##name = { \
656 .opc1 = op1, \
657 .opc2 = op2, \
658 .opc3 = op3, \
659 .pad = { 0, }, \
660 .handler = { \
661 .inval = invl, \
662 .type = _typ, \
663 .handler = &gen_##name, \
664 }, \
665 .oname = onam, \
666 }
667 #endif
668
669 #define GEN_OPCODE_MARK(name) \
670 OPCODES_SECTION opcode_t opc_##name = { \
671 .opc1 = 0xFF, \
672 .opc2 = 0xFF, \
673 .opc3 = 0xFF, \
674 .pad = { 0, }, \
675 .handler = { \
676 .inval = 0x00000000, \
677 .type = 0x00, \
678 .handler = NULL, \
679 }, \
680 .oname = stringify(name), \
681 }
682
683 /* SPR load/store helpers */
684 static always_inline void gen_load_spr(TCGv t, int reg)
685 {
686 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
687 }
688
689 static always_inline void gen_store_spr(int reg, TCGv t)
690 {
691 tcg_gen_st_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
692 }
693
694 /* Start opcode list */
695 GEN_OPCODE_MARK(start);
696
697 /* Invalid instruction */
698 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
699 {
700 GEN_EXCP_INVAL(ctx);
701 }
702
703 static opc_handler_t invalid_handler = {
704 .inval = 0xFFFFFFFF,
705 .type = PPC_NONE,
706 .handler = gen_invalid,
707 };
708
709 /*** Integer comparison ***/
710
711 static always_inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
712 {
713 int l1, l2, l3;
714
715 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_xer);
716 tcg_gen_shri_i32(cpu_crf[crf], cpu_crf[crf], XER_SO);
717 tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1);
718
719 l1 = gen_new_label();
720 l2 = gen_new_label();
721 l3 = gen_new_label();
722 if (s) {
723 tcg_gen_brcond_tl(TCG_COND_LT, arg0, arg1, l1);
724 tcg_gen_brcond_tl(TCG_COND_GT, arg0, arg1, l2);
725 } else {
726 tcg_gen_brcond_tl(TCG_COND_LTU, arg0, arg1, l1);
727 tcg_gen_brcond_tl(TCG_COND_GTU, arg0, arg1, l2);
728 }
729 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ);
730 tcg_gen_br(l3);
731 gen_set_label(l1);
732 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT);
733 tcg_gen_br(l3);
734 gen_set_label(l2);
735 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT);
736 gen_set_label(l3);
737 }
738
739 static always_inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
740 {
741 TCGv t0 = tcg_const_local_tl(arg1);
742 gen_op_cmp(arg0, t0, s, crf);
743 tcg_temp_free(t0);
744 }
745
746 #if defined(TARGET_PPC64)
747 static always_inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
748 {
749 TCGv t0, t1;
750 t0 = tcg_temp_local_new();
751 t1 = tcg_temp_local_new();
752 if (s) {
753 tcg_gen_ext32s_tl(t0, arg0);
754 tcg_gen_ext32s_tl(t1, arg1);
755 } else {
756 tcg_gen_ext32u_tl(t0, arg0);
757 tcg_gen_ext32u_tl(t1, arg1);
758 }
759 gen_op_cmp(t0, t1, s, crf);
760 tcg_temp_free(t1);
761 tcg_temp_free(t0);
762 }
763
764 static always_inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
765 {
766 TCGv t0 = tcg_const_local_tl(arg1);
767 gen_op_cmp32(arg0, t0, s, crf);
768 tcg_temp_free(t0);
769 }
770 #endif
771
772 static always_inline void gen_set_Rc0 (DisasContext *ctx, TCGv reg)
773 {
774 #if defined(TARGET_PPC64)
775 if (!(ctx->sf_mode))
776 gen_op_cmpi32(reg, 0, 1, 0);
777 else
778 #endif
779 gen_op_cmpi(reg, 0, 1, 0);
780 }
781
782 /* cmp */
783 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER)
784 {
785 #if defined(TARGET_PPC64)
786 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
787 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
788 1, crfD(ctx->opcode));
789 else
790 #endif
791 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
792 1, crfD(ctx->opcode));
793 }
794
795 /* cmpi */
796 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
797 {
798 #if defined(TARGET_PPC64)
799 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
800 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
801 1, crfD(ctx->opcode));
802 else
803 #endif
804 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
805 1, crfD(ctx->opcode));
806 }
807
808 /* cmpl */
809 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER)
810 {
811 #if defined(TARGET_PPC64)
812 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
813 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
814 0, crfD(ctx->opcode));
815 else
816 #endif
817 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
818 0, crfD(ctx->opcode));
819 }
820
821 /* cmpli */
822 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
823 {
824 #if defined(TARGET_PPC64)
825 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
826 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
827 0, crfD(ctx->opcode));
828 else
829 #endif
830 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
831 0, crfD(ctx->opcode));
832 }
833
834 /* isel (PowerPC 2.03 specification) */
835 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL)
836 {
837 int l1, l2;
838 uint32_t bi = rC(ctx->opcode);
839 uint32_t mask;
840 TCGv_i32 t0;
841
842 l1 = gen_new_label();
843 l2 = gen_new_label();
844
845 mask = 1 << (3 - (bi & 0x03));
846 t0 = tcg_temp_new_i32();
847 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
848 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
849 if (rA(ctx->opcode) == 0)
850 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
851 else
852 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
853 tcg_gen_br(l2);
854 gen_set_label(l1);
855 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
856 gen_set_label(l2);
857 tcg_temp_free_i32(t0);
858 }
859
860 /*** Integer arithmetic ***/
861
862 static always_inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, TCGv arg1, TCGv arg2, int sub)
863 {
864 int l1;
865 TCGv t0;
866
867 l1 = gen_new_label();
868 /* Start with XER OV disabled, the most likely case */
869 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
870 t0 = tcg_temp_local_new();
871 tcg_gen_xor_tl(t0, arg0, arg1);
872 #if defined(TARGET_PPC64)
873 if (!ctx->sf_mode)
874 tcg_gen_ext32s_tl(t0, t0);
875 #endif
876 if (sub)
877 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
878 else
879 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
880 tcg_gen_xor_tl(t0, arg1, arg2);
881 #if defined(TARGET_PPC64)
882 if (!ctx->sf_mode)
883 tcg_gen_ext32s_tl(t0, t0);
884 #endif
885 if (sub)
886 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
887 else
888 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
889 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
890 gen_set_label(l1);
891 tcg_temp_free(t0);
892 }
893
894 static always_inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1, TCGv arg2, int sub)
895 {
896 int l1 = gen_new_label();
897
898 #if defined(TARGET_PPC64)
899 if (!(ctx->sf_mode)) {
900 TCGv t0, t1;
901 t0 = tcg_temp_new();
902 t1 = tcg_temp_new();
903
904 tcg_gen_ext32u_tl(t0, arg1);
905 tcg_gen_ext32u_tl(t1, arg2);
906 if (sub) {
907 tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l1);
908 } else {
909 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
910 }
911 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
912 gen_set_label(l1);
913 tcg_temp_free(t0);
914 tcg_temp_free(t1);
915 } else
916 #endif
917 {
918 if (sub) {
919 tcg_gen_brcond_tl(TCG_COND_GTU, arg1, arg2, l1);
920 } else {
921 tcg_gen_brcond_tl(TCG_COND_GEU, arg1, arg2, l1);
922 }
923 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
924 gen_set_label(l1);
925 }
926 }
927
928 /* Common add function */
929 static always_inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
930 int add_ca, int compute_ca, int compute_ov)
931 {
932 TCGv t0, t1;
933
934 if ((!compute_ca && !compute_ov) ||
935 (!TCGV_EQUAL(ret,arg1) && !TCGV_EQUAL(ret, arg2))) {
936 t0 = ret;
937 } else {
938 t0 = tcg_temp_local_new();
939 }
940
941 if (add_ca) {
942 t1 = tcg_temp_local_new();
943 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
944 tcg_gen_shri_tl(t1, t1, XER_CA);
945 }
946
947 if (compute_ca && compute_ov) {
948 /* Start with XER CA and OV disabled, the most likely case */
949 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
950 } else if (compute_ca) {
951 /* Start with XER CA disabled, the most likely case */
952 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
953 } else if (compute_ov) {
954 /* Start with XER OV disabled, the most likely case */
955 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
956 }
957
958 tcg_gen_add_tl(t0, arg1, arg2);
959
960 if (compute_ca) {
961 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
962 }
963 if (add_ca) {
964 tcg_gen_add_tl(t0, t0, t1);
965 gen_op_arith_compute_ca(ctx, t0, t1, 0);
966 tcg_temp_free(t1);
967 }
968 if (compute_ov) {
969 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
970 }
971
972 if (unlikely(Rc(ctx->opcode) != 0))
973 gen_set_Rc0(ctx, t0);
974
975 if (!TCGV_EQUAL(t0, ret)) {
976 tcg_gen_mov_tl(ret, t0);
977 tcg_temp_free(t0);
978 }
979 }
980 /* Add functions with two operands */
981 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
982 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER) \
983 { \
984 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
985 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
986 add_ca, compute_ca, compute_ov); \
987 }
988 /* Add functions with one operand and one immediate */
989 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
990 add_ca, compute_ca, compute_ov) \
991 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER) \
992 { \
993 TCGv t0 = tcg_const_local_tl(const_val); \
994 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
995 cpu_gpr[rA(ctx->opcode)], t0, \
996 add_ca, compute_ca, compute_ov); \
997 tcg_temp_free(t0); \
998 }
999
1000 /* add add. addo addo. */
1001 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
1002 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
1003 /* addc addc. addco addco. */
1004 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
1005 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
1006 /* adde adde. addeo addeo. */
1007 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
1008 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
1009 /* addme addme. addmeo addmeo. */
1010 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
1011 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
1012 /* addze addze. addzeo addzeo.*/
1013 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
1014 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
1015 /* addi */
1016 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1017 {
1018 target_long simm = SIMM(ctx->opcode);
1019
1020 if (rA(ctx->opcode) == 0) {
1021 /* li case */
1022 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
1023 } else {
1024 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm);
1025 }
1026 }
1027 /* addic addic.*/
1028 static always_inline void gen_op_addic (DisasContext *ctx, TCGv ret, TCGv arg1,
1029 int compute_Rc0)
1030 {
1031 target_long simm = SIMM(ctx->opcode);
1032
1033 /* Start with XER CA and OV disabled, the most likely case */
1034 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1035
1036 if (likely(simm != 0)) {
1037 TCGv t0 = tcg_temp_local_new();
1038 tcg_gen_addi_tl(t0, arg1, simm);
1039 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
1040 tcg_gen_mov_tl(ret, t0);
1041 tcg_temp_free(t0);
1042 } else {
1043 tcg_gen_mov_tl(ret, arg1);
1044 }
1045 if (compute_Rc0) {
1046 gen_set_Rc0(ctx, ret);
1047 }
1048 }
1049 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1050 {
1051 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
1052 }
1053 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1054 {
1055 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
1056 }
1057 /* addis */
1058 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1059 {
1060 target_long simm = SIMM(ctx->opcode);
1061
1062 if (rA(ctx->opcode) == 0) {
1063 /* lis case */
1064 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
1065 } else {
1066 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm << 16);
1067 }
1068 }
1069
1070 static always_inline void gen_op_arith_divw (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1071 int sign, int compute_ov)
1072 {
1073 int l1 = gen_new_label();
1074 int l2 = gen_new_label();
1075 TCGv_i32 t0 = tcg_temp_local_new_i32();
1076 TCGv_i32 t1 = tcg_temp_local_new_i32();
1077
1078 tcg_gen_trunc_tl_i32(t0, arg1);
1079 tcg_gen_trunc_tl_i32(t1, arg2);
1080 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
1081 if (sign) {
1082 int l3 = gen_new_label();
1083 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
1084 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
1085 gen_set_label(l3);
1086 tcg_gen_div_i32(t0, t0, t1);
1087 } else {
1088 tcg_gen_divu_i32(t0, t0, t1);
1089 }
1090 if (compute_ov) {
1091 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1092 }
1093 tcg_gen_br(l2);
1094 gen_set_label(l1);
1095 if (sign) {
1096 tcg_gen_sari_i32(t0, t0, 31);
1097 } else {
1098 tcg_gen_movi_i32(t0, 0);
1099 }
1100 if (compute_ov) {
1101 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1102 }
1103 gen_set_label(l2);
1104 tcg_gen_extu_i32_tl(ret, t0);
1105 tcg_temp_free_i32(t0);
1106 tcg_temp_free_i32(t1);
1107 if (unlikely(Rc(ctx->opcode) != 0))
1108 gen_set_Rc0(ctx, ret);
1109 }
1110 /* Div functions */
1111 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1112 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) \
1113 { \
1114 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1115 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1116 sign, compute_ov); \
1117 }
1118 /* divwu divwu. divwuo divwuo. */
1119 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1120 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1121 /* divw divw. divwo divwo. */
1122 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1123 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1124 #if defined(TARGET_PPC64)
1125 static always_inline void gen_op_arith_divd (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1126 int sign, int compute_ov)
1127 {
1128 int l1 = gen_new_label();
1129 int l2 = gen_new_label();
1130
1131 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1132 if (sign) {
1133 int l3 = gen_new_label();
1134 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1135 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1136 gen_set_label(l3);
1137 tcg_gen_div_i64(ret, arg1, arg2);
1138 } else {
1139 tcg_gen_divu_i64(ret, arg1, arg2);
1140 }
1141 if (compute_ov) {
1142 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1143 }
1144 tcg_gen_br(l2);
1145 gen_set_label(l1);
1146 if (sign) {
1147 tcg_gen_sari_i64(ret, arg1, 63);
1148 } else {
1149 tcg_gen_movi_i64(ret, 0);
1150 }
1151 if (compute_ov) {
1152 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1153 }
1154 gen_set_label(l2);
1155 if (unlikely(Rc(ctx->opcode) != 0))
1156 gen_set_Rc0(ctx, ret);
1157 }
1158 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1159 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1160 { \
1161 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1162 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1163 sign, compute_ov); \
1164 }
1165 /* divwu divwu. divwuo divwuo. */
1166 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1167 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1168 /* divw divw. divwo divwo. */
1169 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1170 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1171 #endif
1172
1173 /* mulhw mulhw. */
1174 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER)
1175 {
1176 TCGv_i64 t0, t1;
1177
1178 t0 = tcg_temp_new_i64();
1179 t1 = tcg_temp_new_i64();
1180 #if defined(TARGET_PPC64)
1181 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1182 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1183 tcg_gen_mul_i64(t0, t0, t1);
1184 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1185 #else
1186 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1187 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1188 tcg_gen_mul_i64(t0, t0, t1);
1189 tcg_gen_shri_i64(t0, t0, 32);
1190 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1191 #endif
1192 tcg_temp_free_i64(t0);
1193 tcg_temp_free_i64(t1);
1194 if (unlikely(Rc(ctx->opcode) != 0))
1195 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1196 }
1197 /* mulhwu mulhwu. */
1198 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER)
1199 {
1200 TCGv_i64 t0, t1;
1201
1202 t0 = tcg_temp_new_i64();
1203 t1 = tcg_temp_new_i64();
1204 #if defined(TARGET_PPC64)
1205 tcg_gen_ext32u_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1206 tcg_gen_ext32u_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1207 tcg_gen_mul_i64(t0, t0, t1);
1208 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1209 #else
1210 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1211 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1212 tcg_gen_mul_i64(t0, t0, t1);
1213 tcg_gen_shri_i64(t0, t0, 32);
1214 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1215 #endif
1216 tcg_temp_free_i64(t0);
1217 tcg_temp_free_i64(t1);
1218 if (unlikely(Rc(ctx->opcode) != 0))
1219 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1220 }
1221 /* mullw mullw. */
1222 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER)
1223 {
1224 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1225 cpu_gpr[rB(ctx->opcode)]);
1226 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
1227 if (unlikely(Rc(ctx->opcode) != 0))
1228 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1229 }
1230 /* mullwo mullwo. */
1231 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER)
1232 {
1233 int l1;
1234 TCGv_i64 t0, t1;
1235
1236 t0 = tcg_temp_new_i64();
1237 t1 = tcg_temp_new_i64();
1238 l1 = gen_new_label();
1239 /* Start with XER OV disabled, the most likely case */
1240 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1241 #if defined(TARGET_PPC64)
1242 tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1243 tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1244 #else
1245 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1246 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1247 #endif
1248 tcg_gen_mul_i64(t0, t0, t1);
1249 #if defined(TARGET_PPC64)
1250 tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0);
1251 tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1);
1252 #else
1253 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1254 tcg_gen_ext32s_i64(t1, t0);
1255 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
1256 #endif
1257 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1258 gen_set_label(l1);
1259 tcg_temp_free_i64(t0);
1260 tcg_temp_free_i64(t1);
1261 if (unlikely(Rc(ctx->opcode) != 0))
1262 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1263 }
1264 /* mulli */
1265 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1266 {
1267 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1268 SIMM(ctx->opcode));
1269 }
1270 #if defined(TARGET_PPC64)
1271 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
1272 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1273 { \
1274 gen_helper_##name (cpu_gpr[rD(ctx->opcode)], \
1275 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
1276 if (unlikely(Rc(ctx->opcode) != 0)) \
1277 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1278 }
1279 /* mulhd mulhd. */
1280 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00);
1281 /* mulhdu mulhdu. */
1282 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02);
1283 /* mulld mulld. */
1284 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B)
1285 {
1286 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1287 cpu_gpr[rB(ctx->opcode)]);
1288 if (unlikely(Rc(ctx->opcode) != 0))
1289 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1290 }
1291 /* mulldo mulldo. */
1292 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17);
1293 #endif
1294
1295 /* neg neg. nego nego. */
1296 static always_inline void gen_op_arith_neg (DisasContext *ctx, TCGv ret, TCGv arg1, int ov_check)
1297 {
1298 int l1 = gen_new_label();
1299 int l2 = gen_new_label();
1300 TCGv t0 = tcg_temp_local_new();
1301 #if defined(TARGET_PPC64)
1302 if (ctx->sf_mode) {
1303 tcg_gen_mov_tl(t0, arg1);
1304 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT64_MIN, l1);
1305 } else
1306 #endif
1307 {
1308 tcg_gen_ext32s_tl(t0, arg1);
1309 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1);
1310 }
1311 tcg_gen_neg_tl(ret, arg1);
1312 if (ov_check) {
1313 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1314 }
1315 tcg_gen_br(l2);
1316 gen_set_label(l1);
1317 tcg_gen_mov_tl(ret, t0);
1318 if (ov_check) {
1319 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1320 }
1321 gen_set_label(l2);
1322 tcg_temp_free(t0);
1323 if (unlikely(Rc(ctx->opcode) != 0))
1324 gen_set_Rc0(ctx, ret);
1325 }
1326 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER)
1327 {
1328 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
1329 }
1330 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER)
1331 {
1332 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
1333 }
1334
1335 /* Common subf function */
1336 static always_inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1337 int add_ca, int compute_ca, int compute_ov)
1338 {
1339 TCGv t0, t1;
1340
1341 if ((!compute_ca && !compute_ov) ||
1342 (!TCGV_EQUAL(ret, arg1) && !TCGV_EQUAL(ret, arg2))) {
1343 t0 = ret;
1344 } else {
1345 t0 = tcg_temp_local_new();
1346 }
1347
1348 if (add_ca) {
1349 t1 = tcg_temp_local_new();
1350 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
1351 tcg_gen_shri_tl(t1, t1, XER_CA);
1352 }
1353
1354 if (compute_ca && compute_ov) {
1355 /* Start with XER CA and OV disabled, the most likely case */
1356 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
1357 } else if (compute_ca) {
1358 /* Start with XER CA disabled, the most likely case */
1359 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1360 } else if (compute_ov) {
1361 /* Start with XER OV disabled, the most likely case */
1362 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1363 }
1364
1365 if (add_ca) {
1366 tcg_gen_not_tl(t0, arg1);
1367 tcg_gen_add_tl(t0, t0, arg2);
1368 gen_op_arith_compute_ca(ctx, t0, arg2, 0);
1369 tcg_gen_add_tl(t0, t0, t1);
1370 gen_op_arith_compute_ca(ctx, t0, t1, 0);
1371 tcg_temp_free(t1);
1372 } else {
1373 tcg_gen_sub_tl(t0, arg2, arg1);
1374 if (compute_ca) {
1375 gen_op_arith_compute_ca(ctx, t0, arg2, 1);
1376 }
1377 }
1378 if (compute_ov) {
1379 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1380 }
1381
1382 if (unlikely(Rc(ctx->opcode) != 0))
1383 gen_set_Rc0(ctx, t0);
1384
1385 if (!TCGV_EQUAL(t0, ret)) {
1386 tcg_gen_mov_tl(ret, t0);
1387 tcg_temp_free(t0);
1388 }
1389 }
1390 /* Sub functions with Two operands functions */
1391 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1392 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER) \
1393 { \
1394 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1395 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1396 add_ca, compute_ca, compute_ov); \
1397 }
1398 /* Sub functions with one operand and one immediate */
1399 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1400 add_ca, compute_ca, compute_ov) \
1401 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER) \
1402 { \
1403 TCGv t0 = tcg_const_local_tl(const_val); \
1404 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1405 cpu_gpr[rA(ctx->opcode)], t0, \
1406 add_ca, compute_ca, compute_ov); \
1407 tcg_temp_free(t0); \
1408 }
1409 /* subf subf. subfo subfo. */
1410 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1411 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1412 /* subfc subfc. subfco subfco. */
1413 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1414 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1415 /* subfe subfe. subfeo subfo. */
1416 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1417 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1418 /* subfme subfme. subfmeo subfmeo. */
1419 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1420 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1421 /* subfze subfze. subfzeo subfzeo.*/
1422 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1423 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1424 /* subfic */
1425 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1426 {
1427 /* Start with XER CA and OV disabled, the most likely case */
1428 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1429 TCGv t0 = tcg_temp_local_new();
1430 TCGv t1 = tcg_const_local_tl(SIMM(ctx->opcode));
1431 tcg_gen_sub_tl(t0, t1, cpu_gpr[rA(ctx->opcode)]);
1432 gen_op_arith_compute_ca(ctx, t0, t1, 1);
1433 tcg_temp_free(t1);
1434 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
1435 tcg_temp_free(t0);
1436 }
1437
1438 /*** Integer logical ***/
1439 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1440 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) \
1441 { \
1442 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1443 cpu_gpr[rB(ctx->opcode)]); \
1444 if (unlikely(Rc(ctx->opcode) != 0)) \
1445 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1446 }
1447
1448 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1449 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \
1450 { \
1451 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1452 if (unlikely(Rc(ctx->opcode) != 0)) \
1453 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1454 }
1455
1456 /* and & and. */
1457 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1458 /* andc & andc. */
1459 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1460 /* andi. */
1461 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1462 {
1463 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1464 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1465 }
1466 /* andis. */
1467 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1468 {
1469 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1470 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1471 }
1472 /* cntlzw */
1473 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER)
1474 {
1475 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1476 if (unlikely(Rc(ctx->opcode) != 0))
1477 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1478 }
1479 /* eqv & eqv. */
1480 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1481 /* extsb & extsb. */
1482 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1483 /* extsh & extsh. */
1484 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1485 /* nand & nand. */
1486 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1487 /* nor & nor. */
1488 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1489 /* or & or. */
1490 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
1491 {
1492 int rs, ra, rb;
1493
1494 rs = rS(ctx->opcode);
1495 ra = rA(ctx->opcode);
1496 rb = rB(ctx->opcode);
1497 /* Optimisation for mr. ri case */
1498 if (rs != ra || rs != rb) {
1499 if (rs != rb)
1500 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1501 else
1502 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1503 if (unlikely(Rc(ctx->opcode) != 0))
1504 gen_set_Rc0(ctx, cpu_gpr[ra]);
1505 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1506 gen_set_Rc0(ctx, cpu_gpr[rs]);
1507 #if defined(TARGET_PPC64)
1508 } else {
1509 int prio = 0;
1510
1511 switch (rs) {
1512 case 1:
1513 /* Set process priority to low */
1514 prio = 2;
1515 break;
1516 case 6:
1517 /* Set process priority to medium-low */
1518 prio = 3;
1519 break;
1520 case 2:
1521 /* Set process priority to normal */
1522 prio = 4;
1523 break;
1524 #if !defined(CONFIG_USER_ONLY)
1525 case 31:
1526 if (ctx->supervisor > 0) {
1527 /* Set process priority to very low */
1528 prio = 1;
1529 }
1530 break;
1531 case 5:
1532 if (ctx->supervisor > 0) {
1533 /* Set process priority to medium-hight */
1534 prio = 5;
1535 }
1536 break;
1537 case 3:
1538 if (ctx->supervisor > 0) {
1539 /* Set process priority to high */
1540 prio = 6;
1541 }
1542 break;
1543 case 7:
1544 if (ctx->supervisor > 1) {
1545 /* Set process priority to very high */
1546 prio = 7;
1547 }
1548 break;
1549 #endif
1550 default:
1551 /* nop */
1552 break;
1553 }
1554 if (prio) {
1555 TCGv t0 = tcg_temp_new();
1556 gen_load_spr(t0, SPR_PPR);
1557 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1558 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1559 gen_store_spr(SPR_PPR, t0);
1560 tcg_temp_free(t0);
1561 }
1562 #endif
1563 }
1564 }
1565 /* orc & orc. */
1566 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1567 /* xor & xor. */
1568 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
1569 {
1570 /* Optimisation for "set to zero" case */
1571 if (rS(ctx->opcode) != rB(ctx->opcode))
1572 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1573 else
1574 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1575 if (unlikely(Rc(ctx->opcode) != 0))
1576 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1577 }
1578 /* ori */
1579 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1580 {
1581 target_ulong uimm = UIMM(ctx->opcode);
1582
1583 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1584 /* NOP */
1585 /* XXX: should handle special NOPs for POWER series */
1586 return;
1587 }
1588 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1589 }
1590 /* oris */
1591 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1592 {
1593 target_ulong uimm = UIMM(ctx->opcode);
1594
1595 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1596 /* NOP */
1597 return;
1598 }
1599 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1600 }
1601 /* xori */
1602 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1603 {
1604 target_ulong uimm = UIMM(ctx->opcode);
1605
1606 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1607 /* NOP */
1608 return;
1609 }
1610 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1611 }
1612 /* xoris */
1613 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1614 {
1615 target_ulong uimm = UIMM(ctx->opcode);
1616
1617 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1618 /* NOP */
1619 return;
1620 }
1621 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1622 }
1623 /* popcntb : PowerPC 2.03 specification */
1624 GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB)
1625 {
1626 #if defined(TARGET_PPC64)
1627 if (ctx->sf_mode)
1628 gen_helper_popcntb_64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1629 else
1630 #endif
1631 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1632 }
1633
1634 #if defined(TARGET_PPC64)
1635 /* extsw & extsw. */
1636 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1637 /* cntlzd */
1638 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B)
1639 {
1640 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1641 if (unlikely(Rc(ctx->opcode) != 0))
1642 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1643 }
1644 #endif
1645
1646 /*** Integer rotate ***/
1647 /* rlwimi & rlwimi. */
1648 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1649 {
1650 uint32_t mb, me, sh;
1651
1652 mb = MB(ctx->opcode);
1653 me = ME(ctx->opcode);
1654 sh = SH(ctx->opcode);
1655 if (likely(sh == 0 && mb == 0 && me == 31)) {
1656 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1657 } else {
1658 target_ulong mask;
1659 TCGv t1;
1660 TCGv t0 = tcg_temp_new();
1661 #if defined(TARGET_PPC64)
1662 TCGv_i32 t2 = tcg_temp_new_i32();
1663 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1664 tcg_gen_rotli_i32(t2, t2, sh);
1665 tcg_gen_extu_i32_i64(t0, t2);
1666 tcg_temp_free_i32(t2);
1667 #else
1668 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1669 #endif
1670 #if defined(TARGET_PPC64)
1671 mb += 32;
1672 me += 32;
1673 #endif
1674 mask = MASK(mb, me);
1675 t1 = tcg_temp_new();
1676 tcg_gen_andi_tl(t0, t0, mask);
1677 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1678 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1679 tcg_temp_free(t0);
1680 tcg_temp_free(t1);
1681 }
1682 if (unlikely(Rc(ctx->opcode) != 0))
1683 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1684 }
1685 /* rlwinm & rlwinm. */
1686 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1687 {
1688 uint32_t mb, me, sh;
1689
1690 sh = SH(ctx->opcode);
1691 mb = MB(ctx->opcode);
1692 me = ME(ctx->opcode);
1693
1694 if (likely(mb == 0 && me == (31 - sh))) {
1695 if (likely(sh == 0)) {
1696 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1697 } else {
1698 TCGv t0 = tcg_temp_new();
1699 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1700 tcg_gen_shli_tl(t0, t0, sh);
1701 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1702 tcg_temp_free(t0);
1703 }
1704 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1705 TCGv t0 = tcg_temp_new();
1706 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1707 tcg_gen_shri_tl(t0, t0, mb);
1708 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1709 tcg_temp_free(t0);
1710 } else {
1711 TCGv t0 = tcg_temp_new();
1712 #if defined(TARGET_PPC64)
1713 TCGv_i32 t1 = tcg_temp_new_i32();
1714 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1715 tcg_gen_rotli_i32(t1, t1, sh);
1716 tcg_gen_extu_i32_i64(t0, t1);
1717 tcg_temp_free_i32(t1);
1718 #else
1719 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1720 #endif
1721 #if defined(TARGET_PPC64)
1722 mb += 32;
1723 me += 32;
1724 #endif
1725 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1726 tcg_temp_free(t0);
1727 }
1728 if (unlikely(Rc(ctx->opcode) != 0))
1729 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1730 }
1731 /* rlwnm & rlwnm. */
1732 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1733 {
1734 uint32_t mb, me;
1735 TCGv t0;
1736 #if defined(TARGET_PPC64)
1737 TCGv_i32 t1, t2;
1738 #endif
1739
1740 mb = MB(ctx->opcode);
1741 me = ME(ctx->opcode);
1742 t0 = tcg_temp_new();
1743 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1744 #if defined(TARGET_PPC64)
1745 t1 = tcg_temp_new_i32();
1746 t2 = tcg_temp_new_i32();
1747 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1748 tcg_gen_trunc_i64_i32(t2, t0);
1749 tcg_gen_rotl_i32(t1, t1, t2);
1750 tcg_gen_extu_i32_i64(t0, t1);
1751 tcg_temp_free_i32(t1);
1752 tcg_temp_free_i32(t2);
1753 #else
1754 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1755 #endif
1756 if (unlikely(mb != 0 || me != 31)) {
1757 #if defined(TARGET_PPC64)
1758 mb += 32;
1759 me += 32;
1760 #endif
1761 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1762 } else {
1763 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1764 }
1765 tcg_temp_free(t0);
1766 if (unlikely(Rc(ctx->opcode) != 0))
1767 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1768 }
1769
1770 #if defined(TARGET_PPC64)
1771 #define GEN_PPC64_R2(name, opc1, opc2) \
1772 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1773 { \
1774 gen_##name(ctx, 0); \
1775 } \
1776 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1777 PPC_64B) \
1778 { \
1779 gen_##name(ctx, 1); \
1780 }
1781 #define GEN_PPC64_R4(name, opc1, opc2) \
1782 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1783 { \
1784 gen_##name(ctx, 0, 0); \
1785 } \
1786 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
1787 PPC_64B) \
1788 { \
1789 gen_##name(ctx, 0, 1); \
1790 } \
1791 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1792 PPC_64B) \
1793 { \
1794 gen_##name(ctx, 1, 0); \
1795 } \
1796 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
1797 PPC_64B) \
1798 { \
1799 gen_##name(ctx, 1, 1); \
1800 }
1801
1802 static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
1803 uint32_t me, uint32_t sh)
1804 {
1805 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1806 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1807 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1808 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1809 } else {
1810 TCGv t0 = tcg_temp_new();
1811 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1812 if (likely(mb == 0 && me == 63)) {
1813 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1814 } else {
1815 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1816 }
1817 tcg_temp_free(t0);
1818 }
1819 if (unlikely(Rc(ctx->opcode) != 0))
1820 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1821 }
1822 /* rldicl - rldicl. */
1823 static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
1824 {
1825 uint32_t sh, mb;
1826
1827 sh = SH(ctx->opcode) | (shn << 5);
1828 mb = MB(ctx->opcode) | (mbn << 5);
1829 gen_rldinm(ctx, mb, 63, sh);
1830 }
1831 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1832 /* rldicr - rldicr. */
1833 static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn)
1834 {
1835 uint32_t sh, me;
1836
1837 sh = SH(ctx->opcode) | (shn << 5);
1838 me = MB(ctx->opcode) | (men << 5);
1839 gen_rldinm(ctx, 0, me, sh);
1840 }
1841 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1842 /* rldic - rldic. */
1843 static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
1844 {
1845 uint32_t sh, mb;
1846
1847 sh = SH(ctx->opcode) | (shn << 5);
1848 mb = MB(ctx->opcode) | (mbn << 5);
1849 gen_rldinm(ctx, mb, 63 - sh, sh);
1850 }
1851 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1852
1853 static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
1854 uint32_t me)
1855 {
1856 TCGv t0;
1857
1858 mb = MB(ctx->opcode);
1859 me = ME(ctx->opcode);
1860 t0 = tcg_temp_new();
1861 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1862 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1863 if (unlikely(mb != 0 || me != 63)) {
1864 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1865 } else {
1866 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1867 }
1868 tcg_temp_free(t0);
1869 if (unlikely(Rc(ctx->opcode) != 0))
1870 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1871 }
1872
1873 /* rldcl - rldcl. */
1874 static always_inline void gen_rldcl (DisasContext *ctx, int mbn)
1875 {
1876 uint32_t mb;
1877
1878 mb = MB(ctx->opcode) | (mbn << 5);
1879 gen_rldnm(ctx, mb, 63);
1880 }
1881 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1882 /* rldcr - rldcr. */
1883 static always_inline void gen_rldcr (DisasContext *ctx, int men)
1884 {
1885 uint32_t me;
1886
1887 me = MB(ctx->opcode) | (men << 5);
1888 gen_rldnm(ctx, 0, me);
1889 }
1890 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1891 /* rldimi - rldimi. */
1892 static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
1893 {
1894 uint32_t sh, mb, me;
1895
1896 sh = SH(ctx->opcode) | (shn << 5);
1897 mb = MB(ctx->opcode) | (mbn << 5);
1898 me = 63 - sh;
1899 if (unlikely(sh == 0 && mb == 0)) {
1900 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1901 } else {
1902 TCGv t0, t1;
1903 target_ulong mask;
1904
1905 t0 = tcg_temp_new();
1906 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1907 t1 = tcg_temp_new();
1908 mask = MASK(mb, me);
1909 tcg_gen_andi_tl(t0, t0, mask);
1910 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1911 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1912 tcg_temp_free(t0);
1913 tcg_temp_free(t1);
1914 }
1915 if (unlikely(Rc(ctx->opcode) != 0))
1916 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1917 }
1918 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1919 #endif
1920
1921 /*** Integer shift ***/
1922 /* slw & slw. */
1923 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER)
1924 {
1925 TCGv t0;
1926 int l1, l2;
1927 l1 = gen_new_label();
1928 l2 = gen_new_label();
1929
1930 t0 = tcg_temp_local_new();
1931 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1932 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
1933 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1934 tcg_gen_br(l2);
1935 gen_set_label(l1);
1936 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
1937 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1938 gen_set_label(l2);
1939 tcg_temp_free(t0);
1940 if (unlikely(Rc(ctx->opcode) != 0))
1941 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1942 }
1943 /* sraw & sraw. */
1944 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER)
1945 {
1946 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)],
1947 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1948 if (unlikely(Rc(ctx->opcode) != 0))
1949 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1950 }
1951 /* srawi & srawi. */
1952 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
1953 {
1954 int sh = SH(ctx->opcode);
1955 if (sh != 0) {
1956 int l1, l2;
1957 TCGv t0;
1958 l1 = gen_new_label();
1959 l2 = gen_new_label();
1960 t0 = tcg_temp_local_new();
1961 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1962 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
1963 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1964 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
1965 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
1966 tcg_gen_br(l2);
1967 gen_set_label(l1);
1968 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1969 gen_set_label(l2);
1970 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1971 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh);
1972 tcg_temp_free(t0);
1973 } else {
1974 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1975 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1976 }
1977 if (unlikely(Rc(ctx->opcode) != 0))
1978 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1979 }
1980 /* srw & srw. */
1981 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER)
1982 {
1983 TCGv t0, t1;
1984 int l1, l2;
1985 l1 = gen_new_label();
1986 l2 = gen_new_label();
1987
1988 t0 = tcg_temp_local_new();
1989 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1990 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
1991 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1992 tcg_gen_br(l2);
1993 gen_set_label(l1);
1994 t1 = tcg_temp_new();
1995 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
1996 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t1, t0);
1997 tcg_temp_free(t1);
1998 gen_set_label(l2);
1999 tcg_temp_free(t0);
2000 if (unlikely(Rc(ctx->opcode) != 0))
2001 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2002 }
2003 #if defined(TARGET_PPC64)
2004 /* sld & sld. */
2005 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B)
2006 {
2007 TCGv t0;
2008 int l1, l2;
2009 l1 = gen_new_label();
2010 l2 = gen_new_label();
2011
2012 t0 = tcg_temp_local_new();
2013 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
2014 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
2015 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2016 tcg_gen_br(l2);
2017 gen_set_label(l1);
2018 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
2019 gen_set_label(l2);
2020 tcg_temp_free(t0);
2021 if (unlikely(Rc(ctx->opcode) != 0))
2022 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2023 }
2024 /* srad & srad. */
2025 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B)
2026 {
2027 gen_helper_srad(cpu_gpr[rA(ctx->opcode)],
2028 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2029 if (unlikely(Rc(ctx->opcode) != 0))
2030 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2031 }
2032 /* sradi & sradi. */
2033 static always_inline void gen_sradi (DisasContext *ctx, int n)
2034 {
2035 int sh = SH(ctx->opcode) + (n << 5);
2036 if (sh != 0) {
2037 int l1, l2;
2038 TCGv t0;
2039 l1 = gen_new_label();
2040 l2 = gen_new_label();
2041 t0 = tcg_temp_local_new();
2042 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
2043 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
2044 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2045 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
2046 tcg_gen_br(l2);
2047 gen_set_label(l1);
2048 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
2049 gen_set_label(l2);
2050 tcg_temp_free(t0);
2051 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
2052 } else {
2053 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
2054 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
2055 }
2056 if (unlikely(Rc(ctx->opcode) != 0))
2057 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2058 }
2059 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B)
2060 {
2061 gen_sradi(ctx, 0);
2062 }
2063 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B)
2064 {
2065 gen_sradi(ctx, 1);
2066 }
2067 /* srd & srd. */
2068 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B)
2069 {
2070 TCGv t0;
2071 int l1, l2;
2072 l1 = gen_new_label();
2073 l2 = gen_new_label();
2074
2075 t0 = tcg_temp_local_new();
2076 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
2077 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
2078 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2079 tcg_gen_br(l2);
2080 gen_set_label(l1);
2081 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
2082 gen_set_label(l2);
2083 tcg_temp_free(t0);
2084 if (unlikely(Rc(ctx->opcode) != 0))
2085 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2086 }
2087 #endif
2088
2089 /*** Floating-Point arithmetic ***/
2090 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
2091 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \
2092 { \
2093 if (unlikely(!ctx->fpu_enabled)) { \
2094 GEN_EXCP_NO_FP(ctx); \
2095 return; \
2096 } \
2097 gen_reset_fpstatus(); \
2098 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2099 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2100 if (isfloat) { \
2101 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
2102 } \
2103 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
2104 Rc(ctx->opcode) != 0); \
2105 }
2106
2107 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2108 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2109 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2110
2111 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2112 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
2113 { \
2114 if (unlikely(!ctx->fpu_enabled)) { \
2115 GEN_EXCP_NO_FP(ctx); \
2116 return; \
2117 } \
2118 gen_reset_fpstatus(); \
2119 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2120 cpu_fpr[rB(ctx->opcode)]); \
2121 if (isfloat) { \
2122 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
2123 } \
2124 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2125 set_fprf, Rc(ctx->opcode) != 0); \
2126 }
2127 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2128 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2129 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2130
2131 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2132 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
2133 { \
2134 if (unlikely(!ctx->fpu_enabled)) { \
2135 GEN_EXCP_NO_FP(ctx); \
2136 return; \
2137 } \
2138 gen_reset_fpstatus(); \
2139 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2140 cpu_fpr[rC(ctx->opcode)]); \
2141 if (isfloat) { \
2142 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
2143 } \
2144 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2145 set_fprf, Rc(ctx->opcode) != 0); \
2146 }
2147 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2148 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2149 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2150
2151 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2152 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \
2153 { \
2154 if (unlikely(!ctx->fpu_enabled)) { \
2155 GEN_EXCP_NO_FP(ctx); \
2156 return; \
2157 } \
2158 gen_reset_fpstatus(); \
2159 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2160 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2161 set_fprf, Rc(ctx->opcode) != 0); \
2162 }
2163
2164 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2165 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \
2166 { \
2167 if (unlikely(!ctx->fpu_enabled)) { \
2168 GEN_EXCP_NO_FP(ctx); \
2169 return; \
2170 } \
2171 gen_reset_fpstatus(); \
2172 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2173 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2174 set_fprf, Rc(ctx->opcode) != 0); \
2175 }
2176
2177 /* fadd - fadds */
2178 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2179 /* fdiv - fdivs */
2180 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2181 /* fmul - fmuls */
2182 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2183
2184 /* fre */
2185 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2186
2187 /* fres */
2188 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2189
2190 /* frsqrte */
2191 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2192
2193 /* frsqrtes */
2194 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES)
2195 {
2196 if (unlikely(!ctx->fpu_enabled)) {
2197 GEN_EXCP_NO_FP(ctx);
2198 return;
2199 }
2200 gen_reset_fpstatus();
2201 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2202 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2203 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2204 }
2205
2206 /* fsel */
2207 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2208 /* fsub - fsubs */
2209 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2210 /* Optional: */
2211 /* fsqrt */
2212 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
2213 {
2214 if (unlikely(!ctx->fpu_enabled)) {
2215 GEN_EXCP_NO_FP(ctx);
2216 return;
2217 }
2218 gen_reset_fpstatus();
2219 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2220 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2221 }
2222
2223 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
2224 {
2225 if (unlikely(!ctx->fpu_enabled)) {
2226 GEN_EXCP_NO_FP(ctx);
2227 return;
2228 }
2229 gen_reset_fpstatus();
2230 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2231 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2232 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2233 }
2234
2235 /*** Floating-Point multiply-and-add ***/
2236 /* fmadd - fmadds */
2237 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2238 /* fmsub - fmsubs */
2239 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2240 /* fnmadd - fnmadds */
2241 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2242 /* fnmsub - fnmsubs */
2243 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2244
2245 /*** Floating-Point round & convert ***/
2246 /* fctiw */
2247 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2248 /* fctiwz */
2249 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2250 /* frsp */
2251 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2252 #if defined(TARGET_PPC64)
2253 /* fcfid */
2254 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
2255 /* fctid */
2256 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
2257 /* fctidz */
2258 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
2259 #endif
2260
2261 /* frin */
2262 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2263 /* friz */
2264 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2265 /* frip */
2266 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2267 /* frim */
2268 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2269
2270 /*** Floating-Point compare ***/
2271 /* fcmpo */
2272 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
2273 {
2274 if (unlikely(!ctx->fpu_enabled)) {
2275 GEN_EXCP_NO_FP(ctx);
2276 return;
2277 }
2278 gen_reset_fpstatus();
2279 gen_helper_fcmpo(cpu_crf[crfD(ctx->opcode)],
2280 cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2281 gen_helper_float_check_status();
2282 }
2283
2284 /* fcmpu */
2285 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
2286 {
2287 if (unlikely(!ctx->fpu_enabled)) {
2288 GEN_EXCP_NO_FP(ctx);
2289 return;
2290 }
2291 gen_reset_fpstatus();
2292 gen_helper_fcmpu(cpu_crf[crfD(ctx->opcode)],
2293 cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2294 gen_helper_float_check_status();
2295 }
2296
2297 /*** Floating-point move ***/
2298 /* fabs */
2299 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2300 GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
2301
2302 /* fmr - fmr. */
2303 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2304 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
2305 {
2306 if (unlikely(!ctx->fpu_enabled)) {
2307 GEN_EXCP_NO_FP(ctx);
2308 return;
2309 }
2310 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2311 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2312 }
2313
2314 /* fnabs */
2315 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2316 GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
2317 /* fneg */
2318 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2319 GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
2320
2321 /*** Floating-Point status & ctrl register ***/
2322 /* mcrfs */
2323 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
2324 {
2325 int bfa;
2326
2327 if (unlikely(!ctx->fpu_enabled)) {
2328 GEN_EXCP_NO_FP(ctx);
2329 return;
2330 }
2331 gen_optimize_fprf();
2332 bfa = 4 * (7 - crfS(ctx->opcode));
2333 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa);
2334 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2335 tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
2336 }
2337
2338 /* mffs */
2339 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
2340 {
2341 if (unlikely(!ctx->fpu_enabled)) {
2342 GEN_EXCP_NO_FP(ctx);
2343 return;
2344 }
2345 gen_optimize_fprf();
2346 gen_reset_fpstatus();
2347 tcg_gen_extu_i32_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2348 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2349 }
2350
2351 /* mtfsb0 */
2352 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
2353 {
2354 uint8_t crb;
2355
2356 if (unlikely(!ctx->fpu_enabled)) {
2357 GEN_EXCP_NO_FP(ctx);
2358 return;
2359 }
2360 crb = 32 - (crbD(ctx->opcode) >> 2);
2361 gen_optimize_fprf();
2362 gen_reset_fpstatus();
2363 if (likely(crb != 30 && crb != 29))
2364 tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(1 << crb));
2365 if (unlikely(Rc(ctx->opcode) != 0)) {
2366 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2367 }
2368 }
2369
2370 /* mtfsb1 */
2371 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
2372 {
2373 uint8_t crb;
2374
2375 if (unlikely(!ctx->fpu_enabled)) {
2376 GEN_EXCP_NO_FP(ctx);
2377 return;
2378 }
2379 crb = 32 - (crbD(ctx->opcode) >> 2);
2380 gen_optimize_fprf();
2381 gen_reset_fpstatus();
2382 /* XXX: we pretend we can only do IEEE floating-point computations */
2383 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2384 TCGv_i32 t0 = tcg_const_i32(crb);
2385 gen_helper_fpscr_setbit(t0);
2386 tcg_temp_free_i32(t0);
2387 }
2388 if (unlikely(Rc(ctx->opcode) != 0)) {
2389 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2390 }
2391 /* We can raise a differed exception */
2392 gen_helper_float_check_status();
2393 }
2394
2395 /* mtfsf */
2396 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
2397 {
2398 TCGv_i32 t0;
2399
2400 if (unlikely(!ctx->fpu_enabled)) {
2401 GEN_EXCP_NO_FP(ctx);
2402 return;
2403 }
2404 gen_optimize_fprf();
2405 gen_reset_fpstatus();
2406 t0 = tcg_const_i32(FM(ctx->opcode));
2407 gen_helper_store_fpscr(cpu_fpr[rB(ctx->opcode)], t0);
2408 tcg_temp_free_i32(t0);
2409 if (unlikely(Rc(ctx->opcode) != 0)) {
2410 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2411 }
2412 /* We can raise a differed exception */
2413 gen_helper_float_check_status();
2414 }
2415
2416 /* mtfsfi */
2417 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
2418 {
2419 int bf, sh;
2420 TCGv_i64 t0;
2421 TCGv_i32 t1;
2422
2423 if (unlikely(!ctx->fpu_enabled)) {
2424 GEN_EXCP_NO_FP(ctx);
2425 return;
2426 }
2427 bf = crbD(ctx->opcode) >> 2;
2428 sh = 7 - bf;
2429 gen_optimize_fprf();
2430 gen_reset_fpstatus();
2431 t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
2432 t1 = tcg_const_i32(1 << sh);
2433 gen_helper_store_fpscr(t0, t1);
2434 tcg_temp_free_i64(t0);
2435 tcg_temp_free_i32(t1);
2436 if (unlikely(Rc(ctx->opcode) != 0)) {
2437 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2438 }
2439 /* We can raise a differed exception */
2440 gen_helper_float_check_status();
2441 }
2442
2443 /*** Addressing modes ***/
2444 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2445 static always_inline void gen_addr_imm_index (TCGv EA,
2446 DisasContext *ctx,
2447 target_long maskl)
2448 {
2449 target_long simm = SIMM(ctx->opcode);
2450
2451 simm &= ~maskl;
2452 if (rA(ctx->opcode) == 0)
2453 tcg_gen_movi_tl(EA, simm);
2454 else if (likely(simm != 0))
2455 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2456 else
2457 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2458 }
2459
2460 static always_inline void gen_addr_reg_index (TCGv EA,
2461 DisasContext *ctx)
2462 {
2463 if (rA(ctx->opcode) == 0)
2464 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2465 else
2466 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2467 }
2468
2469 static always_inline void gen_addr_register (TCGv EA,
2470 DisasContext *ctx)
2471 {
2472 if (rA(ctx->opcode) == 0)
2473 tcg_gen_movi_tl(EA, 0);
2474 else
2475 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2476 }
2477
2478 static always_inline void gen_check_align (DisasContext *ctx, TCGv EA, int mask)
2479 {
2480 int l1 = gen_new_label();
2481 TCGv t0 = tcg_temp_new();
2482 TCGv_i32 t1, t2;
2483 /* NIP cannot be restored if the memory exception comes from an helper */
2484 gen_update_nip(ctx, ctx->nip - 4);
2485 tcg_gen_andi_tl(t0, EA, mask);
2486 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2487 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2488 t2 = tcg_const_i32(0);
2489 gen_helper_raise_exception_err(t1, t2);
2490 tcg_temp_free_i32(t1);
2491 tcg_temp_free_i32(t2);
2492 gen_set_label(l1);
2493 tcg_temp_free(t0);
2494 }
2495
2496 /*** Integer load ***/
2497 #if defined(TARGET_PPC64)
2498 #define GEN_QEMU_LD_PPC64(width) \
2499 static always_inline void gen_qemu_ld##width##_ppc64(TCGv t0, TCGv t1, int flags)\
2500 { \
2501 if (likely(flags & 2)) \
2502 tcg_gen_qemu_ld##width(t0, t1, flags >> 2); \
2503 else { \
2504 TCGv addr = tcg_temp_new(); \
2505 tcg_gen_ext32u_tl(addr, t1); \
2506 tcg_gen_qemu_ld##width(t0, addr, flags >> 2); \
2507 tcg_temp_free(addr); \
2508 } \
2509 }
2510 GEN_QEMU_LD_PPC64(8u)
2511 GEN_QEMU_LD_PPC64(8s)
2512 GEN_QEMU_LD_PPC64(16u)
2513 GEN_QEMU_LD_PPC64(16s)
2514 GEN_QEMU_LD_PPC64(32u)
2515 GEN_QEMU_LD_PPC64(32s)
2516 GEN_QEMU_LD_PPC64(64)
2517
2518 #define GEN_QEMU_ST_PPC64(width) \
2519 static always_inline void gen_qemu_st##width##_ppc64(TCGv t0, TCGv t1, int flags)\
2520 { \
2521 if (likely(flags & 2)) \
2522 tcg_gen_qemu_st##width(t0, t1, flags >> 2); \
2523 else { \
2524 TCGv addr = tcg_temp_new(); \
2525 tcg_gen_ext32u_tl(addr, t1); \
2526 tcg_gen_qemu_st##width(t0, addr, flags >> 2); \
2527 tcg_temp_free(addr); \
2528 } \
2529 }
2530 GEN_QEMU_ST_PPC64(8)
2531 GEN_QEMU_ST_PPC64(16)
2532 GEN_QEMU_ST_PPC64(32)
2533 GEN_QEMU_ST_PPC64(64)
2534
2535 static always_inline void gen_qemu_ld8u(TCGv arg0, TCGv arg1, int flags)
2536 {
2537 gen_qemu_ld8u_ppc64(arg0, arg1, flags);
2538 }
2539
2540 static always_inline void gen_qemu_ld8s(TCGv arg0, TCGv arg1, int flags)
2541 {
2542 gen_qemu_ld8s_ppc64(arg0, arg1, flags);
2543 }
2544
2545 static always_inline void gen_qemu_ld16u(TCGv arg0, TCGv arg1, int flags)
2546 {
2547 if (unlikely(flags & 1)) {
2548 TCGv_i32 t0;
2549 gen_qemu_ld16u_ppc64(arg0, arg1, flags);
2550 t0 = tcg_temp_new_i32();
2551 tcg_gen_trunc_tl_i32(t0, arg0);
2552 tcg_gen_bswap16_i32(t0, t0);
2553 tcg_gen_extu_i32_tl(arg0, t0);
2554 tcg_temp_free_i32(t0);
2555 } else
2556 gen_qemu_ld16u_ppc64(arg0, arg1, flags);
2557 }
2558
2559 static always_inline void gen_qemu_ld16s(TCGv arg0, TCGv arg1, int flags)
2560 {
2561 if (unlikely(flags & 1)) {
2562 TCGv_i32 t0;
2563 gen_qemu_ld16u_ppc64(arg0, arg1, flags);
2564 t0 = tcg_temp_new_i32();
2565 tcg_gen_trunc_tl_i32(t0, arg0);
2566 tcg_gen_bswap16_i32(t0, t0);
2567 tcg_gen_extu_i32_tl(arg0, t0);
2568 tcg_gen_ext16s_tl(arg0, arg0);
2569 tcg_temp_free_i32(t0);
2570 } else
2571 gen_qemu_ld16s_ppc64(arg0, arg1, flags);
2572 }
2573
2574 static always_inline void gen_qemu_ld32u(TCGv arg0, TCGv arg1, int flags)
2575 {
2576 if (unlikely(flags & 1)) {
2577 TCGv_i32 t0;
2578 gen_qemu_ld32u_ppc64(arg0, arg1, flags);
2579 t0 = tcg_temp_new_i32();
2580 tcg_gen_trunc_tl_i32(t0, arg0);
2581 tcg_gen_bswap_i32(t0, t0);
2582 tcg_gen_extu_i32_tl(arg0, t0);
2583 tcg_temp_free_i32(t0);
2584 } else
2585 gen_qemu_ld32u_ppc64(arg0, arg1, flags);
2586 }
2587
2588 static always_inline void gen_qemu_ld32s(TCGv arg0, TCGv arg1, int flags)
2589 {
2590 if (unlikely(flags & 1)) {
2591 TCGv_i32 t0;
2592 gen_qemu_ld32u_ppc64(arg0, arg1, flags);
2593 t0 = tcg_temp_new_i32();
2594 tcg_gen_trunc_tl_i32(t0, arg0);
2595 tcg_gen_bswap_i32(t0, t0);
2596 tcg_gen_ext_i32_tl(arg0, t0);
2597 tcg_temp_free_i32(t0);
2598 } else
2599 gen_qemu_ld32s_ppc64(arg0, arg1, flags);
2600 }
2601
2602 static always_inline void gen_qemu_ld64(TCGv arg0, TCGv arg1, int flags)
2603 {
2604 gen_qemu_ld64_ppc64(arg0, arg1, flags);
2605 if (unlikely(flags & 1))
2606 tcg_gen_bswap_i64(arg0, arg0);
2607 }
2608
2609 static always_inline void gen_qemu_st8(TCGv arg0, TCGv arg1, int flags)
2610 {
2611 gen_qemu_st8_ppc64(arg0, arg1, flags);
2612 }
2613
2614 static always_inline void gen_qemu_st16(TCGv arg0, TCGv arg1, int flags)
2615 {
2616 if (unlikely(flags & 1)) {
2617 TCGv_i32 t0;
2618 TCGv_i64 t1;
2619 t0 = tcg_temp_new_i32();
2620 tcg_gen_trunc_tl_i32(t0, arg0);
2621 tcg_gen_ext16u_i32(t0, t0);
2622 tcg_gen_bswap16_i32(t0, t0);
2623 t1 = tcg_temp_new_i64();
2624 tcg_gen_extu_i32_tl(t1, t0);
2625 tcg_temp_free_i32(t0);
2626 gen_qemu_st16_ppc64(t1, arg1, flags);
2627 tcg_temp_free_i64(t1);
2628 } else
2629 gen_qemu_st16_ppc64(arg0, arg1, flags);
2630 }
2631
2632 static always_inline void gen_qemu_st32(TCGv arg0, TCGv arg1, int flags)
2633 {
2634 if (unlikely(flags & 1)) {
2635 TCGv_i32 t0;
2636 TCGv_i64 t1;
2637 t0 = tcg_temp_new_i32();
2638 tcg_gen_trunc_tl_i32(t0, arg0);
2639 tcg_gen_bswap_i32(t0, t0);
2640 t1 = tcg_temp_new_i64();
2641 tcg_gen_extu_i32_tl(t1, t0);
2642 tcg_temp_free_i32(t0);
2643 gen_qemu_st32_ppc64(t1, arg1, flags);
2644 tcg_temp_free_i64(t1);
2645 } else
2646 gen_qemu_st32_ppc64(arg0, arg1, flags);
2647 }
2648
2649 static always_inline void gen_qemu_st64(TCGv arg0, TCGv arg1, int flags)
2650 {
2651 if (unlikely(flags & 1)) {
2652 TCGv_i64 t0 = tcg_temp_new_i64();
2653 tcg_gen_bswap_i64(t0, arg0);
2654 gen_qemu_st64_ppc64(t0, arg1, flags);
2655 tcg_temp_free_i64(t0);
2656 } else
2657 gen_qemu_st64_ppc64(arg0, arg1, flags);
2658 }
2659
2660
2661 #else /* defined(TARGET_PPC64) */
2662 #define GEN_QEMU_LD_PPC32(width) \
2663 static always_inline void gen_qemu_ld##width##_ppc32(TCGv arg0, TCGv arg1, int flags) \
2664 { \
2665 tcg_gen_qemu_ld##width(arg0, arg1, flags >> 1); \
2666 }
2667 GEN_QEMU_LD_PPC32(8u)
2668 GEN_QEMU_LD_PPC32(8s)
2669 GEN_QEMU_LD_PPC32(16u)
2670 GEN_QEMU_LD_PPC32(16s)
2671 GEN_QEMU_LD_PPC32(32u)
2672 GEN_QEMU_LD_PPC32(32s)
2673 static always_inline void gen_qemu_ld64_ppc32(TCGv_i64 arg0, TCGv arg1, int flags)
2674 {
2675 tcg_gen_qemu_ld64(arg0, arg1, flags >> 1);
2676 }
2677
2678 #define GEN_QEMU_ST_PPC32(width) \
2679 static always_inline void gen_qemu_st##width##_ppc32(TCGv arg0, TCGv arg1, int flags) \
2680 { \
2681 tcg_gen_qemu_st##width(arg0, arg1, flags >> 1); \
2682 }
2683 GEN_QEMU_ST_PPC32(8)
2684 GEN_QEMU_ST_PPC32(16)
2685 GEN_QEMU_ST_PPC32(32)
2686 static always_inline void gen_qemu_st64_ppc32(TCGv_i64 arg0, TCGv arg1, int flags)
2687 {
2688 tcg_gen_qemu_st64(arg0, arg1, flags >> 1);
2689 }
2690
2691 static always_inline void gen_qemu_ld8u(TCGv arg0, TCGv arg1, int flags)
2692 {
2693 gen_qemu_ld8u_ppc32(arg0, arg1, flags >> 1);
2694 }
2695
2696 static always_inline void gen_qemu_ld8s(TCGv arg0, TCGv arg1, int flags)
2697 {
2698 gen_qemu_ld8s_ppc32(arg0, arg1, flags >> 1);
2699 }
2700
2701 static always_inline void gen_qemu_ld16u(TCGv arg0, TCGv arg1, int flags)
2702 {
2703 gen_qemu_ld16u_ppc32(arg0, arg1, flags >> 1);
2704 if (unlikely(flags & 1))
2705 tcg_gen_bswap16_i32(arg0, arg0);
2706 }
2707
2708 static always_inline void gen_qemu_ld16s(TCGv arg0, TCGv arg1, int flags)
2709 {
2710 if (unlikely(flags & 1)) {
2711 gen_qemu_ld16u_ppc32(arg0, arg1, flags);
2712 tcg_gen_bswap16_i32(arg0, arg0);
2713 tcg_gen_ext16s_i32(arg0, arg0);
2714 } else
2715 gen_qemu_ld16s_ppc32(arg0, arg1, flags);
2716 }
2717
2718 static always_inline void gen_qemu_ld32u(TCGv arg0, TCGv arg1, int flags)
2719 {
2720 gen_qemu_ld32u_ppc32(arg0, arg1, flags);
2721 if (unlikely(flags & 1))
2722 tcg_gen_bswap_i32(arg0, arg0);
2723 }
2724
2725 static always_inline void gen_qemu_ld64(TCGv_i64 arg0, TCGv arg1, int flags)
2726 {
2727 gen_qemu_ld64_ppc32(arg0, arg1, flags);
2728 if (unlikely(flags & 1))
2729 tcg_gen_bswap_i64(arg0, arg0);
2730 }
2731
2732 static always_inline void gen_qemu_st8(TCGv arg0, TCGv arg1, int flags)
2733 {
2734 gen_qemu_st8_ppc32(arg0, arg1, flags);
2735 }
2736
2737 static always_inline void gen_qemu_st16(TCGv arg0, TCGv arg1, int flags)
2738 {
2739 if (unlikely(flags & 1)) {
2740 TCGv_i32 temp = tcg_temp_new_i32();
2741 tcg_gen_ext16u_i32(temp, arg0);
2742 tcg_gen_bswap16_i32(temp, temp);
2743 gen_qemu_st16_ppc32(temp, arg1, flags);
2744 tcg_temp_free_i32(temp);
2745 } else
2746 gen_qemu_st16_ppc32(arg0, arg1, flags);
2747 }
2748
2749 static always_inline void gen_qemu_st32(TCGv arg0, TCGv arg1, int flags)
2750 {
2751 if (unlikely(flags & 1)) {
2752 TCGv_i32 temp = tcg_temp_new_i32();
2753 tcg_gen_bswap_i32(temp, arg0);
2754 gen_qemu_st32_ppc32(temp, arg1, flags);
2755 tcg_temp_free_i32(temp);
2756 } else
2757 gen_qemu_st32_ppc32(arg0, arg1, flags);
2758 }
2759
2760 static always_inline void gen_qemu_st64(TCGv_i64 arg0, TCGv arg1, int flags)
2761 {
2762 if (unlikely(flags & 1)) {
2763 TCGv_i64 temp = tcg_temp_new_i64();
2764 tcg_gen_bswap_i64(temp, arg0);
2765 gen_qemu_st64_ppc32(temp, arg1, flags);
2766 tcg_temp_free_i64(temp);
2767 } else
2768 gen_qemu_st64_ppc32(arg0, arg1, flags);
2769 }
2770 #endif
2771
2772 #define GEN_LD(name, ldop, opc, type) \
2773 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
2774 { \
2775 TCGv EA = tcg_temp_new(); \
2776 gen_set_access_type(ACCESS_INT); \
2777 gen_addr_imm_index(EA, ctx, 0); \
2778 gen_qemu_##ldop(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
2779 tcg_temp_free(EA); \
2780 }
2781
2782 #define GEN_LDU(name, ldop, opc, type) \
2783 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2784 { \
2785 TCGv EA; \
2786 if (unlikely(rA(ctx->opcode) == 0 || \
2787 rA(ctx->opcode) == rD(ctx->opcode))) { \
2788 GEN_EXCP_INVAL(ctx); \
2789 return; \
2790 } \
2791 EA = tcg_temp_new(); \
2792 gen_set_access_type(ACCESS_INT); \
2793 if (type == PPC_64B) \
2794 gen_addr_imm_index(EA, ctx, 0x03); \
2795 else \
2796 gen_addr_imm_index(EA, ctx, 0); \
2797 gen_qemu_##ldop(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
2798 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2799 tcg_temp_free(EA); \
2800 }
2801
2802 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2803 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2804 { \
2805 TCGv EA; \
2806 if (unlikely(rA(ctx->opcode) == 0 || \
2807 rA(ctx->opcode) == rD(ctx->opcode))) { \
2808 GEN_EXCP_INVAL(ctx); \
2809 return; \
2810 } \
2811 EA = tcg_temp_new(); \
2812 gen_set_access_type(ACCESS_INT); \
2813 gen_addr_reg_index(EA, ctx); \
2814 gen_qemu_##ldop(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
2815 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2816 tcg_temp_free(EA); \
2817 }
2818
2819 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2820 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
2821 { \
2822 TCGv EA = tcg_temp_new(); \
2823 gen_set_access_type(ACCESS_INT); \
2824 gen_addr_reg_index(EA, ctx); \
2825 gen_qemu_##ldop(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
2826 tcg_temp_free(EA); \
2827 }
2828
2829 #define GEN_LDS(name, ldop, op, type) \
2830 GEN_LD(name, ldop, op | 0x20, type); \
2831 GEN_LDU(name, ldop, op | 0x21, type); \
2832 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2833 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2834
2835 /* lbz lbzu lbzux lbzx */
2836 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2837 /* lha lhau lhaux lhax */
2838 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2839 /* lhz lhzu lhzux lhzx */
2840 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2841 /* lwz lwzu lwzux lwzx */
2842 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2843 #if defined(TARGET_PPC64)
2844 /* lwaux */
2845 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2846 /* lwax */
2847 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2848 /* ldux */
2849 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2850 /* ldx */
2851 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2852 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
2853 {
2854 TCGv EA;
2855 if (Rc(ctx->opcode)) {
2856 if (unlikely(rA(ctx->opcode) == 0 ||
2857 rA(ctx->opcode) == rD(ctx->opcode))) {
2858 GEN_EXCP_INVAL(ctx);
2859 return;
2860 }
2861 }
2862 EA = tcg_temp_new();
2863 gen_set_access_type(ACCESS_INT);
2864 gen_addr_imm_index(EA, ctx, 0x03);
2865 if (ctx->opcode & 0x02) {
2866 /* lwa (lwau is undefined) */
2867 gen_qemu_ld32s(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx);
2868 } else {
2869 /* ld - ldu */
2870 gen_qemu_ld64(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx);
2871 }
2872 if (Rc(ctx->opcode))
2873 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2874 tcg_temp_free(EA);
2875 }
2876 /* lq */
2877 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2878 {
2879 #if defined(CONFIG_USER_ONLY)
2880 GEN_EXCP_PRIVOPC(ctx);
2881 #else
2882 int ra, rd;
2883 TCGv EA;
2884
2885 /* Restore CPU state */
2886 if (unlikely(ctx->supervisor == 0)) {
2887 GEN_EXCP_PRIVOPC(ctx);
2888 return;
2889 }
2890 ra = rA(ctx->opcode);
2891 rd = rD(ctx->opcode);
2892 if (unlikely((rd & 1) || rd == ra)) {
2893 GEN_EXCP_INVAL(ctx);
2894 return;
2895 }
2896 if (unlikely(ctx->mem_idx & 1)) {
2897 /* Little-endian mode is not handled */
2898 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2899 return;
2900 }
2901 EA = tcg_temp_new();
2902 gen_set_access_type(ACCESS_INT);
2903 gen_addr_imm_index(EA, ctx, 0x0F);
2904 gen_qemu_ld64(cpu_gpr[rd], EA, ctx->mem_idx);
2905 tcg_gen_addi_tl(EA, EA, 8);
2906 gen_qemu_ld64(cpu_gpr[rd+1], EA, ctx->mem_idx);
2907 tcg_temp_free(EA);
2908 #endif
2909 }
2910 #endif
2911
2912 /*** Integer store ***/
2913 #define GEN_ST(name, stop, opc, type) \
2914 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
2915 { \
2916 TCGv EA = tcg_temp_new(); \
2917 gen_set_access_type(ACCESS_INT); \
2918 gen_addr_imm_index(EA, ctx, 0); \
2919 gen_qemu_##stop(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
2920 tcg_temp_free(EA); \
2921 }
2922
2923 #define GEN_STU(name, stop, opc, type) \
2924 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2925 { \
2926 TCGv EA; \
2927 if (unlikely(rA(ctx->opcode) == 0)) { \
2928 GEN_EXCP_INVAL(ctx); \
2929 return; \
2930 } \
2931 EA = tcg_temp_new(); \
2932 gen_set_access_type(ACCESS_INT); \
2933 if (type == PPC_64B) \
2934 gen_addr_imm_index(EA, ctx, 0x03); \
2935 else \
2936 gen_addr_imm_index(EA, ctx, 0); \
2937 gen_qemu_##stop(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
2938 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2939 tcg_temp_free(EA); \
2940 }
2941
2942 #define GEN_STUX(name, stop, opc2, opc3, type) \
2943 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2944 { \
2945 TCGv EA; \
2946 if (unlikely(rA(ctx->opcode) == 0)) { \
2947 GEN_EXCP_INVAL(ctx); \
2948 return; \
2949 } \
2950 EA = tcg_temp_new(); \
2951 gen_set_access_type(ACCESS_INT); \
2952 gen_addr_reg_index(EA, ctx); \
2953 gen_qemu_##stop(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
2954 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2955 tcg_temp_free(EA); \
2956 }
2957
2958 #define GEN_STX(name, stop, opc2, opc3, type) \
2959 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
2960 { \
2961 TCGv EA = tcg_temp_new(); \
2962 gen_set_access_type(ACCESS_INT); \
2963 gen_addr_reg_index(EA, ctx); \
2964 gen_qemu_##stop(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
2965 tcg_temp_free(EA); \
2966 }
2967
2968 #define GEN_STS(name, stop, op, type) \
2969 GEN_ST(name, stop, op | 0x20, type); \
2970 GEN_STU(name, stop, op | 0x21, type); \
2971 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2972 GEN_STX(name, stop, 0x17, op | 0x00, type)
2973
2974 /* stb stbu stbux stbx */
2975 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2976 /* sth sthu sthux sthx */
2977 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2978 /* stw stwu stwux stwx */
2979 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2980 #if defined(TARGET_PPC64)
2981 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2982 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2983 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
2984 {
2985 int rs;
2986 TCGv EA;
2987
2988 rs = rS(ctx->opcode);
2989 if ((ctx->opcode & 0x3) == 0x2) {
2990 #if defined(CONFIG_USER_ONLY)
2991 GEN_EXCP_PRIVOPC(ctx);
2992 #else
2993 /* stq */
2994 if (unlikely(ctx->supervisor == 0)) {
2995 GEN_EXCP_PRIVOPC(ctx);
2996 return;
2997 }
2998 if (unlikely(rs & 1)) {
2999 GEN_EXCP_INVAL(ctx);
3000 return;
3001 }
3002 if (unlikely(ctx->mem_idx & 1)) {
3003 /* Little-endian mode is not handled */
3004 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
3005 return;
3006 }
3007 EA = tcg_temp_new();
3008 gen_set_access_type(ACCESS_INT);
3009 gen_addr_imm_index(EA, ctx, 0x03);
3010 gen_qemu_st64(cpu_gpr[rs], EA, ctx->mem_idx);
3011 tcg_gen_addi_tl(EA, EA, 8);
3012 gen_qemu_st64(cpu_gpr[rs+1], EA, ctx->mem_idx);
3013 tcg_temp_free(EA);
3014 #endif
3015 } else {
3016 /* std / stdu */
3017 if (Rc(ctx->opcode)) {
3018 if (unlikely(rA(ctx->opcode) == 0)) {
3019 GEN_EXCP_INVAL(ctx);
3020 return;
3021 }
3022 }
3023 EA = tcg_temp_new();
3024 gen_set_access_type(ACCESS_INT);
3025 gen_addr_imm_index(EA, ctx, 0x03);
3026 gen_qemu_st64(cpu_gpr[rs], EA, ctx->mem_idx);
3027 if (Rc(ctx->opcode))
3028 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
3029 tcg_temp_free(EA);
3030 }
3031 }
3032 #endif
3033 /*** Integer load and store with byte reverse ***/
3034 /* lhbrx */
3035 void always_inline gen_qemu_ld16ur(TCGv t0, TCGv t1, int flags)
3036 {
3037 TCGv_i32 temp = tcg_temp_new_i32();
3038 gen_qemu_ld16u(t0, t1, flags);
3039 tcg_gen_trunc_tl_i32(temp, t0);
3040 tcg_gen_bswap16_i32(temp, temp);
3041 tcg_gen_extu_i32_tl(t0, temp);
3042 tcg_temp_free_i32(temp);
3043 }
3044 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
3045
3046 /* lwbrx */
3047 void always_inline gen_qemu_ld32ur(TCGv t0, TCGv t1, int flags)
3048 {
3049 TCGv_i32 temp = tcg_temp_new_i32();
3050 gen_qemu_ld32u(t0, t1, flags);
3051 tcg_gen_trunc_tl_i32(temp, t0);
3052 tcg_gen_bswap_i32(temp, temp);
3053 tcg_gen_extu_i32_tl(t0, temp);
3054 tcg_temp_free_i32(temp);
3055 }
3056 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
3057
3058 /* sthbrx */
3059 void always_inline gen_qemu_st16r(TCGv t0, TCGv t1, int flags)
3060 {
3061 TCGv_i32 temp = tcg_temp_new_i32();
3062 TCGv t2 = tcg_temp_new();
3063 tcg_gen_trunc_tl_i32(temp, t0);
3064 tcg_gen_ext16u_i32(temp, temp);
3065 tcg_gen_bswap16_i32(temp, temp);
3066 tcg_gen_extu_i32_tl(t2, temp);
3067 tcg_temp_free_i32(temp);
3068 gen_qemu_st16(t2, t1, flags);
3069 tcg_temp_free(t2);
3070 }
3071 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
3072
3073 /* stwbrx */
3074 void always_inline gen_qemu_st32r(TCGv t0, TCGv t1, int flags)
3075 {
3076 TCGv_i32 temp = tcg_temp_new_i32();
3077 TCGv t2 = tcg_temp_new();
3078 tcg_gen_trunc_tl_i32(temp, t0);
3079 tcg_gen_bswap_i32(temp, temp);
3080 tcg_gen_extu_i32_tl(t2, temp);
3081 tcg_temp_free_i32(temp);
3082 gen_qemu_st32(t2, t1, flags);
3083 tcg_temp_free(t2);
3084 }
3085 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
3086
3087 /*** Integer load and store multiple ***/
3088 /* lmw */
3089 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3090 {
3091 TCGv t0 = tcg_temp_new();
3092 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
3093 /* NIP cannot be restored if the memory exception comes from an helper */
3094 gen_update_nip(ctx, ctx->nip - 4);
3095 gen_addr_imm_index(t0, ctx, 0);
3096 gen_helper_lmw(t0, t1);
3097 tcg_temp_free(t0);
3098 tcg_temp_free_i32(t1);
3099 }
3100
3101 /* stmw */
3102 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3103 {
3104 TCGv t0 = tcg_temp_new();
3105 TCGv_i32 t1 = tcg_const_i32(rS(ctx->opcode));
3106 /* NIP cannot be restored if the memory exception comes from an helper */
3107 gen_update_nip(ctx, ctx->nip - 4);
3108 gen_addr_imm_index(t0, ctx, 0);
3109 gen_helper_stmw(t0, t1);
3110 tcg_temp_free(t0);
3111 tcg_temp_free_i32(t1);
3112 }
3113
3114 /*** Integer load and store strings ***/
3115 /* lswi */
3116 /* PowerPC32 specification says we must generate an exception if
3117 * rA is in the range of registers to be loaded.
3118 * In an other hand, IBM says this is valid, but rA won't be loaded.
3119 * For now, I'll follow the spec...
3120 */
3121 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING)
3122 {
3123 TCGv t0;
3124 TCGv_i32 t1, t2;
3125 int nb = NB(ctx->opcode);
3126 int start = rD(ctx->opcode);
3127 int ra = rA(ctx->opcode);
3128 int nr;
3129
3130 if (nb == 0)
3131 nb = 32;
3132 nr = nb / 4;
3133 if (unlikely(((start + nr) > 32 &&
3134 start <= ra && (start + nr - 32) > ra) ||
3135 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
3136 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3137 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_LSWX);
3138 return;
3139 }
3140 /* NIP cannot be restored if the memory exception comes from an helper */
3141 gen_update_nip(ctx, ctx->nip - 4);
3142 t0 = tcg_temp_new();
3143 gen_addr_register(t0, ctx);
3144 t1 = tcg_const_i32(nb);
3145 t2 = tcg_const_i32(start);
3146 gen_helper_lsw(t0, t1, t2);
3147 tcg_temp_free(t0);
3148 tcg_temp_free_i32(t1);
3149 tcg_temp_free_i32(t2);
3150 }
3151
3152 /* lswx */
3153 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING)
3154 {
3155 TCGv t0 = tcg_temp_new();
3156 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
3157 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
3158 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
3159 /* NIP cannot be restored if the memory exception comes from an helper */
3160 gen_update_nip(ctx, ctx->nip - 4);
3161 gen_addr_reg_index(t0, ctx);
3162 gen_helper_lswx(t0, t1, t2, t3);
3163 tcg_temp_free(t0);
3164 tcg_temp_free_i32(t1);
3165 tcg_temp_free_i32(t2);
3166 tcg_temp_free_i32(t3);
3167 }
3168
3169 /* stswi */
3170 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING)
3171 {
3172 int nb = NB(ctx->opcode);
3173 TCGv t0 = tcg_temp_new();
3174 TCGv_i32 t1;
3175 TCGv_i32 t2 = tcg_const_i32(rS(ctx->opcode));
3176 /* NIP cannot be restored if the memory exception comes from an helper */
3177 gen_update_nip(ctx, ctx->nip - 4);
3178 gen_addr_register(t0, ctx);
3179 if (nb == 0)
3180 nb = 32;
3181 t1 = tcg_const_i32(nb);
3182 gen_helper_stsw(t0, t1, t2);
3183 tcg_temp_free(t0);
3184 tcg_temp_free_i32(t1);
3185 tcg_temp_free_i32(t2);
3186 }
3187
3188 /* stswx */
3189 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING)
3190 {
3191 TCGv t0 = tcg_temp_new();
3192 TCGv_i32 t1 = tcg_temp_new_i32();
3193 TCGv_i32 t2 = tcg_const_i32(rS(ctx->opcode));
3194 /* NIP cannot be restored if the memory exception comes from an helper */
3195 gen_update_nip(ctx, ctx->nip - 4);
3196 gen_addr_reg_index(t0, ctx);
3197 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3198 tcg_gen_andi_i32(t1, t1, 0x7F);
3199 gen_helper_stsw(t0, t1, t2);
3200 tcg_temp_free(t0);
3201 tcg_temp_free_i32(t1);
3202 tcg_temp_free_i32(t2);
3203 }
3204
3205 /*** Memory synchronisation ***/
3206 /* eieio */
3207 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO)
3208 {
3209 }
3210
3211 /* isync */
3212 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM)
3213 {
3214 GEN_STOP(ctx);
3215 }
3216
3217 /* lwarx */
3218 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
3219 {
3220 TCGv t0 = tcg_temp_local_new();
3221 gen_set_access_type(ACCESS_RES);
3222 gen_addr_reg_index(t0, ctx);
3223 gen_check_align(ctx, t0, 0x03);
3224 #if defined(TARGET_PPC64)
3225 if (!ctx->sf_mode)
3226 tcg_gen_ext32u_tl(t0, t0);
3227 #endif
3228 gen_qemu_ld32u(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx);
3229 tcg_gen_mov_tl(cpu_reserve, t0);
3230 tcg_temp_free(t0);
3231 }
3232
3233 /* stwcx. */
3234 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
3235 {
3236 int l1 = gen_new_label();
3237 TCGv t0 = tcg_temp_local_new();
3238 gen_set_access_type(ACCESS_RES);
3239 gen_addr_reg_index(t0, ctx);
3240 gen_check_align(ctx, t0, 0x03);
3241 #if defined(TARGET_PPC64)
3242 if (!ctx->sf_mode)
3243 tcg_gen_ext32u_tl(t0, t0);
3244 #endif
3245 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3246 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3247 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
3248 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3249 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3250 gen_qemu_st32(cpu_gpr[rS(ctx->opcode)], t0, ctx->mem_idx);
3251 gen_set_label(l1);
3252 tcg_gen_movi_tl(cpu_reserve, -1);
3253 tcg_temp_free(t0);
3254 }
3255
3256 #if defined(TARGET_PPC64)
3257 /* ldarx */
3258 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
3259 {
3260 TCGv t0 = tcg_temp_local_new();
3261 gen_set_access_type(ACCESS_RES);
3262 gen_addr_reg_index(t0, ctx);
3263 gen_check_align(ctx, t0, 0x07);
3264 if (!ctx->sf_mode)
3265 tcg_gen_ext32u_tl(t0, t0);
3266 gen_qemu_ld64(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx);
3267 tcg_gen_mov_tl(cpu_reserve, t0);
3268 tcg_temp_free(t0);
3269 }
3270
3271 /* stdcx. */
3272 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
3273 {
3274 int l1 = gen_new_label();
3275 TCGv t0 = tcg_temp_local_new();
3276 gen_set_access_type(ACCESS_RES);
3277 gen_addr_reg_index(t0, ctx);
3278 gen_check_align(ctx, t0, 0x07);
3279 if (!ctx->sf_mode)
3280 tcg_gen_ext32u_tl(t0, t0);
3281 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3282 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3283 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
3284 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3285 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3286 gen_qemu_st64(cpu_gpr[rS(ctx->opcode)], t0, ctx->mem_idx);
3287 gen_set_label(l1);
3288 tcg_gen_movi_tl(cpu_reserve, -1);
3289 tcg_temp_free(t0);
3290 }
3291 #endif /* defined(TARGET_PPC64) */
3292
3293 /* sync */
3294 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC)
3295 {
3296 }
3297
3298 /* wait */
3299 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT)
3300 {
3301 TCGv_i32 t0 = tcg_temp_new_i32();
3302 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, halted));
3303 tcg_temp_free_i32(t0);
3304 /* Stop translation, as the CPU is supposed to sleep from now */
3305 GEN_EXCP(ctx, EXCP_HLT, 1);
3306 }
3307
3308 /*** Floating-point load ***/
3309 #define GEN_LDF(name, ldop, opc, type) \
3310 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
3311 { \
3312 TCGv EA; \
3313 if (unlikely(!ctx->fpu_enabled)) { \
3314 GEN_EXCP_NO_FP(ctx); \
3315 return; \
3316 } \
3317 gen_set_access_type(ACCESS_FLOAT); \
3318 EA = tcg_temp_new(); \
3319 gen_addr_imm_index(EA, ctx, 0); \
3320 gen_qemu_##ldop(cpu_fpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
3321 tcg_temp_free(EA); \
3322 }
3323
3324 #define GEN_LDUF(name, ldop, opc, type) \
3325 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
3326 { \
3327 TCGv EA; \
3328 if (unlikely(!ctx->fpu_enabled)) { \
3329 GEN_EXCP_NO_FP(ctx); \
3330 return; \
3331 } \
3332 if (unlikely(rA(ctx->opcode) == 0)) { \
3333 GEN_EXCP_INVAL(ctx); \
3334 return; \
3335 } \
3336 gen_set_access_type(ACCESS_FLOAT); \
3337 EA = tcg_temp_new(); \
3338 gen_addr_imm_index(EA, ctx, 0); \
3339 gen_qemu_##ldop(cpu_fpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
3340 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3341 tcg_temp_free(EA); \
3342 }
3343
3344 #define GEN_LDUXF(name, ldop, opc, type) \
3345 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \
3346 { \
3347 TCGv EA; \
3348 if (unlikely(!ctx->fpu_enabled)) { \
3349 GEN_EXCP_NO_FP(ctx); \
3350 return; \
3351 } \
3352 if (unlikely(rA(ctx->opcode) == 0)) { \
3353 GEN_EXCP_INVAL(ctx); \
3354 return; \
3355 } \
3356 gen_set_access_type(ACCESS_FLOAT); \
3357 EA = tcg_temp_new(); \
3358 gen_addr_reg_index(EA, ctx); \
3359 gen_qemu_##ldop(cpu_fpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
3360 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3361 tcg_temp_free(EA); \
3362 }
3363
3364 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3365 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
3366 { \
3367 TCGv EA; \
3368 if (unlikely(!ctx->fpu_enabled)) { \
3369 GEN_EXCP_NO_FP(ctx); \
3370 return; \
3371 } \
3372 gen_set_access_type(ACCESS_FLOAT); \
3373 EA = tcg_temp_new(); \
3374 gen_addr_reg_index(EA, ctx); \
3375 gen_qemu_##ldop(cpu_fpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
3376 tcg_temp_free(EA); \
3377 }
3378
3379 #define GEN_LDFS(name, ldop, op, type) \
3380 GEN_LDF(name, ldop, op | 0x20, type); \
3381 GEN_LDUF(name, ldop, op | 0x21, type); \
3382 GEN_LDUXF(name, ldop, op | 0x01, type); \
3383 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3384
3385 static always_inline void gen_qemu_ld32fs(TCGv_i64 arg1, TCGv arg2, int flags)
3386 {
3387 TCGv t0 = tcg_temp_new();
3388 TCGv_i32 t1 = tcg_temp_new_i32();
3389 gen_qemu_ld32u(t0, arg2, flags);
3390 tcg_gen_trunc_tl_i32(t1, t0);
3391 tcg_temp_free(t0);
3392 gen_helper_float32_to_float64(arg1, t1);
3393 tcg_temp_free_i32(t1);
3394 }
3395
3396 /* lfd lfdu lfdux lfdx */
3397 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3398 /* lfs lfsu lfsux lfsx */
3399 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3400
3401 /*** Floating-point store ***/
3402 #define GEN_STF(name, stop, opc, type) \
3403 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
3404 { \
3405 TCGv EA; \
3406 if (unlikely(!ctx->fpu_enabled)) { \
3407 GEN_EXCP_NO_FP(ctx); \
3408 return; \
3409 } \
3410 gen_set_access_type(ACCESS_FLOAT); \
3411 EA = tcg_temp_new(); \
3412 gen_addr_imm_index(EA, ctx, 0); \
3413 gen_qemu_##stop(cpu_fpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
3414 tcg_temp_free(EA); \
3415 }
3416
3417 #define GEN_STUF(name, stop, opc, type) \
3418 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
3419 { \
3420 TCGv EA; \
3421 if (unlikely(!ctx->fpu_enabled)) { \
3422 GEN_EXCP_NO_FP(ctx); \
3423 return; \
3424 } \
3425 if (unlikely(rA(ctx->opcode) == 0)) { \
3426 GEN_EXCP_INVAL(ctx); \
3427 return; \
3428 } \
3429 gen_set_access_type(ACCESS_FLOAT); \
3430 EA = tcg_temp_new(); \
3431 gen_addr_imm_index(EA, ctx, 0); \
3432 gen_qemu_##stop(cpu_fpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
3433 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3434 tcg_temp_free(EA); \
3435 }
3436
3437 #define GEN_STUXF(name, stop, opc, type) \
3438 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \
3439 { \
3440 TCGv EA; \
3441 if (unlikely(!ctx->fpu_enabled)) { \
3442 GEN_EXCP_NO_FP(ctx); \
3443 return; \
3444 } \
3445 if (unlikely(rA(ctx->opcode) == 0)) { \
3446 GEN_EXCP_INVAL(ctx); \
3447 return; \
3448 } \
3449 gen_set_access_type(ACCESS_FLOAT); \
3450 EA = tcg_temp_new(); \
3451 gen_addr_reg_index(EA, ctx); \
3452 gen_qemu_##stop(cpu_fpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
3453 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3454 tcg_temp_free(EA); \
3455 }
3456
3457 #define GEN_STXF(name, stop, opc2, opc3, type) \
3458 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
3459 { \
3460 TCGv EA; \
3461 if (unlikely(!ctx->fpu_enabled)) { \
3462 GEN_EXCP_NO_FP(ctx); \
3463 return; \
3464 } \
3465 gen_set_access_type(ACCESS_FLOAT); \
3466 EA = tcg_temp_new(); \
3467 gen_addr_reg_index(EA, ctx); \
3468 gen_qemu_##stop(cpu_fpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
3469 tcg_temp_free(EA); \
3470 }
3471
3472 #define GEN_STFS(name, stop, op, type) \
3473 GEN_STF(name, stop, op | 0x20, type); \
3474 GEN_STUF(name, stop, op | 0x21, type); \
3475 GEN_STUXF(name, stop, op | 0x01, type); \
3476 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3477
3478 static always_inline void gen_qemu_st32fs(TCGv_i64 arg1, TCGv arg2, int flags)
3479 {
3480 TCGv_i32 t0 = tcg_temp_new_i32();
3481 TCGv t1 = tcg_temp_new();
3482 gen_helper_float64_to_float32(t0, arg1);
3483 tcg_gen_extu_i32_tl(t1, t0);
3484 tcg_temp_free_i32(t0);
3485 gen_qemu_st32(t1, arg2, flags);
3486 tcg_temp_free(t1);
3487 }
3488
3489 /* stfd stfdu stfdux stfdx */
3490 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3491 /* stfs stfsu stfsux stfsx */
3492 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3493
3494 /* Optional: */
3495 static always_inline void gen_qemu_st32fiw(TCGv_i64 arg1, TCGv arg2, int flags)
3496 {
3497 TCGv t0 = tcg_temp_new();
3498 tcg_gen_trunc_i64_tl(t0, arg1),
3499 gen_qemu_st32(t0, arg2, flags);
3500 tcg_temp_free(t0);
3501 }
3502 /* stfiwx */
3503 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3504
3505 /*** Branch ***/
3506 static always_inline void gen_goto_tb (DisasContext *ctx, int n,
3507 target_ulong dest)
3508 {
3509 TranslationBlock *tb;
3510 tb = ctx->tb;
3511 #if defined(TARGET_PPC64)
3512 if (!ctx->sf_mode)
3513 dest = (uint32_t) dest;
3514 #endif
3515 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3516 likely(!ctx->singlestep_enabled)) {
3517 tcg_gen_goto_tb(n);
3518 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3519 tcg_gen_exit_tb((long)tb + n);
3520 } else {
3521 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3522 if (unlikely(ctx->singlestep_enabled)) {
3523 if ((ctx->singlestep_enabled &
3524 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3525 ctx->exception == POWERPC_EXCP_BRANCH) {
3526 target_ulong tmp = ctx->nip;
3527 ctx->nip = dest;
3528 GEN_EXCP(ctx, POWERPC_EXCP_TRACE, 0);
3529 ctx->nip = tmp;
3530 }
3531 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3532 gen_update_nip(ctx, dest);
3533 gen_helper_raise_debug();
3534 }
3535 }
3536 tcg_gen_exit_tb(0);
3537 }
3538 }
3539
3540 static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip)
3541 {
3542 #if defined(TARGET_PPC64)
3543 if (ctx->sf_mode == 0)
3544 tcg_gen_movi_tl(cpu_lr, (uint32_t)nip);
3545 else
3546 #endif
3547 tcg_gen_movi_tl(cpu_lr, nip);
3548 }
3549
3550 /* b ba bl bla */
3551 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3552 {
3553 target_ulong li, target;
3554
3555 ctx->exception = POWERPC_EXCP_BRANCH;
3556 /* sign extend LI */
3557 #if defined(TARGET_PPC64)
3558 if (ctx->sf_mode)
3559 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3560 else
3561 #endif
3562 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
3563 if (likely(AA(ctx->opcode) == 0))
3564 target = ctx->nip + li - 4;
3565 else
3566 target = li;
3567 if (LK(ctx->opcode))
3568 gen_setlr(ctx, ctx->nip);
3569 gen_goto_tb(ctx, 0, target);
3570 }
3571
3572 #define BCOND_IM 0
3573 #define BCOND_LR 1
3574 #define BCOND_CTR 2
3575
3576 static always_inline void gen_bcond (DisasContext *ctx, int type)
3577 {
3578 uint32_t bo = BO(ctx->opcode);
3579 int l1 = gen_new_label();
3580 TCGv target;
3581
3582 ctx->exception = POWERPC_EXCP_BRANCH;
3583 if (type == BCOND_LR || type == BCOND_CTR) {
3584 target = tcg_temp_local_new();
3585 if (type == BCOND_CTR)
3586 tcg_gen_mov_tl(target, cpu_ctr);
3587 else
3588 tcg_gen_mov_tl(target, cpu_lr);
3589 }
3590 if (LK(ctx->opcode))
3591 gen_setlr(ctx, ctx->nip);
3592 l1 = gen_new_label();
3593 if ((bo & 0x4) == 0) {
3594 /* Decrement and test CTR */
3595 TCGv temp = tcg_temp_new();
3596 if (unlikely(type == BCOND_CTR)) {
3597 GEN_EXCP_INVAL(ctx);
3598 return;
3599 }
3600 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3601 #if defined(TARGET_PPC64)
3602 if (!ctx->sf_mode)
3603 tcg_gen_ext32u_tl(temp, cpu_ctr);
3604 else
3605 #endif
3606 tcg_gen_mov_tl(temp, cpu_ctr);
3607 if (bo & 0x2) {
3608 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3609 } else {
3610 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3611 }
3612 tcg_temp_free(temp);
3613 }
3614 if ((bo & 0x10) == 0) {
3615 /* Test CR */
3616 uint32_t bi = BI(ctx->opcode);
3617 uint32_t mask = 1 << (3 - (bi & 0x03));
3618 TCGv_i32 temp = tcg_temp_new_i32();
3619
3620 if (bo & 0x8) {
3621 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3622 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3623 } else {
3624 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3625 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3626 }
3627 tcg_temp_free_i32(temp);
3628 }
3629 if (type == BCOND_IM) {
3630 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3631 if (likely(AA(ctx->opcode) == 0)) {
3632 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3633 } else {
3634 gen_goto_tb(ctx, 0, li);
3635 }
3636 gen_set_label(l1);
3637 gen_goto_tb(ctx, 1, ctx->nip);
3638 } else {
3639 #if defined(TARGET_PPC64)
3640 if (!(ctx->sf_mode))
3641 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3642 else
3643 #endif
3644 tcg_gen_andi_tl(cpu_nip, target, ~3);
3645 tcg_gen_exit_tb(0);
3646 gen_set_label(l1);
3647 #if defined(TARGET_PPC64)
3648 if (!(ctx->sf_mode))
3649 tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip);
3650 else
3651 #endif
3652 tcg_gen_movi_tl(cpu_nip, ctx->nip);
3653 tcg_gen_exit_tb(0);
3654 }
3655 }
3656
3657 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3658 {
3659 gen_bcond(ctx, BCOND_IM);
3660 }
3661
3662 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
3663 {
3664 gen_bcond(ctx, BCOND_CTR);
3665 }
3666
3667 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
3668 {
3669 gen_bcond(ctx, BCOND_LR);
3670 }
3671
3672 /*** Condition register logical ***/
3673 #define GEN_CRLOGIC(name, tcg_op, opc) \
3674 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
3675 { \
3676 uint8_t bitmask; \
3677 int sh; \
3678 TCGv_i32 t0, t1; \
3679 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3680 t0 = tcg_temp_new_i32(); \
3681 if (sh > 0) \
3682 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3683 else if (sh < 0) \
3684 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3685 else \
3686 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3687 t1 = tcg_temp_new_i32(); \
3688 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3689 if (sh > 0) \
3690 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3691 else if (sh < 0) \
3692 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3693 else \
3694 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3695 tcg_op(t0, t0, t1); \
3696 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3697 tcg_gen_andi_i32(t0, t0, bitmask); \
3698 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3699 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3700 tcg_temp_free_i32(t0); \
3701 tcg_temp_free_i32(t1); \
3702 }
3703
3704 /* crand */
3705 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3706 /* crandc */
3707 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3708 /* creqv */
3709 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3710 /* crnand */
3711 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3712 /* crnor */
3713 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3714 /* cror */
3715 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3716 /* crorc */
3717 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3718 /* crxor */
3719 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3720 /* mcrf */
3721 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
3722 {
3723 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3724 }
3725
3726 /*** System linkage ***/
3727 /* rfi (supervisor only) */
3728 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW)
3729 {
3730 #if defined(CONFIG_USER_ONLY)
3731 GEN_EXCP_PRIVOPC(ctx);
3732 #else
3733 /* Restore CPU state */
3734 if (unlikely(!ctx->supervisor)) {
3735 GEN_EXCP_PRIVOPC(ctx);
3736 return;
3737 }
3738 gen_helper_rfi();
3739 GEN_SYNC(ctx);
3740 #endif
3741 }
3742
3743 #if defined(TARGET_PPC64)
3744 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B)
3745 {
3746 #if defined(CONFIG_USER_ONLY)
3747 GEN_EXCP_PRIVOPC(ctx);
3748 #else
3749 /* Restore CPU state */
3750 if (unlikely(!ctx->supervisor)) {
3751 GEN_EXCP_PRIVOPC(ctx);
3752 return;
3753 }
3754 gen_helper_rfid();
3755 GEN_SYNC(ctx);
3756 #endif
3757 }
3758
3759 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H)
3760 {
3761 #if defined(CONFIG_USER_ONLY)
3762 GEN_EXCP_PRIVOPC(ctx);
3763 #else
3764 /* Restore CPU state */
3765 if (unlikely(ctx->supervisor <= 1)) {
3766 GEN_EXCP_PRIVOPC(ctx);
3767 return;
3768 }
3769 gen_helper_hrfid();
3770 GEN_SYNC(ctx);
3771 #endif
3772 }
3773 #endif
3774
3775 /* sc */
3776 #if defined(CONFIG_USER_ONLY)
3777 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3778 #else
3779 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3780 #endif
3781 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW)
3782 {
3783 uint32_t lev;
3784
3785 lev = (ctx->opcode >> 5) & 0x7F;
3786 GEN_EXCP(ctx, POWERPC_SYSCALL, lev);
3787 }
3788
3789 /*** Trap ***/
3790 /* tw */
3791 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
3792 {
3793 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3794 /* Update the nip since this might generate a trap exception */
3795 gen_update_nip(ctx, ctx->nip);
3796 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3797 tcg_temp_free_i32(t0);
3798 }
3799
3800 /* twi */
3801 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3802 {
3803 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3804 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3805 /* Update the nip since this might generate a trap exception */
3806 gen_update_nip(ctx, ctx->nip);
3807 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], t0, t1);
3808 tcg_temp_free(t0);
3809 tcg_temp_free_i32(t1);
3810 }
3811
3812 #if defined(TARGET_PPC64)
3813 /* td */
3814 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
3815 {
3816 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3817 /* Update the nip since this might generate a trap exception */
3818 gen_update_nip(ctx, ctx->nip);
3819 gen_helper_td(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3820 tcg_temp_free_i32(t0);
3821 }
3822
3823 /* tdi */
3824 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B)
3825 {
3826 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3827 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3828 /* Update the nip since this might generate a trap exception */
3829 gen_update_nip(ctx, ctx->nip);
3830 gen_helper_td(cpu_gpr[rA(ctx->opcode)], t0, t1);
3831 tcg_temp_free(t0);
3832 tcg_temp_free_i32(t1);
3833 }
3834 #endif
3835
3836 /*** Processor control ***/
3837 /* mcrxr */
3838 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
3839 {
3840 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], cpu_xer);
3841 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], XER_CA);
3842 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA));
3843 }
3844
3845 /* mfcr */
3846 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
3847 {
3848 uint32_t crm, crn;
3849
3850 if (likely(ctx->opcode & 0x00100000)) {
3851 crm = CRM(ctx->opcode);
3852 if (likely((crm ^ (crm - 1)) == 0)) {
3853 crn = ffs(crm);
3854 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3855 }
3856 } else {
3857 gen_helper_load_cr(cpu_gpr[rD(ctx->opcode)]);
3858 }
3859 }
3860
3861 /* mfmsr */
3862 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
3863 {
3864 #if defined(CONFIG_USER_ONLY)
3865 GEN_EXCP_PRIVREG(ctx);
3866 #else
3867 if (unlikely(!ctx->supervisor)) {
3868 GEN_EXCP_PRIVREG(ctx);
3869 return;
3870 }
3871 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
3872 #endif
3873 }
3874
3875 #if 1
3876 #define SPR_NOACCESS ((void *)(-1UL))
3877 #else
3878 static void spr_noaccess (void *opaque, int sprn)
3879 {
3880 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3881 printf("ERROR: try to access SPR %d !\n", sprn);
3882 }
3883 #define SPR_NOACCESS (&spr_noaccess)
3884 #endif
3885
3886 /* mfspr */
3887 static always_inline void gen_op_mfspr (DisasContext *ctx)
3888 {
3889 void (*read_cb)(void *opaque, int sprn);
3890 uint32_t sprn = SPR(ctx->opcode);
3891
3892 #if !defined(CONFIG_USER_ONLY)
3893 if (ctx->supervisor == 2)
3894 read_cb = ctx->spr_cb[sprn].hea_read;
3895 else if (ctx->supervisor)
3896 read_cb = ctx->spr_cb[sprn].oea_read;
3897 else
3898 #endif
3899 read_cb = ctx->spr_cb[sprn].uea_read;
3900 if (likely(read_cb != NULL)) {
3901 if (likely(read_cb != SPR_NOACCESS)) {
3902 (*read_cb)(ctx, sprn);
3903 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
3904 } else {
3905 /* Privilege exception */
3906 /* This is a hack to avoid warnings when running Linux:
3907 * this OS breaks the PowerPC virtualisation model,
3908 * allowing userland application to read the PVR
3909 */
3910 if (sprn != SPR_PVR) {
3911 if (loglevel != 0) {
3912 fprintf(logfile, "Trying to read privileged spr %d %03x at "
3913 ADDRX "\n", sprn, sprn, ctx->nip);
3914 }
3915 printf("Trying to read privileged spr %d %03x at " ADDRX "\n",
3916 sprn, sprn, ctx->nip);
3917 }
3918 GEN_EXCP_PRIVREG(ctx);
3919 }
3920 } else {
3921 /* Not defined */
3922 if (loglevel != 0) {
3923 fprintf(logfile, "Trying to read invalid spr %d %03x at "
3924 ADDRX "\n", sprn, sprn, ctx->nip);
3925 }
3926 printf("Trying to read invalid spr %d %03x at " ADDRX "\n",
3927 sprn, sprn, ctx->nip);
3928 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3929 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
3930 }
3931 }
3932
3933 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
3934 {
3935 gen_op_mfspr(ctx);
3936 }
3937
3938 /* mftb */
3939 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB)
3940 {
3941 gen_op_mfspr(ctx);
3942 }
3943
3944 /* mtcrf */
3945 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
3946 {
3947 uint32_t crm, crn;
3948
3949 crm = CRM(ctx->opcode);
3950 if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) {
3951 TCGv_i32 temp = tcg_temp_new_i32();
3952 crn = ffs(crm);
3953 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3954 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
3955 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
3956 tcg_temp_free_i32(temp);
3957 } else {
3958 TCGv_i32 temp = tcg_const_i32(crm);
3959 gen_helper_store_cr(cpu_gpr[rS(ctx->opcode)], temp);
3960 tcg_temp_free_i32(temp);
3961 }
3962 }
3963
3964 /* mtmsr */
3965 #if defined(TARGET_PPC64)
3966 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B)
3967 {
3968 #if defined(CONFIG_USER_ONLY)
3969 GEN_EXCP_PRIVREG(ctx);
3970 #else
3971 if (unlikely(!ctx->supervisor)) {
3972 GEN_EXCP_PRIVREG(ctx);
3973 return;
3974 }
3975 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
3976 if (ctx->opcode & 0x00010000) {
3977 /* Special form that does not need any synchronisation */
3978 TCGv t0 = tcg_temp_new();
3979 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3980 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3981 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3982 tcg_temp_free(t0);
3983 } else {
3984 /* XXX: we need to update nip before the store
3985 * if we enter power saving mode, we will exit the loop
3986 * directly from ppc_store_msr
3987 */
3988 gen_update_nip(ctx, ctx->nip);
3989 gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
3990 /* Must stop the translation as machine state (may have) changed */
3991 /* Note that mtmsr is not always defined as context-synchronizing */
3992 ctx->exception = POWERPC_EXCP_STOP;
3993 }
3994 #endif
3995 }
3996 #endif
3997
3998 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
3999 {
4000 #if defined(CONFIG_USER_ONLY)
4001 GEN_EXCP_PRIVREG(ctx);
4002 #else
4003 if (unlikely(!ctx->supervisor)) {
4004 GEN_EXCP_PRIVREG(ctx);
4005 return;
4006 }
4007 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4008 if (ctx->opcode & 0x00010000) {
4009 /* Special form that does not need any synchronisation */
4010 TCGv t0 = tcg_temp_new();
4011 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4012 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4013 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4014 tcg_temp_free(t0);
4015 } else {
4016 /* XXX: we need to update nip before the store
4017 * if we enter power saving mode, we will exit the loop
4018 * directly from ppc_store_msr
4019 */
4020 gen_update_nip(ctx, ctx->nip);
4021 #if defined(TARGET_PPC64)
4022 if (!ctx->sf_mode) {
4023 TCGv t0 = tcg_temp_new();
4024 TCGv t1 = tcg_temp_new();
4025 tcg_gen_andi_tl(t0, cpu_msr, 0xFFFFFFFF00000000ULL);
4026 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
4027 tcg_gen_or_tl(t0, t0, t1);
4028 tcg_temp_free(t1);
4029 gen_helper_store_msr(t0);
4030 tcg_temp_free(t0);
4031 } else
4032 #endif
4033 gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
4034 /* Must stop the translation as machine state (may have) changed */
4035 /* Note that mtmsr is not always defined as context-synchronizing */
4036 ctx->exception = POWERPC_EXCP_STOP;
4037 }
4038 #endif
4039 }
4040
4041 /* mtspr */
4042 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
4043 {
4044 void (*write_cb)(void *opaque, int sprn);
4045 uint32_t sprn = SPR(ctx->opcode);
4046
4047 #if !defined(CONFIG_USER_ONLY)
4048 if (ctx->supervisor == 2)
4049 write_cb = ctx->spr_cb[sprn].hea_write;
4050 else if (ctx->supervisor)
4051 write_cb = ctx->spr_cb[sprn].oea_write;
4052 else
4053 #endif
4054 write_cb = ctx->spr_cb[sprn].uea_write;
4055 if (likely(write_cb != NULL)) {
4056 if (likely(write_cb != SPR_NOACCESS)) {
4057 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4058 (*write_cb)(ctx, sprn);
4059 } else {
4060 /* Privilege exception */
4061 if (loglevel != 0) {
4062 fprintf(logfile, "Trying to write privileged spr %d %03x at "
4063 ADDRX "\n", sprn, sprn, ctx->nip);
4064 }
4065 printf("Trying to write privileged spr %d %03x at " ADDRX "\n",
4066 sprn, sprn, ctx->nip);
4067 GEN_EXCP_PRIVREG(ctx);
4068 }
4069 } else {
4070 /* Not defined */
4071 if (loglevel != 0) {
4072 fprintf(logfile, "Trying to write invalid spr %d %03x at "
4073 ADDRX "\n", sprn, sprn, ctx->nip);
4074 }
4075 printf("Trying to write invalid spr %d %03x at " ADDRX "\n",
4076 sprn, sprn, ctx->nip);
4077 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
4078 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
4079 }
4080 }
4081
4082 /*** Cache management ***/
4083 /* dcbf */
4084 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
4085 {
4086 /* XXX: specification says this is treated as a load by the MMU */
4087 TCGv t0 = tcg_temp_new();
4088 gen_set_access_type(ACCESS_CACHE);
4089 gen_addr_reg_index(t0, ctx);
4090 gen_qemu_ld8u(t0, t0, ctx->mem_idx);
4091 tcg_temp_free(t0);
4092 }
4093
4094 /* dcbi (Supervisor only) */
4095 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
4096 {
4097 #if defined(CONFIG_USER_ONLY)
4098 GEN_EXCP_PRIVOPC(ctx);
4099 #else
4100 TCGv EA, val;
4101 if (unlikely(!ctx->supervisor)) {
4102 GEN_EXCP_PRIVOPC(ctx);
4103 return;
4104 }
4105 EA = tcg_temp_new();
4106 gen_set_access_type(ACCESS_CACHE);
4107 gen_addr_reg_index(EA, ctx);
4108 val = tcg_temp_new();
4109 /* XXX: specification says this should be treated as a store by the MMU */
4110 gen_qemu_ld8u(val, EA, ctx->mem_idx);
4111 gen_qemu_st8(val, EA, ctx->mem_idx);
4112 tcg_temp_free(val);
4113 tcg_temp_free(EA);
4114 #endif
4115 }
4116
4117 /* dcdst */
4118 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
4119 {
4120 /* XXX: specification say this is treated as a load by the MMU */
4121 TCGv t0 = tcg_temp_new();
4122 gen_set_access_type(ACCESS_CACHE);
4123 gen_addr_reg_index(t0, ctx);
4124 gen_qemu_ld8u(t0, t0, ctx->mem_idx);
4125 tcg_temp_free(t0);
4126 }
4127
4128 /* dcbt */
4129 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE)
4130 {
4131 /* interpreted as no-op */
4132 /* XXX: specification say this is treated as a load by the MMU
4133 * but does not generate any exception
4134 */
4135 }
4136
4137 /* dcbtst */
4138 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE)
4139 {
4140 /* interpreted as no-op */
4141 /* XXX: specification say this is treated as a load by the MMU
4142 * but does not generate any exception
4143 */
4144 }
4145
4146 /* dcbz */
4147 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ)
4148 {
4149 TCGv t0 = tcg_temp_new();
4150 gen_addr_reg_index(t0, ctx);
4151 /* NIP cannot be restored if the memory exception comes from an helper */
4152 gen_update_nip(ctx, ctx->nip - 4);
4153 gen_helper_dcbz(t0);
4154 tcg_temp_free(t0);
4155 }
4156
4157 GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
4158 {
4159 TCGv t0 = tcg_temp_new();
4160 gen_addr_reg_index(t0, ctx);
4161 /* NIP cannot be restored if the memory exception comes from an helper */
4162 gen_update_nip(ctx, ctx->nip - 4);
4163 if (ctx->opcode & 0x00200000)
4164 gen_helper_dcbz(t0);
4165 else
4166 gen_helper_dcbz_970(t0);
4167 tcg_temp_free(t0);
4168 }
4169
4170 /* icbi */
4171 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI)
4172 {
4173 TCGv t0 = tcg_temp_new();
4174 /* NIP cannot be restored if the memory exception comes from an helper */
4175 gen_update_nip(ctx, ctx->nip - 4);
4176 gen_addr_reg_index(t0, ctx);
4177 gen_helper_icbi(t0);
4178 tcg_temp_free(t0);
4179 }
4180
4181 /* Optional: */
4182 /* dcba */
4183 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA)
4184 {
4185 /* interpreted as no-op */
4186 /* XXX: specification say this is treated as a store by the MMU
4187 * but does not generate any exception
4188 */
4189 }
4190
4191 /*** Segment register manipulation ***/
4192 /* Supervisor only: */
4193 /* mfsr */
4194 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
4195 {
4196 #if defined(CONFIG_USER_ONLY)
4197 GEN_EXCP_PRIVREG(ctx);
4198 #else
4199 TCGv t0;
4200 if (unlikely(!ctx->supervisor)) {
4201 GEN_EXCP_PRIVREG(ctx);
4202 return;
4203 }
4204 t0 = tcg_const_tl(SR(ctx->opcode));
4205 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4206 tcg_temp_free(t0);
4207 #endif
4208 }
4209
4210 /* mfsrin */
4211 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
4212 {
4213 #if defined(CONFIG_USER_ONLY)
4214 GEN_EXCP_PRIVREG(ctx);
4215 #else
4216 TCGv t0;
4217 if (unlikely(!ctx->supervisor)) {
4218 GEN_EXCP_PRIVREG(ctx);
4219 return;
4220 }
4221 t0 = tcg_temp_new();
4222 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4223 tcg_gen_andi_tl(t0, t0, 0xF);
4224 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4225 tcg_temp_free(t0);
4226 #endif
4227 }
4228
4229 /* mtsr */
4230 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
4231 {
4232 #if defined(CONFIG_USER_ONLY)
4233 GEN_EXCP_PRIVREG(ctx);
4234 #else
4235 TCGv t0;
4236 if (unlikely(!ctx->supervisor)) {
4237 GEN_EXCP_PRIVREG(ctx);
4238 return;
4239 }
4240 t0 = tcg_const_tl(SR(ctx->opcode));
4241 gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
4242 tcg_temp_free(t0);
4243 #endif
4244 }
4245
4246 /* mtsrin */
4247 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
4248 {
4249 #if defined(CONFIG_USER_ONLY)
4250 GEN_EXCP_PRIVREG(ctx);
4251 #else
4252 TCGv t0;
4253 if (unlikely(!ctx->supervisor)) {
4254 GEN_EXCP_PRIVREG(ctx);
4255 return;
4256 }
4257 t0 = tcg_temp_new();
4258 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4259 tcg_gen_andi_tl(t0, t0, 0xF);
4260 gen_helper_store_sr(t0, cpu_gpr[rD(ctx->opcode)]);
4261 tcg_temp_free(t0);
4262 #endif
4263 }
4264
4265 #if defined(TARGET_PPC64)
4266 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4267 /* mfsr */
4268 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
4269 {
4270 #if defined(CONFIG_USER_ONLY)
4271 GEN_EXCP_PRIVREG(ctx);
4272 #else
4273 TCGv t0;
4274 if (unlikely(!ctx->supervisor)) {
4275 GEN_EXCP_PRIVREG(ctx);
4276 return;
4277 }
4278 t0 = tcg_const_tl(SR(ctx->opcode));
4279 gen_helper_load_slb(cpu_gpr[rD(ctx->opcode)], t0);
4280 tcg_temp_free(t0);
4281 #endif
4282 }
4283
4284 /* mfsrin */
4285 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
4286 PPC_SEGMENT_64B)
4287 {
4288 #if defined(CONFIG_USER_ONLY)
4289 GEN_EXCP_PRIVREG(ctx);
4290 #else
4291 TCGv t0;
4292 if (unlikely(!ctx->supervisor)) {
4293 GEN_EXCP_PRIVREG(ctx);
4294 return;
4295 }
4296 t0 = tcg_temp_new();
4297 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4298 tcg_gen_andi_tl(t0, t0, 0xF);
4299 gen_helper_load_slb(cpu_gpr[rD(ctx->opcode)], t0);
4300 tcg_temp_free(t0);
4301 #endif
4302 }
4303
4304 /* mtsr */
4305 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
4306 {
4307 #if defined(CONFIG_USER_ONLY)
4308 GEN_EXCP_PRIVREG(ctx);
4309 #else
4310 TCGv t0;
4311 if (unlikely(!ctx->supervisor)) {
4312 GEN_EXCP_PRIVREG(ctx);
4313 return;
4314 }
4315 t0 = tcg_const_tl(SR(ctx->opcode));
4316 gen_helper_store_slb(t0, cpu_gpr[rS(ctx->opcode)]);
4317 tcg_temp_free(t0);
4318 #endif
4319 }
4320
4321 /* mtsrin */
4322 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
4323 PPC_SEGMENT_64B)
4324 {
4325 #if defined(CONFIG_USER_ONLY)
4326 GEN_EXCP_PRIVREG(ctx);
4327 #else
4328 TCGv t0;
4329 if (unlikely(!ctx->supervisor)) {
4330 GEN_EXCP_PRIVREG(ctx);
4331 return;
4332 }
4333 t0 = tcg_temp_new();
4334 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4335 tcg_gen_andi_tl(t0, t0, 0xF);
4336 gen_helper_store_slb(t0, cpu_gpr[rS(ctx->opcode)]);
4337 tcg_temp_free(t0);
4338 #endif
4339 }
4340 #endif /* defined(TARGET_PPC64) */
4341
4342 /*** Lookaside buffer management ***/
4343 /* Optional & supervisor only: */
4344 /* tlbia */
4345 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
4346 {
4347 #if defined(CONFIG_USER_ONLY)
4348 GEN_EXCP_PRIVOPC(ctx);
4349 #else
4350 if (unlikely(!ctx->supervisor)) {
4351 GEN_EXCP_PRIVOPC(ctx);
4352 return;
4353 }
4354 gen_helper_tlbia();
4355 #endif
4356 }
4357
4358 /* tlbie */
4359 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE)
4360 {
4361 #if defined(CONFIG_USER_ONLY)
4362 GEN_EXCP_PRIVOPC(ctx);
4363 #else
4364 if (unlikely(!ctx->supervisor)) {
4365 GEN_EXCP_PRIVOPC(ctx);
4366 return;
4367 }
4368 #if defined(TARGET_PPC64)
4369 if (!ctx->sf_mode) {
4370 TCGv t0 = tcg_temp_new();
4371 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4372 gen_helper_tlbie(t0);
4373 tcg_temp_free(t0);
4374 } else
4375 #endif
4376 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
4377 #endif
4378 }
4379
4380 /* tlbsync */
4381 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC)
4382 {
4383 #if defined(CONFIG_USER_ONLY)
4384 GEN_EXCP_PRIVOPC(ctx);
4385 #else
4386 if (unlikely(!ctx->supervisor)) {
4387 GEN_EXCP_PRIVOPC(ctx);
4388 return;
4389 }
4390 /* This has no effect: it should ensure that all previous
4391 * tlbie have completed
4392 */
4393 GEN_STOP(ctx);
4394 #endif
4395 }
4396
4397 #if defined(TARGET_PPC64)
4398 /* slbia */
4399 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI)
4400 {
4401 #if defined(CONFIG_USER_ONLY)
4402 GEN_EXCP_PRIVOPC(ctx);
4403 #else
4404 if (unlikely(!ctx->supervisor)) {
4405 GEN_EXCP_PRIVOPC(ctx);
4406 return;
4407 }
4408 gen_helper_slbia();
4409 #endif
4410 }
4411
4412 /* slbie */
4413 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI)
4414 {
4415 #if defined(CONFIG_USER_ONLY)
4416 GEN_EXCP_PRIVOPC(ctx);
4417 #else
4418 if (unlikely(!ctx->supervisor)) {
4419 GEN_EXCP_PRIVOPC(ctx);
4420 return;
4421 }
4422 gen_helper_slbie(cpu_gpr[rB(ctx->opcode)]);
4423 #endif
4424 }
4425 #endif
4426
4427 /*** External control ***/
4428 /* Optional: */
4429 /* eciwx */
4430 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
4431 {
4432 /* Should check EAR[E] ! */
4433 TCGv t0 = tcg_temp_new();
4434 gen_set_access_type(ACCESS_RES);
4435 gen_addr_reg_index(t0, ctx);
4436 gen_check_align(ctx, t0, 0x03);
4437 gen_qemu_ld32u(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx);
4438 tcg_temp_free(t0);
4439 }
4440
4441 /* ecowx */
4442 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
4443 {
4444 /* Should check EAR[E] ! */
4445 TCGv t0 = tcg_temp_new();
4446 gen_set_access_type(ACCESS_RES);
4447 gen_addr_reg_index(t0, ctx);
4448 gen_check_align(ctx, t0, 0x03);
4449 gen_qemu_st32(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx);
4450 tcg_temp_free(t0);
4451 }
4452
4453 /* PowerPC 601 specific instructions */
4454 /* abs - abs. */
4455 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR)
4456 {
4457 int l1 = gen_new_label();
4458 int l2 = gen_new_label();
4459 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4460 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4461 tcg_gen_br(l2);
4462 gen_set_label(l1);
4463 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4464 gen_set_label(l2);
4465 if (unlikely(Rc(ctx->opcode) != 0))
4466 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4467 }
4468
4469 /* abso - abso. */
4470 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR)
4471 {
4472 int l1 = gen_new_label();
4473 int l2 = gen_new_label();
4474 int l3 = gen_new_label();
4475 /* Start with XER OV disabled, the most likely case */
4476 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4477 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4478 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4479 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4480 tcg_gen_br(l2);
4481 gen_set_label(l1);
4482 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4483 tcg_gen_br(l3);
4484 gen_set_label(l2);
4485 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4486 gen_set_label(l3);
4487 if (unlikely(Rc(ctx->opcode) != 0))
4488 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4489 }
4490
4491 /* clcs */
4492 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR)
4493 {
4494 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4495 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], t0);
4496 tcg_temp_free_i32(t0);
4497 /* Rc=1 sets CR0 to an undefined state */
4498 }
4499
4500 /* div - div. */
4501 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR)
4502 {
4503 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4504 if (unlikely(Rc(ctx->opcode) != 0))
4505 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4506 }
4507
4508 /* divo - divo. */
4509 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR)
4510 {
4511 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4512 if (unlikely(Rc(ctx->opcode) != 0))
4513 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4514 }
4515
4516 /* divs - divs. */
4517 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR)
4518 {
4519 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4520 if (unlikely(Rc(ctx->opcode) != 0))
4521 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4522 }
4523
4524 /* divso - divso. */
4525 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR)
4526 {
4527 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4528 if (unlikely(Rc(ctx->opcode) != 0))
4529 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4530 }
4531
4532 /* doz - doz. */
4533 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR)
4534 {
4535 int l1 = gen_new_label();
4536 int l2 = gen_new_label();
4537 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4538 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4539 tcg_gen_br(l2);
4540 gen_set_label(l1);
4541 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4542 gen_set_label(l2);
4543 if (unlikely(Rc(ctx->opcode) != 0))
4544 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4545 }
4546
4547 /* dozo - dozo. */
4548 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR)
4549 {
4550 int l1 = gen_new_label();
4551 int l2 = gen_new_label();
4552 TCGv t0 = tcg_temp_new();
4553 TCGv t1 = tcg_temp_new();
4554 TCGv t2 = tcg_temp_new();
4555 /* Start with XER OV disabled, the most likely case */
4556 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4557 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4558 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4559 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4560 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4561 tcg_gen_andc_tl(t1, t1, t2);
4562 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4563 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4564 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4565 tcg_gen_br(l2);
4566 gen_set_label(l1);
4567 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4568 gen_set_label(l2);
4569 tcg_temp_free(t0);
4570 tcg_temp_free(t1);
4571 tcg_temp_free(t2);
4572 if (unlikely(Rc(ctx->opcode) != 0))
4573 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4574 }
4575
4576 /* dozi */
4577 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4578 {
4579 target_long simm = SIMM(ctx->opcode);
4580 int l1 = gen_new_label();
4581 int l2 = gen_new_label();
4582 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4583 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4584 tcg_gen_br(l2);
4585 gen_set_label(l1);
4586 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4587 gen_set_label(l2);
4588 if (unlikely(Rc(ctx->opcode) != 0))
4589 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4590 }
4591
4592 /* lscbx - lscbx. */
4593 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR)
4594 {
4595 TCGv t0 = tcg_temp_new();
4596 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4597 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4598 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4599
4600 gen_addr_reg_index(t0, ctx);
4601 /* NIP cannot be restored if the memory exception comes from an helper */
4602 gen_update_nip(ctx, ctx->nip - 4);
4603 gen_helper_lscbx(t0, t0, t1, t2, t3);
4604 tcg_temp_free_i32(t1);
4605 tcg_temp_free_i32(t2);
4606 tcg_temp_free_i32(t3);
4607 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4608 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4609 if (unlikely(Rc(ctx->opcode) != 0))
4610 gen_set_Rc0(ctx, t0);
4611 tcg_temp_free(t0);
4612 }
4613
4614 /* maskg - maskg. */
4615 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR)
4616 {
4617 int l1 = gen_new_label();
4618 TCGv t0 = tcg_temp_new();
4619 TCGv t1 = tcg_temp_new();
4620 TCGv t2 = tcg_temp_new();
4621 TCGv t3 = tcg_temp_new();
4622 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4623 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4624 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4625 tcg_gen_addi_tl(t2, t0, 1);
4626 tcg_gen_shr_tl(t2, t3, t2);
4627 tcg_gen_shr_tl(t3, t3, t1);
4628 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4629 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4630 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4631 gen_set_label(l1);
4632 tcg_temp_free(t0);
4633 tcg_temp_free(t1);
4634 tcg_temp_free(t2);
4635 tcg_temp_free(t3);
4636 if (unlikely(Rc(ctx->opcode) != 0))
4637 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4638 }
4639
4640 /* maskir - maskir. */
4641 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR)
4642 {
4643 TCGv t0 = tcg_temp_new();
4644 TCGv t1 = tcg_temp_new();
4645 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4646 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4647 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4648 tcg_temp_free(t0);
4649 tcg_temp_free(t1);
4650 if (unlikely(Rc(ctx->opcode) != 0))
4651 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4652 }
4653
4654 /* mul - mul. */
4655 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR)
4656 {
4657 TCGv_i64 t0 = tcg_temp_new_i64();
4658 TCGv_i64 t1 = tcg_temp_new_i64();
4659 TCGv t2 = tcg_temp_new();
4660 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4661 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4662 tcg_gen_mul_i64(t0, t0, t1);
4663 tcg_gen_trunc_i64_tl(t2, t0);
4664 gen_store_spr(SPR_MQ, t2);
4665 tcg_gen_shri_i64(t1, t0, 32);
4666 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4667 tcg_temp_free_i64(t0);
4668 tcg_temp_free_i64(t1);
4669 tcg_temp_free(t2);
4670 if (unlikely(Rc(ctx->opcode) != 0))
4671 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4672 }
4673
4674 /* mulo - mulo. */
4675 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR)
4676 {
4677 int l1 = gen_new_label();
4678 TCGv_i64 t0 = tcg_temp_new_i64();
4679 TCGv_i64 t1 = tcg_temp_new_i64();
4680 TCGv t2 = tcg_temp_new();
4681 /* Start with XER OV disabled, the most likely case */
4682 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4683 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4684 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4685 tcg_gen_mul_i64(t0, t0, t1);
4686 tcg_gen_trunc_i64_tl(t2, t0);
4687 gen_store_spr(SPR_MQ, t2);
4688 tcg_gen_shri_i64(t1, t0, 32);
4689 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4690 tcg_gen_ext32s_i64(t1, t0);
4691 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4692 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4693 gen_set_label(l1);
4694 tcg_temp_free_i64(t0);
4695 tcg_temp_free_i64(t1);
4696 tcg_temp_free(t2);
4697 if (unlikely(Rc(ctx->opcode) != 0))
4698 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4699 }
4700
4701 /* nabs - nabs. */
4702 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR)
4703 {
4704 int l1 = gen_new_label();
4705 int l2 = gen_new_label();
4706 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4707 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4708 tcg_gen_br(l2);
4709 gen_set_label(l1);
4710 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4711 gen_set_label(l2);
4712 if (unlikely(Rc(ctx->opcode) != 0))
4713 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4714 }
4715
4716 /* nabso - nabso. */
4717 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR)
4718 {
4719 int l1 = gen_new_label();
4720 int l2 = gen_new_label();
4721 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4722 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4723 tcg_gen_br(l2);
4724 gen_set_label(l1);
4725 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4726 gen_set_label(l2);
4727 /* nabs never overflows */
4728 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4729 if (unlikely(Rc(ctx->opcode) != 0))
4730 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4731 }
4732
4733 /* rlmi - rlmi. */
4734 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4735 {
4736 uint32_t mb = MB(ctx->opcode);
4737 uint32_t me = ME(ctx->opcode);
4738 TCGv t0 = tcg_temp_new();
4739 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4740 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4741 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4742 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4743 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4744 tcg_temp_free(t0);
4745 if (unlikely(Rc(ctx->opcode) != 0))
4746 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4747 }
4748
4749 /* rrib - rrib. */
4750 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR)
4751 {
4752 TCGv t0 = tcg_temp_new();
4753 TCGv t1 = tcg_temp_new();
4754 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4755 tcg_gen_movi_tl(t1, 0x80000000);
4756 tcg_gen_shr_tl(t1, t1, t0);
4757 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4758 tcg_gen_and_tl(t0, t0, t1);
4759 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4760 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4761 tcg_temp_free(t0);
4762 tcg_temp_free(t1);
4763 if (unlikely(Rc(ctx->opcode) != 0))
4764 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4765 }
4766
4767 /* sle - sle. */
4768 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR)
4769 {
4770 TCGv t0 = tcg_temp_new();
4771 TCGv t1 = tcg_temp_new();
4772 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4773 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4774 tcg_gen_subfi_tl(t1, 32, t1);
4775 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4776 tcg_gen_or_tl(t1, t0, t1);
4777 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4778 gen_store_spr(SPR_MQ, t1);
4779 tcg_temp_free(t0);
4780 tcg_temp_free(t1);
4781 if (unlikely(Rc(ctx->opcode) != 0))
4782 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4783 }
4784
4785 /* sleq - sleq. */
4786 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR)
4787 {
4788 TCGv t0 = tcg_temp_new();
4789 TCGv t1 = tcg_temp_new();
4790 TCGv t2 = tcg_temp_new();
4791 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4792 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4793 tcg_gen_shl_tl(t2, t2, t0);
4794 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4795 gen_load_spr(t1, SPR_MQ);
4796 gen_store_spr(SPR_MQ, t0);
4797 tcg_gen_and_tl(t0, t0, t2);
4798 tcg_gen_andc_tl(t1, t1, t2);
4799 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4800 tcg_temp_free(t0);
4801 tcg_temp_free(t1);
4802 tcg_temp_free(t2);
4803 if (unlikely(Rc(ctx->opcode) != 0))
4804 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4805 }
4806
4807 /* sliq - sliq. */
4808 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR)
4809 {
4810 int sh = SH(ctx->opcode);
4811 TCGv t0 = tcg_temp_new();
4812 TCGv t1 = tcg_temp_new();
4813 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4814 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4815 tcg_gen_or_tl(t1, t0, t1);
4816 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4817 gen_store_spr(SPR_MQ, t1);
4818 tcg_temp_free(t0);
4819 tcg_temp_free(t1);
4820 if (unlikely(Rc(ctx->opcode) != 0))
4821 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4822 }
4823
4824 /* slliq - slliq. */
4825 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR)
4826 {
4827 int sh = SH(ctx->opcode);
4828 TCGv t0 = tcg_temp_new();
4829 TCGv t1 = tcg_temp_new();
4830 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4831 gen_load_spr(t1, SPR_MQ);
4832 gen_store_spr(SPR_MQ, t0);
4833 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
4834 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4835 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4836 tcg_temp_free(t0);
4837 tcg_temp_free(t1);
4838 if (unlikely(Rc(ctx->opcode) != 0))
4839 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4840 }
4841
4842 /* sllq - sllq. */
4843 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR)
4844 {
4845 int l1 = gen_new_label();
4846 int l2 = gen_new_label();
4847 TCGv t0 = tcg_temp_local_new();
4848 TCGv t1 = tcg_temp_local_new();
4849 TCGv t2 = tcg_temp_local_new();
4850 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4851 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4852 tcg_gen_shl_tl(t1, t1, t2);
4853 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4854 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4855 gen_load_spr(t0, SPR_MQ);
4856 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4857 tcg_gen_br(l2);
4858 gen_set_label(l1);
4859 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4860 gen_load_spr(t2, SPR_MQ);
4861 tcg_gen_andc_tl(t1, t2, t1);
4862 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4863 gen_set_label(l2);
4864 tcg_temp_free(t0);
4865 tcg_temp_free(t1);
4866 tcg_temp_free(t2);
4867 if (unlikely(Rc(ctx->opcode) != 0))
4868 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4869 }
4870
4871 /* slq - slq. */
4872 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR)
4873 {
4874 int l1 = gen_new_label();
4875 TCGv t0 = tcg_temp_new();
4876 TCGv t1 = tcg_temp_new();
4877 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4878 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4879 tcg_gen_subfi_tl(t1, 32, t1);
4880 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4881 tcg_gen_or_tl(t1, t0, t1);
4882 gen_store_spr(SPR_MQ, t1);
4883 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4884 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4885 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4886 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4887 gen_set_label(l1);
4888 tcg_temp_free(t0);
4889 tcg_temp_free(t1);
4890 if (unlikely(Rc(ctx->opcode) != 0))
4891 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4892 }
4893
4894 /* sraiq - sraiq. */
4895 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR)
4896 {
4897 int sh = SH(ctx->opcode);
4898 int l1 = gen_new_label();
4899 TCGv t0 = tcg_temp_new();
4900 TCGv t1 = tcg_temp_new();
4901 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4902 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4903 tcg_gen_or_tl(t0, t0, t1);
4904 gen_store_spr(SPR_MQ, t0);
4905 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4906 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4907 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
4908 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4909 gen_set_label(l1);
4910 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
4911 tcg_temp_free(t0);
4912 tcg_temp_free(t1);
4913 if (unlikely(Rc(ctx->opcode) != 0))
4914 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4915 }
4916
4917 /* sraq - sraq. */
4918 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR)
4919 {
4920 int l1 = gen_new_label();
4921 int l2 = gen_new_label();
4922 TCGv t0 = tcg_temp_new();
4923 TCGv t1 = tcg_temp_local_new();
4924 TCGv t2 = tcg_temp_local_new();
4925 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4926 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4927 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
4928 tcg_gen_subfi_tl(t2, 32, t2);
4929 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
4930 tcg_gen_or_tl(t0, t0, t2);
4931 gen_store_spr(SPR_MQ, t0);
4932 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4933 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
4934 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
4935 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
4936 gen_set_label(l1);
4937 tcg_temp_free(t0);
4938 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
4939 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4940 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4941 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
4942 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4943 gen_set_label(l2);
4944 tcg_temp_free(t1);
4945 tcg_temp_free(t2);
4946 if (unlikely(Rc(ctx->opcode) != 0))
4947 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4948 }
4949
4950 /* sre - sre. */
4951 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR)
4952 {
4953 TCGv t0 = tcg_temp_new();
4954 TCGv t1 = tcg_temp_new();
4955 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4956 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4957 tcg_gen_subfi_tl(t1, 32, t1);
4958 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4959 tcg_gen_or_tl(t1, t0, t1);
4960 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4961 gen_store_spr(SPR_MQ, t1);
4962 tcg_temp_free(t0);
4963 tcg_temp_free(t1);
4964 if (unlikely(Rc(ctx->opcode) != 0))
4965 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4966 }
4967
4968 /* srea - srea. */
4969 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR)
4970 {
4971 TCGv t0 = tcg_temp_new();
4972 TCGv t1 = tcg_temp_new();
4973 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4974 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4975 gen_store_spr(SPR_MQ, t0);
4976 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
4977 tcg_temp_free(t0);
4978 tcg_temp_free(t1);
4979 if (unlikely(Rc(ctx->opcode) != 0))
4980 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4981 }
4982
4983 /* sreq */
4984 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR)
4985 {
4986 TCGv t0 = tcg_temp_new();
4987 TCGv t1 = tcg_temp_new();
4988 TCGv t2 = tcg_temp_new();
4989 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4990 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4991 tcg_gen_shr_tl(t1, t1, t0);
4992 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4993 gen_load_spr(t2, SPR_MQ);
4994 gen_store_spr(SPR_MQ, t0);
4995 tcg_gen_and_tl(t0, t0, t1);
4996 tcg_gen_andc_tl(t2, t2, t1);
4997 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
4998 tcg_temp_free(t0);
4999 tcg_temp_free(t1);
5000 tcg_temp_free(t2);
5001 if (unlikely(Rc(ctx->opcode) != 0))
5002 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5003 }
5004
5005 /* sriq */
5006 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR)
5007 {
5008 int sh = SH(ctx->opcode);
5009 TCGv t0 = tcg_temp_new();
5010 TCGv t1 = tcg_temp_new();
5011 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5012 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5013 tcg_gen_or_tl(t1, t0, t1);
5014 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5015 gen_store_spr(SPR_MQ, t1);
5016 tcg_temp_free(t0);
5017 tcg_temp_free(t1);
5018 if (unlikely(Rc(ctx->opcode) != 0))
5019 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5020 }
5021
5022 /* srliq */
5023 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR)
5024 {
5025 int sh = SH(ctx->opcode);
5026 TCGv t0 = tcg_temp_new();
5027 TCGv t1 = tcg_temp_new();
5028 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5029 gen_load_spr(t1, SPR_MQ);
5030 gen_store_spr(SPR_MQ, t0);
5031 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5032 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5033 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5034 tcg_temp_free(t0);
5035 tcg_temp_free(t1);
5036 if (unlikely(Rc(ctx->opcode) != 0))
5037 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5038 }
5039
5040 /* srlq */
5041 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR)
5042 {
5043 int l1 = gen_new_label();
5044 int l2 = gen_new_label();
5045 TCGv t0 = tcg_temp_local_new();
5046 TCGv t1 = tcg_temp_local_new();
5047 TCGv t2 = tcg_temp_local_new();
5048 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5049 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5050 tcg_gen_shr_tl(t2, t1, t2);
5051 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5052 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5053 gen_load_spr(t0, SPR_MQ);
5054 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5055 tcg_gen_br(l2);
5056 gen_set_label(l1);
5057 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5058 tcg_gen_and_tl(t0, t0, t2);
5059 gen_load_spr(t1, SPR_MQ);
5060 tcg_gen_andc_tl(t1, t1, t2);
5061 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5062 gen_set_label(l2);
5063 tcg_temp_free(t0);
5064 tcg_temp_free(t1);
5065 tcg_temp_free(t2);
5066 if (unlikely(Rc(ctx->opcode) != 0))
5067 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5068 }
5069
5070 /* srq */
5071 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR)
5072 {
5073 int l1 = gen_new_label();
5074 TCGv t0 = tcg_temp_new();
5075 TCGv t1 = tcg_temp_new();
5076 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5077 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5078 tcg_gen_subfi_tl(t1, 32, t1);
5079 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5080 tcg_gen_or_tl(t1, t0, t1);
5081 gen_store_spr(SPR_MQ, t1);
5082 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5083 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5084 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5085 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5086 gen_set_label(l1);
5087 tcg_temp_free(t0);
5088 tcg_temp_free(t1);
5089 if (unlikely(Rc(ctx->opcode) != 0))
5090 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5091 }
5092
5093 /* PowerPC 602 specific instructions */
5094 /* dsa */
5095 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC)
5096 {
5097 /* XXX: TODO */
5098 GEN_EXCP_INVAL(ctx);
5099 }
5100
5101 /* esa */
5102 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC)
5103 {
5104 /* XXX: TODO */
5105 GEN_EXCP_INVAL(ctx);
5106 }
5107
5108 /* mfrom */
5109 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC)
5110 {
5111 #if defined(CONFIG_USER_ONLY)
5112 GEN_EXCP_PRIVOPC(ctx);
5113 #else
5114 if (unlikely(!ctx->supervisor)) {
5115 GEN_EXCP_PRIVOPC(ctx);
5116 return;
5117 }
5118 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5119 #endif
5120 }
5121
5122 /* 602 - 603 - G2 TLB management */
5123 /* tlbld */
5124 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
5125 {
5126 #if defined(CONFIG_USER_ONLY)
5127 GEN_EXCP_PRIVOPC(ctx);
5128 #else
5129 if (unlikely(!ctx->supervisor)) {
5130 GEN_EXCP_PRIVOPC(ctx);
5131 return;
5132 }
5133 gen_helper_6xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
5134 #endif
5135 }
5136
5137 /* tlbli */
5138 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
5139 {
5140 #if defined(CONFIG_USER_ONLY)
5141 GEN_EXCP_PRIVOPC(ctx);
5142 #else
5143 if (unlikely(!ctx->supervisor)) {
5144 GEN_EXCP_PRIVOPC(ctx);
5145 return;
5146 }
5147 gen_helper_6xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
5148 #endif
5149 }
5150
5151 /* 74xx TLB management */
5152 /* tlbld */
5153 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)
5154 {
5155 #if defined(CONFIG_USER_ONLY)
5156 GEN_EXCP_PRIVOPC(ctx);
5157 #else
5158 if (unlikely(!ctx->supervisor)) {
5159 GEN_EXCP_PRIVOPC(ctx);
5160 return;
5161 }
5162 gen_helper_74xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
5163 #endif
5164 }
5165
5166 /* tlbli */
5167 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB)
5168 {
5169 #if defined(CONFIG_USER_ONLY)
5170 GEN_EXCP_PRIVOPC(ctx);
5171 #else
5172 if (unlikely(!ctx->supervisor)) {
5173 GEN_EXCP_PRIVOPC(ctx);
5174 return;
5175 }
5176 gen_helper_74xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
5177 #endif
5178 }
5179
5180 /* POWER instructions not in PowerPC 601 */
5181 /* clf */
5182 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER)
5183 {
5184 /* Cache line flush: implemented as no-op */
5185 }
5186
5187 /* cli */
5188 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER)
5189 {
5190 /* Cache line invalidate: privileged and treated as no-op */
5191 #if defined(CONFIG_USER_ONLY)
5192 GEN_EXCP_PRIVOPC(ctx);
5193 #else
5194 if (unlikely(!ctx->supervisor)) {
5195 GEN_EXCP_PRIVOPC(ctx);
5196 return;
5197 }
5198 #endif
5199 }
5200
5201 /* dclst */
5202 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER)
5203 {
5204 /* Data cache line store: treated as no-op */
5205 }
5206
5207 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER)
5208 {
5209 #if defined(CONFIG_USER_ONLY)
5210 GEN_EXCP_PRIVOPC(ctx);
5211 #else
5212 int ra = rA(ctx->opcode);
5213 int rd = rD(ctx->opcode);
5214 TCGv t0;
5215 if (unlikely(!ctx->supervisor)) {
5216 GEN_EXCP_PRIVOPC(ctx);
5217 return;
5218 }
5219 t0 = tcg_temp_new();
5220 gen_addr_reg_index(t0, ctx);
5221 tcg_gen_shri_tl(t0, t0, 28);
5222 tcg_gen_andi_tl(t0, t0, 0xF);
5223 gen_helper_load_sr(cpu_gpr[rd], t0);
5224 tcg_temp_free(t0);
5225 if (ra != 0 && ra != rd)
5226 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5227 #endif
5228 }
5229
5230 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER)
5231 {
5232 #if defined(CONFIG_USER_ONLY)
5233 GEN_EXCP_PRIVOPC(ctx);
5234 #else
5235 TCGv t0;
5236 if (unlikely(!ctx->supervisor)) {
5237 GEN_EXCP_PRIVOPC(ctx);
5238 return;
5239 }
5240 t0 = tcg_temp_new();
5241 gen_addr_reg_index(t0, ctx);
5242 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], t0);
5243 tcg_temp_free(t0);
5244 #endif
5245 }
5246
5247 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER)
5248 {
5249 #if defined(CONFIG_USER_ONLY)
5250 GEN_EXCP_PRIVOPC(ctx);
5251 #else
5252 if (unlikely(!ctx->supervisor)) {
5253 GEN_EXCP_PRIVOPC(ctx);
5254 return;
5255 }
5256 gen_helper_rfsvc();
5257 GEN_SYNC(ctx);
5258 #endif
5259 }
5260
5261 /* svc is not implemented for now */
5262
5263 /* POWER2 specific instructions */
5264 /* Quad manipulation (load/store two floats at a time) */
5265
5266 /* lfq */
5267 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5268 {
5269 int rd = rD(ctx->opcode);
5270 TCGv t0 = tcg_temp_new();
5271 gen_addr_imm_index(t0, ctx, 0);
5272 gen_qemu_ld64(cpu_fpr[rd], t0, ctx->mem_idx);
5273 tcg_gen_addi_tl(t0, t0, 8);
5274 gen_qemu_ld64(cpu_fpr[(rd + 1) % 32], t0, ctx->mem_idx);
5275 tcg_temp_free(t0);
5276 }
5277
5278 /* lfqu */
5279 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5280 {
5281 int ra = rA(ctx->opcode);
5282 int rd = rD(ctx->opcode);
5283 TCGv t0 = tcg_temp_new();
5284 TCGv t1 = tcg_temp_new();
5285 gen_addr_imm_index(t0, ctx, 0);
5286 gen_qemu_ld64(cpu_fpr[rd], t0, ctx->mem_idx);
5287 tcg_gen_addi_tl(t1, t0, 8);
5288 gen_qemu_ld64(cpu_fpr[(rd + 1) % 32], t1, ctx->mem_idx);
5289 if (ra != 0)
5290 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5291 tcg_temp_free(t0);
5292 tcg_temp_free(t1);
5293 }
5294
5295 /* lfqux */
5296 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2)
5297 {
5298 int ra = rA(ctx->opcode);
5299 int rd = rD(ctx->opcode);
5300 TCGv t0 = tcg_temp_new();
5301 TCGv t1 = tcg_temp_new();
5302 gen_addr_reg_index(t0, ctx);
5303 gen_qemu_ld64(cpu_fpr[rd], t0, ctx->mem_idx);
5304 tcg_gen_addi_tl(t1, t0, 8);
5305 gen_qemu_ld64(cpu_fpr[(rd + 1) % 32], t1, ctx->mem_idx);
5306 if (ra != 0)
5307 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5308 tcg_temp_free(t0);
5309 tcg_temp_free(t1);
5310 }
5311
5312 /* lfqx */
5313 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2)
5314 {
5315 int rd = rD(ctx->opcode);
5316 TCGv t0 = tcg_temp_new();
5317 gen_addr_reg_index(t0, ctx);
5318 gen_qemu_ld64(cpu_fpr[rd], t0, ctx->mem_idx);
5319 tcg_gen_addi_tl(t0, t0, 8);
5320 gen_qemu_ld64(cpu_fpr[(rd + 1) % 32], t0, ctx->mem_idx);
5321 tcg_temp_free(t0);
5322 }
5323
5324 /* stfq */
5325 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5326 {
5327 int rd = rD(ctx->opcode);
5328 TCGv t0 = tcg_temp_new();
5329 gen_addr_imm_index(t0, ctx, 0);
5330 gen_qemu_st64(cpu_fpr[rd], t0, ctx->mem_idx);
5331 tcg_gen_addi_tl(t0, t0, 8);
5332 gen_qemu_st64(cpu_fpr[(rd + 1) % 32], t0, ctx->mem_idx);
5333 tcg_temp_free(t0);
5334 }
5335
5336 /* stfqu */
5337 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5338 {
5339 int ra = rA(ctx->opcode);
5340 int rd = rD(ctx->opcode);
5341 TCGv t0 = tcg_temp_new();
5342 TCGv t1 = tcg_temp_new();
5343 gen_addr_imm_index(t0, ctx, 0);
5344 gen_qemu_st64(cpu_fpr[rd], t0, ctx->mem_idx);
5345 tcg_gen_addi_tl(t1, t0, 8);
5346 gen_qemu_st64(cpu_fpr[(rd + 1) % 32], t1, ctx->mem_idx);
5347 if (ra != 0)
5348 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5349 tcg_temp_free(t0);
5350 tcg_temp_free(t1);
5351 }
5352
5353 /* stfqux */
5354 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2)
5355 {
5356 int ra = rA(ctx->opcode);
5357 int rd = rD(ctx->opcode);
5358 TCGv t0 = tcg_temp_new();
5359 TCGv t1 = tcg_temp_new();
5360 gen_addr_reg_index(t0, ctx);
5361 gen_qemu_st64(cpu_fpr[rd], t0, ctx->mem_idx);
5362 tcg_gen_addi_tl(t1, t0, 8);
5363 gen_qemu_st64(cpu_fpr[(rd + 1) % 32], t1, ctx->mem_idx);
5364 if (ra != 0)
5365 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5366 tcg_temp_free(t0);
5367 tcg_temp_free(t1);
5368 }
5369
5370 /* stfqx */
5371 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2)
5372 {
5373 int rd = rD(ctx->opcode);
5374 TCGv t0 = tcg_temp_new();
5375 gen_addr_reg_index(t0, ctx);
5376 gen_qemu_st64(cpu_fpr[rd], t0, ctx->mem_idx);
5377 tcg_gen_addi_tl(t0, t0, 8);
5378 gen_qemu_st64(cpu_fpr[(rd + 1) % 32], t0, ctx->mem_idx);
5379 tcg_temp_free(t0);
5380 }
5381
5382 /* BookE specific instructions */
5383 /* XXX: not implemented on 440 ? */
5384 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI)
5385 {
5386 /* XXX: TODO */
5387 GEN_EXCP_INVAL(ctx);
5388 }
5389
5390 /* XXX: not implemented on 440 ? */
5391 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA)
5392 {
5393 #if defined(CONFIG_USER_ONLY)
5394 GEN_EXCP_PRIVOPC(ctx);
5395 #else
5396 TCGv t0;
5397 if (unlikely(!ctx->supervisor)) {
5398 GEN_EXCP_PRIVOPC(ctx);
5399 return;
5400 }
5401 gen_addr_reg_index(t0, ctx);
5402 #if defined(TARGET_PPC64)
5403 if (!ctx->sf_mode)
5404 tcg_gen_ext32u_tl(t0, t0);
5405 #endif
5406 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
5407 tcg_temp_free(t0);
5408 #endif
5409 }
5410
5411 /* All 405 MAC instructions are translated here */
5412 static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
5413 int opc2, int opc3,
5414 int ra, int rb, int rt, int Rc)
5415 {
5416 TCGv t0, t1;
5417
5418 t0 = tcg_temp_local_new();
5419 t1 = tcg_temp_local_new();
5420
5421 switch (opc3 & 0x0D) {
5422 case 0x05:
5423 /* macchw - macchw. - macchwo - macchwo. */
5424 /* macchws - macchws. - macchwso - macchwso. */
5425 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5426 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5427 /* mulchw - mulchw. */
5428 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5429 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5430 tcg_gen_ext16s_tl(t1, t1);
5431 break;
5432 case 0x04:
5433 /* macchwu - macchwu. - macchwuo - macchwuo. */
5434 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5435 /* mulchwu - mulchwu. */
5436 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5437 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5438 tcg_gen_ext16u_tl(t1, t1);
5439 break;
5440 case 0x01:
5441 /* machhw - machhw. - machhwo - machhwo. */
5442 /* machhws - machhws. - machhwso - machhwso. */
5443 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5444 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5445 /* mulhhw - mulhhw. */
5446 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5447 tcg_gen_ext16s_tl(t0, t0);
5448 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5449 tcg_gen_ext16s_tl(t1, t1);
5450 break;
5451 case 0x00:
5452 /* machhwu - machhwu. - machhwuo - machhwuo. */
5453 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5454 /* mulhhwu - mulhhwu. */
5455 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5456 tcg_gen_ext16u_tl(t0, t0);
5457 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5458 tcg_gen_ext16u_tl(t1, t1);
5459 break;
5460 case 0x0D:
5461 /* maclhw - maclhw. - maclhwo - maclhwo. */
5462 /* maclhws - maclhws. - maclhwso - maclhwso. */
5463 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5464 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5465 /* mullhw - mullhw. */
5466 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5467 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5468 break;
5469 case 0x0C:
5470 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5471 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5472 /* mullhwu - mullhwu. */
5473 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5474 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5475 break;
5476 }
5477 if (opc2 & 0x04) {
5478 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5479 tcg_gen_mul_tl(t1, t0, t1);
5480 if (opc2 & 0x02) {
5481 /* nmultiply-and-accumulate (0x0E) */
5482 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5483 } else {
5484 /* multiply-and-accumulate (0x0C) */
5485 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5486 }
5487
5488 if (opc3 & 0x12) {
5489 /* Check overflow and/or saturate */
5490 int l1 = gen_new_label();
5491
5492 if (opc3 & 0x10) {
5493 /* Start with XER OV disabled, the most likely case */
5494 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
5495 }
5496 if (opc3 & 0x01) {
5497 /* Signed */
5498 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5499 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5500 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5501 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5502 if (opc3 & 0x02) {
5503 /* Saturate */
5504 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5505 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5506 }
5507 } else {
5508 /* Unsigned */
5509 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5510 if (opc3 & 0x02) {
5511 /* Saturate */
5512 tcg_gen_movi_tl(t0, UINT32_MAX);
5513 }
5514 }
5515 if (opc3 & 0x10) {
5516 /* Check overflow */
5517 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
5518 }
5519 gen_set_label(l1);
5520 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5521 }
5522 } else {
5523 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5524 }
5525 tcg_temp_free(t0);
5526 tcg_temp_free(t1);
5527 if (unlikely(Rc) != 0) {
5528 /* Update Rc0 */
5529 gen_set_Rc0(ctx, cpu_gpr[rt]);
5530 }
5531 }
5532
5533 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5534 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) \
5535 { \
5536 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5537 rD(ctx->opcode), Rc(ctx->opcode)); \
5538 }
5539
5540 /* macchw - macchw. */
5541 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5542 /* macchwo - macchwo. */
5543 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5544 /* macchws - macchws. */
5545 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5546 /* macchwso - macchwso. */
5547 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5548 /* macchwsu - macchwsu. */
5549 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5550 /* macchwsuo - macchwsuo. */
5551 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5552 /* macchwu - macchwu. */
5553 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5554 /* macchwuo - macchwuo. */
5555 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5556 /* machhw - machhw. */
5557 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5558 /* machhwo - machhwo. */
5559 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5560 /* machhws - machhws. */
5561 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5562 /* machhwso - machhwso. */
5563 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5564 /* machhwsu - machhwsu. */
5565 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5566 /* machhwsuo - machhwsuo. */
5567 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5568 /* machhwu - machhwu. */
5569 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5570 /* machhwuo - machhwuo. */
5571 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5572 /* maclhw - maclhw. */
5573 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5574 /* maclhwo - maclhwo. */
5575 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5576 /* maclhws - maclhws. */
5577 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5578 /* maclhwso - maclhwso. */
5579 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5580 /* maclhwu - maclhwu. */
5581 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5582 /* maclhwuo - maclhwuo. */
5583 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5584 /* maclhwsu - maclhwsu. */
5585 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5586 /* maclhwsuo - maclhwsuo. */
5587 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5588 /* nmacchw - nmacchw. */
5589 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5590 /* nmacchwo - nmacchwo. */
5591 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5592 /* nmacchws - nmacchws. */
5593 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5594 /* nmacchwso - nmacchwso. */
5595 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5596 /* nmachhw - nmachhw. */
5597 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5598 /* nmachhwo - nmachhwo. */
5599 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5600 /* nmachhws - nmachhws. */
5601 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5602 /* nmachhwso - nmachhwso. */
5603 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5604 /* nmaclhw - nmaclhw. */
5605 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5606 /* nmaclhwo - nmaclhwo. */
5607 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5608 /* nmaclhws - nmaclhws. */
5609 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5610 /* nmaclhwso - nmaclhwso. */
5611 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5612
5613 /* mulchw - mulchw. */
5614 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5615 /* mulchwu - mulchwu. */
5616 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5617 /* mulhhw - mulhhw. */
5618 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5619 /* mulhhwu - mulhhwu. */
5620 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5621 /* mullhw - mullhw. */
5622 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5623 /* mullhwu - mullhwu. */
5624 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5625
5626 /* mfdcr */
5627 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR)
5628 {
5629 #if defined(CONFIG_USER_ONLY)
5630 GEN_EXCP_PRIVREG(ctx);
5631 #else
5632 TCGv dcrn;
5633 if (unlikely(!ctx->supervisor)) {
5634 GEN_EXCP_PRIVREG(ctx);
5635 return;
5636 }
5637 /* NIP cannot be restored if the memory exception comes from an helper */
5638 gen_update_nip(ctx, ctx->nip - 4);
5639 dcrn = tcg_const_tl(SPR(ctx->opcode));
5640 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], dcrn);
5641 tcg_temp_free(dcrn);
5642 #endif
5643 }
5644
5645 /* mtdcr */
5646 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR)
5647 {
5648 #if defined(CONFIG_USER_ONLY)
5649 GEN_EXCP_PRIVREG(ctx);
5650 #else
5651 TCGv dcrn;
5652 if (unlikely(!ctx->supervisor)) {
5653 GEN_EXCP_PRIVREG(ctx);
5654 return;
5655 }
5656 /* NIP cannot be restored if the memory exception comes from an helper */
5657 gen_update_nip(ctx, ctx->nip - 4);
5658 dcrn = tcg_const_tl(SPR(ctx->opcode));
5659 gen_helper_store_dcr(dcrn, cpu_gpr[rS(ctx->opcode)]);
5660 tcg_temp_free(dcrn);
5661 #endif
5662 }
5663
5664 /* mfdcrx */
5665 /* XXX: not implemented on 440 ? */
5666 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX)
5667 {
5668 #if defined(CONFIG_USER_ONLY)
5669 GEN_EXCP_PRIVREG(ctx);
5670 #else
5671 if (unlikely(!ctx->supervisor)) {
5672 GEN_EXCP_PRIVREG(ctx);
5673 return;
5674 }
5675 /* NIP cannot be restored if the memory exception comes from an helper */
5676 gen_update_nip(ctx, ctx->nip - 4);
5677 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5678 /* Note: Rc update flag set leads to undefined state of Rc0 */
5679 #endif
5680 }
5681
5682 /* mtdcrx */
5683 /* XXX: not implemented on 440 ? */
5684 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX)
5685 {
5686 #if defined(CONFIG_USER_ONLY)
5687 GEN_EXCP_PRIVREG(ctx);
5688 #else
5689 if (unlikely(!ctx->supervisor)) {
5690 GEN_EXCP_PRIVREG(ctx);
5691 return;
5692 }
5693 /* NIP cannot be restored if the memory exception comes from an helper */
5694 gen_update_nip(ctx, ctx->nip - 4);
5695 gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5696 /* Note: Rc update flag set leads to undefined state of Rc0 */
5697 #endif
5698 }
5699
5700 /* mfdcrux (PPC 460) : user-mode access to DCR */
5701 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX)
5702 {
5703 /* NIP cannot be restored if the memory exception comes from an helper */
5704 gen_update_nip(ctx, ctx->nip - 4);
5705 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5706 /* Note: Rc update flag set leads to undefined state of Rc0 */
5707 }
5708
5709 /* mtdcrux (PPC 460) : user-mode access to DCR */
5710 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX)
5711 {
5712 /* NIP cannot be restored if the memory exception comes from an helper */
5713 gen_update_nip(ctx, ctx->nip - 4);
5714 gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5715 /* Note: Rc update flag set leads to undefined state of Rc0 */
5716 }
5717
5718 /* dccci */
5719 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON)
5720 {
5721 #if defined(CONFIG_USER_ONLY)
5722 GEN_EXCP_PRIVOPC(ctx);
5723 #else
5724 if (unlikely(!ctx->supervisor)) {
5725 GEN_EXCP_PRIVOPC(ctx);
5726 return;
5727 }
5728 /* interpreted as no-op */
5729 #endif
5730 }
5731
5732 /* dcread */
5733 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON)
5734 {
5735 #if defined(CONFIG_USER_ONLY)
5736 GEN_EXCP_PRIVOPC(ctx);
5737 #else
5738 TCGv EA, val;
5739 if (unlikely(!ctx->supervisor)) {
5740 GEN_EXCP_PRIVOPC(ctx);
5741 return;
5742 }
5743 EA = tcg_temp_new();
5744 gen_set_access_type(ACCESS_CACHE);
5745 gen_addr_reg_index(EA, ctx);
5746 val = tcg_temp_new();
5747 gen_qemu_ld32u(val, EA, ctx->mem_idx);
5748 tcg_temp_free(val);
5749 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5750 tcg_temp_free(EA);
5751 #endif
5752 }
5753
5754 /* icbt */
5755 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT)
5756 {
5757 /* interpreted as no-op */
5758 /* XXX: specification say this is treated as a load by the MMU
5759 * but does not generate any exception
5760 */
5761 }
5762
5763 /* iccci */
5764 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON)
5765 {
5766 #if defined(CONFIG_USER_ONLY)
5767 GEN_EXCP_PRIVOPC(ctx);
5768 #else
5769 if (unlikely(!ctx->supervisor)) {
5770 GEN_EXCP_PRIVOPC(ctx);
5771 return;
5772 }
5773 /* interpreted as no-op */
5774 #endif
5775 }
5776
5777 /* icread */
5778 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON)
5779 {
5780 #if defined(CONFIG_USER_ONLY)
5781 GEN_EXCP_PRIVOPC(ctx);
5782 #else
5783 if (unlikely(!ctx->supervisor)) {
5784 GEN_EXCP_PRIVOPC(ctx);
5785 return;
5786 }
5787 /* interpreted as no-op */
5788 #endif
5789 }
5790
5791 /* rfci (supervisor only) */
5792 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP)
5793 {
5794 #if defined(CONFIG_USER_ONLY)
5795 GEN_EXCP_PRIVOPC(ctx);
5796 #else
5797 if (unlikely(!ctx->supervisor)) {
5798 GEN_EXCP_PRIVOPC(ctx);
5799 return;
5800 }
5801 /* Restore CPU state */
5802 gen_helper_40x_rfci();
5803 GEN_SYNC(ctx);
5804 #endif
5805 }
5806
5807 GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE)
5808 {
5809 #if defined(CONFIG_USER_ONLY)
5810 GEN_EXCP_PRIVOPC(ctx);
5811 #else
5812 if (unlikely(!ctx->supervisor)) {
5813 GEN_EXCP_PRIVOPC(ctx);
5814 return;
5815 }
5816 /* Restore CPU state */
5817 gen_helper_rfci();
5818 GEN_SYNC(ctx);
5819 #endif
5820 }
5821
5822 /* BookE specific */
5823 /* XXX: not implemented on 440 ? */
5824 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI)
5825 {
5826 #if defined(CONFIG_USER_ONLY)
5827 GEN_EXCP_PRIVOPC(ctx);
5828 #else
5829 if (unlikely(!ctx->supervisor)) {
5830 GEN_EXCP_PRIVOPC(ctx);
5831 return;
5832 }
5833 /* Restore CPU state */
5834 gen_helper_rfdi();
5835 GEN_SYNC(ctx);
5836 #endif
5837 }
5838
5839 /* XXX: not implemented on 440 ? */
5840 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI)
5841 {
5842 #if defined(CONFIG_USER_ONLY)
5843 GEN_EXCP_PRIVOPC(ctx);
5844 #else
5845 if (unlikely(!ctx->supervisor)) {
5846 GEN_EXCP_PRIVOPC(ctx);
5847 return;
5848 }
5849 /* Restore CPU state */
5850 gen_helper_rfmci();
5851 GEN_SYNC(ctx);
5852 #endif
5853 }
5854
5855 /* TLB management - PowerPC 405 implementation */
5856 /* tlbre */
5857 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB)
5858 {
5859 #if defined(CONFIG_USER_ONLY)
5860 GEN_EXCP_PRIVOPC(ctx);
5861 #else
5862 if (unlikely(!ctx->supervisor)) {
5863 GEN_EXCP_PRIVOPC(ctx);
5864 return;
5865 }
5866 switch (rB(ctx->opcode)) {
5867 case 0:
5868 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5869 break;
5870 case 1:
5871 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5872 break;
5873 default:
5874 GEN_EXCP_INVAL(ctx);
5875 break;
5876 }
5877 #endif
5878 }
5879
5880 /* tlbsx - tlbsx. */
5881 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB)
5882 {
5883 #if defined(CONFIG_USER_ONLY)
5884 GEN_EXCP_PRIVOPC(ctx);
5885 #else
5886 TCGv t0;
5887 if (unlikely(!ctx->supervisor)) {
5888 GEN_EXCP_PRIVOPC(ctx);
5889 return;
5890 }
5891 t0 = tcg_temp_new();
5892 gen_addr_reg_index(t0, ctx);
5893 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], t0);
5894 tcg_temp_free(t0);
5895 if (Rc(ctx->opcode)) {
5896 int l1 = gen_new_label();
5897 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
5898 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
5899 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
5900 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5901 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5902 gen_set_label(l1);
5903 }
5904 #endif
5905 }
5906
5907 /* tlbwe */
5908 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB)
5909 {
5910 #if defined(CONFIG_USER_ONLY)
5911 GEN_EXCP_PRIVOPC(ctx);
5912 #else
5913 if (unlikely(!ctx->supervisor)) {
5914 GEN_EXCP_PRIVOPC(ctx);
5915 return;
5916 }
5917 switch (rB(ctx->opcode)) {
5918 case 0:
5919 gen_helper_4xx_tlbwe_hi(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5920 break;
5921 case 1:
5922 gen_helper_4xx_tlbwe_lo(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5923 break;
5924 default:
5925 GEN_EXCP_INVAL(ctx);
5926 break;
5927 }
5928 #endif
5929 }
5930
5931 /* TLB management - PowerPC 440 implementation */
5932 /* tlbre */
5933 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE)
5934 {
5935 #if defined(CONFIG_USER_ONLY)
5936 GEN_EXCP_PRIVOPC(ctx);
5937 #else
5938 if (unlikely(!ctx->supervisor)) {
5939 GEN_EXCP_PRIVOPC(ctx);
5940 return;
5941 }
5942 switch (rB(ctx->opcode)) {
5943 case 0:
5944 case 1:
5945 case 2:
5946 {
5947 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5948 gen_helper_440_tlbwe(t0, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5949 tcg_temp_free_i32(t0);
5950 }
5951 break;
5952 default:
5953 GEN_EXCP_INVAL(ctx);
5954 break;
5955 }
5956 #endif
5957 }
5958
5959 /* tlbsx - tlbsx. */
5960 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE)
5961 {
5962 #if defined(CONFIG_USER_ONLY)
5963 GEN_EXCP_PRIVOPC(ctx);
5964 #else
5965 TCGv t0;
5966 if (unlikely(!ctx->supervisor)) {
5967 GEN_EXCP_PRIVOPC(ctx);
5968 return;
5969 }
5970 t0 = tcg_temp_new();
5971 gen_addr_reg_index(t0, ctx);
5972 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], t0);
5973 tcg_temp_free(t0);
5974 if (Rc(ctx->opcode)) {
5975 int l1 = gen_new_label();
5976 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
5977 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
5978 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
5979 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5980 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5981 gen_set_label(l1);
5982 }
5983 #endif
5984 }
5985
5986 /* tlbwe */
5987 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE)
5988 {
5989 #if defined(CONFIG_USER_ONLY)
5990 GEN_EXCP_PRIVOPC(ctx);
5991 #else
5992 if (unlikely(!ctx->supervisor)) {
5993 GEN_EXCP_PRIVOPC(ctx);
5994 return;
5995 }
5996 switch (rB(ctx->opcode)) {
5997 case 0:
5998 case 1:
5999 case 2:
6000 {
6001 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6002 gen_helper_440_tlbwe(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
6003 tcg_temp_free_i32(t0);
6004 }
6005 break;
6006 default:
6007 GEN_EXCP_INVAL(ctx);
6008 break;
6009 }
6010 #endif
6011 }
6012
6013 /* wrtee */
6014 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE)
6015 {
6016 #if defined(CONFIG_USER_ONLY)
6017 GEN_EXCP_PRIVOPC(ctx);
6018 #else
6019 TCGv t0;
6020 if (unlikely(!ctx->supervisor)) {
6021 GEN_EXCP_PRIVOPC(ctx);
6022 return;
6023 }
6024 t0 = tcg_temp_new();
6025 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6026 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6027 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6028 tcg_temp_free(t0);
6029 /* Stop translation to have a chance to raise an exception
6030 * if we just set msr_ee to 1
6031 */
6032 GEN_STOP(ctx);
6033 #endif
6034 }
6035
6036 /* wrteei */
6037 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE)
6038 {
6039 #if defined(CONFIG_USER_ONLY)
6040 GEN_EXCP_PRIVOPC(ctx);
6041 #else
6042 if (unlikely(!ctx->supervisor)) {
6043 GEN_EXCP_PRIVOPC(ctx);
6044 return;
6045 }
6046 if (ctx->opcode & 0x00010000) {
6047 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6048 /* Stop translation to have a chance to raise an exception */
6049 GEN_STOP(ctx);
6050 } else {
6051 tcg_gen_andi_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6052 }
6053 #endif
6054 }
6055
6056 /* PowerPC 440 specific instructions */
6057 /* dlmzb */
6058 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC)
6059 {
6060 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6061 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
6062 cpu_gpr[rB(ctx->opcode)], t0);
6063 tcg_temp_free_i32(t0);
6064 }
6065
6066 /* mbar replaces eieio on 440 */
6067 GEN_HANDLER(mbar, 0x1F, 0x16, 0x13, 0x001FF801, PPC_BOOKE)
6068 {
6069 /* interpreted as no-op */
6070 }
6071
6072 /* msync replaces sync on 440 */
6073 GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE)
6074 {
6075 /* interpreted as no-op */
6076 }
6077
6078 /* icbt */
6079 GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE)
6080 {
6081 /* interpreted as no-op */
6082 /* XXX: specification say this is treated as a load by the MMU
6083 * but does not generate any exception
6084 */
6085 }
6086
6087 /*** Altivec vector extension ***/
6088 /* Altivec registers moves */
6089
6090 #define GEN_VR_LDX(name, opc2, opc3) \
6091 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6092 { \
6093 TCGv EA; \
6094 if (unlikely(!ctx->altivec_enabled)) { \
6095 GEN_EXCP_NO_VR(ctx); \
6096 return; \
6097 } \
6098 EA = tcg_temp_new(); \
6099 gen_addr_reg_index(EA, ctx); \
6100 tcg_gen_andi_tl(EA, EA, ~0xf); \
6101 if (ctx->mem_idx & 1) { \
6102 gen_qemu_ld64(cpu_avrl[rD(ctx->opcode)], EA, ctx->mem_idx); \
6103 tcg_gen_addi_tl(EA, EA, 8); \
6104 gen_qemu_ld64(cpu_avrh[rD(ctx->opcode)], EA, ctx->mem_idx); \
6105 } else { \
6106 gen_qemu_ld64(cpu_avrh[rD(ctx->opcode)], EA, ctx->mem_idx); \
6107 tcg_gen_addi_tl(EA, EA, 8); \
6108 gen_qemu_ld64(cpu_avrl[rD(ctx->opcode)], EA, ctx->mem_idx); \
6109 } \
6110 tcg_temp_free(EA); \
6111 }
6112
6113 #define GEN_VR_STX(name, opc2, opc3) \
6114 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6115 { \
6116 TCGv EA; \
6117 if (unlikely(!ctx->altivec_enabled)) { \
6118 GEN_EXCP_NO_VR(ctx); \
6119 return; \
6120 } \
6121 EA = tcg_temp_new(); \
6122 gen_addr_reg_index(EA, ctx); \
6123 tcg_gen_andi_tl(EA, EA, ~0xf); \
6124 if (ctx->mem_idx & 1) { \
6125 gen_qemu_st64(cpu_avrl[rD(ctx->opcode)], EA, ctx->mem_idx); \
6126 tcg_gen_addi_tl(EA, EA, 8); \
6127 gen_qemu_st64(cpu_avrh[rD(ctx->opcode)], EA, ctx->mem_idx); \
6128 } else { \
6129 gen_qemu_st64(cpu_avrh[rD(ctx->opcode)], EA, ctx->mem_idx); \
6130 tcg_gen_addi_tl(EA, EA, 8); \
6131 gen_qemu_st64(cpu_avrl[rD(ctx->opcode)], EA, ctx->mem_idx); \
6132 } \
6133 tcg_temp_free(EA); \
6134 }
6135
6136 GEN_VR_LDX(lvx, 0x07, 0x03);
6137 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6138 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6139
6140 GEN_VR_STX(svx, 0x07, 0x07);
6141 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6142 GEN_VR_STX(svxl, 0x07, 0x0F);
6143
6144 /*** SPE extension ***/
6145 /* Register moves */
6146
6147 static always_inline void gen_load_gpr64(TCGv_i64 t, int reg) {
6148 #if defined(TARGET_PPC64)
6149 tcg_gen_mov_i64(t, cpu_gpr[reg]);
6150 #else
6151 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
6152 #endif
6153 }
6154
6155 static always_inline void gen_store_gpr64(int reg, TCGv_i64 t) {
6156 #if defined(TARGET_PPC64)
6157 tcg_gen_mov_i64(cpu_gpr[reg], t);
6158 #else
6159 TCGv_i64 tmp = tcg_temp_new_i64();
6160 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
6161 tcg_gen_shri_i64(tmp, t, 32);
6162 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
6163 tcg_temp_free_i64(tmp);
6164 #endif
6165 }
6166
6167 #define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
6168 GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \
6169 { \
6170 if (Rc(ctx->opcode)) \
6171 gen_##name1(ctx); \
6172 else \
6173 gen_##name0(ctx); \
6174 }
6175
6176 /* Handler for undefined SPE opcodes */
6177 static always_inline void gen_speundef (DisasContext *ctx)
6178 {
6179 GEN_EXCP_INVAL(ctx);
6180 }
6181
6182 /* SPE logic */
6183 #if defined(TARGET_PPC64)
6184 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6185 static always_inline void gen_##name (DisasContext *ctx) \
6186 { \
6187 if (unlikely(!ctx->spe_enabled)) { \
6188 GEN_EXCP_NO_AP(ctx); \
6189 return; \
6190 } \
6191 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6192 cpu_gpr[rB(ctx->opcode)]); \
6193 }
6194 #else
6195 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6196 static always_inline void gen_##name (DisasContext *ctx) \
6197 { \
6198 if (unlikely(!ctx->spe_enabled)) { \
6199 GEN_EXCP_NO_AP(ctx); \
6200 return; \
6201 } \
6202 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6203 cpu_gpr[rB(ctx->opcode)]); \
6204 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6205 cpu_gprh[rB(ctx->opcode)]); \
6206 }
6207 #endif
6208
6209 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
6210 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
6211 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
6212 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
6213 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
6214 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
6215 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
6216 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
6217
6218 /* SPE logic immediate */
6219 #if defined(TARGET_PPC64)
6220 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6221 static always_inline void gen_##name (DisasContext *ctx) \
6222 { \
6223 if (unlikely(!ctx->spe_enabled)) { \
6224 GEN_EXCP_NO_AP(ctx); \
6225 return; \
6226 } \
6227 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6228 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6229 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6230 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6231 tcg_opi(t0, t0, rB(ctx->opcode)); \
6232 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6233 tcg_gen_trunc_i64_i32(t1, t2); \
6234 tcg_temp_free_i64(t2); \
6235 tcg_opi(t1, t1, rB(ctx->opcode)); \
6236 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6237 tcg_temp_free_i32(t0); \
6238 tcg_temp_free_i32(t1); \
6239 }
6240 #else
6241 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6242 static always_inline void gen_##name (DisasContext *ctx) \
6243 { \
6244 if (unlikely(!ctx->spe_enabled)) { \
6245 GEN_EXCP_NO_AP(ctx); \
6246 return; \
6247 } \
6248 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6249 rB(ctx->opcode)); \
6250 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6251 rB(ctx->opcode)); \
6252 }
6253 #endif
6254 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
6255 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
6256 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
6257 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
6258
6259 /* SPE arithmetic */
6260 #if defined(TARGET_PPC64)
6261 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6262 static always_inline void gen_##name (DisasContext *ctx) \
6263 { \
6264 if (unlikely(!ctx->spe_enabled)) { \
6265 GEN_EXCP_NO_AP(ctx); \
6266 return; \
6267 } \
6268 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6269 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6270 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6271 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6272 tcg_op(t0, t0); \
6273 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6274 tcg_gen_trunc_i64_i32(t1, t2); \
6275 tcg_temp_free_i64(t2); \
6276 tcg_op(t1, t1); \
6277 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6278 tcg_temp_free_i32(t0); \
6279 tcg_temp_free_i32(t1); \
6280 }
6281 #else
6282 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6283 static always_inline void gen_##name (DisasContext *ctx) \
6284 { \
6285 if (unlikely(!ctx->spe_enabled)) { \
6286 GEN_EXCP_NO_AP(ctx); \
6287 return; \
6288 } \
6289 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
6290 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
6291 }
6292 #endif
6293
6294 static always_inline void gen_op_evabs (TCGv_i32 ret, TCGv_i32 arg1)
6295 {
6296 int l1 = gen_new_label();
6297 int l2 = gen_new_label();
6298
6299 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
6300 tcg_gen_neg_i32(ret, arg1);
6301 tcg_gen_br(l2);
6302 gen_set_label(l1);
6303 tcg_gen_mov_i32(ret, arg1);
6304 gen_set_label(l2);
6305 }
6306 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
6307 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
6308 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
6309 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
6310 static always_inline void gen_op_evrndw (TCGv_i32 ret, TCGv_i32 arg1)
6311 {
6312 tcg_gen_addi_i32(ret, arg1, 0x8000);
6313 tcg_gen_ext16u_i32(ret, ret);
6314 }
6315 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
6316 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
6317 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
6318
6319 #if defined(TARGET_PPC64)
6320 #define GEN_SPEOP_ARITH2(name, tcg_op) \
6321 static always_inline void gen_##name (DisasContext *ctx) \
6322 { \
6323 if (unlikely(!ctx->spe_enabled)) { \
6324 GEN_EXCP_NO_AP(ctx); \
6325 return; \
6326 } \
6327 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6328 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6329 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
6330 TCGv_i64 t3 = tcg_temp_local_new(TCG_TYPE_I64); \
6331 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6332 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
6333 tcg_op(t0, t0, t2); \
6334 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
6335 tcg_gen_trunc_i64_i32(t1, t3); \
6336 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
6337 tcg_gen_trunc_i64_i32(t2, t3); \
6338 tcg_temp_free_i64(t3); \
6339 tcg_op(t1, t1, t2); \
6340 tcg_temp_free_i32(t2); \
6341 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6342 tcg_temp_free_i32(t0); \
6343 tcg_temp_free_i32(t1); \
6344 }
6345 #else
6346 #define GEN_SPEOP_ARITH2(name, tcg_op) \
6347 static always_inline void gen_##name (DisasContext *ctx) \
6348 { \
6349 if (unlikely(!ctx->spe_enabled)) { \
6350 GEN_EXCP_NO_AP(ctx); \
6351 return; \
6352 } \
6353 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6354 cpu_gpr[rB(ctx->opcode)]); \
6355 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6356 cpu_gprh[rB(ctx->opcode)]); \
6357 }
6358 #endif
6359
6360 static always_inline void gen_op_evsrwu (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6361 {
6362 TCGv_i32 t0;
6363 int l1, l2;
6364
6365 l1 = gen_new_label();
6366 l2 = gen_new_label();
6367 t0 = tcg_temp_local_new_i32();
6368 /* No error here: 6 bits are used */
6369 tcg_gen_andi_i32(t0, arg2, 0x3F);
6370 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6371 tcg_gen_shr_i32(ret, arg1, t0);
6372 tcg_gen_br(l2);
6373 gen_set_label(l1);
6374 tcg_gen_movi_i32(ret, 0);
6375 tcg_gen_br(l2);
6376 tcg_temp_free_i32(t0);
6377 }
6378 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
6379 static always_inline void gen_op_evsrws (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6380 {
6381 TCGv_i32 t0;
6382 int l1, l2;
6383
6384 l1 = gen_new_label();
6385 l2 = gen_new_label();
6386 t0 = tcg_temp_local_new_i32();
6387 /* No error here: 6 bits are used */
6388 tcg_gen_andi_i32(t0, arg2, 0x3F);
6389 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6390 tcg_gen_sar_i32(ret, arg1, t0);
6391 tcg_gen_br(l2);
6392 gen_set_label(l1);
6393 tcg_gen_movi_i32(ret, 0);
6394 tcg_gen_br(l2);
6395 tcg_temp_free_i32(t0);
6396 }
6397 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
6398 static always_inline void gen_op_evslw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6399 {
6400 TCGv_i32 t0;
6401 int l1, l2;
6402
6403 l1 = gen_new_label();
6404 l2 = gen_new_label();
6405 t0 = tcg_temp_local_new_i32();
6406 /* No error here: 6 bits are used */
6407 tcg_gen_andi_i32(t0, arg2, 0x3F);
6408 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6409 tcg_gen_shl_i32(ret, arg1, t0);
6410 tcg_gen_br(l2);
6411 gen_set_label(l1);
6412 tcg_gen_movi_i32(ret, 0);
6413 tcg_gen_br(l2);
6414 tcg_temp_free_i32(t0);
6415 }
6416 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
6417 static always_inline void gen_op_evrlw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6418 {
6419 TCGv_i32 t0 = tcg_temp_new_i32();
6420 tcg_gen_andi_i32(t0, arg2, 0x1F);
6421 tcg_gen_rotl_i32(ret, arg1, t0);
6422 tcg_temp_free_i32(t0);
6423 }
6424 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
6425 static always_inline void gen_evmergehi (DisasContext *ctx)
6426 {
6427 if (unlikely(!ctx->spe_enabled)) {
6428 GEN_EXCP_NO_AP(ctx);
6429 return;
6430 }
6431 #if defined(TARGET_PPC64)
6432 TCGv t0 = tcg_temp_new();
6433 TCGv t1 = tcg_temp_new();
6434 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
6435 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
6436 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6437 tcg_temp_free(t0);
6438 tcg_temp_free(t1);
6439 #else
6440 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6441 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6442 #endif
6443 }
6444 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
6445 static always_inline void gen_op_evsubf (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6446 {
6447 tcg_gen_sub_i32(ret, arg2, arg1);
6448 }
6449 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
6450
6451 /* SPE arithmetic immediate */
6452 #if defined(TARGET_PPC64)
6453 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6454 static always_inline void gen_##name (DisasContext *ctx) \
6455 { \
6456 if (unlikely(!ctx->spe_enabled)) { \
6457 GEN_EXCP_NO_AP(ctx); \
6458 return; \
6459 } \
6460 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6461 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6462 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6463 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
6464 tcg_op(t0, t0, rA(ctx->opcode)); \
6465 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6466 tcg_gen_trunc_i64_i32(t1, t2); \
6467 tcg_temp_free_i64(t2); \
6468 tcg_op(t1, t1, rA(ctx->opcode)); \
6469 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6470 tcg_temp_free_i32(t0); \
6471 tcg_temp_free_i32(t1); \
6472 }
6473 #else
6474 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6475 static always_inline void gen_##name (DisasContext *ctx) \
6476 { \
6477 if (unlikely(!ctx->spe_enabled)) { \
6478 GEN_EXCP_NO_AP(ctx); \
6479 return; \
6480 } \
6481 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
6482 rA(ctx->opcode)); \
6483 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
6484 rA(ctx->opcode)); \
6485 }
6486 #endif
6487 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
6488 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
6489
6490 /* SPE comparison */
6491 #if defined(TARGET_PPC64)
6492 #define GEN_SPEOP_COMP(name, tcg_cond) \
6493 static always_inline void gen_##name (DisasContext *ctx) \
6494 { \
6495 if (unlikely(!ctx->spe_enabled)) { \
6496 GEN_EXCP_NO_AP(ctx); \
6497 return; \
6498 } \
6499 int l1 = gen_new_label(); \
6500 int l2 = gen_new_label(); \
6501 int l3 = gen_new_label(); \
6502 int l4 = gen_new_label(); \
6503 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6504 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6505 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6506 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6507 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
6508 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
6509 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
6510 tcg_gen_br(l2); \
6511 gen_set_label(l1); \
6512 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
6513 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
6514 gen_set_label(l2); \
6515 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6516 tcg_gen_trunc_i64_i32(t0, t2); \
6517 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6518 tcg_gen_trunc_i64_i32(t1, t2); \
6519 tcg_temp_free_i64(t2); \
6520 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
6521 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6522 ~(CRF_CH | CRF_CH_AND_CL)); \
6523 tcg_gen_br(l4); \
6524 gen_set_label(l3); \
6525 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6526 CRF_CH | CRF_CH_OR_CL); \
6527 gen_set_label(l4); \
6528 tcg_temp_free_i32(t0); \
6529 tcg_temp_free_i32(t1); \
6530 }
6531 #else
6532 #define GEN_SPEOP_COMP(name, tcg_cond) \
6533 static always_inline void gen_##name (DisasContext *ctx) \
6534 { \
6535 if (unlikely(!ctx->spe_enabled)) { \
6536 GEN_EXCP_NO_AP(ctx); \
6537 return; \
6538 } \
6539 int l1 = gen_new_label(); \
6540 int l2 = gen_new_label(); \
6541 int l3 = gen_new_label(); \
6542 int l4 = gen_new_label(); \
6543 \
6544 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
6545 cpu_gpr[rB(ctx->opcode)], l1); \
6546 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
6547 tcg_gen_br(l2); \
6548 gen_set_label(l1); \
6549 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
6550 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
6551 gen_set_label(l2); \
6552 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
6553 cpu_gprh[rB(ctx->opcode)], l3); \
6554 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6555 ~(CRF_CH | CRF_CH_AND_CL)); \
6556 tcg_gen_br(l4); \
6557 gen_set_label(l3); \
6558 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6559 CRF_CH | CRF_CH_OR_CL); \
6560 gen_set_label(l4); \
6561 }
6562 #endif
6563 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
6564 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
6565 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
6566 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
6567 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
6568
6569 /* SPE misc */
6570 static always_inline void gen_brinc (DisasContext *ctx)
6571 {
6572 /* Note: brinc is usable even if SPE is disabled */
6573 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
6574 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6575 }
6576 static always_inline void gen_evmergelo (DisasContext *ctx)
6577 {
6578 if (unlikely(!ctx->spe_enabled)) {
6579 GEN_EXCP_NO_AP(ctx);
6580 return;
6581 }
6582 #if defined(TARGET_PPC64)
6583 TCGv t0 = tcg_temp_new();
6584 TCGv t1 = tcg_temp_new();
6585 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
6586 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
6587 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6588 tcg_temp_free(t0);
6589 tcg_temp_free(t1);
6590 #else
6591 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6592 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6593 #endif
6594 }
6595 static always_inline void gen_evmergehilo (DisasContext *ctx)
6596 {
6597 if (unlikely(!ctx->spe_enabled)) {
6598 GEN_EXCP_NO_AP(ctx);
6599 return;
6600 }
6601 #if defined(TARGET_PPC64)
6602 TCGv t0 = tcg_temp_new();
6603 TCGv t1 = tcg_temp_new();
6604 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
6605 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
6606 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6607 tcg_temp_free(t0);
6608 tcg_temp_free(t1);
6609 #else
6610 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6611 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6612 #endif
6613 }
6614 static always_inline void gen_evmergelohi (DisasContext *ctx)
6615 {
6616 if (unlikely(!ctx->spe_enabled)) {
6617 GEN_EXCP_NO_AP(ctx);
6618 return;
6619 }
6620 #if defined(TARGET_PPC64)
6621 TCGv t0 = tcg_temp_new();
6622 TCGv t1 = tcg_temp_new();
6623 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
6624 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
6625 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6626 tcg_temp_free(t0);
6627 tcg_temp_free(t1);
6628 #else
6629 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6630 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6631 #endif
6632 }
6633 static always_inline void gen_evsplati (DisasContext *ctx)
6634 {
6635 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 11)) >> 27;
6636
6637 #if defined(TARGET_PPC64)
6638 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
6639 #else
6640 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
6641 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
6642 #endif
6643 }
6644 static always_inline void gen_evsplatfi (DisasContext *ctx)
6645 {
6646 uint64_t imm = rA(ctx->opcode) << 11;
6647
6648 #if defined(TARGET_PPC64)
6649 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
6650 #else
6651 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
6652 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
6653 #endif
6654 }
6655
6656 static always_inline void gen_evsel (DisasContext *ctx)
6657 {
6658 int l1 = gen_new_label();
6659 int l2 = gen_new_label();
6660 int l3 = gen_new_label();
6661 int l4 = gen_new_label();
6662 TCGv_i32 t0 = tcg_temp_local_new_i32();
6663 #if defined(TARGET_PPC64)
6664 TCGv t1 = tcg_temp_local_new();
6665 TCGv t2 = tcg_temp_local_new();
6666 #endif
6667 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
6668 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
6669 #if defined(TARGET_PPC64)
6670 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
6671 #else
6672 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6673 #endif
6674 tcg_gen_br(l2);
6675 gen_set_label(l1);
6676 #if defined(TARGET_PPC64)
6677 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
6678 #else
6679 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6680 #endif
6681 gen_set_label(l2);
6682 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
6683 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
6684 #if defined(TARGET_PPC64)
6685 tcg_gen_andi_tl(t2, cpu_gpr[rA(ctx->opcode)], 0x00000000FFFFFFFFULL);
6686 #else
6687 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6688 #endif
6689 tcg_gen_br(l4);
6690 gen_set_label(l3);
6691 #if defined(TARGET_PPC64)
6692 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFULL);
6693 #else
6694 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6695 #endif
6696 gen_set_label(l4);
6697 tcg_temp_free_i32(t0);
6698 #if defined(TARGET_PPC64)
6699 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
6700 tcg_temp_free(t1);
6701 tcg_temp_free(t2);
6702 #endif
6703 }
6704 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE)
6705 {
6706 gen_evsel(ctx);
6707 }
6708 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE)
6709 {
6710 gen_evsel(ctx);
6711 }
6712 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE)
6713 {
6714 gen_evsel(ctx);
6715 }
6716 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE)
6717 {
6718 gen_evsel(ctx);
6719 }
6720
6721 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE); ////
6722 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE);
6723 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE); ////
6724 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE);
6725 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE); ////
6726 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE); ////
6727 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE); ////
6728 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE); //
6729 GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE); ////
6730 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE); ////
6731 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE); ////
6732 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE); ////
6733 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE); ////
6734 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE); ////
6735 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE); ////
6736 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE);
6737 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE); ////
6738 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE);
6739 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE); //
6740 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE);
6741 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE); ////
6742 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE); ////
6743 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE); ////
6744 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); ////
6745 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); ////
6746
6747 /* SPE load and stores */
6748 static always_inline void gen_addr_spe_imm_index (TCGv EA, DisasContext *ctx, int sh)
6749 {
6750 target_ulong uimm = rB(ctx->opcode);
6751
6752 if (rA(ctx->opcode) == 0)
6753 tcg_gen_movi_tl(EA, uimm << sh);
6754 else
6755 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
6756 }
6757
6758 static always_inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
6759 {
6760 #if defined(TARGET_PPC64)
6761 gen_qemu_ld64(cpu_gpr[rD(ctx->opcode)], addr, ctx->mem_idx);
6762 #else
6763 TCGv_i64 t0 = tcg_temp_new_i64();
6764 gen_qemu_ld64(t0, addr, ctx->mem_idx);
6765 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
6766 tcg_gen_shri_i64(t0, t0, 32);
6767 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
6768 tcg_temp_free_i64(t0);
6769 #endif
6770 }
6771
6772 static always_inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
6773 {
6774 #if defined(TARGET_PPC64)
6775 TCGv t0 = tcg_temp_new();
6776 gen_qemu_ld32u(t0, addr, ctx->mem_idx);
6777 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
6778 tcg_gen_addi_tl(addr, addr, 4);
6779 gen_qemu_ld32u(t0, addr, ctx->mem_idx);
6780 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6781 tcg_temp_free(t0);
6782 #else
6783 gen_qemu_ld32u(cpu_gprh[rD(ctx->opcode)], addr, ctx->mem_idx);
6784 tcg_gen_addi_tl(addr, addr, 4);
6785 gen_qemu_ld32u(cpu_gpr[rD(ctx->opcode)], addr, ctx->mem_idx);
6786 #endif
6787 }
6788
6789 static always_inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
6790 {
6791 TCGv t0 = tcg_temp_new();
6792 #if defined(TARGET_PPC64)
6793 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6794 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
6795 tcg_gen_addi_tl(addr, addr, 2);
6796 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6797 tcg_gen_shli_tl(t0, t0, 32);
6798 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6799 tcg_gen_addi_tl(addr, addr, 2);
6800 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6801 tcg_gen_shli_tl(t0, t0, 16);
6802 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6803 tcg_gen_addi_tl(addr, addr, 2);
6804 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6805 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6806 #else
6807 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6808 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
6809 tcg_gen_addi_tl(addr, addr, 2);
6810 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6811 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
6812 tcg_gen_addi_tl(addr, addr, 2);
6813 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6814 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
6815 tcg_gen_addi_tl(addr, addr, 2);
6816 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6817 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6818 #endif
6819 tcg_temp_free(t0);
6820 }
6821
6822 static always_inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
6823 {
6824 TCGv t0 = tcg_temp_new();
6825 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6826 #if defined(TARGET_PPC64)
6827 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
6828 tcg_gen_shli_tl(t0, t0, 16);
6829 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6830 #else
6831 tcg_gen_shli_tl(t0, t0, 16);
6832 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
6833 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6834 #endif
6835 tcg_temp_free(t0);
6836 }
6837
6838 static always_inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
6839 {
6840 TCGv t0 = tcg_temp_new();
6841 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6842 #if defined(TARGET_PPC64)
6843 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
6844 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6845 #else
6846 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
6847 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6848 #endif
6849 tcg_temp_free(t0);
6850 }
6851
6852 static always_inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
6853 {
6854 TCGv t0 = tcg_temp_new();
6855 gen_qemu_ld16s(t0, addr, ctx->mem_idx);
6856 #if defined(TARGET_PPC64)
6857 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
6858 tcg_gen_ext32u_tl(t0, t0);
6859 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6860 #else
6861 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
6862 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6863 #endif
6864 tcg_temp_free(t0);
6865 }
6866
6867 static always_inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
6868 {
6869 TCGv t0 = tcg_temp_new();
6870 #if defined(TARGET_PPC64)
6871 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6872 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
6873 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6874 tcg_gen_shli_tl(t0, t0, 16);
6875 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6876 #else
6877 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6878 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
6879 tcg_gen_addi_tl(addr, addr, 2);
6880 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6881 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
6882 #endif
6883 tcg_temp_free(t0);
6884 }
6885
6886 static always_inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
6887 {
6888 #if defined(TARGET_PPC64)
6889 TCGv t0 = tcg_temp_new();
6890 gen_qemu_ld16u(cpu_gpr[rD(ctx->opcode)], addr, ctx->mem_idx);
6891 tcg_gen_addi_tl(addr, addr, 2);
6892 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6893 tcg_gen_shli_tl(t0, t0, 32);
6894 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6895 tcg_temp_free(t0);
6896 #else
6897 gen_qemu_ld16u(cpu_gprh[rD(ctx->opcode)], addr, ctx->mem_idx);
6898 tcg_gen_addi_tl(addr, addr, 2);
6899 gen_qemu_ld16u(cpu_gpr[rD(ctx->opcode)], addr, ctx->mem_idx);
6900 #endif
6901 }
6902
6903 static always_inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
6904 {
6905 #if defined(TARGET_PPC64)
6906 TCGv t0 = tcg_temp_new();
6907 gen_qemu_ld16s(t0, addr, ctx->mem_idx);
6908 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
6909 tcg_gen_addi_tl(addr, addr, 2);
6910 gen_qemu_ld16s(t0, addr, ctx->mem_idx);
6911 tcg_gen_shli_tl(t0, t0, 32);
6912 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6913 tcg_temp_free(t0);
6914 #else
6915 gen_qemu_ld16s(cpu_gprh[rD(ctx->opcode)], addr, ctx->mem_idx);
6916 tcg_gen_addi_tl(addr, addr, 2);
6917 gen_qemu_ld16s(cpu_gpr[rD(ctx->opcode)], addr, ctx->mem_idx);
6918 #endif
6919 }
6920
6921 static always_inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
6922 {
6923 TCGv t0 = tcg_temp_new();
6924 gen_qemu_ld32u(t0, addr, ctx->mem_idx);
6925 #if defined(TARGET_PPC64)
6926 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
6927 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6928 #else
6929 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
6930 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
6931 #endif
6932 tcg_temp_free(t0);
6933 }
6934
6935 static always_inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
6936 {
6937 TCGv t0 = tcg_temp_new();
6938 #if defined(TARGET_PPC64)
6939 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6940 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
6941 tcg_gen_shli_tl(t0, t0, 32);
6942 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6943 tcg_gen_addi_tl(addr, addr, 2);
6944 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6945 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6946 tcg_gen_shli_tl(t0, t0, 16);
6947 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
6948 #else
6949 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6950 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
6951 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
6952 tcg_gen_addi_tl(addr, addr, 2);
6953 gen_qemu_ld16u(t0, addr, ctx->mem_idx);
6954 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
6955 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
6956 #endif
6957 tcg_temp_free(t0);
6958 }
6959
6960 static always_inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
6961 {
6962 #if defined(TARGET_PPC64)
6963 gen_qemu_st64(cpu_gpr[rS(ctx->opcode)], addr, ctx->mem_idx);
6964 #else
6965 TCGv_i64 t0 = tcg_temp_new_i64();
6966 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
6967 gen_qemu_st64(t0, addr, ctx->mem_idx);
6968 tcg_temp_free_i64(t0);
6969 #endif
6970 }
6971
6972 static always_inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
6973 {
6974 #if defined(TARGET_PPC64)
6975 TCGv t0 = tcg_temp_new();
6976 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
6977 gen_qemu_st32(t0, addr, ctx->mem_idx);
6978 tcg_temp_free(t0);
6979 #else
6980 gen_qemu_st32(cpu_gprh[rS(ctx->opcode)], addr, ctx->mem_idx);
6981 #endif
6982 tcg_gen_addi_tl(addr, addr, 4);
6983 gen_qemu_st32(cpu_gpr[rS(ctx->opcode)], addr, ctx->mem_idx);
6984 }
6985
6986 static always_inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
6987 {
6988 TCGv t0 = tcg_temp_new();
6989 #if defined(TARGET_PPC64)
6990 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
6991 #else
6992 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
6993 #endif
6994 gen_qemu_st16(t0, addr, ctx->mem_idx);
6995 tcg_gen_addi_tl(addr, addr, 2);
6996 #if defined(TARGET_PPC64)
6997 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
6998 gen_qemu_st16(t0, addr, ctx->mem_idx);
6999 #else
7000 gen_qemu_st16(cpu_gprh[rS(ctx->opcode)], addr, ctx->mem_idx);
7001 #endif
7002 tcg_gen_addi_tl(addr, addr, 2);
7003 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7004 gen_qemu_st16(t0, addr, ctx->mem_idx);
7005 tcg_temp_free(t0);
7006 tcg_gen_addi_tl(addr, addr, 2);
7007 gen_qemu_st16(cpu_gpr[rS(ctx->opcode)], addr, ctx->mem_idx);
7008 }
7009
7010 static always_inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
7011 {
7012 TCGv t0 = tcg_temp_new();
7013 #if defined(TARGET_PPC64)
7014 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7015 #else
7016 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7017 #endif
7018 gen_qemu_st16(t0, addr, ctx->mem_idx);
7019 tcg_gen_addi_tl(addr, addr, 2);
7020 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7021 gen_qemu_st16(t0, addr, ctx->mem_idx);
7022 tcg_temp_free(t0);
7023 }
7024
7025 static always_inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
7026 {
7027 #if defined(TARGET_PPC64)
7028 TCGv t0 = tcg_temp_new();
7029 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7030 gen_qemu_st16(t0, addr, ctx->mem_idx);
7031 tcg_temp_free(t0);
7032 #else
7033 gen_qemu_st16(cpu_gprh[rS(ctx->opcode)], addr, ctx->mem_idx);
7034 #endif
7035 tcg_gen_addi_tl(addr, addr, 2);
7036 gen_qemu_st16(cpu_gpr[rS(ctx->opcode)], addr, ctx->mem_idx);
7037 }
7038
7039 static always_inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
7040 {
7041 #if defined(TARGET_PPC64)
7042 TCGv t0 = tcg_temp_new();
7043 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7044 gen_qemu_st32(t0, addr, ctx->mem_idx);
7045 tcg_temp_free(t0);
7046 #else
7047 gen_qemu_st32(cpu_gprh[rS(ctx->opcode)], addr, ctx->mem_idx);
7048 #endif
7049 }
7050
7051 static always_inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
7052 {
7053 gen_qemu_st32(cpu_gpr[rS(ctx->opcode)], addr, ctx->mem_idx);
7054 }
7055
7056 #define GEN_SPEOP_LDST(name, opc2, sh) \
7057 GEN_HANDLER(gen_##name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE) \
7058 { \
7059 TCGv t0; \
7060 if (unlikely(!ctx->spe_enabled)) { \
7061 GEN_EXCP_NO_AP(ctx); \
7062 return; \
7063 } \
7064 t0 = tcg_temp_new(); \
7065 if (Rc(ctx->opcode)) { \
7066 gen_addr_spe_imm_index(t0, ctx, sh); \
7067 } else { \
7068 gen_addr_reg_index(t0, ctx); \
7069 } \
7070 gen_op_##name(ctx, t0); \
7071 tcg_temp_free(t0); \
7072 }
7073
7074 GEN_SPEOP_LDST(evldd, 0x00, 3);
7075 GEN_SPEOP_LDST(evldw, 0x01, 3);
7076 GEN_SPEOP_LDST(evldh, 0x02, 3);
7077 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
7078 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
7079 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
7080 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
7081 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
7082 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
7083 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
7084 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
7085
7086 GEN_SPEOP_LDST(evstdd, 0x10, 3);
7087 GEN_SPEOP_LDST(evstdw, 0x11, 3);
7088 GEN_SPEOP_LDST(evstdh, 0x12, 3);
7089 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
7090 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
7091 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
7092 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
7093
7094 /* Multiply and add - TODO */
7095 #if 0
7096 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0x00000000, PPC_SPE);
7097 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0x00000000, PPC_SPE);
7098 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, PPC_SPE);
7099 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0x00000000, PPC_SPE);
7100 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, PPC_SPE);
7101 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0x00000000, PPC_SPE);
7102 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0x00000000, PPC_SPE);
7103 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0x00000000, PPC_SPE);
7104 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, PPC_SPE);
7105 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0x00000000, PPC_SPE);
7106 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, PPC_SPE);
7107 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0x00000000, PPC_SPE);
7108
7109 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0x00000000, PPC_SPE);
7110 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, PPC_SPE);
7111 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, PPC_SPE);
7112 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0x00000000, PPC_SPE);
7113 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0x00000000, PPC_SPE);
7114 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE);
7115 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0x00000000, PPC_SPE);
7116 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0x00000000, PPC_SPE);
7117 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, PPC_SPE);
7118 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, PPC_SPE);
7119 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0x00000000, PPC_SPE);
7120 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0x00000000, PPC_SPE);
7121 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE);
7122 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0x00000000, PPC_SPE);
7123
7124 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, PPC_SPE);
7125 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, PPC_SPE);
7126 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, PPC_SPE);
7127 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, PPC_SPE);
7128 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, PPC_SPE);
7129 GEN_SPE(evmra, speundef, 0x07, 0x13, 0x0000F800, PPC_SPE);
7130
7131 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, PPC_SPE);
7132 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0x00000000, PPC_SPE);
7133 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, PPC_SPE);
7134 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0x00000000, PPC_SPE);
7135 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, PPC_SPE);
7136 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0x00000000, PPC_SPE);
7137 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, PPC_SPE);
7138 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0x00000000, PPC_SPE);
7139 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, PPC_SPE);
7140 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0x00000000, PPC_SPE);
7141 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, PPC_SPE);
7142 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0x00000000, PPC_SPE);
7143
7144 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, PPC_SPE);
7145 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, PPC_SPE);
7146 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0x00000000, PPC_SPE);
7147 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE);
7148 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0x00000000, PPC_SPE);
7149
7150 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, PPC_SPE);
7151 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0x00000000, PPC_SPE);
7152 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, PPC_SPE);
7153 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0x00000000, PPC_SPE);
7154 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, PPC_SPE);
7155 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0x00000000, PPC_SPE);
7156 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, PPC_SPE);
7157 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0x00000000, PPC_SPE);
7158 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, PPC_SPE);
7159 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0x00000000, PPC_SPE);
7160 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, PPC_SPE);
7161 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0x00000000, PPC_SPE);
7162
7163 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, PPC_SPE);
7164 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, PPC_SPE);
7165 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0x00000000, PPC_SPE);
7166 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, PPC_SPE);
7167 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE);
7168 #endif
7169
7170 /*** SPE floating-point extension ***/
7171 #if defined(TARGET_PPC64)
7172 #define GEN_SPEFPUOP_CONV_32_32(name) \
7173 static always_inline void gen_##name (DisasContext *ctx) \
7174 { \
7175 TCGv_i32 t0; \
7176 TCGv t1; \
7177 t0 = tcg_temp_new_i32(); \
7178 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7179 gen_helper_##name(t0, t0); \
7180 t1 = tcg_temp_new(); \
7181 tcg_gen_extu_i32_tl(t1, t0); \
7182 tcg_temp_free_i32(t0); \
7183 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7184 0xFFFFFFFF00000000ULL); \
7185 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
7186 tcg_temp_free(t1); \
7187 }
7188 #define GEN_SPEFPUOP_CONV_32_64(name) \
7189 static always_inline void gen_##name (DisasContext *ctx) \
7190 { \
7191 TCGv_i32 t0; \
7192 TCGv t1; \
7193 t0 = tcg_temp_new_i32(); \
7194 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
7195 t1 = tcg_temp_new(); \
7196 tcg_gen_extu_i32_tl(t1, t0); \
7197 tcg_temp_free_i32(t0); \
7198 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7199 0xFFFFFFFF00000000ULL); \
7200 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
7201 tcg_temp_free(t1); \
7202 }
7203 #define GEN_SPEFPUOP_CONV_64_32(name) \
7204 static always_inline void gen_##name (DisasContext *ctx) \
7205 { \
7206 TCGv_i32 t0 = tcg_temp_new_i32(); \
7207 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7208 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
7209 tcg_temp_free_i32(t0); \
7210 }
7211 #define GEN_SPEFPUOP_CONV_64_64(name) \
7212 static always_inline void gen_##name (DisasContext *ctx) \
7213 { \
7214 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7215 }
7216 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
7217 static always_inline void gen_##name (DisasContext *ctx) \
7218 { \
7219 TCGv_i32 t0, t1; \
7220 TCGv_i64 t2; \
7221 if (unlikely(!ctx->spe_enabled)) { \
7222 GEN_EXCP_NO_AP(ctx); \
7223 return; \
7224 } \
7225 t0 = tcg_temp_new_i32(); \
7226 t1 = tcg_temp_new_i32(); \
7227 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7228 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7229 gen_helper_##name(t0, t0, t1); \
7230 tcg_temp_free_i32(t1); \
7231 t2 = tcg_temp_new(); \
7232 tcg_gen_extu_i32_tl(t2, t0); \
7233 tcg_temp_free_i32(t0); \
7234 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7235 0xFFFFFFFF00000000ULL); \
7236 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
7237 tcg_temp_free(t2); \
7238 }
7239 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
7240 static always_inline void gen_##name (DisasContext *ctx) \
7241 { \
7242 if (unlikely(!ctx->spe_enabled)) { \
7243 GEN_EXCP_NO_AP(ctx); \
7244 return; \
7245 } \
7246 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7247 cpu_gpr[rB(ctx->opcode)]); \
7248 }
7249 #define GEN_SPEFPUOP_COMP_32(name) \
7250 static always_inline void gen_##name (DisasContext *ctx) \
7251 { \
7252 TCGv_i32 t0, t1; \
7253 if (unlikely(!ctx->spe_enabled)) { \
7254 GEN_EXCP_NO_AP(ctx); \
7255 return; \
7256 } \
7257 t0 = tcg_temp_new_i32(); \
7258 t1 = tcg_temp_new_i32(); \
7259 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7260 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7261 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
7262 tcg_temp_free_i32(t0); \
7263 tcg_temp_free_i32(t1); \
7264 }
7265 #define GEN_SPEFPUOP_COMP_64(name) \
7266 static always_inline void gen_##name (DisasContext *ctx) \
7267 { \
7268 if (unlikely(!ctx->spe_enabled)) { \
7269 GEN_EXCP_NO_AP(ctx); \
7270 return; \
7271 } \
7272 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
7273 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7274 }
7275 #else
7276 #define GEN_SPEFPUOP_CONV_32_32(name) \
7277 static always_inline void gen_##name (DisasContext *ctx) \
7278 { \
7279 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7280 }
7281 #define GEN_SPEFPUOP_CONV_32_64(name) \
7282 static always_inline void gen_##name (DisasContext *ctx) \
7283 { \
7284 TCGv_i64 t0 = tcg_temp_new_i64(); \
7285 gen_load_gpr64(t0, rB(ctx->opcode)); \
7286 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
7287 tcg_temp_free_i64(t0); \
7288 }
7289 #define GEN_SPEFPUOP_CONV_64_32(name) \
7290 static always_inline void gen_##name (DisasContext *ctx) \
7291 { \
7292 TCGv_i64 t0 = tcg_temp_new_i64(); \
7293 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
7294 gen_store_gpr64(rD(ctx->opcode), t0); \
7295 tcg_temp_free_i64(t0); \
7296 }
7297 #define GEN_SPEFPUOP_CONV_64_64(name) \
7298 static always_inline void gen_##name (DisasContext *ctx) \
7299 { \
7300 TCGv_i64 t0 = tcg_temp_new_i64(); \
7301 gen_load_gpr64(t0, rB(ctx->opcode)); \
7302 gen_helper_##name(t0, t0); \
7303 gen_store_gpr64(rD(ctx->opcode), t0); \
7304 tcg_temp_free_i64(t0); \
7305 }
7306 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
7307 static always_inline void gen_##name (DisasContext *ctx) \
7308 { \
7309 if (unlikely(!ctx->spe_enabled)) { \
7310 GEN_EXCP_NO_AP(ctx); \
7311 return; \
7312 } \
7313 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], \
7314 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7315 }
7316 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
7317 static always_inline void gen_##name (DisasContext *ctx) \
7318 { \
7319 TCGv_i64 t0, t1; \
7320 if (unlikely(!ctx->spe_enabled)) { \
7321 GEN_EXCP_NO_AP(ctx); \
7322 return; \
7323 } \
7324 t0 = tcg_temp_new_i64(); \
7325 t1 = tcg_temp_new_i64(); \
7326 gen_load_gpr64(t0, rA(ctx->opcode)); \
7327 gen_load_gpr64(t1, rB(ctx->opcode)); \
7328 gen_helper_##name(t0, t0, t1); \
7329 gen_store_gpr64(rD(ctx->opcode), t0); \
7330 tcg_temp_free_i64(t0); \
7331 tcg_temp_free_i64(t1); \
7332 }
7333 #define GEN_SPEFPUOP_COMP_32(name) \
7334 static always_inline void gen_##name (DisasContext *ctx) \
7335 { \
7336 if (unlikely(!ctx->spe_enabled)) { \
7337 GEN_EXCP_NO_AP(ctx); \
7338 return; \
7339 } \
7340 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
7341 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7342 }
7343 #define GEN_SPEFPUOP_COMP_64(name) \
7344 static always_inline void gen_##name (DisasContext *ctx) \
7345 { \
7346 TCGv_i64 t0, t1; \
7347 if (unlikely(!ctx->spe_enabled)) { \
7348 GEN_EXCP_NO_AP(ctx); \
7349 return; \
7350 } \
7351 t0 = tcg_temp_new_i64(); \
7352 t1 = tcg_temp_new_i64(); \
7353 gen_load_gpr64(t0, rA(ctx->opcode)); \
7354 gen_load_gpr64(t1, rB(ctx->opcode)); \
7355 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
7356 tcg_temp_free_i64(t0); \
7357 tcg_temp_free_i64(t1); \
7358 }
7359 #endif
7360
7361 /* Single precision floating-point vectors operations */
7362 /* Arithmetic */
7363 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
7364 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
7365 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
7366 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
7367 static always_inline void gen_evfsabs (DisasContext *ctx)
7368 {
7369 if (unlikely(!ctx->spe_enabled)) {
7370 GEN_EXCP_NO_AP(ctx);
7371 return;
7372 }
7373 #if defined(TARGET_PPC64)
7374 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
7375 #else
7376 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
7377 tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
7378 #endif
7379 }
7380 static always_inline void gen_evfsnabs (DisasContext *ctx)
7381 {
7382 if (unlikely(!ctx->spe_enabled)) {
7383 GEN_EXCP_NO_AP(ctx);
7384 return;
7385 }
7386 #if defined(TARGET_PPC64)
7387 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
7388 #else
7389 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7390 tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7391 #endif
7392 }
7393 static always_inline void gen_evfsneg (DisasContext *ctx)
7394 {
7395 if (unlikely(!ctx->spe_enabled)) {
7396 GEN_EXCP_NO_AP(ctx);
7397 return;
7398 }
7399 #if defined(TARGET_PPC64)
7400 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
7401 #else
7402 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7403 tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7404 #endif
7405 }
7406
7407 /* Conversion */
7408 GEN_SPEFPUOP_CONV_64_64(evfscfui);
7409 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
7410 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
7411 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
7412 GEN_SPEFPUOP_CONV_64_64(evfsctui);
7413 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
7414 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
7415 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
7416 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
7417 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
7418
7419 /* Comparison */
7420 GEN_SPEFPUOP_COMP_64(evfscmpgt);
7421 GEN_SPEFPUOP_COMP_64(evfscmplt);
7422 GEN_SPEFPUOP_COMP_64(evfscmpeq);
7423 GEN_SPEFPUOP_COMP_64(evfststgt);
7424 GEN_SPEFPUOP_COMP_64(evfststlt);
7425 GEN_SPEFPUOP_COMP_64(evfststeq);
7426
7427 /* Opcodes definitions */
7428 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPEFPU); //
7429 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPEFPU); //
7430 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPEFPU); //
7431 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPEFPU); //
7432 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPEFPU); //
7433 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPEFPU); //
7434 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPEFPU); //
7435 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPEFPU); //
7436 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPEFPU); //
7437 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPEFPU); //
7438 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPEFPU); //
7439 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPEFPU); //
7440 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPEFPU); //
7441 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPEFPU); //
7442
7443 /* Single precision floating-point operations */
7444 /* Arithmetic */
7445 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
7446 GEN_SPEFPUOP_ARITH2_32_32(efssub);
7447 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
7448 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
7449 static always_inline void gen_efsabs (DisasContext *ctx)
7450 {
7451 if (unlikely(!ctx->spe_enabled)) {
7452 GEN_EXCP_NO_AP(ctx);
7453 return;
7454 }
7455 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
7456 }
7457 static always_inline void gen_efsnabs (DisasContext *ctx)
7458 {
7459 if (unlikely(!ctx->spe_enabled)) {
7460 GEN_EXCP_NO_AP(ctx);
7461 return;
7462 }
7463 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7464 }
7465 static always_inline void gen_efsneg (DisasContext *ctx)
7466 {
7467 if (unlikely(!ctx->spe_enabled)) {
7468 GEN_EXCP_NO_AP(ctx);
7469 return;
7470 }
7471 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7472 }
7473
7474 /* Conversion */
7475 GEN_SPEFPUOP_CONV_32_32(efscfui);
7476 GEN_SPEFPUOP_CONV_32_32(efscfsi);
7477 GEN_SPEFPUOP_CONV_32_32(efscfuf);
7478 GEN_SPEFPUOP_CONV_32_32(efscfsf);
7479 GEN_SPEFPUOP_CONV_32_32(efsctui);
7480 GEN_SPEFPUOP_CONV_32_32(efsctsi);
7481 GEN_SPEFPUOP_CONV_32_32(efsctuf);
7482 GEN_SPEFPUOP_CONV_32_32(efsctsf);
7483 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
7484 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
7485 GEN_SPEFPUOP_CONV_32_64(efscfd);
7486
7487 /* Comparison */
7488 GEN_SPEFPUOP_COMP_32(efscmpgt);
7489 GEN_SPEFPUOP_COMP_32(efscmplt);
7490 GEN_SPEFPUOP_COMP_32(efscmpeq);
7491 GEN_SPEFPUOP_COMP_32(efststgt);
7492 GEN_SPEFPUOP_COMP_32(efststlt);
7493 GEN_SPEFPUOP_COMP_32(efststeq);
7494
7495 /* Opcodes definitions */
7496 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPEFPU); //
7497 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPEFPU); //
7498 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPEFPU); //
7499 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPEFPU); //
7500 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPEFPU); //
7501 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPEFPU); //
7502 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPEFPU); //
7503 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPEFPU); //
7504 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPEFPU); //
7505 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPEFPU); //
7506 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, PPC_SPEFPU); //
7507 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, PPC_SPEFPU); //
7508 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPEFPU); //
7509 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPEFPU); //
7510
7511 /* Double precision floating-point operations */
7512 /* Arithmetic */
7513 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
7514 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
7515 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
7516 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
7517 static always_inline void gen_efdabs (DisasContext *ctx)
7518 {
7519 if (unlikely(!ctx->spe_enabled)) {
7520 GEN_EXCP_NO_AP(ctx);
7521 return;
7522 }
7523 #if defined(TARGET_PPC64)
7524 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
7525 #else
7526 tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
7527 #endif
7528 }
7529 static always_inline void gen_efdnabs (DisasContext *ctx)
7530 {
7531 if (unlikely(!ctx->spe_enabled)) {
7532 GEN_EXCP_NO_AP(ctx);
7533 return;
7534 }
7535 #if defined(TARGET_PPC64)
7536 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
7537 #else
7538 tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7539 #endif
7540 }
7541 static always_inline void gen_efdneg (DisasContext *ctx)
7542 {
7543 if (unlikely(!ctx->spe_enabled)) {
7544 GEN_EXCP_NO_AP(ctx);
7545 return;
7546 }
7547 #if defined(TARGET_PPC64)
7548 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
7549 #else
7550 tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7551 #endif
7552 }
7553
7554 /* Conversion */
7555 GEN_SPEFPUOP_CONV_64_32(efdcfui);
7556 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
7557 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
7558 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
7559 GEN_SPEFPUOP_CONV_32_64(efdctui);
7560 GEN_SPEFPUOP_CONV_32_64(efdctsi);
7561 GEN_SPEFPUOP_CONV_32_64(efdctuf);
7562 GEN_SPEFPUOP_CONV_32_64(efdctsf);
7563 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
7564 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
7565 GEN_SPEFPUOP_CONV_64_32(efdcfs);
7566 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
7567 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
7568 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
7569 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
7570
7571 /* Comparison */
7572 GEN_SPEFPUOP_COMP_64(efdcmpgt);
7573 GEN_SPEFPUOP_COMP_64(efdcmplt);
7574 GEN_SPEFPUOP_COMP_64(efdcmpeq);
7575 GEN_SPEFPUOP_COMP_64(efdtstgt);
7576 GEN_SPEFPUOP_COMP_64(efdtstlt);
7577 GEN_SPEFPUOP_COMP_64(efdtsteq);
7578
7579 /* Opcodes definitions */
7580 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPEFPU); //
7581 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPEFPU); //
7582 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPEFPU); //
7583 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPEFPU); //
7584 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPEFPU); //
7585 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPEFPU); //
7586 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPEFPU); //
7587 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPEFPU); //
7588 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPEFPU); //
7589 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPEFPU); //
7590 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPEFPU); //
7591 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPEFPU); //
7592 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPEFPU); //
7593 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPEFPU); //
7594 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPEFPU); //
7595 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPEFPU); //
7596
7597 /* End opcode list */
7598 GEN_OPCODE_MARK(end);
7599
7600 #include "translate_init.c"
7601 #include "helper_regs.h"
7602
7603 /*****************************************************************************/
7604 /* Misc PowerPC helpers */
7605 void cpu_dump_state (CPUState *env, FILE *f,
7606 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
7607 int flags)
7608 {
7609 #define RGPL 4
7610 #define RFPL 4
7611
7612 int i;
7613
7614 cpu_fprintf(f, "NIP " ADDRX " LR " ADDRX " CTR " ADDRX " XER %08x\n",
7615 env->nip, env->lr, env->ctr, env->xer);
7616 cpu_fprintf(f, "MSR " ADDRX " HID0 " ADDRX " HF " ADDRX " idx %d\n",
7617 env->msr, env->spr[SPR_HID0], env->hflags, env->mmu_idx);
7618 #if !defined(NO_TIMER_DUMP)
7619 cpu_fprintf(f, "TB %08x %08x "
7620 #if !defined(CONFIG_USER_ONLY)
7621 "DECR %08x"
7622 #endif
7623 "\n",
7624 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
7625 #if !defined(CONFIG_USER_ONLY)
7626 , cpu_ppc_load_decr(env)
7627 #endif
7628 );
7629 #endif
7630 for (i = 0; i < 32; i++) {
7631 if ((i & (RGPL - 1)) == 0)
7632 cpu_fprintf(f, "GPR%02d", i);
7633 cpu_fprintf(f, " " REGX, ppc_dump_gpr(env, i));
7634 if ((i & (RGPL - 1)) == (RGPL - 1))
7635 cpu_fprintf(f, "\n");
7636 }
7637 cpu_fprintf(f, "CR ");
7638 for (i = 0; i < 8; i++)
7639 cpu_fprintf(f, "%01x", env->crf[i]);
7640 cpu_fprintf(f, " [");
7641 for (i = 0; i < 8; i++) {
7642 char a = '-';
7643 if (env->crf[i] & 0x08)
7644 a = 'L';
7645 else if (env->crf[i] & 0x04)
7646 a = 'G';
7647 else if (env->crf[i] & 0x02)
7648 a = 'E';
7649 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
7650 }
7651 cpu_fprintf(f, " ] RES " ADDRX "\n", env->reserve);
7652 for (i = 0; i < 32; i++) {
7653 if ((i & (RFPL - 1)) == 0)
7654 cpu_fprintf(f, "FPR%02d", i);
7655 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
7656 if ((i & (RFPL - 1)) == (RFPL - 1))
7657 cpu_fprintf(f, "\n");
7658 }
7659 #if !defined(CONFIG_USER_ONLY)
7660 cpu_fprintf(f, "SRR0 " ADDRX " SRR1 " ADDRX " SDR1 " ADDRX "\n",
7661 env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1);
7662 #endif
7663
7664 #undef RGPL
7665 #undef RFPL
7666 }
7667
7668 void cpu_dump_statistics (CPUState *env, FILE*f,
7669 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
7670 int flags)
7671 {
7672 #if defined(DO_PPC_STATISTICS)
7673 opc_handler_t **t1, **t2, **t3, *handler;
7674 int op1, op2, op3;
7675
7676 t1 = env->opcodes;
7677 for (op1 = 0; op1 < 64; op1++) {
7678 handler = t1[op1];
7679 if (is_indirect_opcode(handler)) {
7680 t2 = ind_table(handler);
7681 for (op2 = 0; op2 < 32; op2++) {
7682 handler = t2[op2];
7683 if (is_indirect_opcode(handler)) {
7684 t3 = ind_table(handler);
7685 for (op3 = 0; op3 < 32; op3++) {
7686 handler = t3[op3];
7687 if (handler->count == 0)
7688 continue;
7689 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
7690 "%016llx %lld\n",
7691 op1, op2, op3, op1, (op3 << 5) | op2,
7692 handler->oname,
7693 handler->count, handler->count);
7694 }
7695 } else {
7696 if (handler->count == 0)
7697 continue;
7698 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
7699 "%016llx %lld\n",
7700 op1, op2, op1, op2, handler->oname,
7701 handler->count, handler->count);
7702 }
7703 }
7704 } else {
7705 if (handler->count == 0)
7706 continue;
7707 cpu_fprintf(f, "%02x (%02x ) %16s: %016llx %lld\n",
7708 op1, op1, handler->oname,
7709 handler->count, handler->count);
7710 }
7711 }
7712 #endif
7713 }
7714
7715 /*****************************************************************************/
7716 static always_inline void gen_intermediate_code_internal (CPUState *env,
7717 TranslationBlock *tb,
7718 int search_pc)
7719 {
7720 DisasContext ctx, *ctxp = &ctx;
7721 opc_handler_t **table, *handler;
7722 target_ulong pc_start;
7723 uint16_t *gen_opc_end;
7724 int supervisor, little_endian;
7725 CPUBreakpoint *bp;
7726 int j, lj = -1;
7727 int num_insns;
7728 int max_insns;
7729
7730 pc_start = tb->pc;
7731 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
7732 #if defined(OPTIMIZE_FPRF_UPDATE)
7733 gen_fprf_ptr = gen_fprf_buf;
7734 #endif
7735 ctx.nip = pc_start;
7736 ctx.tb = tb;
7737 ctx.exception = POWERPC_EXCP_NONE;
7738 ctx.spr_cb = env->spr_cb;
7739 supervisor = env->mmu_idx;
7740 #if !defined(CONFIG_USER_ONLY)
7741 ctx.supervisor = supervisor;
7742 #endif
7743 little_endian = env->hflags & (1 << MSR_LE) ? 1 : 0;
7744 #if defined(TARGET_PPC64)
7745 ctx.sf_mode = msr_sf;
7746 ctx.mem_idx = (supervisor << 2) | (msr_sf << 1) | little_endian;
7747 #else
7748 ctx.mem_idx = (supervisor << 1) | little_endian;
7749 #endif
7750 ctx.fpu_enabled = msr_fp;
7751 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
7752 ctx.spe_enabled = msr_spe;
7753 else
7754 ctx.spe_enabled = 0;
7755 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
7756 ctx.altivec_enabled = msr_vr;
7757 else
7758 ctx.altivec_enabled = 0;
7759 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
7760 ctx.singlestep_enabled = CPU_SINGLE_STEP;
7761 else
7762 ctx.singlestep_enabled = 0;
7763 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
7764 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
7765 if (unlikely(env->singlestep_enabled))
7766 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
7767 #if defined (DO_SINGLE_STEP) && 0
7768 /* Single step trace mode */
7769 msr_se = 1;
7770 #endif
7771 num_insns = 0;
7772 max_insns = tb->cflags & CF_COUNT_MASK;
7773 if (max_insns == 0)
7774 max_insns = CF_COUNT_MASK;
7775
7776 gen_icount_start();
7777 /* Set env in case of segfault during code fetch */
7778 while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
7779 if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) {
7780 TAILQ_FOREACH(bp, &env->breakpoints, entry) {
7781 if (bp->pc == ctx.nip) {
7782 gen_update_nip(&ctx, ctx.nip);
7783 gen_helper_raise_debug();
7784 break;
7785 }
7786 }
7787 }
7788 if (unlikely(search_pc)) {
7789 j = gen_opc_ptr - gen_opc_buf;
7790 if (lj < j) {
7791 lj++;
7792 while (lj < j)
7793 gen_opc_instr_start[lj++] = 0;
7794 gen_opc_pc[lj] = ctx.nip;
7795 gen_opc_instr_start[lj] = 1;
7796 gen_opc_icount[lj] = num_insns;
7797 }
7798 }
7799 #if defined PPC_DEBUG_DISAS
7800 if (loglevel & CPU_LOG_TB_IN_ASM) {
7801 fprintf(logfile, "----------------\n");
7802 fprintf(logfile, "nip=" ADDRX " super=%d ir=%d\n",
7803 ctx.nip, supervisor, (int)msr_ir);
7804 }
7805 #endif
7806 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
7807 gen_io_start();
7808 if (unlikely(little_endian)) {
7809 ctx.opcode = bswap32(ldl_code(ctx.nip));
7810 } else {
7811 ctx.opcode = ldl_code(ctx.nip);
7812 }
7813 #if defined PPC_DEBUG_DISAS
7814 if (loglevel & CPU_LOG_TB_IN_ASM) {
7815 fprintf(logfile, "translate opcode %08x (%02x %02x %02x) (%s)\n",
7816 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
7817 opc3(ctx.opcode), little_endian ? "little" : "big");
7818 }
7819 #endif
7820 ctx.nip += 4;
7821 table = env->opcodes;
7822 num_insns++;
7823 handler = table[opc1(ctx.opcode)];
7824 if (is_indirect_opcode(handler)) {
7825 table = ind_table(handler);
7826 handler = table[opc2(ctx.opcode)];
7827 if (is_indirect_opcode(handler)) {
7828 table = ind_table(handler);
7829 handler = table[opc3(ctx.opcode)];
7830 }
7831 }
7832 /* Is opcode *REALLY* valid ? */
7833 if (unlikely(handler->handler == &gen_invalid)) {
7834 if (loglevel != 0) {
7835 fprintf(logfile, "invalid/unsupported opcode: "
7836 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
7837 opc1(ctx.opcode), opc2(ctx.opcode),
7838 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
7839 } else {
7840 printf("invalid/unsupported opcode: "
7841 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
7842 opc1(ctx.opcode), opc2(ctx.opcode),
7843 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
7844 }
7845 } else {
7846 if (unlikely((ctx.opcode & handler->inval) != 0)) {
7847 if (loglevel != 0) {
7848 fprintf(logfile, "invalid bits: %08x for opcode: "
7849 "%02x - %02x - %02x (%08x) " ADDRX "\n",
7850 ctx.opcode & handler->inval, opc1(ctx.opcode),
7851 opc2(ctx.opcode), opc3(ctx.opcode),
7852 ctx.opcode, ctx.nip - 4);
7853 } else {
7854 printf("invalid bits: %08x for opcode: "
7855 "%02x - %02x - %02x (%08x) " ADDRX "\n",
7856 ctx.opcode & handler->inval, opc1(ctx.opcode),
7857 opc2(ctx.opcode), opc3(ctx.opcode),
7858 ctx.opcode, ctx.nip - 4);
7859 }
7860 GEN_EXCP_INVAL(ctxp);
7861 break;
7862 }
7863 }
7864 (*(handler->handler))(&ctx);
7865 #if defined(DO_PPC_STATISTICS)
7866 handler->count++;
7867 #endif
7868 /* Check trace mode exceptions */
7869 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
7870 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
7871 ctx.exception != POWERPC_SYSCALL &&
7872 ctx.exception != POWERPC_EXCP_TRAP &&
7873 ctx.exception != POWERPC_EXCP_BRANCH)) {
7874 GEN_EXCP(ctxp, POWERPC_EXCP_TRACE, 0);
7875 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
7876 (env->singlestep_enabled) ||
7877 num_insns >= max_insns)) {
7878 /* if we reach a page boundary or are single stepping, stop
7879 * generation
7880 */
7881 break;
7882 }
7883 #if defined (DO_SINGLE_STEP)
7884 break;
7885 #endif
7886 }
7887 if (tb->cflags & CF_LAST_IO)
7888 gen_io_end();
7889 if (ctx.exception == POWERPC_EXCP_NONE) {
7890 gen_goto_tb(&ctx, 0, ctx.nip);
7891 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
7892 if (unlikely(env->singlestep_enabled)) {
7893 gen_update_nip(&ctx, ctx.nip);
7894 gen_helper_raise_debug();
7895 }
7896 /* Generate the return instruction */
7897 tcg_gen_exit_tb(0);
7898 }
7899 gen_icount_end(tb, num_insns);
7900 *gen_opc_ptr = INDEX_op_end;
7901 if (unlikely(search_pc)) {
7902 j = gen_opc_ptr - gen_opc_buf;
7903 lj++;
7904 while (lj <= j)
7905 gen_opc_instr_start[lj++] = 0;
7906 } else {
7907 tb->size = ctx.nip - pc_start;
7908 tb->icount = num_insns;
7909 }
7910 #if defined(DEBUG_DISAS)
7911 if (loglevel & CPU_LOG_TB_CPU) {
7912 fprintf(logfile, "---------------- excp: %04x\n", ctx.exception);
7913 cpu_dump_state(env, logfile, fprintf, 0);
7914 }
7915 if (loglevel & CPU_LOG_TB_IN_ASM) {
7916 int flags;
7917 flags = env->bfd_mach;
7918 flags |= little_endian << 16;
7919 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
7920 target_disas(logfile, pc_start, ctx.nip - pc_start, flags);
7921 fprintf(logfile, "\n");
7922 }
7923 #endif
7924 }
7925
7926 void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
7927 {
7928 gen_intermediate_code_internal(env, tb, 0);
7929 }
7930
7931 void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
7932 {
7933 gen_intermediate_code_internal(env, tb, 1);
7934 }
7935
7936 void gen_pc_load(CPUState *env, TranslationBlock *tb,
7937 unsigned long searched_pc, int pc_pos, void *puc)
7938 {
7939 env->nip = gen_opc_pc[pc_pos];
7940 }
Patches shipped by Fedora